1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2019-2021, Ampere Computing LLC *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
22 ***************************************************************************/
24 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
25 #define OPENOCD_TARGET_ARM_ADI_V5_H
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
34 #include <helper/list.h>
36 #include "helper/bits.h"
38 /* JEP106 ID for ARM */
41 /* three-bit ACK values for SWD access (sent LSB first) */
42 #define SWD_ACK_OK 0x1
43 #define SWD_ACK_WAIT 0x2
44 #define SWD_ACK_FAULT 0x4
49 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
51 /* A[3:0] for DP registers; A[1:0] are always zero.
52 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
53 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
54 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
56 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
57 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
58 #define DP_DPIDR1 BANK_REG(0x1, 0x0) /* DPv3: ro */
59 #define DP_BASEPTR0 BANK_REG(0x2, 0x0) /* DPv3: ro */
60 #define DP_BASEPTR1 BANK_REG(0x3, 0x0) /* DPv3: ro */
61 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
62 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
63 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
64 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
65 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
66 #define DP_SELECT1 BANK_REG(0x5, 0x4) /* DPv3: ro */
67 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
68 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
69 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
70 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
72 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
74 /* Fields of DP_DPIDR register */
75 #define DP_DPIDR_VERSION_SHIFT 12
76 #define DP_DPIDR_VERSION_MASK (0xFUL << DP_DPIDR_VERSION_SHIFT)
78 /* Fields of the DP's AP ABORT register */
79 #define DAPABORT (1UL << 0)
80 #define STKCMPCLR (1UL << 1) /* SWD-only */
81 #define STKERRCLR (1UL << 2) /* SWD-only */
82 #define WDERRCLR (1UL << 3) /* SWD-only */
83 #define ORUNERRCLR (1UL << 4) /* SWD-only */
85 /* Fields of register DP_DPIDR1 */
86 #define DP_DPIDR1_ASIZE_MASK (0x7F)
87 #define DP_DPIDR1_ERRMODE BIT(7)
89 /* Fields of the DP's CTRL/STAT register */
90 #define CORUNDETECT (1UL << 0)
91 #define SSTICKYORUN (1UL << 1)
92 /* 3:2 - transaction mode (e.g. pushed compare) */
93 #define SSTICKYCMP (1UL << 4)
94 #define SSTICKYERR (1UL << 5)
95 #define READOK (1UL << 6) /* SWD-only */
96 #define WDATAERR (1UL << 7) /* SWD-only */
97 /* 11:8 - mask lanes for pushed compare or verify ops */
98 /* 21:12 - transaction counter */
99 #define CDBGRSTREQ (1UL << 26)
100 #define CDBGRSTACK (1UL << 27)
101 #define CDBGPWRUPREQ (1UL << 28)
102 #define CDBGPWRUPACK (1UL << 29)
103 #define CSYSPWRUPREQ (1UL << 30)
104 #define CSYSPWRUPACK (1UL << 31)
106 #define DP_DLPIDR_PROTVSN 1u
108 #define DP_SELECT_APSEL 0xFF000000
109 #define DP_SELECT_APBANK 0x000000F0
110 #define DP_SELECT_DPBANK 0x0000000F
111 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
113 #define DP_APSEL_MAX (255)
114 #define DP_APSEL_INVALID (-1)
116 #define DP_TARGETSEL_INVALID 0xFFFFFFFFU
117 #define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU
118 #define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U
119 #define DP_TARGETSEL_INSTANCEID_SHIFT 28
122 /* MEM-AP register addresses */
123 #define ADIV5_MEM_AP_REG_CSW (0x00)
124 #define ADIV5_MEM_AP_REG_TAR (0x04)
125 #define ADIV5_MEM_AP_REG_TAR64 (0x08) /* RW: Large Physical Address Extension */
126 #define ADIV5_MEM_AP_REG_DRW (0x0C) /* RW: Data Read/Write register */
127 #define ADIV5_MEM_AP_REG_BD0 (0x10) /* RW: Banked Data register 0-3 */
128 #define ADIV5_MEM_AP_REG_BD1 (0x14)
129 #define ADIV5_MEM_AP_REG_BD2 (0x18)
130 #define ADIV5_MEM_AP_REG_BD3 (0x1C)
131 #define ADIV5_MEM_AP_REG_MBT (0x20) /* --: Memory Barrier Transfer register */
132 #define ADIV5_MEM_AP_REG_BASE64 (0xF0) /* RO: Debug Base Address (LA) register */
133 #define ADIV5_MEM_AP_REG_CFG (0xF4) /* RO: Configuration register */
134 #define ADIV5_MEM_AP_REG_BASE (0xF8) /* RO: Debug Base Address register */
136 #define ADIV6_MEM_AP_REG_CSW (0xD00 + ADIV5_MEM_AP_REG_CSW)
137 #define ADIV6_MEM_AP_REG_TAR (0xD00 + ADIV5_MEM_AP_REG_TAR)
138 #define ADIV6_MEM_AP_REG_TAR64 (0xD00 + ADIV5_MEM_AP_REG_TAR64)
139 #define ADIV6_MEM_AP_REG_DRW (0xD00 + ADIV5_MEM_AP_REG_DRW)
140 #define ADIV6_MEM_AP_REG_BD0 (0xD00 + ADIV5_MEM_AP_REG_BD0)
141 #define ADIV6_MEM_AP_REG_BD1 (0xD00 + ADIV5_MEM_AP_REG_BD1)
142 #define ADIV6_MEM_AP_REG_BD2 (0xD00 + ADIV5_MEM_AP_REG_BD2)
143 #define ADIV6_MEM_AP_REG_BD3 (0xD00 + ADIV5_MEM_AP_REG_BD3)
144 #define ADIV6_MEM_AP_REG_MBT (0xD00 + ADIV5_MEM_AP_REG_MBT)
145 #define ADIV6_MEM_AP_REG_BASE64 (0xD00 + ADIV5_MEM_AP_REG_BASE64)
146 #define ADIV6_MEM_AP_REG_CFG (0xD00 + ADIV5_MEM_AP_REG_CFG)
147 #define ADIV6_MEM_AP_REG_BASE (0xD00 + ADIV5_MEM_AP_REG_BASE)
149 #define MEM_AP_REG_CSW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CSW : ADIV5_MEM_AP_REG_CSW)
150 #define MEM_AP_REG_TAR(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR : ADIV5_MEM_AP_REG_TAR)
151 #define MEM_AP_REG_TAR64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_TAR64 : ADIV5_MEM_AP_REG_TAR64)
152 #define MEM_AP_REG_DRW(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_DRW : ADIV5_MEM_AP_REG_DRW)
153 #define MEM_AP_REG_BD0(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD0 : ADIV5_MEM_AP_REG_BD0)
154 #define MEM_AP_REG_BD1(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD1 : ADIV5_MEM_AP_REG_BD1)
155 #define MEM_AP_REG_BD2(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD2 : ADIV5_MEM_AP_REG_BD2)
156 #define MEM_AP_REG_BD3(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BD3 : ADIV5_MEM_AP_REG_BD3)
157 #define MEM_AP_REG_MBT(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_MBT : ADIV5_MEM_AP_REG_MBT)
158 #define MEM_AP_REG_BASE64(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE64 : ADIV5_MEM_AP_REG_BASE64)
159 #define MEM_AP_REG_CFG(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_CFG : ADIV5_MEM_AP_REG_CFG)
160 #define MEM_AP_REG_BASE(dap) (is_adiv6(dap) ? ADIV6_MEM_AP_REG_BASE : ADIV5_MEM_AP_REG_BASE)
162 /* Generic AP register address */
163 #define ADIV5_AP_REG_IDR (0xFC) /* RO: Identification Register */
164 #define ADIV6_AP_REG_IDR (0xD00 + ADIV5_AP_REG_IDR)
165 #define AP_REG_IDR(dap) (is_adiv6(dap) ? ADIV6_AP_REG_IDR : ADIV5_AP_REG_IDR)
167 /* Fields of the MEM-AP's CSW register */
168 #define CSW_SIZE_MASK 7
172 #define CSW_ADDRINC_MASK (3UL << 4)
173 #define CSW_ADDRINC_OFF 0UL
174 #define CSW_ADDRINC_SINGLE (1UL << 4)
175 #define CSW_ADDRINC_PACKED (2UL << 4)
176 #define CSW_DEVICE_EN (1UL << 6)
177 #define CSW_TRIN_PROG (1UL << 7)
179 /* All fields in bits 12 and above are implementation-defined
180 * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
181 * Some bits are shared between buses
183 #define CSW_SPIDEN (1UL << 23)
184 #define CSW_DBGSWENABLE (1UL << 31)
186 /* AHB: Privileged */
187 #define CSW_AHB_HPROT1 (1UL << 25)
188 /* AHB: set HMASTER signals to AHB-AP ID */
189 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
190 /* AHB5: non-secure access via HNONSEC
191 * AHB3: SBO, UNPREDICTABLE if zero */
192 #define CSW_AHB_SPROT (1UL << 30)
193 /* AHB: initial value of csw_default */
194 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
196 /* AXI: Privileged */
197 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
198 /* AXI: Non-secure */
199 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
200 /* AXI: initial value of csw_default */
201 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
203 /* APB: initial value of csw_default */
204 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
206 /* Fields of the MEM-AP's CFG register */
207 #define MEM_AP_REG_CFG_BE BIT(0)
208 #define MEM_AP_REG_CFG_LA BIT(1)
209 #define MEM_AP_REG_CFG_LD BIT(2)
210 #define MEM_AP_REG_CFG_INVALID 0xFFFFFFF8
212 /* Fields of the MEM-AP's IDR register */
213 #define AP_REG_IDR_REVISION_MASK (0xF0000000)
214 #define AP_REG_IDR_REVISION_SHIFT (28)
215 #define AP_REG_IDR_DESIGNER_MASK (0x0FFE0000)
216 #define AP_REG_IDR_DESIGNER_SHIFT (17)
217 #define AP_REG_IDR_CLASS_MASK (0x0001E000)
218 #define AP_REG_IDR_CLASS_SHIFT (13)
219 #define AP_REG_IDR_VARIANT_MASK (0x000000F0)
220 #define AP_REG_IDR_VARIANT_SHIFT (4)
221 #define AP_REG_IDR_TYPE_MASK (0x0000000F)
222 #define AP_REG_IDR_TYPE_SHIFT (0)
224 #define AP_REG_IDR_CLASS_NONE (0x0)
225 #define AP_REG_IDR_CLASS_COM (0x1)
226 #define AP_REG_IDR_CLASS_MEM_AP (0x8)
228 #define AP_REG_IDR_VALUE(d, c, t) (\
229 (((d) << AP_REG_IDR_DESIGNER_SHIFT) & AP_REG_IDR_DESIGNER_MASK) | \
230 (((c) << AP_REG_IDR_CLASS_SHIFT) & AP_REG_IDR_CLASS_MASK) | \
231 (((t) << AP_REG_IDR_TYPE_SHIFT) & AP_REG_IDR_TYPE_MASK) \
234 #define AP_TYPE_MASK (AP_REG_IDR_DESIGNER_MASK | AP_REG_IDR_CLASS_MASK | AP_REG_IDR_TYPE_MASK)
236 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
237 enum swd_special_seq
{
248 * This represents an ARM Debug Interface (v5) Access Port (AP).
249 * Most common is a MEM-AP, for memory access.
253 * DAP this AP belongs to.
255 struct adiv5_dap
*dap
;
263 * Default value for (MEM-AP) AP_REG_CSW register.
265 uint32_t csw_default
;
268 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
269 * configure an access mode, such as autoincrementing AP_REG_TAR during
270 * word access. "-1" indicates no cached value.
275 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
276 * configure the address being read or written
277 * "-1" indicates no cached value.
279 target_addr_t tar_value
;
282 * Configures how many extra tck clocks are added after starting a
283 * MEM-AP access before we try to read its status (and/or result).
285 uint32_t memaccess_tck
;
287 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
288 uint32_t tar_autoincr_block
;
290 /* true if packed transfers are supported by the MEM-AP */
291 bool packed_transfers
;
293 /* true if unaligned memory access is not supported by the MEM-AP */
294 bool unaligned_access_bad
;
296 /* true if tar_value is in sync with TAR register */
299 /* MEM AP configuration register indicating LPAE support */
302 /* references counter */
303 unsigned int refcount
;
305 /* AP referenced during config. Never put it, even when refcount reaches zero */
306 bool config_ap_never_release
;
311 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
312 * A DAP has two types of component: one Debug Port (DP), which is a
313 * transport agent; and at least one Access Port (AP), controlling
316 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
317 * Accordingly, this interface is responsible for hiding the transport
318 * differences so upper layer code can largely ignore them.
320 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
321 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
322 * a choice made at board design time (by only using the SWD pins), or
323 * as part of setting up a debug session (if all the dual-role JTAG/SWD
324 * signals are available).
327 const struct dap_ops
*ops
;
329 /* dap transaction list for WAIT support */
330 struct list_head cmd_journal
;
332 /* pool for dap_cmd objects */
333 struct list_head cmd_pool
;
335 /* number of dap_cmd objects in the pool */
336 size_t cmd_pool_size
;
338 struct jtag_tap
*tap
;
340 uint32_t dp_ctrl_stat
;
342 struct adiv5_ap ap
[DP_APSEL_MAX
+ 1];
344 /* The current manually selected AP by the "dap apsel" command */
348 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
349 * indicates no cached value and forces rewrite of the register.
353 /* information about current pending SWjDP-AHBAP transaction */
357 * Holds the pointer to the destination word for the last queued read,
358 * for use with posted AP read sequence optimization.
362 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
363 * despite lack of support in the ARMv7 architecture. Memory access through
364 * the AHB-AP has strange byte ordering these processors, and we need to
365 * swizzle appropriately. */
366 bool ti_be_32_quirks
;
369 * STLINK adapter need to know if last AP operation was read or write, and
370 * in case of write has to flush it with a dummy read from DP_RDBUFF
372 bool stlink_flush_ap_write
;
375 * Signals that an attempt to reestablish communication afresh
376 * should be performed before the next access.
380 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
381 * do not set this bit until later in the bringup sequence */
382 bool ignore_syspwrupack
;
384 /** Value to select DP in SWD multidrop mode or DP_TARGETSEL_INVALID */
385 uint32_t multidrop_targetsel
;
386 /** TPARTNO and TDESIGNER fields of multidrop_targetsel have been configured */
387 bool multidrop_dp_id_valid
;
388 /** TINSTANCE field of multidrop_targetsel has been configured */
389 bool multidrop_instance_id_valid
;
392 * Record if enter in SWD required passing through DORMANT
394 bool switch_through_dormant
;
396 /** Indicates ADI version (5, 6 or 0 for unknown) being used */
397 unsigned int adi_version
;
401 * Transport-neutral representation of queued DAP transactions, supporting
402 * both JTAG and SWD transports. All submitted transactions are logically
403 * queued, until the queue is executed by run(). Some implementations might
404 * execute transactions as soon as they're submitted, but no status is made
405 * available until run().
408 /** connect operation for SWD */
409 int (*connect
)(struct adiv5_dap
*dap
);
411 /** send a sequence to the DAP */
412 int (*send_sequence
)(struct adiv5_dap
*dap
, enum swd_special_seq seq
);
414 /** DP register read. */
415 int (*queue_dp_read
)(struct adiv5_dap
*dap
, unsigned reg
,
417 /** DP register write. */
418 int (*queue_dp_write
)(struct adiv5_dap
*dap
, unsigned reg
,
421 /** AP register read. */
422 int (*queue_ap_read
)(struct adiv5_ap
*ap
, unsigned reg
,
424 /** AP register write. */
425 int (*queue_ap_write
)(struct adiv5_ap
*ap
, unsigned reg
,
428 /** AP operation abort. */
429 int (*queue_ap_abort
)(struct adiv5_dap
*dap
, uint8_t *ack
);
431 /** Executes all queued DAP operations. */
432 int (*run
)(struct adiv5_dap
*dap
);
434 /** Executes all queued DAP operations but doesn't check
435 * sticky error conditions */
436 int (*sync
)(struct adiv5_dap
*dap
);
438 /** Optional; called at OpenOCD exit */
439 void (*quit
)(struct adiv5_dap
*dap
);
446 AP_TYPE_JTAG_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_NONE
, 0), /* JTAG-AP */
447 AP_TYPE_COM_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_COM
, 0), /* COM-AP */
448 AP_TYPE_AHB3_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 1), /* AHB3 Memory-AP */
449 AP_TYPE_APB_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 2), /* APB2 or APB3 Memory-AP */
450 AP_TYPE_AXI_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 4), /* AXI3 or AXI4 Memory-AP */
451 AP_TYPE_AHB5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 5), /* AHB5 Memory-AP */
452 AP_TYPE_APB4_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 6), /* APB4 Memory-AP */
453 AP_TYPE_AXI5_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 7), /* AXI5 Memory-AP */
454 AP_TYPE_AHB5H_AP
= AP_REG_IDR_VALUE(ARM_ID
, AP_REG_IDR_CLASS_MEM_AP
, 8), /* AHB5 with enhanced HPROT Memory-AP */
457 /* Check the ap->cfg_reg Long Address field (bit 1)
459 * 0b0: The AP only supports physical addresses 32 bits or smaller
460 * 0b1: The AP supports physical addresses larger than 32 bits
462 * @param ap The AP used for reading.
464 * @return true for 64 bit, false for 32 bit
466 static inline bool is_64bit_ap(struct adiv5_ap
*ap
)
468 return (ap
->cfg_reg
& MEM_AP_REG_CFG_LA
) != 0;
472 * Check if DAP is ADIv6
474 * @param dap The DAP to test
476 * @return true for ADIv6, false for either ADIv5 or unknown version
478 static inline bool is_adiv6(const struct adiv5_dap
*dap
)
480 return dap
->adi_version
== 6;
484 * Send an adi-v5 sequence to the DAP.
486 * @param dap The DAP used for reading.
487 * @param seq The sequence to send.
489 * @return ERROR_OK for success, else a fault code.
491 static inline int dap_send_sequence(struct adiv5_dap
*dap
,
492 enum swd_special_seq seq
)
495 return dap
->ops
->send_sequence(dap
, seq
);
499 * Queue a DP register read.
500 * Note that not all DP registers are readable; also, that JTAG and SWD
501 * have slight differences in DP register support.
503 * @param dap The DAP used for reading.
504 * @param reg The two-bit number of the DP register being read.
505 * @param data Pointer saying where to store the register's value
506 * (in host endianness).
508 * @return ERROR_OK for success, else a fault code.
510 static inline int dap_queue_dp_read(struct adiv5_dap
*dap
,
511 unsigned reg
, uint32_t *data
)
514 return dap
->ops
->queue_dp_read(dap
, reg
, data
);
518 * Queue a DP register write.
519 * Note that not all DP registers are writable; also, that JTAG and SWD
520 * have slight differences in DP register support.
522 * @param dap The DAP used for writing.
523 * @param reg The two-bit number of the DP register being written.
524 * @param data Value being written (host endianness)
526 * @return ERROR_OK for success, else a fault code.
528 static inline int dap_queue_dp_write(struct adiv5_dap
*dap
,
529 unsigned reg
, uint32_t data
)
532 return dap
->ops
->queue_dp_write(dap
, reg
, data
);
536 * Queue an AP register read.
538 * @param ap The AP used for reading.
539 * @param reg The number of the AP register being read.
540 * @param data Pointer saying where to store the register's value
541 * (in host endianness).
543 * @return ERROR_OK for success, else a fault code.
545 static inline int dap_queue_ap_read(struct adiv5_ap
*ap
,
546 unsigned reg
, uint32_t *data
)
548 assert(ap
->dap
->ops
);
549 if (ap
->refcount
== 0) {
551 LOG_ERROR("BUG: refcount AP#%" PRIu8
" used without get", ap
->ap_num
);
553 return ap
->dap
->ops
->queue_ap_read(ap
, reg
, data
);
557 * Queue an AP register write.
559 * @param ap The AP used for writing.
560 * @param reg The number of the AP register being written.
561 * @param data Value being written (host endianness)
563 * @return ERROR_OK for success, else a fault code.
565 static inline int dap_queue_ap_write(struct adiv5_ap
*ap
,
566 unsigned reg
, uint32_t data
)
568 assert(ap
->dap
->ops
);
569 if (ap
->refcount
== 0) {
571 LOG_ERROR("BUG: refcount AP#%" PRIu8
" used without get", ap
->ap_num
);
573 return ap
->dap
->ops
->queue_ap_write(ap
, reg
, data
);
577 * Queue an AP abort operation. The current AP transaction is aborted,
578 * including any update of the transaction counter. The AP is left in
579 * an unknown state (so it must be re-initialized). For use only after
580 * the AP has reported WAIT status for an extended period.
582 * @param dap The DAP used for writing.
583 * @param ack Pointer to where transaction status will be stored.
585 * @return ERROR_OK for success, else a fault code.
587 static inline int dap_queue_ap_abort(struct adiv5_dap
*dap
, uint8_t *ack
)
590 return dap
->ops
->queue_ap_abort(dap
, ack
);
594 * Perform all queued DAP operations, and clear any errors posted in the
595 * CTRL_STAT register when they are done. Note that if more than one AP
596 * operation will be queued, one of the first operations in the queue
597 * should probably enable CORUNDETECT in the CTRL/STAT register.
599 * @param dap The DAP used.
601 * @return ERROR_OK for success, else a fault code.
603 static inline int dap_run(struct adiv5_dap
*dap
)
606 return dap
->ops
->run(dap
);
609 static inline int dap_sync(struct adiv5_dap
*dap
)
613 return dap
->ops
->sync(dap
);
617 static inline int dap_dp_read_atomic(struct adiv5_dap
*dap
, unsigned reg
,
622 retval
= dap_queue_dp_read(dap
, reg
, value
);
623 if (retval
!= ERROR_OK
)
629 static inline int dap_dp_poll_register(struct adiv5_dap
*dap
, unsigned reg
,
630 uint32_t mask
, uint32_t value
, int timeout
)
633 assert((value
& mask
) == value
);
637 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32
", value 0x%08" PRIx32
,
640 ret
= dap_dp_read_atomic(dap
, reg
, ®val
);
644 if ((regval
& mask
) == value
)
651 LOG_DEBUG("DAP: poll %x timeout", reg
);
658 /* Queued MEM-AP memory mapped single word transfers. */
659 int mem_ap_read_u32(struct adiv5_ap
*ap
,
660 target_addr_t address
, uint32_t *value
);
661 int mem_ap_write_u32(struct adiv5_ap
*ap
,
662 target_addr_t address
, uint32_t value
);
664 /* Synchronous MEM-AP memory mapped single word transfers. */
665 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
,
666 target_addr_t address
, uint32_t *value
);
667 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
,
668 target_addr_t address
, uint32_t value
);
670 /* Synchronous MEM-AP memory mapped bus block transfers. */
671 int mem_ap_read_buf(struct adiv5_ap
*ap
,
672 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
673 int mem_ap_write_buf(struct adiv5_ap
*ap
,
674 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
676 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
677 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
678 uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
679 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
680 const uint8_t *buffer
, uint32_t size
, uint32_t count
, target_addr_t address
);
682 /* Initialisation of the debug system, power domains and registers */
683 int dap_dp_init(struct adiv5_dap
*dap
);
684 int dap_dp_init_or_reconnect(struct adiv5_dap
*dap
);
685 int mem_ap_init(struct adiv5_ap
*ap
);
687 /* Invalidate cached DP select and cached TAR and CSW of all APs */
688 void dap_invalidate_cache(struct adiv5_dap
*dap
);
690 /* Probe Access Ports to find a particular type. Increment AP refcount */
691 int dap_find_get_ap(struct adiv5_dap
*dap
,
692 enum ap_type type_to_find
,
693 struct adiv5_ap
**ap_out
);
695 /* Return AP with specified ap_num. Increment AP refcount */
696 struct adiv5_ap
*dap_get_ap(struct adiv5_dap
*dap
, unsigned int ap_num
);
698 /* Return AP with specified ap_num. Increment AP refcount and keep it non-zero */
699 struct adiv5_ap
*dap_get_config_ap(struct adiv5_dap
*dap
, unsigned int ap_num
);
701 /* Decrement AP refcount and release the AP when refcount reaches zero */
702 int dap_put_ap(struct adiv5_ap
*ap
);
704 /** Check if SWD multidrop configuration is valid */
705 static inline bool dap_is_multidrop(struct adiv5_dap
*dap
)
707 return dap
->multidrop_dp_id_valid
&& dap
->multidrop_instance_id_valid
;
710 /* Lookup CoreSight component */
711 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
712 uint8_t type
, target_addr_t
*addr
, int32_t idx
);
716 /* Put debug link into SWD mode */
717 int dap_to_swd(struct adiv5_dap
*dap
);
719 /* Put debug link into JTAG mode */
720 int dap_to_jtag(struct adiv5_dap
*dap
);
722 extern const struct command_registration dap_instance_commands
[];
724 struct arm_dap_object
;
725 extern struct adiv5_dap
*dap_instance_by_jim_obj(Jim_Interp
*interp
, Jim_Obj
*o
);
726 extern struct adiv5_dap
*adiv5_get_dap(struct arm_dap_object
*obj
);
727 extern int dap_info_command(struct command_invocation
*cmd
,
728 struct adiv5_ap
*ap
);
729 extern int dap_register_commands(struct command_context
*cmd_ctx
);
730 extern const char *adiv5_dap_name(struct adiv5_dap
*self
);
731 extern const struct swd_driver
*adiv5_dap_swd_driver(struct adiv5_dap
*self
);
732 extern int dap_cleanup_all(void);
734 struct adiv5_private_config
{
736 struct adiv5_dap
*dap
;
739 extern int adiv5_verify_config(struct adiv5_private_config
*pc
);
740 extern int adiv5_jim_configure(struct target
*target
, struct jim_getopt_info
*goi
);
742 struct adiv5_mem_ap_spot
{
743 struct adiv5_dap
*dap
;
748 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot
*p
);
749 extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot
*cfg
,
750 struct jim_getopt_info
*goi
);
752 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)