63d7f286e8c916727112edc3eff23c1df614289a
[openocd.git] / src / target / arm_adi_v5.h
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
22 ***************************************************************************/
23
24 #ifndef ARM_ADI_V5_H
25 #define ARM_ADI_V5_H
26
27 /**
28 * @file
29 * This defines formats and data structures used to talk to ADIv5 entities.
30 * Those include a DAP, different types of Debug Port (DP), and memory mapped
31 * resources accessed through a MEM-AP.
32 */
33
34 #include "arm_jtag.h"
35
36 /* FIXME remove these JTAG-specific decls when mem_ap_read_buf_u32()
37 * is no longer JTAG-specific
38 */
39 #define JTAG_DP_DPACC 0xA
40 #define JTAG_DP_APACC 0xB
41
42 /* three-bit ACK values for SWD access (sent LSB first) */
43 #define SWD_ACK_OK 0x1
44 #define SWD_ACK_WAIT 0x2
45 #define SWD_ACK_FAULT 0x4
46
47 #define DPAP_WRITE 0
48 #define DPAP_READ 1
49
50 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
51
52 /* A[3:0] for DP registers; A[1:0] are always zero.
53 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
54 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
55 * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
56 */
57 #define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */
58 #define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */
59 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */
60 #define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */
61 #define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */
62 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */
63 #define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */
64
65 #define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */
66 #define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */
67
68 /* Fields of the DP's AP ABORT register */
69 #define DAPABORT (1UL << 0)
70 #define STKCMPCLR (1UL << 1) /* SWD-only */
71 #define STKERRCLR (1UL << 2) /* SWD-only */
72 #define WDERRCLR (1UL << 3) /* SWD-only */
73 #define ORUNERRCLR (1UL << 4) /* SWD-only */
74
75 /* Fields of the DP's CTRL/STAT register */
76 #define CORUNDETECT (1UL << 0)
77 #define SSTICKYORUN (1UL << 1)
78 /* 3:2 - transaction mode (e.g. pushed compare) */
79 #define SSTICKYCMP (1UL << 4)
80 #define SSTICKYERR (1UL << 5)
81 #define READOK (1UL << 6) /* SWD-only */
82 #define WDATAERR (1UL << 7) /* SWD-only */
83 /* 11:8 - mask lanes for pushed compare or verify ops */
84 /* 21:12 - transaction counter */
85 #define CDBGRSTREQ (1UL << 26)
86 #define CDBGRSTACK (1UL << 27)
87 #define CDBGPWRUPREQ (1UL << 28)
88 #define CDBGPWRUPACK (1UL << 29)
89 #define CSYSPWRUPREQ (1UL << 30)
90 #define CSYSPWRUPACK (1UL << 31)
91
92 /* MEM-AP register addresses */
93 #define MEM_AP_REG_CSW 0x00
94 #define MEM_AP_REG_TAR 0x04
95 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
96 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
97 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
98 #define MEM_AP_REG_BD1 0x14
99 #define MEM_AP_REG_BD2 0x18
100 #define MEM_AP_REG_BD3 0x1C
101 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
102 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
103 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
104 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
105 /* Generic AP register address */
106 #define AP_REG_IDR 0xFC /* RO: Identification Register */
107
108 /* Fields of the MEM-AP's CSW register */
109 #define CSW_8BIT 0
110 #define CSW_16BIT 1
111 #define CSW_32BIT 2
112 #define CSW_ADDRINC_MASK (3UL << 4)
113 #define CSW_ADDRINC_OFF 0UL
114 #define CSW_ADDRINC_SINGLE (1UL << 4)
115 #define CSW_ADDRINC_PACKED (2UL << 4)
116 #define CSW_DEVICE_EN (1UL << 6)
117 #define CSW_TRIN_PROG (1UL << 7)
118 #define CSW_SPIDEN (1UL << 23)
119 /* 30:24 - implementation-defined! */
120 #define CSW_HPROT (1UL << 25) /* ? */
121 #define CSW_MASTER_DEBUG (1UL << 29) /* ? */
122 #define CSW_SPROT (1UL << 30)
123 #define CSW_DBGSWENABLE (1UL << 31)
124
125 /* Fields of the MEM-AP's IDR register */
126 #define IDR_REV (0xFUL << 28)
127 #define IDR_JEP106 (0x7FFUL << 17)
128 #define IDR_CLASS (0xFUL << 13)
129 #define IDR_VARIANT (0xFUL << 4)
130 #define IDR_TYPE (0xFUL << 0)
131
132 #define IDR_JEP106_ARM 0x04760000
133
134 /**
135 * This represents an ARM Debug Interface (v5) Access Port (AP).
136 * Most common is a MEM-AP, for memory access.
137 */
138 struct adiv5_ap {
139 /**
140 * DAP this AP belongs to.
141 */
142 struct adiv5_dap *dap;
143
144 /**
145 * Number of this AP.
146 */
147 uint8_t ap_num;
148
149 /**
150 * Default value for (MEM-AP) AP_REG_CSW register.
151 */
152 uint32_t csw_default;
153
154 /**
155 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
156 * configure an access mode, such as autoincrementing AP_REG_TAR during
157 * word access. "-1" indicates no cached value.
158 */
159 uint32_t csw_value;
160
161 /**
162 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
163 * configure the address being read or written
164 * "-1" indicates no cached value.
165 */
166 uint32_t tar_value;
167
168 /**
169 * Configures how many extra tck clocks are added after starting a
170 * MEM-AP access before we try to read its status (and/or result).
171 */
172 uint32_t memaccess_tck;
173
174 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
175 uint32_t tar_autoincr_block;
176
177 /* true if packed transfers are supported by the MEM-AP */
178 bool packed_transfers;
179
180 /* true if unaligned memory access is not supported by the MEM-AP */
181 bool unaligned_access_bad;
182 };
183
184
185 /**
186 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
187 * A DAP has two types of component: one Debug Port (DP), which is a
188 * transport agent; and at least one Access Port (AP), controlling
189 * resource access.
190 *
191 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
192 * Accordingly, this interface is responsible for hiding the transport
193 * differences so upper layer code can largely ignore them.
194 *
195 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
196 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
197 * a choice made at board design time (by only using the SWD pins), or
198 * as part of setting up a debug session (if all the dual-role JTAG/SWD
199 * signals are available).
200 */
201 struct adiv5_dap {
202 const struct dap_ops *ops;
203
204 struct jtag_tap *tap;
205 /* Control config */
206 uint32_t dp_ctrl_stat;
207
208 struct adiv5_ap ap[256];
209
210 /* The current manually selected AP by the "dap apsel" command */
211 uint32_t apsel;
212
213 /**
214 * Cache for DP_SELECT bits identifying the current AP. A DAP may
215 * connect to multiple APs, such as one MEM-AP for general access,
216 * another reserved for accessing debug modules, and a JTAG-DP.
217 * "-1" indicates no cached value.
218 */
219 uint32_t ap_current;
220
221 /**
222 * Cache for DP_SELECT bits identifying the current four-word AP
223 * register bank. This caches AP register addresss bits 7:4; JTAG
224 * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
225 * "-1" indicates no cached value.
226 */
227 uint32_t ap_bank_value;
228
229 /**
230 * Cache for DP_SELECT bits identifying the current four-word DP
231 * register bank. This caches DP register addresss bits 7:4; JTAG
232 * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
233 */
234 uint32_t dp_bank_value;
235
236 /* information about current pending SWjDP-AHBAP transaction */
237 uint8_t ack;
238
239 /**
240 * Holds the pointer to the destination word for the last queued read,
241 * for use with posted AP read sequence optimization.
242 */
243 uint32_t *last_read;
244
245 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
246 * despite lack of support in the ARMv7 architecture. Memory access through
247 * the AHB-AP has strange byte ordering these processors, and we need to
248 * swizzle appropriately. */
249 bool ti_be_32_quirks;
250
251 /**
252 * Signals that an attempt to reestablish communication afresh
253 * should be performed before the next access.
254 */
255 bool do_reconnect;
256 };
257
258 /**
259 * Transport-neutral representation of queued DAP transactions, supporting
260 * both JTAG and SWD transports. All submitted transactions are logically
261 * queued, until the queue is executed by run(). Some implementations might
262 * execute transactions as soon as they're submitted, but no status is made
263 * available until run().
264 */
265 struct dap_ops {
266 /** DP register read. */
267 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
268 uint32_t *data);
269 /** DP register write. */
270 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
271 uint32_t data);
272
273 /** AP register read. */
274 int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
275 uint32_t *data);
276 /** AP register write. */
277 int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
278 uint32_t data);
279
280 /** AP operation abort. */
281 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
282
283 /** Executes all queued DAP operations. */
284 int (*run)(struct adiv5_dap *dap);
285 };
286
287 /*
288 * Access Port classes
289 */
290 enum ap_class {
291 AP_CLASS_NONE = 0x00000, /* No class defined */
292 AP_CLASS_MEM_AP = 0x10000, /* MEM-AP */
293 };
294
295 /*
296 * Access Port types
297 */
298 enum ap_type {
299 AP_TYPE_JTAG_AP = 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
300 AP_TYPE_AHB_AP = 0x1, /* AHB Memory-AP */
301 AP_TYPE_APB_AP = 0x2, /* APB Memory-AP */
302 AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
303 };
304
305 /* AP selection applies to future AP transactions */
306 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
307
308 /**
309 * Queue a DP register read.
310 * Note that not all DP registers are readable; also, that JTAG and SWD
311 * have slight differences in DP register support.
312 *
313 * @param dap The DAP used for reading.
314 * @param reg The two-bit number of the DP register being read.
315 * @param data Pointer saying where to store the register's value
316 * (in host endianness).
317 *
318 * @return ERROR_OK for success, else a fault code.
319 */
320 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
321 unsigned reg, uint32_t *data)
322 {
323 assert(dap->ops != NULL);
324 return dap->ops->queue_dp_read(dap, reg, data);
325 }
326
327 /**
328 * Queue a DP register write.
329 * Note that not all DP registers are writable; also, that JTAG and SWD
330 * have slight differences in DP register support.
331 *
332 * @param dap The DAP used for writing.
333 * @param reg The two-bit number of the DP register being written.
334 * @param data Value being written (host endianness)
335 *
336 * @return ERROR_OK for success, else a fault code.
337 */
338 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
339 unsigned reg, uint32_t data)
340 {
341 assert(dap->ops != NULL);
342 return dap->ops->queue_dp_write(dap, reg, data);
343 }
344
345 /**
346 * Queue an AP register read.
347 *
348 * @param ap The AP used for reading.
349 * @param reg The number of the AP register being read.
350 * @param data Pointer saying where to store the register's value
351 * (in host endianness).
352 *
353 * @return ERROR_OK for success, else a fault code.
354 */
355 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
356 unsigned reg, uint32_t *data)
357 {
358 assert(ap->dap->ops != NULL);
359 dap_ap_select(ap->dap, ap->ap_num);
360 return ap->dap->ops->queue_ap_read(ap->dap, reg, data);
361 }
362
363 /**
364 * Queue an AP register write.
365 *
366 * @param ap The AP used for writing.
367 * @param reg The number of the AP register being written.
368 * @param data Value being written (host endianness)
369 *
370 * @return ERROR_OK for success, else a fault code.
371 */
372 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
373 unsigned reg, uint32_t data)
374 {
375 assert(ap->dap->ops != NULL);
376 dap_ap_select(ap->dap, ap->ap_num);
377 return ap->dap->ops->queue_ap_write(ap->dap, reg, data);
378 }
379
380 /**
381 * Queue an AP abort operation. The current AP transaction is aborted,
382 * including any update of the transaction counter. The AP is left in
383 * an unknown state (so it must be re-initialized). For use only after
384 * the AP has reported WAIT status for an extended period.
385 *
386 * @param dap The DAP used for writing.
387 * @param ack Pointer to where transaction status will be stored.
388 *
389 * @return ERROR_OK for success, else a fault code.
390 */
391 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
392 {
393 assert(dap->ops != NULL);
394 return dap->ops->queue_ap_abort(dap, ack);
395 }
396
397 /**
398 * Perform all queued DAP operations, and clear any errors posted in the
399 * CTRL_STAT register when they are done. Note that if more than one AP
400 * operation will be queued, one of the first operations in the queue
401 * should probably enable CORUNDETECT in the CTRL/STAT register.
402 *
403 * @param dap The DAP used.
404 *
405 * @return ERROR_OK for success, else a fault code.
406 */
407 static inline int dap_run(struct adiv5_dap *dap)
408 {
409 assert(dap->ops != NULL);
410 return dap->ops->run(dap);
411 }
412
413 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
414 uint32_t *value)
415 {
416 int retval;
417
418 retval = dap_queue_dp_read(dap, reg, value);
419 if (retval != ERROR_OK)
420 return retval;
421
422 return dap_run(dap);
423 }
424
425 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
426 uint32_t mask, uint32_t value, int timeout)
427 {
428 assert(timeout > 0);
429 assert((value & mask) == value);
430
431 int ret;
432 uint32_t regval;
433 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
434 reg, mask, value);
435 do {
436 ret = dap_dp_read_atomic(dap, reg, &regval);
437 if (ret != ERROR_OK)
438 return ret;
439
440 if ((regval & mask) == value)
441 break;
442
443 alive_sleep(10);
444 } while (--timeout);
445
446 if (!timeout) {
447 LOG_DEBUG("DAP: poll %x timeout", reg);
448 return ERROR_WAIT;
449 } else {
450 return ERROR_OK;
451 }
452 }
453
454 /** Accessor for currently selected DAP-AP number (0..255) */
455 static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
456 {
457 return (uint8_t)(swjdp->ap_current >> 24);
458 }
459
460 /* Queued MEM-AP memory mapped single word transfers. */
461 int mem_ap_read_u32(struct adiv5_ap *ap,
462 uint32_t address, uint32_t *value);
463 int mem_ap_write_u32(struct adiv5_ap *ap,
464 uint32_t address, uint32_t value);
465
466 /* Synchronous MEM-AP memory mapped single word transfers. */
467 int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
468 uint32_t address, uint32_t *value);
469 int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
470 uint32_t address, uint32_t value);
471
472 /* Synchronous MEM-AP memory mapped bus block transfers. */
473 int mem_ap_read_buf(struct adiv5_ap *ap,
474 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
475 int mem_ap_write_buf(struct adiv5_ap *ap,
476 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
477
478 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
479 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
480 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
481 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
482 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
483
484 /* Create DAP struct */
485 struct adiv5_dap *dap_init(void);
486
487 /* Initialisation of the debug system, power domains and registers */
488 int dap_dp_init(struct adiv5_dap *dap);
489 int mem_ap_init(struct adiv5_ap *ap);
490
491 /* Probe the AP for ROM Table location */
492 int dap_get_debugbase(struct adiv5_ap *ap,
493 uint32_t *dbgbase, uint32_t *apid);
494
495 /* Probe Access Ports to find a particular type */
496 int dap_find_ap(struct adiv5_dap *dap,
497 enum ap_type type_to_find,
498 struct adiv5_ap **ap_out);
499
500 static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num)
501 {
502 return &dap->ap[ap_num];
503 }
504
505 /* Lookup CoreSight component */
506 int dap_lookup_cs_component(struct adiv5_ap *ap,
507 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
508
509 struct target;
510
511 /* Put debug link into SWD mode */
512 int dap_to_swd(struct target *target);
513
514 /* Put debug link into JTAG mode */
515 int dap_to_jtag(struct target *target);
516
517 extern const struct command_registration dap_command_handlers[];
518
519 #endif