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arm_adi_v5: dap_partnums - correction of partnumbers, new added
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
31
32 /**
33 * @file
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
39 *
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
48 *
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 */
60
61 /*
62 * Relevant specifications from ARM include:
63 *
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
66 *
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
69 */
70
71 #ifdef HAVE_CONFIG_H
72 #include "config.h"
73 #endif
74
75 #include "jtag/interface.h"
76 #include "arm.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
79 #include <helper/list.h>
80
81 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
82
83 /*
84 uint32_t tar_block_size(uint32_t address)
85 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 */
87 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 {
89 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
90 }
91
92 /***************************************************************************
93 * *
94 * DP and MEM-AP register access through APACC and DPACC *
95 * *
96 ***************************************************************************/
97
98 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 {
100 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
101 ap->csw_default;
102
103 if (csw != ap->csw_value) {
104 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
105 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
106 if (retval != ERROR_OK)
107 return retval;
108 ap->csw_value = csw;
109 }
110 return ERROR_OK;
111 }
112
113 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
114 {
115 if (tar != ap->tar_value ||
116 (ap->csw_value & CSW_ADDRINC_MASK)) {
117 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
118 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
119 if (retval != ERROR_OK)
120 return retval;
121 ap->tar_value = tar;
122 }
123 return ERROR_OK;
124 }
125
126 /**
127 * Queue transactions setting up transfer parameters for the
128 * currently selected MEM-AP.
129 *
130 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
131 * initiate data reads or writes using memory or peripheral addresses.
132 * If the CSW is configured for it, the TAR may be automatically
133 * incremented after each transfer.
134 *
135 * @param ap The MEM-AP.
136 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
137 * matches the cached value, the register is not changed.
138 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
139 * matches the cached address, the register is not changed.
140 *
141 * @return ERROR_OK if the transaction was properly queued, else a fault code.
142 */
143 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
144 {
145 int retval;
146 retval = mem_ap_setup_csw(ap, csw);
147 if (retval != ERROR_OK)
148 return retval;
149 retval = mem_ap_setup_tar(ap, tar);
150 if (retval != ERROR_OK)
151 return retval;
152 return ERROR_OK;
153 }
154
155 /**
156 * Asynchronous (queued) read of a word from memory or a system register.
157 *
158 * @param ap The MEM-AP to access.
159 * @param address Address of the 32-bit word to read; it must be
160 * readable by the currently selected MEM-AP.
161 * @param value points to where the word will be stored when the
162 * transaction queue is flushed (assuming no errors).
163 *
164 * @return ERROR_OK for success. Otherwise a fault code.
165 */
166 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
167 uint32_t *value)
168 {
169 int retval;
170
171 /* Use banked addressing (REG_BDx) to avoid some link traffic
172 * (updating TAR) when reading several consecutive addresses.
173 */
174 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
175 address & 0xFFFFFFF0);
176 if (retval != ERROR_OK)
177 return retval;
178
179 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
180 }
181
182 /**
183 * Synchronous read of a word from memory or a system register.
184 * As a side effect, this flushes any queued transactions.
185 *
186 * @param ap The MEM-AP to access.
187 * @param address Address of the 32-bit word to read; it must be
188 * readable by the currently selected MEM-AP.
189 * @param value points to where the result will be stored.
190 *
191 * @return ERROR_OK for success; *value holds the result.
192 * Otherwise a fault code.
193 */
194 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
195 uint32_t *value)
196 {
197 int retval;
198
199 retval = mem_ap_read_u32(ap, address, value);
200 if (retval != ERROR_OK)
201 return retval;
202
203 return dap_run(ap->dap);
204 }
205
206 /**
207 * Asynchronous (queued) write of a word to memory or a system register.
208 *
209 * @param ap The MEM-AP to access.
210 * @param address Address to be written; it must be writable by
211 * the currently selected MEM-AP.
212 * @param value Word that will be written to the address when transaction
213 * queue is flushed (assuming no errors).
214 *
215 * @return ERROR_OK for success. Otherwise a fault code.
216 */
217 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
218 uint32_t value)
219 {
220 int retval;
221
222 /* Use banked addressing (REG_BDx) to avoid some link traffic
223 * (updating TAR) when writing several consecutive addresses.
224 */
225 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
226 address & 0xFFFFFFF0);
227 if (retval != ERROR_OK)
228 return retval;
229
230 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
231 value);
232 }
233
234 /**
235 * Synchronous write of a word to memory or a system register.
236 * As a side effect, this flushes any queued transactions.
237 *
238 * @param ap The MEM-AP to access.
239 * @param address Address to be written; it must be writable by
240 * the currently selected MEM-AP.
241 * @param value Word that will be written.
242 *
243 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
244 */
245 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
246 uint32_t value)
247 {
248 int retval = mem_ap_write_u32(ap, address, value);
249
250 if (retval != ERROR_OK)
251 return retval;
252
253 return dap_run(ap->dap);
254 }
255
256 /**
257 * Synchronous write of a block of memory, using a specific access size.
258 *
259 * @param ap The MEM-AP to access.
260 * @param buffer The data buffer to write. No particular alignment is assumed.
261 * @param size Which access size to use, in bytes. 1, 2 or 4.
262 * @param count The number of writes to do (in size units, not bytes).
263 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
264 * @param addrinc Whether the target address should be increased for each write or not. This
265 * should normally be true, except when writing to e.g. a FIFO.
266 * @return ERROR_OK on success, otherwise an error code.
267 */
268 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
269 uint32_t address, bool addrinc)
270 {
271 struct adiv5_dap *dap = ap->dap;
272 size_t nbytes = size * count;
273 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
274 uint32_t csw_size;
275 uint32_t addr_xor;
276 int retval;
277
278 /* TI BE-32 Quirks mode:
279 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
280 * size write address bytes written in order
281 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
282 * 2 TAR ^ 2 (val >> 8), (val)
283 * 1 TAR ^ 3 (val)
284 * For example, if you attempt to write a single byte to address 0, the processor
285 * will actually write a byte to address 3.
286 *
287 * To make writes of size < 4 work as expected, we xor a value with the address before
288 * setting the TAP, and we set the TAP after every transfer rather then relying on
289 * address increment. */
290
291 if (size == 4) {
292 csw_size = CSW_32BIT;
293 addr_xor = 0;
294 } else if (size == 2) {
295 csw_size = CSW_16BIT;
296 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
297 } else if (size == 1) {
298 csw_size = CSW_8BIT;
299 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
300 } else {
301 return ERROR_TARGET_UNALIGNED_ACCESS;
302 }
303
304 if (ap->unaligned_access_bad && (address % size != 0))
305 return ERROR_TARGET_UNALIGNED_ACCESS;
306
307 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
308 if (retval != ERROR_OK)
309 return retval;
310
311 while (nbytes > 0) {
312 uint32_t this_size = size;
313
314 /* Select packed transfer if possible */
315 if (addrinc && ap->packed_transfers && nbytes >= 4
316 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
317 this_size = 4;
318 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
319 } else {
320 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
321 }
322
323 if (retval != ERROR_OK)
324 break;
325
326 /* How many source bytes each transfer will consume, and their location in the DRW,
327 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
328 uint32_t outvalue = 0;
329 if (dap->ti_be_32_quirks) {
330 switch (this_size) {
331 case 4:
332 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
333 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
334 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
335 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
336 break;
337 case 2:
338 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
339 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
340 break;
341 case 1:
342 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
343 break;
344 }
345 } else {
346 switch (this_size) {
347 case 4:
348 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
349 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
350 case 2:
351 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
352 case 1:
353 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
354 }
355 }
356
357 nbytes -= this_size;
358
359 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
360 if (retval != ERROR_OK)
361 break;
362
363 /* Rewrite TAR if it wrapped or we're xoring addresses */
364 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
365 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
366 if (retval != ERROR_OK)
367 break;
368 }
369 }
370
371 /* REVISIT: Might want to have a queued version of this function that does not run. */
372 if (retval == ERROR_OK)
373 retval = dap_run(dap);
374
375 if (retval != ERROR_OK) {
376 uint32_t tar;
377 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
378 && dap_run(dap) == ERROR_OK)
379 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
380 else
381 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
382 }
383
384 return retval;
385 }
386
387 /**
388 * Synchronous read of a block of memory, using a specific access size.
389 *
390 * @param ap The MEM-AP to access.
391 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
392 * @param size Which access size to use, in bytes. 1, 2 or 4.
393 * @param count The number of reads to do (in size units, not bytes).
394 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
395 * @param addrinc Whether the target address should be increased after each read or not. This
396 * should normally be true, except when reading from e.g. a FIFO.
397 * @return ERROR_OK on success, otherwise an error code.
398 */
399 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
400 uint32_t adr, bool addrinc)
401 {
402 struct adiv5_dap *dap = ap->dap;
403 size_t nbytes = size * count;
404 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
405 uint32_t csw_size;
406 uint32_t address = adr;
407 int retval;
408
409 /* TI BE-32 Quirks mode:
410 * Reads on big-endian TMS570 behave strangely differently than writes.
411 * They read from the physical address requested, but with DRW byte-reversed.
412 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
413 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
414 * so avoid them. */
415
416 if (size == 4)
417 csw_size = CSW_32BIT;
418 else if (size == 2)
419 csw_size = CSW_16BIT;
420 else if (size == 1)
421 csw_size = CSW_8BIT;
422 else
423 return ERROR_TARGET_UNALIGNED_ACCESS;
424
425 if (ap->unaligned_access_bad && (adr % size != 0))
426 return ERROR_TARGET_UNALIGNED_ACCESS;
427
428 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
429 * over-allocation if packed transfers are going to be used, but determining the real need at
430 * this point would be messy. */
431 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
432 uint32_t *read_ptr = read_buf;
433 if (read_buf == NULL) {
434 LOG_ERROR("Failed to allocate read buffer");
435 return ERROR_FAIL;
436 }
437
438 retval = mem_ap_setup_tar(ap, address);
439 if (retval != ERROR_OK) {
440 free(read_buf);
441 return retval;
442 }
443
444 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
445 * useful bytes it contains, and their location in the word, depends on the type of transfer
446 * and alignment. */
447 while (nbytes > 0) {
448 uint32_t this_size = size;
449
450 /* Select packed transfer if possible */
451 if (addrinc && ap->packed_transfers && nbytes >= 4
452 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
453 this_size = 4;
454 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
455 } else {
456 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
457 }
458 if (retval != ERROR_OK)
459 break;
460
461 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
462 if (retval != ERROR_OK)
463 break;
464
465 nbytes -= this_size;
466 address += this_size;
467
468 /* Rewrite TAR if it wrapped */
469 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
470 retval = mem_ap_setup_tar(ap, address);
471 if (retval != ERROR_OK)
472 break;
473 }
474 }
475
476 if (retval == ERROR_OK)
477 retval = dap_run(dap);
478
479 /* Restore state */
480 address = adr;
481 nbytes = size * count;
482 read_ptr = read_buf;
483
484 /* If something failed, read TAR to find out how much data was successfully read, so we can
485 * at least give the caller what we have. */
486 if (retval != ERROR_OK) {
487 uint32_t tar;
488 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
489 && dap_run(dap) == ERROR_OK) {
490 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
491 if (nbytes > tar - address)
492 nbytes = tar - address;
493 } else {
494 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
495 nbytes = 0;
496 }
497 }
498
499 /* Replay loop to populate caller's buffer from the correct word and byte lane */
500 while (nbytes > 0) {
501 uint32_t this_size = size;
502
503 if (addrinc && ap->packed_transfers && nbytes >= 4
504 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
505 this_size = 4;
506 }
507
508 if (dap->ti_be_32_quirks) {
509 switch (this_size) {
510 case 4:
511 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
512 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
513 case 2:
514 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
515 case 1:
516 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
517 }
518 } else {
519 switch (this_size) {
520 case 4:
521 *buffer++ = *read_ptr >> 8 * (address++ & 3);
522 *buffer++ = *read_ptr >> 8 * (address++ & 3);
523 case 2:
524 *buffer++ = *read_ptr >> 8 * (address++ & 3);
525 case 1:
526 *buffer++ = *read_ptr >> 8 * (address++ & 3);
527 }
528 }
529
530 read_ptr++;
531 nbytes -= this_size;
532 }
533
534 free(read_buf);
535 return retval;
536 }
537
538 int mem_ap_read_buf(struct adiv5_ap *ap,
539 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
540 {
541 return mem_ap_read(ap, buffer, size, count, address, true);
542 }
543
544 int mem_ap_write_buf(struct adiv5_ap *ap,
545 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
546 {
547 return mem_ap_write(ap, buffer, size, count, address, true);
548 }
549
550 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
551 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
552 {
553 return mem_ap_read(ap, buffer, size, count, address, false);
554 }
555
556 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
557 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
558 {
559 return mem_ap_write(ap, buffer, size, count, address, false);
560 }
561
562 /*--------------------------------------------------------------------------*/
563
564
565 #define DAP_POWER_DOMAIN_TIMEOUT (10)
566
567 /* FIXME don't import ... just initialize as
568 * part of DAP transport setup
569 */
570 extern const struct dap_ops jtag_dp_ops;
571
572 /*--------------------------------------------------------------------------*/
573
574 /**
575 * Create a new DAP
576 */
577 struct adiv5_dap *dap_init(void)
578 {
579 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
580 int i;
581 /* Set up with safe defaults */
582 for (i = 0; i <= 255; i++) {
583 dap->ap[i].dap = dap;
584 dap->ap[i].ap_num = i;
585 /* memaccess_tck max is 255 */
586 dap->ap[i].memaccess_tck = 255;
587 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
588 dap->ap[i].tar_autoincr_block = (1<<10);
589 }
590 INIT_LIST_HEAD(&dap->cmd_journal);
591 return dap;
592 }
593
594 /**
595 * Initialize a DAP. This sets up the power domains, prepares the DP
596 * for further use and activates overrun checking.
597 *
598 * @param dap The DAP being initialized.
599 */
600 int dap_dp_init(struct adiv5_dap *dap)
601 {
602 int retval;
603
604 LOG_DEBUG(" ");
605 /* JTAG-DP or SWJ-DP, in JTAG mode
606 * ... for SWD mode this is patched as part
607 * of link switchover
608 * FIXME: This should already be setup by the respective transport specific DAP creation.
609 */
610 if (!dap->ops)
611 dap->ops = &jtag_dp_ops;
612
613 dap->select = DP_SELECT_INVALID;
614 dap->last_read = NULL;
615
616 for (size_t i = 0; i < 10; i++) {
617 /* DP initialization */
618
619 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
620 if (retval != ERROR_OK)
621 continue;
622
623 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
624 if (retval != ERROR_OK)
625 continue;
626
627 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
628 if (retval != ERROR_OK)
629 continue;
630
631 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
632 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
633 if (retval != ERROR_OK)
634 continue;
635
636 /* Check that we have debug power domains activated */
637 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
638 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
639 CDBGPWRUPACK, CDBGPWRUPACK,
640 DAP_POWER_DOMAIN_TIMEOUT);
641 if (retval != ERROR_OK)
642 continue;
643
644 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
645 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
646 CSYSPWRUPACK, CSYSPWRUPACK,
647 DAP_POWER_DOMAIN_TIMEOUT);
648 if (retval != ERROR_OK)
649 continue;
650
651 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
652 if (retval != ERROR_OK)
653 continue;
654
655 /* With debug power on we can activate OVERRUN checking */
656 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
657 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
658 if (retval != ERROR_OK)
659 continue;
660 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
661 if (retval != ERROR_OK)
662 continue;
663
664 retval = dap_run(dap);
665 if (retval != ERROR_OK)
666 continue;
667
668 break;
669 }
670
671 return retval;
672 }
673
674 /**
675 * Initialize a DAP. This sets up the power domains, prepares the DP
676 * for further use, and arranges to use AP #0 for all AP operations
677 * until dap_ap-select() changes that policy.
678 *
679 * @param ap The MEM-AP being initialized.
680 */
681 int mem_ap_init(struct adiv5_ap *ap)
682 {
683 /* check that we support packed transfers */
684 uint32_t csw, cfg;
685 int retval;
686 struct adiv5_dap *dap = ap->dap;
687
688 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
689 if (retval != ERROR_OK)
690 return retval;
691
692 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
693 if (retval != ERROR_OK)
694 return retval;
695
696 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
697 if (retval != ERROR_OK)
698 return retval;
699
700 retval = dap_run(dap);
701 if (retval != ERROR_OK)
702 return retval;
703
704 if (csw & CSW_ADDRINC_PACKED)
705 ap->packed_transfers = true;
706 else
707 ap->packed_transfers = false;
708
709 /* Packed transfers on TI BE-32 processors do not work correctly in
710 * many cases. */
711 if (dap->ti_be_32_quirks)
712 ap->packed_transfers = false;
713
714 LOG_DEBUG("MEM_AP Packed Transfers: %s",
715 ap->packed_transfers ? "enabled" : "disabled");
716
717 /* The ARM ADI spec leaves implementation-defined whether unaligned
718 * memory accesses work, only work partially, or cause a sticky error.
719 * On TI BE-32 processors, reads seem to return garbage in some bytes
720 * and unaligned writes seem to cause a sticky error.
721 * TODO: it would be nice to have a way to detect whether unaligned
722 * operations are supported on other processors. */
723 ap->unaligned_access_bad = dap->ti_be_32_quirks;
724
725 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
726 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
727
728 return ERROR_OK;
729 }
730
731 /* CID interpretation -- see ARM IHI 0029B section 3
732 * and ARM IHI 0031A table 13-3.
733 */
734 static const char *class_description[16] = {
735 "Reserved", "ROM table", "Reserved", "Reserved",
736 "Reserved", "Reserved", "Reserved", "Reserved",
737 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
738 "Reserved", "OptimoDE DESS",
739 "Generic IP component", "PrimeCell or System component"
740 };
741
742 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
743 {
744 return cid3 == 0xb1 && cid2 == 0x05
745 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
746 }
747
748 /*
749 * This function checks the ID for each access port to find the requested Access Port type
750 */
751 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
752 {
753 int ap_num;
754
755 /* Maximum AP number is 255 since the SELECT register is 8 bits */
756 for (ap_num = 0; ap_num <= 255; ap_num++) {
757
758 /* read the IDR register of the Access Port */
759 uint32_t id_val = 0;
760
761 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
762 if (retval != ERROR_OK)
763 return retval;
764
765 retval = dap_run(dap);
766
767 /* IDR bits:
768 * 31-28 : Revision
769 * 27-24 : JEDEC bank (0x4 for ARM)
770 * 23-17 : JEDEC code (0x3B for ARM)
771 * 16-13 : Class (0b1000=Mem-AP)
772 * 12-8 : Reserved
773 * 7-4 : AP Variant (non-zero for JTAG-AP)
774 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
775 */
776
777 /* Reading register for a non-existant AP should not cause an error,
778 * but just to be sure, try to continue searching if an error does happen.
779 */
780 if ((retval == ERROR_OK) && /* Register read success */
781 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
782 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
783
784 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
785 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
786 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
787 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
788 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
789 ap_num, id_val);
790
791 *ap_out = &dap->ap[ap_num];
792 return ERROR_OK;
793 }
794 }
795
796 LOG_DEBUG("No %s found",
797 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
798 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
799 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
800 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
801 return ERROR_FAIL;
802 }
803
804 int dap_get_debugbase(struct adiv5_ap *ap,
805 uint32_t *dbgbase, uint32_t *apid)
806 {
807 struct adiv5_dap *dap = ap->dap;
808 int retval;
809
810 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
811 if (retval != ERROR_OK)
812 return retval;
813 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
814 if (retval != ERROR_OK)
815 return retval;
816 retval = dap_run(dap);
817 if (retval != ERROR_OK)
818 return retval;
819
820 return ERROR_OK;
821 }
822
823 int dap_lookup_cs_component(struct adiv5_ap *ap,
824 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
825 {
826 uint32_t romentry, entry_offset = 0, component_base, devtype;
827 int retval;
828
829 *addr = 0;
830
831 do {
832 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
833 entry_offset, &romentry);
834 if (retval != ERROR_OK)
835 return retval;
836
837 component_base = (dbgbase & 0xFFFFF000)
838 + (romentry & 0xFFFFF000);
839
840 if (romentry & 0x1) {
841 uint32_t c_cid1;
842 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
843 if (retval != ERROR_OK) {
844 LOG_ERROR("Can't read component with base address 0x%" PRIx32
845 ", the corresponding core might be turned off", component_base);
846 return retval;
847 }
848 if (((c_cid1 >> 4) & 0x0f) == 1) {
849 retval = dap_lookup_cs_component(ap, component_base,
850 type, addr, idx);
851 if (retval == ERROR_OK)
852 break;
853 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
854 return retval;
855 }
856
857 retval = mem_ap_read_atomic_u32(ap,
858 (component_base & 0xfffff000) | 0xfcc,
859 &devtype);
860 if (retval != ERROR_OK)
861 return retval;
862 if ((devtype & 0xff) == type) {
863 if (!*idx) {
864 *addr = component_base;
865 break;
866 } else
867 (*idx)--;
868 }
869 }
870 entry_offset += 4;
871 } while (romentry > 0);
872
873 if (!*addr)
874 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
875
876 return ERROR_OK;
877 }
878
879 /* The designer identity code is encoded as:
880 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
881 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
882 * a legacy ASCII Identity Code.
883 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
884 * JEP106 is a standard available from jedec.org
885 */
886
887 /* Part number interpretations are from Cortex
888 * core specs, the CoreSight components TRM
889 * (ARM DDI 0314H), CoreSight System Design
890 * Guide (ARM DGI 0012D) and ETM specs; also
891 * from chip observation (e.g. TI SDTI).
892 */
893
894 /* The legacy code only used the part number field to identify CoreSight peripherals.
895 * This meant that the same part number from two different manufacturers looked the same.
896 * It is desirable for all future additions to identify with both part number and JEP106.
897 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
898 */
899
900 #define ANY_ID 0x1000
901
902 #define ARM_ID 0x4BB
903
904 static const struct {
905 uint16_t designer_id;
906 uint16_t part_num;
907 const char *type;
908 const char *full;
909 } dap_partnums[] = {
910 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
911 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
912 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
913 { ARM_ID, 0x003, "Cortex-M3 FBP", "(Flash Patch and Breakpoint)", },
914 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
915 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
916 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
917 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
918 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
919 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
920 { ARM_ID, 0x4c7, "Cortex-M7 PPB", "(Private Peripheral Bus ROM Table)", },
921 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
922 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
923 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
924 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
925 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
926 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
927 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
928 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
929 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
930 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
931 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
932 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
933 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
934 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
935 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
936 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
937 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
938 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
939 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
940 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
941 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
942 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
943 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
944 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
945 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
946 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
947 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
948 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
949 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
950 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
951 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
952 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
953 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
954 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitoring Unit)", },
955 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
956 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
957 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
958 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
959 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
960 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
961 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
962 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
963 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
964 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
965 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
966 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
967 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
968 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
969 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
970 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
971 /* legacy comment: 0x113: what? */
972 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
973 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
974 };
975
976 static int dap_rom_display(struct command_context *cmd_ctx,
977 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
978 {
979 struct adiv5_dap *dap = ap->dap;
980 int retval;
981 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
982 uint16_t entry_offset;
983 char tabs[7] = "";
984
985 if (depth > 16) {
986 command_print(cmd_ctx, "\tTables too deep");
987 return ERROR_FAIL;
988 }
989
990 if (depth)
991 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
992
993 /* bit 16 of apid indicates a memory access port */
994 if (dbgbase & 0x02)
995 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
996 else
997 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
998
999 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1000 retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1001 if (retval != ERROR_OK)
1002 return retval;
1003 retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1004 if (retval != ERROR_OK)
1005 return retval;
1006 retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1007 if (retval != ERROR_OK)
1008 return retval;
1009 retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1010 if (retval != ERROR_OK)
1011 return retval;
1012 retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1013 if (retval != ERROR_OK)
1014 return retval;
1015 retval = dap_run(dap);
1016 if (retval != ERROR_OK)
1017 return retval;
1018
1019 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1020 command_print(cmd_ctx, "\t%sCID3 0x%02x"
1021 ", CID2 0x%02x"
1022 ", CID1 0x%02x"
1023 ", CID0 0x%02x",
1024 tabs,
1025 (unsigned)cid3, (unsigned)cid2,
1026 (unsigned)cid1, (unsigned)cid0);
1027 if (memtype & 0x01)
1028 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1029 else
1030 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1031
1032 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1033 for (entry_offset = 0; ; entry_offset += 4) {
1034 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1035 if (retval != ERROR_OK)
1036 return retval;
1037 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1038 tabs, entry_offset, romentry);
1039 if (romentry & 0x01) {
1040 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1041 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1042 uint32_t component_base;
1043 uint16_t part_num, designer_id;
1044 const char *type, *full;
1045
1046 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1047
1048 /* IDs are in last 4K section */
1049 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
1050 if (retval != ERROR_OK) {
1051 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1052 ", the corresponding core might be turned off", tabs, component_base);
1053 continue;
1054 }
1055 c_pid0 &= 0xff;
1056 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
1057 if (retval != ERROR_OK)
1058 return retval;
1059 c_pid1 &= 0xff;
1060 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
1061 if (retval != ERROR_OK)
1062 return retval;
1063 c_pid2 &= 0xff;
1064 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
1065 if (retval != ERROR_OK)
1066 return retval;
1067 c_pid3 &= 0xff;
1068 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
1069 if (retval != ERROR_OK)
1070 return retval;
1071 c_pid4 &= 0xff;
1072
1073 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
1074 if (retval != ERROR_OK)
1075 return retval;
1076 c_cid0 &= 0xff;
1077 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
1078 if (retval != ERROR_OK)
1079 return retval;
1080 c_cid1 &= 0xff;
1081 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
1082 if (retval != ERROR_OK)
1083 return retval;
1084 c_cid2 &= 0xff;
1085 retval = mem_ap_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
1086 if (retval != ERROR_OK)
1087 return retval;
1088 c_cid3 &= 0xff;
1089
1090 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1091 "start address 0x%" PRIx32, component_base,
1092 /* component may take multiple 4K pages */
1093 (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1094 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1095 (uint8_t)((c_cid1 >> 4) & 0xf),
1096 /* See ARM IHI 0029B Table 3-3 */
1097 class_description[(c_cid1 >> 4) & 0xf]);
1098
1099 /* CoreSight component? */
1100 if (((c_cid1 >> 4) & 0x0f) == 9) {
1101 uint32_t devtype;
1102 unsigned minor;
1103 const char *major = "Reserved", *subtype = "Reserved";
1104
1105 retval = mem_ap_read_atomic_u32(ap,
1106 (component_base & 0xfffff000) | 0xfcc,
1107 &devtype);
1108 if (retval != ERROR_OK)
1109 return retval;
1110 minor = (devtype >> 4) & 0x0f;
1111 switch (devtype & 0x0f) {
1112 case 0:
1113 major = "Miscellaneous";
1114 switch (minor) {
1115 case 0:
1116 subtype = "other";
1117 break;
1118 case 4:
1119 subtype = "Validation component";
1120 break;
1121 }
1122 break;
1123 case 1:
1124 major = "Trace Sink";
1125 switch (minor) {
1126 case 0:
1127 subtype = "other";
1128 break;
1129 case 1:
1130 subtype = "Port";
1131 break;
1132 case 2:
1133 subtype = "Buffer";
1134 break;
1135 case 3:
1136 subtype = "Router";
1137 break;
1138 }
1139 break;
1140 case 2:
1141 major = "Trace Link";
1142 switch (minor) {
1143 case 0:
1144 subtype = "other";
1145 break;
1146 case 1:
1147 subtype = "Funnel, router";
1148 break;
1149 case 2:
1150 subtype = "Filter";
1151 break;
1152 case 3:
1153 subtype = "FIFO, buffer";
1154 break;
1155 }
1156 break;
1157 case 3:
1158 major = "Trace Source";
1159 switch (minor) {
1160 case 0:
1161 subtype = "other";
1162 break;
1163 case 1:
1164 subtype = "Processor";
1165 break;
1166 case 2:
1167 subtype = "DSP";
1168 break;
1169 case 3:
1170 subtype = "Engine/Coprocessor";
1171 break;
1172 case 4:
1173 subtype = "Bus";
1174 break;
1175 case 6:
1176 subtype = "Software";
1177 break;
1178 }
1179 break;
1180 case 4:
1181 major = "Debug Control";
1182 switch (minor) {
1183 case 0:
1184 subtype = "other";
1185 break;
1186 case 1:
1187 subtype = "Trigger Matrix";
1188 break;
1189 case 2:
1190 subtype = "Debug Auth";
1191 break;
1192 case 3:
1193 subtype = "Power Requestor";
1194 break;
1195 }
1196 break;
1197 case 5:
1198 major = "Debug Logic";
1199 switch (minor) {
1200 case 0:
1201 subtype = "other";
1202 break;
1203 case 1:
1204 subtype = "Processor";
1205 break;
1206 case 2:
1207 subtype = "DSP";
1208 break;
1209 case 3:
1210 subtype = "Engine/Coprocessor";
1211 break;
1212 case 4:
1213 subtype = "Bus";
1214 break;
1215 case 5:
1216 subtype = "Memory";
1217 break;
1218 }
1219 break;
1220 case 6:
1221 major = "Perfomance Monitor";
1222 switch (minor) {
1223 case 0:
1224 subtype = "other";
1225 break;
1226 case 1:
1227 subtype = "Processor";
1228 break;
1229 case 2:
1230 subtype = "DSP";
1231 break;
1232 case 3:
1233 subtype = "Engine/Coprocessor";
1234 break;
1235 case 4:
1236 subtype = "Bus";
1237 break;
1238 case 5:
1239 subtype = "Memory";
1240 break;
1241 }
1242 break;
1243 }
1244 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1245 (uint8_t)(devtype & 0xff),
1246 major, subtype);
1247 /* REVISIT also show 0xfc8 DevId */
1248 }
1249
1250 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1251 command_print(cmd_ctx,
1252 "\t\tCID3 0%02x"
1253 ", CID2 0%02x"
1254 ", CID1 0%02x"
1255 ", CID0 0%02x",
1256 (int)c_cid3,
1257 (int)c_cid2,
1258 (int)c_cid1,
1259 (int)c_cid0);
1260 command_print(cmd_ctx,
1261 "\t\tPeripheral ID[4..0] = hex "
1262 "%02x %02x %02x %02x %02x",
1263 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1264 (int)c_pid1, (int)c_pid0);
1265
1266 part_num = (c_pid0 & 0xff);
1267 part_num |= (c_pid1 & 0x0f) << 8;
1268 designer_id = (c_pid1 & 0xf0) >> 4;
1269 designer_id |= (c_pid2 & 0x0f) << 4;
1270 designer_id |= (c_pid4 & 0x0f) << 8;
1271 if ((designer_id & 0x80) == 0) {
1272 /* Legacy ASCII ID, clear invalid bits */
1273 designer_id &= 0x7f;
1274 }
1275
1276 /* default values to be overwritten upon finding a match */
1277 type = NULL;
1278 full = "";
1279
1280 /* search dap_partnums[] array for a match */
1281 unsigned entry;
1282 for (entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1283
1284 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1285 continue;
1286
1287 if (dap_partnums[entry].part_num != part_num)
1288 continue;
1289
1290 type = dap_partnums[entry].type;
1291 full = dap_partnums[entry].full;
1292 break;
1293 }
1294
1295 if (type) {
1296 command_print(cmd_ctx, "\t\tPart is %s %s",
1297 type, full);
1298 } else {
1299 command_print(cmd_ctx, "\t\tUnrecognized (Part 0x%" PRIx16 ", designer 0x%" PRIx16 ")",
1300 part_num, designer_id);
1301 }
1302
1303 /* ROM Table? */
1304 if (((c_cid1 >> 4) & 0x0f) == 1) {
1305 retval = dap_rom_display(cmd_ctx, ap, component_base, depth + 1);
1306 if (retval != ERROR_OK)
1307 return retval;
1308 }
1309 } else {
1310 if (romentry)
1311 command_print(cmd_ctx, "\t\tComponent not present");
1312 else
1313 break;
1314 }
1315 }
1316 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1317 return ERROR_OK;
1318 }
1319
1320 static int dap_info_command(struct command_context *cmd_ctx,
1321 struct adiv5_ap *ap)
1322 {
1323 int retval;
1324 uint32_t dbgbase, apid;
1325 int romtable_present = 0;
1326 uint8_t mem_ap;
1327
1328 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1329 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1330 if (retval != ERROR_OK)
1331 return retval;
1332
1333 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1334 if (apid == 0) {
1335 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1336 return ERROR_FAIL;
1337 }
1338
1339 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1340 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1341 command_print(cmd_ctx, "\tType is JTAG-AP");
1342 break;
1343 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1344 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1345 break;
1346 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1347 command_print(cmd_ctx, "\tType is MEM-AP APB");
1348 break;
1349 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1350 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1351 break;
1352 default:
1353 command_print(cmd_ctx, "\tUnknown AP type");
1354 break;
1355 }
1356
1357 /* NOTE: a MEM-AP may have a single CoreSight component that's
1358 * not a ROM table ... or have no such components at all.
1359 */
1360 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1361 if (mem_ap) {
1362 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1363
1364 romtable_present = dbgbase != 0xFFFFFFFF;
1365 if (romtable_present)
1366 dap_rom_display(cmd_ctx, ap, dbgbase, 0);
1367 else
1368 command_print(cmd_ctx, "\tNo ROM table present");
1369 }
1370
1371 return ERROR_OK;
1372 }
1373
1374 COMMAND_HANDLER(handle_dap_info_command)
1375 {
1376 struct target *target = get_current_target(CMD_CTX);
1377 struct arm *arm = target_to_arm(target);
1378 struct adiv5_dap *dap = arm->dap;
1379 uint32_t apsel;
1380
1381 switch (CMD_ARGC) {
1382 case 0:
1383 apsel = dap->apsel;
1384 break;
1385 case 1:
1386 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1387 if (apsel >= 256)
1388 return ERROR_COMMAND_SYNTAX_ERROR;
1389 break;
1390 default:
1391 return ERROR_COMMAND_SYNTAX_ERROR;
1392 }
1393
1394 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1395 }
1396
1397 COMMAND_HANDLER(dap_baseaddr_command)
1398 {
1399 struct target *target = get_current_target(CMD_CTX);
1400 struct arm *arm = target_to_arm(target);
1401 struct adiv5_dap *dap = arm->dap;
1402
1403 uint32_t apsel, baseaddr;
1404 int retval;
1405
1406 switch (CMD_ARGC) {
1407 case 0:
1408 apsel = dap->apsel;
1409 break;
1410 case 1:
1411 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1412 /* AP address is in bits 31:24 of DP_SELECT */
1413 if (apsel >= 256)
1414 return ERROR_COMMAND_SYNTAX_ERROR;
1415 break;
1416 default:
1417 return ERROR_COMMAND_SYNTAX_ERROR;
1418 }
1419
1420 /* NOTE: assumes we're talking to a MEM-AP, which
1421 * has a base address. There are other kinds of AP,
1422 * though they're not common for now. This should
1423 * use the ID register to verify it's a MEM-AP.
1424 */
1425 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1426 if (retval != ERROR_OK)
1427 return retval;
1428 retval = dap_run(dap);
1429 if (retval != ERROR_OK)
1430 return retval;
1431
1432 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1433
1434 return retval;
1435 }
1436
1437 COMMAND_HANDLER(dap_memaccess_command)
1438 {
1439 struct target *target = get_current_target(CMD_CTX);
1440 struct arm *arm = target_to_arm(target);
1441 struct adiv5_dap *dap = arm->dap;
1442
1443 uint32_t memaccess_tck;
1444
1445 switch (CMD_ARGC) {
1446 case 0:
1447 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1448 break;
1449 case 1:
1450 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1451 break;
1452 default:
1453 return ERROR_COMMAND_SYNTAX_ERROR;
1454 }
1455 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1456
1457 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1458 dap->ap[dap->apsel].memaccess_tck);
1459
1460 return ERROR_OK;
1461 }
1462
1463 COMMAND_HANDLER(dap_apsel_command)
1464 {
1465 struct target *target = get_current_target(CMD_CTX);
1466 struct arm *arm = target_to_arm(target);
1467 struct adiv5_dap *dap = arm->dap;
1468
1469 uint32_t apsel, apid;
1470 int retval;
1471
1472 switch (CMD_ARGC) {
1473 case 0:
1474 apsel = dap->apsel;
1475 break;
1476 case 1:
1477 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1478 /* AP address is in bits 31:24 of DP_SELECT */
1479 if (apsel >= 256)
1480 return ERROR_COMMAND_SYNTAX_ERROR;
1481 break;
1482 default:
1483 return ERROR_COMMAND_SYNTAX_ERROR;
1484 }
1485
1486 dap->apsel = apsel;
1487
1488 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1489 if (retval != ERROR_OK)
1490 return retval;
1491 retval = dap_run(dap);
1492 if (retval != ERROR_OK)
1493 return retval;
1494
1495 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1496 apsel, apid);
1497
1498 return retval;
1499 }
1500
1501 COMMAND_HANDLER(dap_apcsw_command)
1502 {
1503 struct target *target = get_current_target(CMD_CTX);
1504 struct arm *arm = target_to_arm(target);
1505 struct adiv5_dap *dap = arm->dap;
1506
1507 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1508
1509 switch (CMD_ARGC) {
1510 case 0:
1511 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1512 (dap->apsel), apcsw);
1513 break;
1514 case 1:
1515 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1516 /* AP address is in bits 31:24 of DP_SELECT */
1517 if (sprot > 1)
1518 return ERROR_COMMAND_SYNTAX_ERROR;
1519 if (sprot)
1520 apcsw |= CSW_SPROT;
1521 else
1522 apcsw &= ~CSW_SPROT;
1523 break;
1524 default:
1525 return ERROR_COMMAND_SYNTAX_ERROR;
1526 }
1527 dap->ap[dap->apsel].csw_default = apcsw;
1528
1529 return 0;
1530 }
1531
1532
1533
1534 COMMAND_HANDLER(dap_apid_command)
1535 {
1536 struct target *target = get_current_target(CMD_CTX);
1537 struct arm *arm = target_to_arm(target);
1538 struct adiv5_dap *dap = arm->dap;
1539
1540 uint32_t apsel, apid;
1541 int retval;
1542
1543 switch (CMD_ARGC) {
1544 case 0:
1545 apsel = dap->apsel;
1546 break;
1547 case 1:
1548 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1549 /* AP address is in bits 31:24 of DP_SELECT */
1550 if (apsel >= 256)
1551 return ERROR_COMMAND_SYNTAX_ERROR;
1552 break;
1553 default:
1554 return ERROR_COMMAND_SYNTAX_ERROR;
1555 }
1556
1557 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1558 if (retval != ERROR_OK)
1559 return retval;
1560 retval = dap_run(dap);
1561 if (retval != ERROR_OK)
1562 return retval;
1563
1564 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1565
1566 return retval;
1567 }
1568
1569 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1570 {
1571 struct target *target = get_current_target(CMD_CTX);
1572 struct arm *arm = target_to_arm(target);
1573 struct adiv5_dap *dap = arm->dap;
1574
1575 uint32_t enable = dap->ti_be_32_quirks;
1576
1577 switch (CMD_ARGC) {
1578 case 0:
1579 break;
1580 case 1:
1581 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1582 if (enable > 1)
1583 return ERROR_COMMAND_SYNTAX_ERROR;
1584 break;
1585 default:
1586 return ERROR_COMMAND_SYNTAX_ERROR;
1587 }
1588 dap->ti_be_32_quirks = enable;
1589 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1590 enable ? "enabled" : "disabled");
1591
1592 return 0;
1593 }
1594
1595 static const struct command_registration dap_commands[] = {
1596 {
1597 .name = "info",
1598 .handler = handle_dap_info_command,
1599 .mode = COMMAND_EXEC,
1600 .help = "display ROM table for MEM-AP "
1601 "(default currently selected AP)",
1602 .usage = "[ap_num]",
1603 },
1604 {
1605 .name = "apsel",
1606 .handler = dap_apsel_command,
1607 .mode = COMMAND_EXEC,
1608 .help = "Set the currently selected AP (default 0) "
1609 "and display the result",
1610 .usage = "[ap_num]",
1611 },
1612 {
1613 .name = "apcsw",
1614 .handler = dap_apcsw_command,
1615 .mode = COMMAND_EXEC,
1616 .help = "Set csw access bit ",
1617 .usage = "[sprot]",
1618 },
1619
1620 {
1621 .name = "apid",
1622 .handler = dap_apid_command,
1623 .mode = COMMAND_EXEC,
1624 .help = "return ID register from AP "
1625 "(default currently selected AP)",
1626 .usage = "[ap_num]",
1627 },
1628 {
1629 .name = "baseaddr",
1630 .handler = dap_baseaddr_command,
1631 .mode = COMMAND_EXEC,
1632 .help = "return debug base address from MEM-AP "
1633 "(default currently selected AP)",
1634 .usage = "[ap_num]",
1635 },
1636 {
1637 .name = "memaccess",
1638 .handler = dap_memaccess_command,
1639 .mode = COMMAND_EXEC,
1640 .help = "set/get number of extra tck for MEM-AP memory "
1641 "bus access [0-255]",
1642 .usage = "[cycles]",
1643 },
1644 {
1645 .name = "ti_be_32_quirks",
1646 .handler = dap_ti_be_32_quirks_command,
1647 .mode = COMMAND_CONFIG,
1648 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1649 .usage = "[enable]",
1650 },
1651 COMMAND_REGISTRATION_DONE
1652 };
1653
1654 const struct command_registration dap_command_handlers[] = {
1655 {
1656 .name = "dap",
1657 .mode = COMMAND_EXEC,
1658 .help = "DAP command group",
1659 .usage = "",
1660 .chain = dap_commands,
1661 },
1662 COMMAND_REGISTRATION_DONE
1663 };
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