1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
85 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
103 void dap_ap_select(struct adiv5_dap
*dap
,uint8_t apsel
)
105 uint32_t select_apsel
= (apsel
<< 24) & 0xFF000000;
107 if (select_apsel
!= dap
->apsel
)
109 dap
->apsel
= select_apsel
;
110 /* Switching AP invalidates cached values.
111 * Values MUST BE UPDATED BEFORE AP ACCESS.
113 dap
->ap_bank_value
= -1;
114 dap
->ap_csw_value
= -1;
115 dap
->ap_tar_value
= -1;
120 * Queue transactions setting up transfer parameters for the
121 * currently selected MEM-AP.
123 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
124 * initiate data reads or writes using memory or peripheral addresses.
125 * If the CSW is configured for it, the TAR may be automatically
126 * incremented after each transfer.
128 * @todo Rename to reflect it being specifically a MEM-AP function.
130 * @param dap The DAP connected to the MEM-AP.
131 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
132 * matches the cached value, the register is not changed.
133 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
134 * matches the cached address, the register is not changed.
136 * @return ERROR_OK if the transaction was properly queued, else a fault code.
138 int dap_setup_accessport(struct adiv5_dap
*dap
, uint32_t csw
, uint32_t tar
)
142 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
143 if (csw
!= dap
->ap_csw_value
)
145 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
146 retval
= dap_queue_ap_write(dap
, AP_REG_CSW
, csw
);
147 if (retval
!= ERROR_OK
)
149 dap
->ap_csw_value
= csw
;
151 if (tar
!= dap
->ap_tar_value
)
153 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
154 retval
= dap_queue_ap_write(dap
, AP_REG_TAR
, tar
);
155 if (retval
!= ERROR_OK
)
157 dap
->ap_tar_value
= tar
;
159 /* Disable TAR cache when autoincrementing */
160 if (csw
& CSW_ADDRINC_MASK
)
161 dap
->ap_tar_value
= -1;
166 * Asynchronous (queued) read of a word from memory or a system register.
168 * @param dap The DAP connected to the MEM-AP performing the read.
169 * @param address Address of the 32-bit word to read; it must be
170 * readable by the currently selected MEM-AP.
171 * @param value points to where the word will be stored when the
172 * transaction queue is flushed (assuming no errors).
174 * @return ERROR_OK for success. Otherwise a fault code.
176 int mem_ap_read_u32(struct adiv5_dap
*dap
, uint32_t address
,
181 /* Use banked addressing (REG_BDx) to avoid some link traffic
182 * (updating TAR) when reading several consecutive addresses.
184 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
185 address
& 0xFFFFFFF0);
186 if (retval
!= ERROR_OK
)
189 return dap_queue_ap_read(dap
, AP_REG_BD0
| (address
& 0xC), value
);
193 * Synchronous read of a word from memory or a system register.
194 * As a side effect, this flushes any queued transactions.
196 * @param dap The DAP connected to the MEM-AP performing the read.
197 * @param address Address of the 32-bit word to read; it must be
198 * readable by the currently selected MEM-AP.
199 * @param value points to where the result will be stored.
201 * @return ERROR_OK for success; *value holds the result.
202 * Otherwise a fault code.
204 int mem_ap_read_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
209 retval
= mem_ap_read_u32(dap
, address
, value
);
210 if (retval
!= ERROR_OK
)
217 * Asynchronous (queued) write of a word to memory or a system register.
219 * @param dap The DAP connected to the MEM-AP.
220 * @param address Address to be written; it must be writable by
221 * the currently selected MEM-AP.
222 * @param value Word that will be written to the address when transaction
223 * queue is flushed (assuming no errors).
225 * @return ERROR_OK for success. Otherwise a fault code.
227 int mem_ap_write_u32(struct adiv5_dap
*dap
, uint32_t address
,
232 /* Use banked addressing (REG_BDx) to avoid some link traffic
233 * (updating TAR) when writing several consecutive addresses.
235 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
236 address
& 0xFFFFFFF0);
237 if (retval
!= ERROR_OK
)
240 return dap_queue_ap_write(dap
, AP_REG_BD0
| (address
& 0xC),
245 * Synchronous write of a word to memory or a system register.
246 * As a side effect, this flushes any queued transactions.
248 * @param dap The DAP connected to the MEM-AP.
249 * @param address Address to be written; it must be writable by
250 * the currently selected MEM-AP.
251 * @param value Word that will be written.
253 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
255 int mem_ap_write_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
258 int retval
= mem_ap_write_u32(dap
, address
, value
);
260 if (retval
!= ERROR_OK
)
266 /*****************************************************************************
268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
270 * Write a buffer in target order (little endian) *
272 *****************************************************************************/
273 int mem_ap_write_buf_u32(struct adiv5_dap
*dap
, uint8_t *buffer
, int count
, uint32_t address
)
275 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
276 uint32_t adr
= address
;
277 uint8_t* pBuffer
= buffer
;
282 /* if we have an unaligned access - reorder data */
285 for (writecount
= 0; writecount
< count
; writecount
++)
289 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
291 for (i
= 0; i
< 4; i
++)
293 *((uint8_t*)pBuffer
+ (adr
& 0x3)) = outvalue
;
297 pBuffer
+= sizeof(uint32_t);
303 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
304 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
305 if (wcount
< blocksize
)
308 /* handle unaligned data at 4k boundary */
312 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
313 if (retval
!= ERROR_OK
)
316 for (writecount
= 0; writecount
< blocksize
; writecount
++)
318 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
,
319 *(uint32_t *) ((void *) (buffer
+ 4 * writecount
)));
320 if (retval
!= ERROR_OK
)
324 if ((retval
= dap_run(dap
)) == ERROR_OK
)
326 wcount
= wcount
- blocksize
;
327 address
= address
+ 4 * blocksize
;
328 buffer
= buffer
+ 4 * blocksize
;
337 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
345 static int mem_ap_write_buf_packed_u16(struct adiv5_dap
*dap
,
346 uint8_t *buffer
, int count
, uint32_t address
)
348 int retval
= ERROR_OK
;
349 int wcount
, blocksize
, writecount
, i
;
357 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
358 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
360 if (wcount
< blocksize
)
363 /* handle unaligned data at 4k boundary */
367 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
368 if (retval
!= ERROR_OK
)
370 writecount
= blocksize
;
374 nbytes
= MIN((writecount
<< 1), 4);
378 retval
= mem_ap_write_buf_u16(dap
, buffer
,
380 if (retval
!= ERROR_OK
)
382 LOG_WARNING("Block write error address "
383 "0x%" PRIx32
", count 0x%x",
388 address
+= nbytes
>> 1;
393 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
395 for (i
= 0; i
< nbytes
; i
++)
397 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
402 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
403 retval
= dap_queue_ap_write(dap
,
404 AP_REG_DRW
, outvalue
);
405 if (retval
!= ERROR_OK
)
408 if ((retval
= dap_run(dap
)) != ERROR_OK
)
410 LOG_WARNING("Block write error address "
411 "0x%" PRIx32
", count 0x%x",
417 buffer
+= nbytes
>> 1;
418 writecount
-= nbytes
>> 1;
420 } while (writecount
);
427 int mem_ap_write_buf_u16(struct adiv5_dap
*dap
, uint8_t *buffer
, int count
, uint32_t address
)
429 int retval
= ERROR_OK
;
432 return mem_ap_write_buf_packed_u16(dap
, buffer
, count
, address
);
436 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
437 if (retval
!= ERROR_OK
)
440 memcpy(&svalue
, buffer
, sizeof(uint16_t));
441 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
442 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, outvalue
);
443 if (retval
!= ERROR_OK
)
446 retval
= dap_run(dap
);
447 if (retval
!= ERROR_OK
)
458 static int mem_ap_write_buf_packed_u8(struct adiv5_dap
*dap
,
459 uint8_t *buffer
, int count
, uint32_t address
)
461 int retval
= ERROR_OK
;
462 int wcount
, blocksize
, writecount
, i
;
470 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
471 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
473 if (wcount
< blocksize
)
476 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
477 if (retval
!= ERROR_OK
)
479 writecount
= blocksize
;
483 nbytes
= MIN(writecount
, 4);
487 retval
= mem_ap_write_buf_u8(dap
, buffer
, nbytes
, address
);
488 if (retval
!= ERROR_OK
)
490 LOG_WARNING("Block write error address "
491 "0x%" PRIx32
", count 0x%x",
501 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
503 for (i
= 0; i
< nbytes
; i
++)
505 *((uint8_t*)buffer
+ (address
& 0x3)) = outvalue
;
510 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
511 retval
= dap_queue_ap_write(dap
,
512 AP_REG_DRW
, outvalue
);
513 if (retval
!= ERROR_OK
)
516 if ((retval
= dap_run(dap
)) != ERROR_OK
)
518 LOG_WARNING("Block write error address "
519 "0x%" PRIx32
", count 0x%x",
526 writecount
-= nbytes
;
528 } while (writecount
);
535 int mem_ap_write_buf_u8(struct adiv5_dap
*dap
, uint8_t *buffer
, int count
, uint32_t address
)
537 int retval
= ERROR_OK
;
540 return mem_ap_write_buf_packed_u8(dap
, buffer
, count
, address
);
544 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
545 if (retval
!= ERROR_OK
)
547 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
548 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, outvalue
);
549 if (retval
!= ERROR_OK
)
552 retval
= dap_run(dap
);
553 if (retval
!= ERROR_OK
)
564 /* FIXME don't import ... this is a temporary workaround for the
565 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
567 extern int adi_jtag_dp_scan(struct adiv5_dap
*dap
,
568 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
569 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
);
572 * Synchronously read a block of 32-bit words into a buffer
573 * @param dap The DAP connected to the MEM-AP.
574 * @param buffer where the words will be stored (in host byte order).
575 * @param count How many words to read.
576 * @param address Memory address from which to read words; all the
577 * words must be readable by the currently selected MEM-AP.
579 int mem_ap_read_buf_u32(struct adiv5_dap
*dap
, uint8_t *buffer
,
580 int count
, uint32_t address
)
582 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
583 uint32_t adr
= address
;
584 uint8_t* pBuffer
= buffer
;
591 /* Adjust to read blocks within boundaries aligned to the
592 * TAR autoincrement size (at least 2^10). Autoincrement
593 * mode avoids an extra per-word roundtrip to update TAR.
595 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
,
597 if (wcount
< blocksize
)
600 /* handle unaligned data at 4k boundary */
604 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_SINGLE
,
606 if (retval
!= ERROR_OK
)
609 /* FIXME remove these three calls to adi_jtag_dp_scan(),
610 * so this routine becomes transport-neutral. Be careful
611 * not to cause performance problems with JTAG; would it
612 * suffice to loop over dap_queue_ap_read(), or would that
613 * be slower when JTAG is the chosen transport?
616 /* Scan out first read */
617 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, AP_REG_DRW
,
618 DPAP_READ
, 0, NULL
, NULL
);
619 if (retval
!= ERROR_OK
)
621 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++)
623 /* Scan out next read; scan in posted value for the
624 * previous one. Assumes read is acked "OK/FAULT",
625 * and CTRL_STAT says that meant "OK".
627 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, AP_REG_DRW
,
628 DPAP_READ
, 0, buffer
+ 4 * readcount
,
630 if (retval
!= ERROR_OK
)
634 /* Scan in last posted value; RDBUFF has no other effect,
635 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
637 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_DPACC
, DP_RDBUFF
,
638 DPAP_READ
, 0, buffer
+ 4 * readcount
,
640 if (retval
!= ERROR_OK
)
643 retval
= dap_run(dap
);
644 if (retval
!= ERROR_OK
)
652 LOG_WARNING("Block read error address 0x%" PRIx32
, address
);
655 wcount
= wcount
- blocksize
;
656 address
+= 4 * blocksize
;
657 buffer
+= 4 * blocksize
;
660 /* if we have an unaligned access - reorder data */
663 for (readcount
= 0; readcount
< count
; readcount
++)
667 memcpy(&data
, pBuffer
, sizeof(uint32_t));
669 for (i
= 0; i
< 4; i
++)
671 *((uint8_t*)pBuffer
) =
672 (data
>> 8 * (adr
& 0x3));
682 static int mem_ap_read_buf_packed_u16(struct adiv5_dap
*dap
,
683 uint8_t *buffer
, int count
, uint32_t address
)
686 int retval
= ERROR_OK
;
687 int wcount
, blocksize
, readcount
, i
;
695 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
696 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
697 if (wcount
< blocksize
)
700 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
701 if (retval
!= ERROR_OK
)
704 /* handle unaligned data at 4k boundary */
707 readcount
= blocksize
;
711 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
712 if (retval
!= ERROR_OK
)
714 if ((retval
= dap_run(dap
)) != ERROR_OK
)
716 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
720 nbytes
= MIN((readcount
<< 1), 4);
722 for (i
= 0; i
< nbytes
; i
++)
724 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
729 readcount
-= (nbytes
>> 1);
738 * Synchronously read a block of 16-bit halfwords into a buffer
739 * @param dap The DAP connected to the MEM-AP.
740 * @param buffer where the halfwords will be stored (in host byte order).
741 * @param count How many halfwords to read.
742 * @param address Memory address from which to read words; all the
743 * words must be readable by the currently selected MEM-AP.
745 int mem_ap_read_buf_u16(struct adiv5_dap
*dap
, uint8_t *buffer
,
746 int count
, uint32_t address
)
749 int retval
= ERROR_OK
;
752 return mem_ap_read_buf_packed_u16(dap
, buffer
, count
, address
);
756 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
757 if (retval
!= ERROR_OK
)
759 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
760 if (retval
!= ERROR_OK
)
763 retval
= dap_run(dap
);
764 if (retval
!= ERROR_OK
)
769 for (i
= 0; i
< 2; i
++)
771 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
778 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
779 memcpy(buffer
, &svalue
, sizeof(uint16_t));
789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
790 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
792 * The solution is to arrange for a large out/in scan in this loop and
793 * and convert data afterwards.
795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap
*dap
,
796 uint8_t *buffer
, int count
, uint32_t address
)
799 int retval
= ERROR_OK
;
800 int wcount
, blocksize
, readcount
, i
;
808 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
809 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
811 if (wcount
< blocksize
)
814 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
815 if (retval
!= ERROR_OK
)
817 readcount
= blocksize
;
821 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
822 if (retval
!= ERROR_OK
)
824 if ((retval
= dap_run(dap
)) != ERROR_OK
)
826 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
830 nbytes
= MIN(readcount
, 4);
832 for (i
= 0; i
< nbytes
; i
++)
834 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
848 * Synchronously read a block of bytes into a buffer
849 * @param dap The DAP connected to the MEM-AP.
850 * @param buffer where the bytes will be stored.
851 * @param count How many bytes to read.
852 * @param address Memory address from which to read data; all the
853 * data must be readable by the currently selected MEM-AP.
855 int mem_ap_read_buf_u8(struct adiv5_dap
*dap
, uint8_t *buffer
,
856 int count
, uint32_t address
)
859 int retval
= ERROR_OK
;
862 return mem_ap_read_buf_packed_u8(dap
, buffer
, count
, address
);
866 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
867 if (retval
!= ERROR_OK
)
869 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
870 if (retval
!= ERROR_OK
)
872 retval
= dap_run(dap
);
873 if (retval
!= ERROR_OK
)
876 *((uint8_t*)buffer
) = (invalue
>> 8 * (address
& 0x3));
885 /*--------------------------------------------------------------------------*/
888 /* FIXME don't import ... just initialize as
889 * part of DAP transport setup
891 extern const struct dap_ops jtag_dp_ops
;
893 /*--------------------------------------------------------------------------*/
896 * Initialize a DAP. This sets up the power domains, prepares the DP
897 * for further use, and arranges to use AP #0 for all AP operations
898 * until dap_ap-select() changes that policy.
900 * @param dap The DAP being initialized.
902 * @todo Rename this. We also need an initialization scheme which account
903 * for SWD transports not just JTAG; that will need to address differences
904 * in layering. (JTAG is useful without any debug target; but not SWD.)
905 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
907 int ahbap_debugport_init(struct adiv5_dap
*dap
)
916 /* JTAG-DP or SWJ-DP, in JTAG mode
917 * ... for SWD mode this is patched as part
921 dap
->ops
= &jtag_dp_ops
;
923 /* Default MEM-AP setup.
925 * REVISIT AP #0 may be an inappropriate default for this.
926 * Should we probe, or take a hint from the caller?
927 * Presumably we can ignore the possibility of multiple APs.
930 dap_ap_select(dap
, 0);
932 /* DP initialization */
934 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &dummy
);
935 if (retval
!= ERROR_OK
)
938 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, SSTICKYERR
);
939 if (retval
!= ERROR_OK
)
942 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &dummy
);
943 if (retval
!= ERROR_OK
)
946 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
947 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
948 if (retval
!= ERROR_OK
)
951 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
952 if (retval
!= ERROR_OK
)
954 if ((retval
= dap_run(dap
)) != ERROR_OK
)
957 /* Check that we have debug power domains activated */
958 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10))
960 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
961 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
962 if (retval
!= ERROR_OK
)
964 if ((retval
= dap_run(dap
)) != ERROR_OK
)
969 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10))
971 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
972 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
973 if (retval
!= ERROR_OK
)
975 if ((retval
= dap_run(dap
)) != ERROR_OK
)
980 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &dummy
);
981 if (retval
!= ERROR_OK
)
983 /* With debug power on we can activate OVERRUN checking */
984 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
985 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
986 if (retval
!= ERROR_OK
)
988 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &dummy
);
989 if (retval
!= ERROR_OK
)
995 /* CID interpretation -- see ARM IHI 0029B section 3
996 * and ARM IHI 0031A table 13-3.
998 static const char *class_description
[16] ={
999 "Reserved", "ROM table", "Reserved", "Reserved",
1000 "Reserved", "Reserved", "Reserved", "Reserved",
1001 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1002 "Reserved", "OptimoDE DESS",
1003 "Generic IP component", "PrimeCell or System component"
1007 is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1009 return cid3
== 0xb1 && cid2
== 0x05
1010 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1016 uint32_t correct_dbgbase
;
1019 { 0x80000000, 0x04770002, 0x60000000, "imx51" },
1022 int dap_get_debugbase(struct adiv5_dap
*dap
, int apsel
,
1023 uint32_t *out_dbgbase
, uint32_t *out_apid
)
1028 uint32_t dbgbase
, apid
;
1030 /* AP address is in bits 31:24 of DP_SELECT */
1032 return ERROR_INVALID_ARGUMENTS
;
1034 apselold
= dap
->apsel
;
1035 dap_ap_select(dap
, apsel
);
1037 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &dbgbase
);
1038 if (retval
!= ERROR_OK
)
1040 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1041 if (retval
!= ERROR_OK
)
1043 retval
= dap_run(dap
);
1044 if (retval
!= ERROR_OK
)
1047 /* Some CPUs are messed up, so fixup if needed. */
1048 for (i
= 0; i
< sizeof(broken_cpus
)/sizeof(struct broken_cpu
); i
++)
1049 if (broken_cpus
[i
].dbgbase
== dbgbase
&&
1050 broken_cpus
[i
].apid
== apid
) {
1051 LOG_WARNING("Found broken CPU (%s), trying to fixup "
1052 "ROM Table location from 0x%08x to 0x%08x",
1053 broken_cpus
[i
].model
, dbgbase
,
1054 broken_cpus
[i
].correct_dbgbase
);
1055 dbgbase
= broken_cpus
[i
].correct_dbgbase
;
1059 dap_ap_select(dap
, apselold
);
1061 /* The asignment happens only here to prevent modification of these
1062 * values before they are certain. */
1063 *out_dbgbase
= dbgbase
;
1069 int dap_lookup_cs_component(struct adiv5_dap
*dap
, int apsel
,
1070 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
)
1073 uint32_t romentry
, entry_offset
= 0, component_base
, devtype
;
1074 int retval
= ERROR_FAIL
;
1077 return ERROR_INVALID_ARGUMENTS
;
1079 apselold
= dap
->apsel
;
1080 dap_ap_select(dap
, apsel
);
1084 retval
= mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) |
1085 entry_offset
, &romentry
);
1086 if (retval
!= ERROR_OK
)
1089 component_base
= (dbgbase
& 0xFFFFF000)
1090 + (romentry
& 0xFFFFF000);
1092 if (romentry
& 0x1) {
1093 retval
= mem_ap_read_atomic_u32(dap
,
1094 (component_base
& 0xfffff000) | 0xfcc,
1096 if ((devtype
& 0xff) == type
) {
1097 *addr
= component_base
;
1103 } while (romentry
> 0);
1105 dap_ap_select(dap
, apselold
);
1110 static int dap_info_command(struct command_context
*cmd_ctx
,
1111 struct adiv5_dap
*dap
, int apsel
)
1114 uint32_t dbgbase
, apid
;
1115 int romtable_present
= 0;
1119 retval
= dap_get_debugbase(dap
, apsel
, &dbgbase
, &apid
);
1120 if (retval
!= ERROR_OK
)
1123 apselold
= dap
->apsel
;
1124 dap_ap_select(dap
, apsel
);
1126 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1127 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1128 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1134 command_print(cmd_ctx
, "\tType is JTAG-AP");
1137 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1140 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1143 command_print(cmd_ctx
, "\tUnknown AP type");
1147 /* NOTE: a MEM-AP may have a single CoreSight component that's
1148 * not a ROM table ... or have no such components at all.
1151 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
,
1156 command_print(cmd_ctx
, "No AP found at this apsel 0x%x", apsel
);
1159 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1160 if (romtable_present
)
1162 uint32_t cid0
,cid1
,cid2
,cid3
,memtype
,romentry
;
1163 uint16_t entry_offset
;
1165 /* bit 16 of apid indicates a memory access port */
1167 command_print(cmd_ctx
, "\tValid ROM table present");
1169 command_print(cmd_ctx
, "\tROM table in legacy format");
1171 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1172 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1173 if (retval
!= ERROR_OK
)
1175 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1176 if (retval
!= ERROR_OK
)
1178 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1179 if (retval
!= ERROR_OK
)
1181 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1182 if (retval
!= ERROR_OK
)
1184 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1185 if (retval
!= ERROR_OK
)
1187 retval
= dap_run(dap
);
1188 if (retval
!= ERROR_OK
)
1191 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1192 command_print(cmd_ctx
, "\tCID3 0x%2.2x"
1196 (unsigned) cid3
, (unsigned)cid2
,
1197 (unsigned) cid1
, (unsigned) cid0
);
1199 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1201 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1202 "Dedicated debug bus.");
1204 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1208 retval
= mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1209 if (retval
!= ERROR_OK
)
1211 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"",entry_offset
,romentry
);
1214 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1215 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1216 uint32_t component_base
;
1220 component_base
= (dbgbase
& 0xFFFFF000)
1221 + (romentry
& 0xFFFFF000);
1223 /* IDs are in last 4K section */
1226 retval
= mem_ap_read_atomic_u32(dap
,
1227 component_base
+ 0xFE0, &c_pid0
);
1228 if (retval
!= ERROR_OK
)
1231 retval
= mem_ap_read_atomic_u32(dap
,
1232 component_base
+ 0xFE4, &c_pid1
);
1233 if (retval
!= ERROR_OK
)
1236 retval
= mem_ap_read_atomic_u32(dap
,
1237 component_base
+ 0xFE8, &c_pid2
);
1238 if (retval
!= ERROR_OK
)
1241 retval
= mem_ap_read_atomic_u32(dap
,
1242 component_base
+ 0xFEC, &c_pid3
);
1243 if (retval
!= ERROR_OK
)
1246 retval
= mem_ap_read_atomic_u32(dap
,
1247 component_base
+ 0xFD0, &c_pid4
);
1248 if (retval
!= ERROR_OK
)
1252 retval
= mem_ap_read_atomic_u32(dap
,
1253 component_base
+ 0xFF0, &c_cid0
);
1254 if (retval
!= ERROR_OK
)
1257 retval
= mem_ap_read_atomic_u32(dap
,
1258 component_base
+ 0xFF4, &c_cid1
);
1259 if (retval
!= ERROR_OK
)
1262 retval
= mem_ap_read_atomic_u32(dap
,
1263 component_base
+ 0xFF8, &c_cid2
);
1264 if (retval
!= ERROR_OK
)
1267 retval
= mem_ap_read_atomic_u32(dap
,
1268 component_base
+ 0xFFC, &c_cid3
);
1269 if (retval
!= ERROR_OK
)
1274 command_print(cmd_ctx
,
1275 "\t\tComponent base address 0x%" PRIx32
1276 ", start address 0x%" PRIx32
,
1278 /* component may take multiple 4K pages */
1279 component_base
- 0x1000*(c_pid4
>> 4));
1280 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1281 (int) (c_cid1
>> 4) & 0xf,
1282 /* See ARM IHI 0029B Table 3-3 */
1283 class_description
[(c_cid1
>> 4) & 0xf]);
1285 /* CoreSight component? */
1286 if (((c_cid1
>> 4) & 0x0f) == 9) {
1289 char *major
= "Reserved", *subtype
= "Reserved";
1291 retval
= mem_ap_read_atomic_u32(dap
,
1292 (component_base
& 0xfffff000) | 0xfcc,
1294 if (retval
!= ERROR_OK
)
1296 minor
= (devtype
>> 4) & 0x0f;
1297 switch (devtype
& 0x0f) {
1299 major
= "Miscellaneous";
1305 subtype
= "Validation component";
1310 major
= "Trace Sink";
1324 major
= "Trace Link";
1330 subtype
= "Funnel, router";
1336 subtype
= "FIFO, buffer";
1341 major
= "Trace Source";
1347 subtype
= "Processor";
1353 subtype
= "Engine/Coprocessor";
1361 major
= "Debug Control";
1367 subtype
= "Trigger Matrix";
1370 subtype
= "Debug Auth";
1375 major
= "Debug Logic";
1381 subtype
= "Processor";
1387 subtype
= "Engine/Coprocessor";
1392 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1393 (unsigned) (devtype
& 0xff),
1395 /* REVISIT also show 0xfc8 DevId */
1398 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1399 command_print(cmd_ctx
,
1408 command_print(cmd_ctx
,
1409 "\t\tPeripheral ID[4..0] = hex "
1410 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1411 (int) c_pid4
, (int) c_pid3
, (int) c_pid2
,
1412 (int) c_pid1
, (int) c_pid0
);
1414 /* Part number interpretations are from Cortex
1415 * core specs, the CoreSight components TRM
1416 * (ARM DDI 0314H), and ETM specs; also from
1417 * chip observation (e.g. TI SDTI).
1419 part_num
= (c_pid0
& 0xff);
1420 part_num
|= (c_pid1
& 0x0f) << 8;
1423 type
= "Cortex-M3 NVIC";
1424 full
= "(Interrupt Controller)";
1427 type
= "Cortex-M3 ITM";
1428 full
= "(Instrumentation Trace Module)";
1431 type
= "Cortex-M3 DWT";
1432 full
= "(Data Watchpoint and Trace)";
1435 type
= "Cortex-M3 FBP";
1436 full
= "(Flash Patch and Breakpoint)";
1439 type
= "CoreSight ETM11";
1440 full
= "(Embedded Trace)";
1442 // case 0x113: what?
1443 case 0x120: /* from OMAP3 memmap */
1445 full
= "(System Debug Trace Interface)";
1447 case 0x343: /* from OMAP3 memmap */
1452 type
= "Coresight CTI";
1453 full
= "(Cross Trigger)";
1456 type
= "Coresight ETB";
1457 full
= "(Trace Buffer)";
1460 type
= "Coresight CSTF";
1461 full
= "(Trace Funnel)";
1464 type
= "CoreSight ETM9";
1465 full
= "(Embedded Trace)";
1468 type
= "Coresight TPIU";
1469 full
= "(Trace Port Interface Unit)";
1472 type
= "Cortex-A8 ETM";
1473 full
= "(Embedded Trace)";
1476 type
= "Cortex-A8 CTI";
1477 full
= "(Cross Trigger)";
1480 type
= "Cortex-M3 TPIU";
1481 full
= "(Trace Port Interface Unit)";
1484 type
= "Cortex-M3 ETM";
1485 full
= "(Embedded Trace)";
1488 type
= "Cortex-A8 Debug";
1489 full
= "(Debug Unit)";
1492 type
= "-*- unrecognized -*-";
1496 command_print(cmd_ctx
, "\t\tPart is %s %s",
1502 command_print(cmd_ctx
, "\t\tComponent not present");
1504 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1507 } while (romentry
> 0);
1511 command_print(cmd_ctx
, "\tNo ROM table present");
1513 dap_ap_select(dap
, apselold
);
1518 COMMAND_HANDLER(handle_dap_info_command
)
1520 struct target
*target
= get_current_target(CMD_CTX
);
1521 struct arm
*arm
= target_to_arm(target
);
1522 struct adiv5_dap
*dap
= arm
->dap
;
1530 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1533 return ERROR_COMMAND_SYNTAX_ERROR
;
1536 return dap_info_command(CMD_CTX
, dap
, apsel
);
1539 COMMAND_HANDLER(dap_baseaddr_command
)
1541 struct target
*target
= get_current_target(CMD_CTX
);
1542 struct arm
*arm
= target_to_arm(target
);
1543 struct adiv5_dap
*dap
= arm
->dap
;
1545 uint32_t apsel
, apselsave
, baseaddr
;
1548 apselsave
= dap
->apsel
;
1554 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1555 /* AP address is in bits 31:24 of DP_SELECT */
1557 return ERROR_INVALID_ARGUMENTS
;
1560 return ERROR_COMMAND_SYNTAX_ERROR
;
1563 if (apselsave
!= apsel
)
1564 dap_ap_select(dap
, apsel
);
1566 /* NOTE: assumes we're talking to a MEM-AP, which
1567 * has a base address. There are other kinds of AP,
1568 * though they're not common for now. This should
1569 * use the ID register to verify it's a MEM-AP.
1571 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &baseaddr
);
1572 if (retval
!= ERROR_OK
)
1574 retval
= dap_run(dap
);
1575 if (retval
!= ERROR_OK
)
1578 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1580 if (apselsave
!= apsel
)
1581 dap_ap_select(dap
, apselsave
);
1586 COMMAND_HANDLER(dap_memaccess_command
)
1588 struct target
*target
= get_current_target(CMD_CTX
);
1589 struct arm
*arm
= target_to_arm(target
);
1590 struct adiv5_dap
*dap
= arm
->dap
;
1592 uint32_t memaccess_tck
;
1596 memaccess_tck
= dap
->memaccess_tck
;
1599 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1602 return ERROR_COMMAND_SYNTAX_ERROR
;
1604 dap
->memaccess_tck
= memaccess_tck
;
1606 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1607 dap
->memaccess_tck
);
1612 COMMAND_HANDLER(dap_apsel_command
)
1614 struct target
*target
= get_current_target(CMD_CTX
);
1615 struct arm
*arm
= target_to_arm(target
);
1616 struct adiv5_dap
*dap
= arm
->dap
;
1618 uint32_t apsel
, apid
;
1626 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1627 /* AP address is in bits 31:24 of DP_SELECT */
1629 return ERROR_INVALID_ARGUMENTS
;
1632 return ERROR_COMMAND_SYNTAX_ERROR
;
1635 dap_ap_select(dap
, apsel
);
1636 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1637 if (retval
!= ERROR_OK
)
1639 retval
= dap_run(dap
);
1640 if (retval
!= ERROR_OK
)
1643 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1649 COMMAND_HANDLER(dap_apid_command
)
1651 struct target
*target
= get_current_target(CMD_CTX
);
1652 struct arm
*arm
= target_to_arm(target
);
1653 struct adiv5_dap
*dap
= arm
->dap
;
1655 uint32_t apsel
, apselsave
, apid
;
1658 apselsave
= dap
->apsel
;
1664 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1665 /* AP address is in bits 31:24 of DP_SELECT */
1667 return ERROR_INVALID_ARGUMENTS
;
1670 return ERROR_COMMAND_SYNTAX_ERROR
;
1673 if (apselsave
!= apsel
)
1674 dap_ap_select(dap
, apsel
);
1676 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1677 if (retval
!= ERROR_OK
)
1679 retval
= dap_run(dap
);
1680 if (retval
!= ERROR_OK
)
1683 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1684 if (apselsave
!= apsel
)
1685 dap_ap_select(dap
, apselsave
);
1690 static const struct command_registration dap_commands
[] = {
1693 .handler
= handle_dap_info_command
,
1694 .mode
= COMMAND_EXEC
,
1695 .help
= "display ROM table for MEM-AP "
1696 "(default currently selected AP)",
1697 .usage
= "[ap_num]",
1701 .handler
= dap_apsel_command
,
1702 .mode
= COMMAND_EXEC
,
1703 .help
= "Set the currently selected AP (default 0) "
1704 "and display the result",
1705 .usage
= "[ap_num]",
1709 .handler
= dap_apid_command
,
1710 .mode
= COMMAND_EXEC
,
1711 .help
= "return ID register from AP "
1712 "(default currently selected AP)",
1713 .usage
= "[ap_num]",
1717 .handler
= dap_baseaddr_command
,
1718 .mode
= COMMAND_EXEC
,
1719 .help
= "return debug base address from MEM-AP "
1720 "(default currently selected AP)",
1721 .usage
= "[ap_num]",
1724 .name
= "memaccess",
1725 .handler
= dap_memaccess_command
,
1726 .mode
= COMMAND_EXEC
,
1727 .help
= "set/get number of extra tck for MEM-AP memory "
1728 "bus access [0-255]",
1729 .usage
= "[cycles]",
1731 COMMAND_REGISTRATION_DONE
1734 const struct command_registration dap_command_handlers
[] = {
1737 .mode
= COMMAND_EXEC
,
1738 .help
= "DAP command group",
1739 .chain
= dap_commands
,
1741 COMMAND_REGISTRATION_DONE
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