dfbc5ade2af1958ceef83b44aea306eb7afd5ab6
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
29
30 /**
31 * @file
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
37 *
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 *
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
57 */
58
59 /*
60 * Relevant specifications from ARM include:
61 *
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 *
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
67 */
68
69 #ifdef HAVE_CONFIG_H
70 #include "config.h"
71 #endif
72
73 #include "jtag/interface.h"
74 #include "arm.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
79
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
81
82 /*
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
85 */
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
87 {
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
89 }
90
91 /***************************************************************************
92 * *
93 * DP and MEM-AP register access through APACC and DPACC *
94 * *
95 ***************************************************************************/
96
97 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
98 {
99 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
100 ap->csw_default;
101
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK)
106 return retval;
107 ap->csw_value = csw;
108 }
109 return ERROR_OK;
110 }
111
112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
113 {
114 if (!ap->tar_valid || tar != ap->tar_value) {
115 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
116 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
117 if (retval != ERROR_OK)
118 return retval;
119 ap->tar_value = tar;
120 ap->tar_valid = true;
121 }
122 return ERROR_OK;
123 }
124
125 static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
126 {
127 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
128 if (retval != ERROR_OK) {
129 ap->tar_valid = false;
130 return retval;
131 }
132
133 retval = dap_run(ap->dap);
134 if (retval != ERROR_OK) {
135 ap->tar_valid = false;
136 return retval;
137 }
138
139 ap->tar_value = *tar;
140 ap->tar_valid = true;
141 return ERROR_OK;
142 }
143
144 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
145 {
146 switch (ap->csw_value & CSW_ADDRINC_MASK) {
147 case CSW_ADDRINC_SINGLE:
148 switch (ap->csw_value & CSW_SIZE_MASK) {
149 case CSW_8BIT:
150 return 1;
151 case CSW_16BIT:
152 return 2;
153 case CSW_32BIT:
154 return 4;
155 }
156 case CSW_ADDRINC_PACKED:
157 return 4;
158 }
159 return 0;
160 }
161
162 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
163 */
164 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
165 {
166 if (!ap->tar_valid)
167 return;
168
169 uint32_t inc = mem_ap_get_tar_increment(ap);
170 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
171 ap->tar_valid = false;
172 else
173 ap->tar_value += inc;
174 }
175
176 /**
177 * Queue transactions setting up transfer parameters for the
178 * currently selected MEM-AP.
179 *
180 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
181 * initiate data reads or writes using memory or peripheral addresses.
182 * If the CSW is configured for it, the TAR may be automatically
183 * incremented after each transfer.
184 *
185 * @param ap The MEM-AP.
186 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
187 * matches the cached value, the register is not changed.
188 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
189 * matches the cached address, the register is not changed.
190 *
191 * @return ERROR_OK if the transaction was properly queued, else a fault code.
192 */
193 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
194 {
195 int retval;
196 retval = mem_ap_setup_csw(ap, csw);
197 if (retval != ERROR_OK)
198 return retval;
199 retval = mem_ap_setup_tar(ap, tar);
200 if (retval != ERROR_OK)
201 return retval;
202 return ERROR_OK;
203 }
204
205 /**
206 * Asynchronous (queued) read of a word from memory or a system register.
207 *
208 * @param ap The MEM-AP to access.
209 * @param address Address of the 32-bit word to read; it must be
210 * readable by the currently selected MEM-AP.
211 * @param value points to where the word will be stored when the
212 * transaction queue is flushed (assuming no errors).
213 *
214 * @return ERROR_OK for success. Otherwise a fault code.
215 */
216 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
217 uint32_t *value)
218 {
219 int retval;
220
221 /* Use banked addressing (REG_BDx) to avoid some link traffic
222 * (updating TAR) when reading several consecutive addresses.
223 */
224 retval = mem_ap_setup_transfer(ap,
225 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
226 address & 0xFFFFFFF0);
227 if (retval != ERROR_OK)
228 return retval;
229
230 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
231 }
232
233 /**
234 * Synchronous read of a word from memory or a system register.
235 * As a side effect, this flushes any queued transactions.
236 *
237 * @param ap The MEM-AP to access.
238 * @param address Address of the 32-bit word to read; it must be
239 * readable by the currently selected MEM-AP.
240 * @param value points to where the result will be stored.
241 *
242 * @return ERROR_OK for success; *value holds the result.
243 * Otherwise a fault code.
244 */
245 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
246 uint32_t *value)
247 {
248 int retval;
249
250 retval = mem_ap_read_u32(ap, address, value);
251 if (retval != ERROR_OK)
252 return retval;
253
254 return dap_run(ap->dap);
255 }
256
257 /**
258 * Asynchronous (queued) write of a word to memory or a system register.
259 *
260 * @param ap The MEM-AP to access.
261 * @param address Address to be written; it must be writable by
262 * the currently selected MEM-AP.
263 * @param value Word that will be written to the address when transaction
264 * queue is flushed (assuming no errors).
265 *
266 * @return ERROR_OK for success. Otherwise a fault code.
267 */
268 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
269 uint32_t value)
270 {
271 int retval;
272
273 /* Use banked addressing (REG_BDx) to avoid some link traffic
274 * (updating TAR) when writing several consecutive addresses.
275 */
276 retval = mem_ap_setup_transfer(ap,
277 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
278 address & 0xFFFFFFF0);
279 if (retval != ERROR_OK)
280 return retval;
281
282 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
283 value);
284 }
285
286 /**
287 * Synchronous write of a word to memory or a system register.
288 * As a side effect, this flushes any queued transactions.
289 *
290 * @param ap The MEM-AP to access.
291 * @param address Address to be written; it must be writable by
292 * the currently selected MEM-AP.
293 * @param value Word that will be written.
294 *
295 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
296 */
297 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
298 uint32_t value)
299 {
300 int retval = mem_ap_write_u32(ap, address, value);
301
302 if (retval != ERROR_OK)
303 return retval;
304
305 return dap_run(ap->dap);
306 }
307
308 /**
309 * Synchronous write of a block of memory, using a specific access size.
310 *
311 * @param ap The MEM-AP to access.
312 * @param buffer The data buffer to write. No particular alignment is assumed.
313 * @param size Which access size to use, in bytes. 1, 2 or 4.
314 * @param count The number of writes to do (in size units, not bytes).
315 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
316 * @param addrinc Whether the target address should be increased for each write or not. This
317 * should normally be true, except when writing to e.g. a FIFO.
318 * @return ERROR_OK on success, otherwise an error code.
319 */
320 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
321 uint32_t address, bool addrinc)
322 {
323 struct adiv5_dap *dap = ap->dap;
324 size_t nbytes = size * count;
325 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
326 uint32_t csw_size;
327 uint32_t addr_xor;
328 int retval = ERROR_OK;
329
330 /* TI BE-32 Quirks mode:
331 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
332 * size write address bytes written in order
333 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
334 * 2 TAR ^ 2 (val >> 8), (val)
335 * 1 TAR ^ 3 (val)
336 * For example, if you attempt to write a single byte to address 0, the processor
337 * will actually write a byte to address 3.
338 *
339 * To make writes of size < 4 work as expected, we xor a value with the address before
340 * setting the TAP, and we set the TAP after every transfer rather then relying on
341 * address increment. */
342
343 if (size == 4) {
344 csw_size = CSW_32BIT;
345 addr_xor = 0;
346 } else if (size == 2) {
347 csw_size = CSW_16BIT;
348 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
349 } else if (size == 1) {
350 csw_size = CSW_8BIT;
351 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
352 } else {
353 return ERROR_TARGET_UNALIGNED_ACCESS;
354 }
355
356 if (ap->unaligned_access_bad && (address % size != 0))
357 return ERROR_TARGET_UNALIGNED_ACCESS;
358
359 while (nbytes > 0) {
360 uint32_t this_size = size;
361
362 /* Select packed transfer if possible */
363 if (addrinc && ap->packed_transfers && nbytes >= 4
364 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
365 this_size = 4;
366 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
367 } else {
368 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
369 }
370
371 if (retval != ERROR_OK)
372 break;
373
374 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
375 if (retval != ERROR_OK)
376 return retval;
377
378 /* How many source bytes each transfer will consume, and their location in the DRW,
379 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
380 uint32_t outvalue = 0;
381 uint32_t drw_byte_idx = address;
382 if (dap->ti_be_32_quirks) {
383 switch (this_size) {
384 case 4:
385 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
386 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
387 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
388 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
389 break;
390 case 2:
391 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
392 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
393 break;
394 case 1:
395 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
396 break;
397 }
398 } else {
399 switch (this_size) {
400 case 4:
401 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
402 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
403 /* fallthrough */
404 case 2:
405 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
406 /* fallthrough */
407 case 1:
408 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
409 }
410 }
411
412 nbytes -= this_size;
413
414 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
415 if (retval != ERROR_OK)
416 break;
417
418 mem_ap_update_tar_cache(ap);
419 if (addrinc)
420 address += this_size;
421 }
422
423 /* REVISIT: Might want to have a queued version of this function that does not run. */
424 if (retval == ERROR_OK)
425 retval = dap_run(dap);
426
427 if (retval != ERROR_OK) {
428 uint32_t tar;
429 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
430 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
431 else
432 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
433 }
434
435 return retval;
436 }
437
438 /**
439 * Synchronous read of a block of memory, using a specific access size.
440 *
441 * @param ap The MEM-AP to access.
442 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
443 * @param size Which access size to use, in bytes. 1, 2 or 4.
444 * @param count The number of reads to do (in size units, not bytes).
445 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
446 * @param addrinc Whether the target address should be increased after each read or not. This
447 * should normally be true, except when reading from e.g. a FIFO.
448 * @return ERROR_OK on success, otherwise an error code.
449 */
450 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
451 uint32_t adr, bool addrinc)
452 {
453 struct adiv5_dap *dap = ap->dap;
454 size_t nbytes = size * count;
455 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
456 uint32_t csw_size;
457 uint32_t address = adr;
458 int retval = ERROR_OK;
459
460 /* TI BE-32 Quirks mode:
461 * Reads on big-endian TMS570 behave strangely differently than writes.
462 * They read from the physical address requested, but with DRW byte-reversed.
463 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
464 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
465 * so avoid them. */
466
467 if (size == 4)
468 csw_size = CSW_32BIT;
469 else if (size == 2)
470 csw_size = CSW_16BIT;
471 else if (size == 1)
472 csw_size = CSW_8BIT;
473 else
474 return ERROR_TARGET_UNALIGNED_ACCESS;
475
476 if (ap->unaligned_access_bad && (adr % size != 0))
477 return ERROR_TARGET_UNALIGNED_ACCESS;
478
479 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
480 * over-allocation if packed transfers are going to be used, but determining the real need at
481 * this point would be messy. */
482 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
483 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
484 uint32_t *read_ptr = read_buf;
485 if (read_buf == NULL) {
486 LOG_ERROR("Failed to allocate read buffer");
487 return ERROR_FAIL;
488 }
489
490 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
491 * useful bytes it contains, and their location in the word, depends on the type of transfer
492 * and alignment. */
493 while (nbytes > 0) {
494 uint32_t this_size = size;
495
496 /* Select packed transfer if possible */
497 if (addrinc && ap->packed_transfers && nbytes >= 4
498 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
499 this_size = 4;
500 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
501 } else {
502 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
503 }
504 if (retval != ERROR_OK)
505 break;
506
507 retval = mem_ap_setup_tar(ap, address);
508 if (retval != ERROR_OK)
509 break;
510
511 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
512 if (retval != ERROR_OK)
513 break;
514
515 nbytes -= this_size;
516 if (addrinc)
517 address += this_size;
518
519 mem_ap_update_tar_cache(ap);
520 }
521
522 if (retval == ERROR_OK)
523 retval = dap_run(dap);
524
525 /* Restore state */
526 address = adr;
527 nbytes = size * count;
528 read_ptr = read_buf;
529
530 /* If something failed, read TAR to find out how much data was successfully read, so we can
531 * at least give the caller what we have. */
532 if (retval != ERROR_OK) {
533 uint32_t tar;
534 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
535 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
536 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
537 if (nbytes > tar - address)
538 nbytes = tar - address;
539 } else {
540 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
541 nbytes = 0;
542 }
543 }
544
545 /* Replay loop to populate caller's buffer from the correct word and byte lane */
546 while (nbytes > 0) {
547 uint32_t this_size = size;
548
549 if (addrinc && ap->packed_transfers && nbytes >= 4
550 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
551 this_size = 4;
552 }
553
554 if (dap->ti_be_32_quirks) {
555 switch (this_size) {
556 case 4:
557 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
558 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
559 /* fallthrough */
560 case 2:
561 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
562 /* fallthrough */
563 case 1:
564 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
565 }
566 } else {
567 switch (this_size) {
568 case 4:
569 *buffer++ = *read_ptr >> 8 * (address++ & 3);
570 *buffer++ = *read_ptr >> 8 * (address++ & 3);
571 /* fallthrough */
572 case 2:
573 *buffer++ = *read_ptr >> 8 * (address++ & 3);
574 /* fallthrough */
575 case 1:
576 *buffer++ = *read_ptr >> 8 * (address++ & 3);
577 }
578 }
579
580 read_ptr++;
581 nbytes -= this_size;
582 }
583
584 free(read_buf);
585 return retval;
586 }
587
588 int mem_ap_read_buf(struct adiv5_ap *ap,
589 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
590 {
591 return mem_ap_read(ap, buffer, size, count, address, true);
592 }
593
594 int mem_ap_write_buf(struct adiv5_ap *ap,
595 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
596 {
597 return mem_ap_write(ap, buffer, size, count, address, true);
598 }
599
600 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
601 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
602 {
603 return mem_ap_read(ap, buffer, size, count, address, false);
604 }
605
606 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
607 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
608 {
609 return mem_ap_write(ap, buffer, size, count, address, false);
610 }
611
612 /*--------------------------------------------------------------------------*/
613
614
615 #define DAP_POWER_DOMAIN_TIMEOUT (10)
616
617 /* FIXME don't import ... just initialize as
618 * part of DAP transport setup
619 */
620 extern const struct dap_ops jtag_dp_ops;
621
622 /*--------------------------------------------------------------------------*/
623
624 /**
625 * Create a new DAP
626 */
627 struct adiv5_dap *dap_init(void)
628 {
629 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
630 int i;
631 /* Set up with safe defaults */
632 for (i = 0; i <= 255; i++) {
633 dap->ap[i].dap = dap;
634 dap->ap[i].ap_num = i;
635 /* memaccess_tck max is 255 */
636 dap->ap[i].memaccess_tck = 255;
637 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
638 dap->ap[i].tar_autoincr_block = (1<<10);
639 }
640 INIT_LIST_HEAD(&dap->cmd_journal);
641 return dap;
642 }
643
644 /**
645 * Invalidate cached DP select and cached TAR and CSW of all APs
646 */
647 void dap_invalidate_cache(struct adiv5_dap *dap)
648 {
649 dap->select = DP_SELECT_INVALID;
650 dap->last_read = NULL;
651
652 int i;
653 for (i = 0; i <= 255; i++) {
654 /* force csw and tar write on the next mem-ap access */
655 dap->ap[i].tar_valid = false;
656 dap->ap[i].csw_value = 0;
657 }
658 }
659
660 /**
661 * Initialize a DAP. This sets up the power domains, prepares the DP
662 * for further use and activates overrun checking.
663 *
664 * @param dap The DAP being initialized.
665 */
666 int dap_dp_init(struct adiv5_dap *dap)
667 {
668 int retval;
669
670 LOG_DEBUG(" ");
671 /* JTAG-DP or SWJ-DP, in JTAG mode
672 * ... for SWD mode this is patched as part
673 * of link switchover
674 * FIXME: This should already be setup by the respective transport specific DAP creation.
675 */
676 if (!dap->ops)
677 dap->ops = &jtag_dp_ops;
678
679 dap_invalidate_cache(dap);
680
681 for (size_t i = 0; i < 30; i++) {
682 /* DP initialization */
683
684 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
685 if (retval == ERROR_OK)
686 break;
687 }
688
689 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
690 if (retval != ERROR_OK)
691 return retval;
692
693 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
694 if (retval != ERROR_OK)
695 return retval;
696
697 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
698 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
699 if (retval != ERROR_OK)
700 return retval;
701
702 /* Check that we have debug power domains activated */
703 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
704 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
705 CDBGPWRUPACK, CDBGPWRUPACK,
706 DAP_POWER_DOMAIN_TIMEOUT);
707 if (retval != ERROR_OK)
708 return retval;
709
710 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
711 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
712 CSYSPWRUPACK, CSYSPWRUPACK,
713 DAP_POWER_DOMAIN_TIMEOUT);
714 if (retval != ERROR_OK)
715 return retval;
716
717 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
718 if (retval != ERROR_OK)
719 return retval;
720
721 /* With debug power on we can activate OVERRUN checking */
722 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
723 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
724 if (retval != ERROR_OK)
725 return retval;
726 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
727 if (retval != ERROR_OK)
728 return retval;
729
730 retval = dap_run(dap);
731 if (retval != ERROR_OK)
732 return retval;
733
734 return retval;
735 }
736
737 /**
738 * Initialize a DAP. This sets up the power domains, prepares the DP
739 * for further use, and arranges to use AP #0 for all AP operations
740 * until dap_ap-select() changes that policy.
741 *
742 * @param ap The MEM-AP being initialized.
743 */
744 int mem_ap_init(struct adiv5_ap *ap)
745 {
746 /* check that we support packed transfers */
747 uint32_t csw, cfg;
748 int retval;
749 struct adiv5_dap *dap = ap->dap;
750
751 ap->tar_valid = false;
752 ap->csw_value = 0; /* force csw and tar write */
753 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
754 if (retval != ERROR_OK)
755 return retval;
756
757 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
758 if (retval != ERROR_OK)
759 return retval;
760
761 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
762 if (retval != ERROR_OK)
763 return retval;
764
765 retval = dap_run(dap);
766 if (retval != ERROR_OK)
767 return retval;
768
769 if (csw & CSW_ADDRINC_PACKED)
770 ap->packed_transfers = true;
771 else
772 ap->packed_transfers = false;
773
774 /* Packed transfers on TI BE-32 processors do not work correctly in
775 * many cases. */
776 if (dap->ti_be_32_quirks)
777 ap->packed_transfers = false;
778
779 LOG_DEBUG("MEM_AP Packed Transfers: %s",
780 ap->packed_transfers ? "enabled" : "disabled");
781
782 /* The ARM ADI spec leaves implementation-defined whether unaligned
783 * memory accesses work, only work partially, or cause a sticky error.
784 * On TI BE-32 processors, reads seem to return garbage in some bytes
785 * and unaligned writes seem to cause a sticky error.
786 * TODO: it would be nice to have a way to detect whether unaligned
787 * operations are supported on other processors. */
788 ap->unaligned_access_bad = dap->ti_be_32_quirks;
789
790 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
791 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
792
793 return ERROR_OK;
794 }
795
796 /* CID interpretation -- see ARM IHI 0029B section 3
797 * and ARM IHI 0031A table 13-3.
798 */
799 static const char *class_description[16] = {
800 "Reserved", "ROM table", "Reserved", "Reserved",
801 "Reserved", "Reserved", "Reserved", "Reserved",
802 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
803 "Reserved", "OptimoDE DESS",
804 "Generic IP component", "PrimeCell or System component"
805 };
806
807 static bool is_dap_cid_ok(uint32_t cid)
808 {
809 return (cid & 0xffff0fff) == 0xb105000d;
810 }
811
812 /*
813 * This function checks the ID for each access port to find the requested Access Port type
814 */
815 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
816 {
817 int ap_num;
818
819 /* Maximum AP number is 255 since the SELECT register is 8 bits */
820 for (ap_num = 0; ap_num <= 255; ap_num++) {
821
822 /* read the IDR register of the Access Port */
823 uint32_t id_val = 0;
824
825 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
826 if (retval != ERROR_OK)
827 return retval;
828
829 retval = dap_run(dap);
830
831 /* IDR bits:
832 * 31-28 : Revision
833 * 27-24 : JEDEC bank (0x4 for ARM)
834 * 23-17 : JEDEC code (0x3B for ARM)
835 * 16-13 : Class (0b1000=Mem-AP)
836 * 12-8 : Reserved
837 * 7-4 : AP Variant (non-zero for JTAG-AP)
838 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
839 */
840
841 /* Reading register for a non-existant AP should not cause an error,
842 * but just to be sure, try to continue searching if an error does happen.
843 */
844 if ((retval == ERROR_OK) && /* Register read success */
845 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
846 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
847
848 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
849 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
850 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
851 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
852 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
853 ap_num, id_val);
854
855 *ap_out = &dap->ap[ap_num];
856 return ERROR_OK;
857 }
858 }
859
860 LOG_DEBUG("No %s found",
861 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
862 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
863 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
864 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
865 return ERROR_FAIL;
866 }
867
868 int dap_get_debugbase(struct adiv5_ap *ap,
869 uint32_t *dbgbase, uint32_t *apid)
870 {
871 struct adiv5_dap *dap = ap->dap;
872 int retval;
873
874 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
875 if (retval != ERROR_OK)
876 return retval;
877 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
878 if (retval != ERROR_OK)
879 return retval;
880 retval = dap_run(dap);
881 if (retval != ERROR_OK)
882 return retval;
883
884 return ERROR_OK;
885 }
886
887 int dap_lookup_cs_component(struct adiv5_ap *ap,
888 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
889 {
890 uint32_t romentry, entry_offset = 0, component_base, devtype;
891 int retval;
892
893 *addr = 0;
894
895 do {
896 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
897 entry_offset, &romentry);
898 if (retval != ERROR_OK)
899 return retval;
900
901 component_base = (dbgbase & 0xFFFFF000)
902 + (romentry & 0xFFFFF000);
903
904 if (romentry & 0x1) {
905 uint32_t c_cid1;
906 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
907 if (retval != ERROR_OK) {
908 LOG_ERROR("Can't read component with base address 0x%" PRIx32
909 ", the corresponding core might be turned off", component_base);
910 return retval;
911 }
912 if (((c_cid1 >> 4) & 0x0f) == 1) {
913 retval = dap_lookup_cs_component(ap, component_base,
914 type, addr, idx);
915 if (retval == ERROR_OK)
916 break;
917 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
918 return retval;
919 }
920
921 retval = mem_ap_read_atomic_u32(ap,
922 (component_base & 0xfffff000) | 0xfcc,
923 &devtype);
924 if (retval != ERROR_OK)
925 return retval;
926 if ((devtype & 0xff) == type) {
927 if (!*idx) {
928 *addr = component_base;
929 break;
930 } else
931 (*idx)--;
932 }
933 }
934 entry_offset += 4;
935 } while (romentry > 0);
936
937 if (!*addr)
938 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
939
940 return ERROR_OK;
941 }
942
943 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
944 {
945 assert((component_base & 0xFFF) == 0);
946 assert(ap != NULL && cid != NULL && pid != NULL);
947
948 uint32_t cid0, cid1, cid2, cid3;
949 uint32_t pid0, pid1, pid2, pid3, pid4;
950 int retval;
951
952 /* IDs are in last 4K section */
953 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
954 if (retval != ERROR_OK)
955 return retval;
956 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
957 if (retval != ERROR_OK)
958 return retval;
959 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
960 if (retval != ERROR_OK)
961 return retval;
962 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
963 if (retval != ERROR_OK)
964 return retval;
965 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
966 if (retval != ERROR_OK)
967 return retval;
968 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
969 if (retval != ERROR_OK)
970 return retval;
971 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
972 if (retval != ERROR_OK)
973 return retval;
974 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
975 if (retval != ERROR_OK)
976 return retval;
977 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
978 if (retval != ERROR_OK)
979 return retval;
980
981 retval = dap_run(ap->dap);
982 if (retval != ERROR_OK)
983 return retval;
984
985 *cid = (cid3 & 0xff) << 24
986 | (cid2 & 0xff) << 16
987 | (cid1 & 0xff) << 8
988 | (cid0 & 0xff);
989 *pid = (uint64_t)(pid4 & 0xff) << 32
990 | (pid3 & 0xff) << 24
991 | (pid2 & 0xff) << 16
992 | (pid1 & 0xff) << 8
993 | (pid0 & 0xff);
994
995 return ERROR_OK;
996 }
997
998 /* The designer identity code is encoded as:
999 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
1000 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
1001 * a legacy ASCII Identity Code.
1002 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
1003 * JEP106 is a standard available from jedec.org
1004 */
1005
1006 /* Part number interpretations are from Cortex
1007 * core specs, the CoreSight components TRM
1008 * (ARM DDI 0314H), CoreSight System Design
1009 * Guide (ARM DGI 0012D) and ETM specs; also
1010 * from chip observation (e.g. TI SDTI).
1011 */
1012
1013 /* The legacy code only used the part number field to identify CoreSight peripherals.
1014 * This meant that the same part number from two different manufacturers looked the same.
1015 * It is desirable for all future additions to identify with both part number and JEP106.
1016 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
1017 */
1018
1019 #define ANY_ID 0x1000
1020
1021 #define ARM_ID 0x4BB
1022
1023 static const struct {
1024 uint16_t designer_id;
1025 uint16_t part_num;
1026 const char *type;
1027 const char *full;
1028 } dap_partnums[] = {
1029 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1030 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1031 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1032 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1033 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1034 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1035 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1036 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1037 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1038 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1039 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1040 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1041 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1042 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1043 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1044 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1045 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1046 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1047 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1048 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1049 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1050 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1051 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1052 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1053 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1054 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1055 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1056 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1057 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1058 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1059 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1060 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1061 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1062 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1063 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1064 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1065 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1066 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1067 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1068 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1069 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1070 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1071 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1072 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1073 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1074 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1075 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1076 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1077 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1078 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1079 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1080 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1081 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1082 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1083 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1084 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1085 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1086 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1087 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1088 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1089 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1090 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1091 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1092 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1093 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1094 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1095 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1096 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1097 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1098 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1099 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1100 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1101 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1102 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1103 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1104 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1105 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1106 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1107 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1108 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1109 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1110 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1111 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1112 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1113 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1114 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1115 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1116 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1117 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1118 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1119 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1120 /* legacy comment: 0x113: what? */
1121 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1122 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1123 };
1124
1125 static int dap_rom_display(struct command_context *cmd_ctx,
1126 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1127 {
1128 int retval;
1129 uint64_t pid;
1130 uint32_t cid;
1131 char tabs[16] = "";
1132
1133 if (depth > 16) {
1134 command_print(cmd_ctx, "\tTables too deep");
1135 return ERROR_FAIL;
1136 }
1137
1138 if (depth)
1139 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1140
1141 uint32_t base_addr = dbgbase & 0xFFFFF000;
1142 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1143
1144 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1145 if (retval != ERROR_OK) {
1146 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1147 return ERROR_OK; /* Don't abort recursion */
1148 }
1149
1150 if (!is_dap_cid_ok(cid)) {
1151 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1152 return ERROR_OK; /* Don't abort recursion */
1153 }
1154
1155 /* component may take multiple 4K pages */
1156 uint32_t size = (pid >> 36) & 0xf;
1157 if (size > 0)
1158 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1159
1160 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1161
1162 uint8_t class = (cid >> 12) & 0xf;
1163 uint16_t part_num = pid & 0xfff;
1164 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1165
1166 if (designer_id & 0x80) {
1167 /* JEP106 code */
1168 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1169 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1170 } else {
1171 /* Legacy ASCII ID, clear invalid bits */
1172 designer_id &= 0x7f;
1173 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1174 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1175 }
1176
1177 /* default values to be overwritten upon finding a match */
1178 const char *type = "Unrecognized";
1179 const char *full = "";
1180
1181 /* search dap_partnums[] array for a match */
1182 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1183
1184 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1185 continue;
1186
1187 if (dap_partnums[entry].part_num != part_num)
1188 continue;
1189
1190 type = dap_partnums[entry].type;
1191 full = dap_partnums[entry].full;
1192 break;
1193 }
1194
1195 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1196 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1197
1198 if (class == 1) { /* ROM Table */
1199 uint32_t memtype;
1200 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1201 if (retval != ERROR_OK)
1202 return retval;
1203
1204 if (memtype & 0x01)
1205 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1206 else
1207 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1208
1209 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1210 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1211 uint32_t romentry;
1212 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1213 if (retval != ERROR_OK)
1214 return retval;
1215 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1216 tabs, entry_offset, romentry);
1217 if (romentry & 0x01) {
1218 /* Recurse */
1219 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1220 if (retval != ERROR_OK)
1221 return retval;
1222 } else if (romentry != 0) {
1223 command_print(cmd_ctx, "\t\tComponent not present");
1224 } else {
1225 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1226 break;
1227 }
1228 }
1229 } else if (class == 9) { /* CoreSight component */
1230 const char *major = "Reserved", *subtype = "Reserved";
1231
1232 uint32_t devtype;
1233 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1234 if (retval != ERROR_OK)
1235 return retval;
1236 unsigned minor = (devtype >> 4) & 0x0f;
1237 switch (devtype & 0x0f) {
1238 case 0:
1239 major = "Miscellaneous";
1240 switch (minor) {
1241 case 0:
1242 subtype = "other";
1243 break;
1244 case 4:
1245 subtype = "Validation component";
1246 break;
1247 }
1248 break;
1249 case 1:
1250 major = "Trace Sink";
1251 switch (minor) {
1252 case 0:
1253 subtype = "other";
1254 break;
1255 case 1:
1256 subtype = "Port";
1257 break;
1258 case 2:
1259 subtype = "Buffer";
1260 break;
1261 case 3:
1262 subtype = "Router";
1263 break;
1264 }
1265 break;
1266 case 2:
1267 major = "Trace Link";
1268 switch (minor) {
1269 case 0:
1270 subtype = "other";
1271 break;
1272 case 1:
1273 subtype = "Funnel, router";
1274 break;
1275 case 2:
1276 subtype = "Filter";
1277 break;
1278 case 3:
1279 subtype = "FIFO, buffer";
1280 break;
1281 }
1282 break;
1283 case 3:
1284 major = "Trace Source";
1285 switch (minor) {
1286 case 0:
1287 subtype = "other";
1288 break;
1289 case 1:
1290 subtype = "Processor";
1291 break;
1292 case 2:
1293 subtype = "DSP";
1294 break;
1295 case 3:
1296 subtype = "Engine/Coprocessor";
1297 break;
1298 case 4:
1299 subtype = "Bus";
1300 break;
1301 case 6:
1302 subtype = "Software";
1303 break;
1304 }
1305 break;
1306 case 4:
1307 major = "Debug Control";
1308 switch (minor) {
1309 case 0:
1310 subtype = "other";
1311 break;
1312 case 1:
1313 subtype = "Trigger Matrix";
1314 break;
1315 case 2:
1316 subtype = "Debug Auth";
1317 break;
1318 case 3:
1319 subtype = "Power Requestor";
1320 break;
1321 }
1322 break;
1323 case 5:
1324 major = "Debug Logic";
1325 switch (minor) {
1326 case 0:
1327 subtype = "other";
1328 break;
1329 case 1:
1330 subtype = "Processor";
1331 break;
1332 case 2:
1333 subtype = "DSP";
1334 break;
1335 case 3:
1336 subtype = "Engine/Coprocessor";
1337 break;
1338 case 4:
1339 subtype = "Bus";
1340 break;
1341 case 5:
1342 subtype = "Memory";
1343 break;
1344 }
1345 break;
1346 case 6:
1347 major = "Perfomance Monitor";
1348 switch (minor) {
1349 case 0:
1350 subtype = "other";
1351 break;
1352 case 1:
1353 subtype = "Processor";
1354 break;
1355 case 2:
1356 subtype = "DSP";
1357 break;
1358 case 3:
1359 subtype = "Engine/Coprocessor";
1360 break;
1361 case 4:
1362 subtype = "Bus";
1363 break;
1364 case 5:
1365 subtype = "Memory";
1366 break;
1367 }
1368 break;
1369 }
1370 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1371 (uint8_t)(devtype & 0xff),
1372 major, subtype);
1373 /* REVISIT also show 0xfc8 DevId */
1374 }
1375
1376 return ERROR_OK;
1377 }
1378
1379 static int dap_info_command(struct command_context *cmd_ctx,
1380 struct adiv5_ap *ap)
1381 {
1382 int retval;
1383 uint32_t dbgbase, apid;
1384 uint8_t mem_ap;
1385
1386 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1387 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1388 if (retval != ERROR_OK)
1389 return retval;
1390
1391 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1392 if (apid == 0) {
1393 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1394 return ERROR_FAIL;
1395 }
1396
1397 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1398 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1399 command_print(cmd_ctx, "\tType is JTAG-AP");
1400 break;
1401 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1402 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1403 break;
1404 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1405 command_print(cmd_ctx, "\tType is MEM-AP APB");
1406 break;
1407 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1408 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1409 break;
1410 default:
1411 command_print(cmd_ctx, "\tUnknown AP type");
1412 break;
1413 }
1414
1415 /* NOTE: a MEM-AP may have a single CoreSight component that's
1416 * not a ROM table ... or have no such components at all.
1417 */
1418 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1419 if (mem_ap) {
1420 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1421
1422 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1423 command_print(cmd_ctx, "\tNo ROM table present");
1424 } else {
1425 if (dbgbase & 0x01)
1426 command_print(cmd_ctx, "\tValid ROM table present");
1427 else
1428 command_print(cmd_ctx, "\tROM table in legacy format");
1429
1430 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1431 }
1432 }
1433
1434 return ERROR_OK;
1435 }
1436
1437 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1438 {
1439 struct adiv5_private_config *pc;
1440 const char *arg;
1441 jim_wide ap_num;
1442 int e;
1443
1444 /* check if argv[0] is for us */
1445 arg = Jim_GetString(goi->argv[0], NULL);
1446 if (strcmp(arg, "-ap-num"))
1447 return JIM_CONTINUE;
1448
1449 e = Jim_GetOpt_String(goi, &arg, NULL);
1450 if (e != JIM_OK)
1451 return e;
1452
1453 if (goi->argc == 0) {
1454 Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-ap-num ?ap-number? ...");
1455 return JIM_ERR;
1456 }
1457
1458 e = Jim_GetOpt_Wide(goi, &ap_num);
1459 if (e != JIM_OK)
1460 return e;
1461
1462 if (target->private_config == NULL) {
1463 pc = calloc(1, sizeof(struct adiv5_private_config));
1464 target->private_config = pc;
1465 pc->ap_num = ap_num;
1466 }
1467
1468
1469 return JIM_OK;
1470 }
1471
1472 COMMAND_HANDLER(handle_dap_info_command)
1473 {
1474 struct target *target = get_current_target(CMD_CTX);
1475 struct arm *arm = target_to_arm(target);
1476 struct adiv5_dap *dap = arm->dap;
1477 uint32_t apsel;
1478
1479 switch (CMD_ARGC) {
1480 case 0:
1481 apsel = dap->apsel;
1482 break;
1483 case 1:
1484 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1485 if (apsel >= 256)
1486 return ERROR_COMMAND_SYNTAX_ERROR;
1487 break;
1488 default:
1489 return ERROR_COMMAND_SYNTAX_ERROR;
1490 }
1491
1492 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1493 }
1494
1495 COMMAND_HANDLER(dap_baseaddr_command)
1496 {
1497 struct target *target = get_current_target(CMD_CTX);
1498 struct arm *arm = target_to_arm(target);
1499 struct adiv5_dap *dap = arm->dap;
1500
1501 uint32_t apsel, baseaddr;
1502 int retval;
1503
1504 switch (CMD_ARGC) {
1505 case 0:
1506 apsel = dap->apsel;
1507 break;
1508 case 1:
1509 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1510 /* AP address is in bits 31:24 of DP_SELECT */
1511 if (apsel >= 256)
1512 return ERROR_COMMAND_SYNTAX_ERROR;
1513 break;
1514 default:
1515 return ERROR_COMMAND_SYNTAX_ERROR;
1516 }
1517
1518 /* NOTE: assumes we're talking to a MEM-AP, which
1519 * has a base address. There are other kinds of AP,
1520 * though they're not common for now. This should
1521 * use the ID register to verify it's a MEM-AP.
1522 */
1523 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1524 if (retval != ERROR_OK)
1525 return retval;
1526 retval = dap_run(dap);
1527 if (retval != ERROR_OK)
1528 return retval;
1529
1530 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1531
1532 return retval;
1533 }
1534
1535 COMMAND_HANDLER(dap_memaccess_command)
1536 {
1537 struct target *target = get_current_target(CMD_CTX);
1538 struct arm *arm = target_to_arm(target);
1539 struct adiv5_dap *dap = arm->dap;
1540
1541 uint32_t memaccess_tck;
1542
1543 switch (CMD_ARGC) {
1544 case 0:
1545 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1546 break;
1547 case 1:
1548 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1549 break;
1550 default:
1551 return ERROR_COMMAND_SYNTAX_ERROR;
1552 }
1553 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1554
1555 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1556 dap->ap[dap->apsel].memaccess_tck);
1557
1558 return ERROR_OK;
1559 }
1560
1561 COMMAND_HANDLER(dap_apsel_command)
1562 {
1563 struct target *target = get_current_target(CMD_CTX);
1564 struct arm *arm = target_to_arm(target);
1565 struct adiv5_dap *dap = arm->dap;
1566
1567 uint32_t apsel, apid;
1568 int retval;
1569
1570 switch (CMD_ARGC) {
1571 case 0:
1572 apsel = dap->apsel;
1573 break;
1574 case 1:
1575 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1576 /* AP address is in bits 31:24 of DP_SELECT */
1577 if (apsel >= 256)
1578 return ERROR_COMMAND_SYNTAX_ERROR;
1579 break;
1580 default:
1581 return ERROR_COMMAND_SYNTAX_ERROR;
1582 }
1583
1584 dap->apsel = apsel;
1585
1586 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1587 if (retval != ERROR_OK)
1588 return retval;
1589 retval = dap_run(dap);
1590 if (retval != ERROR_OK)
1591 return retval;
1592
1593 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1594 apsel, apid);
1595
1596 return retval;
1597 }
1598
1599 COMMAND_HANDLER(dap_apcsw_command)
1600 {
1601 struct target *target = get_current_target(CMD_CTX);
1602 struct arm *arm = target_to_arm(target);
1603 struct adiv5_dap *dap = arm->dap;
1604
1605 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1606
1607 switch (CMD_ARGC) {
1608 case 0:
1609 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1610 (dap->apsel), apcsw);
1611 break;
1612 case 1:
1613 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1614 /* AP address is in bits 31:24 of DP_SELECT */
1615 if (sprot > 1)
1616 return ERROR_COMMAND_SYNTAX_ERROR;
1617 if (sprot)
1618 apcsw |= CSW_SPROT;
1619 else
1620 apcsw &= ~CSW_SPROT;
1621 break;
1622 default:
1623 return ERROR_COMMAND_SYNTAX_ERROR;
1624 }
1625 dap->ap[dap->apsel].csw_default = apcsw;
1626
1627 return 0;
1628 }
1629
1630
1631
1632 COMMAND_HANDLER(dap_apid_command)
1633 {
1634 struct target *target = get_current_target(CMD_CTX);
1635 struct arm *arm = target_to_arm(target);
1636 struct adiv5_dap *dap = arm->dap;
1637
1638 uint32_t apsel, apid;
1639 int retval;
1640
1641 switch (CMD_ARGC) {
1642 case 0:
1643 apsel = dap->apsel;
1644 break;
1645 case 1:
1646 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1647 /* AP address is in bits 31:24 of DP_SELECT */
1648 if (apsel >= 256)
1649 return ERROR_COMMAND_SYNTAX_ERROR;
1650 break;
1651 default:
1652 return ERROR_COMMAND_SYNTAX_ERROR;
1653 }
1654
1655 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1656 if (retval != ERROR_OK)
1657 return retval;
1658 retval = dap_run(dap);
1659 if (retval != ERROR_OK)
1660 return retval;
1661
1662 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1663
1664 return retval;
1665 }
1666
1667 COMMAND_HANDLER(dap_apreg_command)
1668 {
1669 struct target *target = get_current_target(CMD_CTX);
1670 struct arm *arm = target_to_arm(target);
1671 struct adiv5_dap *dap = arm->dap;
1672
1673 uint32_t apsel, reg, value;
1674 int retval;
1675
1676 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1677 return ERROR_COMMAND_SYNTAX_ERROR;
1678
1679 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1680 /* AP address is in bits 31:24 of DP_SELECT */
1681 if (apsel >= 256)
1682 return ERROR_COMMAND_SYNTAX_ERROR;
1683
1684 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1685 if (reg >= 256 || (reg & 3))
1686 return ERROR_COMMAND_SYNTAX_ERROR;
1687
1688 if (CMD_ARGC == 3) {
1689 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1690 retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
1691 } else {
1692 retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
1693 }
1694 if (retval == ERROR_OK)
1695 retval = dap_run(dap);
1696
1697 if (retval != ERROR_OK)
1698 return retval;
1699
1700 if (CMD_ARGC == 2)
1701 command_print(CMD_CTX, "0x%08" PRIx32, value);
1702
1703 return retval;
1704 }
1705
1706 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1707 {
1708 struct target *target = get_current_target(CMD_CTX);
1709 struct arm *arm = target_to_arm(target);
1710 struct adiv5_dap *dap = arm->dap;
1711
1712 uint32_t enable = dap->ti_be_32_quirks;
1713
1714 switch (CMD_ARGC) {
1715 case 0:
1716 break;
1717 case 1:
1718 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1719 if (enable > 1)
1720 return ERROR_COMMAND_SYNTAX_ERROR;
1721 break;
1722 default:
1723 return ERROR_COMMAND_SYNTAX_ERROR;
1724 }
1725 dap->ti_be_32_quirks = enable;
1726 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1727 enable ? "enabled" : "disabled");
1728
1729 return 0;
1730 }
1731
1732 static const struct command_registration dap_commands[] = {
1733 {
1734 .name = "info",
1735 .handler = handle_dap_info_command,
1736 .mode = COMMAND_EXEC,
1737 .help = "display ROM table for MEM-AP "
1738 "(default currently selected AP)",
1739 .usage = "[ap_num]",
1740 },
1741 {
1742 .name = "apsel",
1743 .handler = dap_apsel_command,
1744 .mode = COMMAND_EXEC,
1745 .help = "Set the currently selected AP (default 0) "
1746 "and display the result",
1747 .usage = "[ap_num]",
1748 },
1749 {
1750 .name = "apcsw",
1751 .handler = dap_apcsw_command,
1752 .mode = COMMAND_EXEC,
1753 .help = "Set csw access bit ",
1754 .usage = "[sprot]",
1755 },
1756
1757 {
1758 .name = "apid",
1759 .handler = dap_apid_command,
1760 .mode = COMMAND_EXEC,
1761 .help = "return ID register from AP "
1762 "(default currently selected AP)",
1763 .usage = "[ap_num]",
1764 },
1765 {
1766 .name = "apreg",
1767 .handler = dap_apreg_command,
1768 .mode = COMMAND_EXEC,
1769 .help = "read/write a register from AP "
1770 "(reg is byte address of a word register, like 0 4 8...)",
1771 .usage = "ap_num reg [value]",
1772 },
1773 {
1774 .name = "baseaddr",
1775 .handler = dap_baseaddr_command,
1776 .mode = COMMAND_EXEC,
1777 .help = "return debug base address from MEM-AP "
1778 "(default currently selected AP)",
1779 .usage = "[ap_num]",
1780 },
1781 {
1782 .name = "memaccess",
1783 .handler = dap_memaccess_command,
1784 .mode = COMMAND_EXEC,
1785 .help = "set/get number of extra tck for MEM-AP memory "
1786 "bus access [0-255]",
1787 .usage = "[cycles]",
1788 },
1789 {
1790 .name = "ti_be_32_quirks",
1791 .handler = dap_ti_be_32_quirks_command,
1792 .mode = COMMAND_CONFIG,
1793 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1794 .usage = "[enable]",
1795 },
1796 COMMAND_REGISTRATION_DONE
1797 };
1798
1799 const struct command_registration dap_command_handlers[] = {
1800 {
1801 .name = "dap",
1802 .mode = COMMAND_EXEC,
1803 .help = "DAP command group",
1804 .usage = "",
1805 .chain = dap_commands,
1806 },
1807 COMMAND_REGISTRATION_DONE
1808 };