1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
72 #include "jtag/interface.h"
74 #include "arm_adi_v5.h"
75 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
85 return (tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
)) >> 2;
88 /***************************************************************************
90 * DP and MEM-AP register access through APACC and DPACC *
92 ***************************************************************************/
95 * Select one of the APs connected to the specified DAP. The
96 * selection is implicitly used with future AP transactions.
97 * This is a NOP if the specified AP is already selected.
100 * @param apsel Number of the AP to (implicitly) use with further
101 * transactions. This normally identifies a MEM-AP.
103 void dap_ap_select(struct adiv5_dap
*dap
, uint8_t ap
)
105 uint32_t new_ap
= (ap
<< 24) & 0xFF000000;
107 if (new_ap
!= dap
->ap_current
) {
108 dap
->ap_current
= new_ap
;
109 /* Switching AP invalidates cached values.
110 * Values MUST BE UPDATED BEFORE AP ACCESS.
112 dap
->ap_bank_value
= -1;
113 dap
->ap_csw_value
= -1;
114 dap
->ap_tar_value
= -1;
119 * Queue transactions setting up transfer parameters for the
120 * currently selected MEM-AP.
122 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
123 * initiate data reads or writes using memory or peripheral addresses.
124 * If the CSW is configured for it, the TAR may be automatically
125 * incremented after each transfer.
127 * @todo Rename to reflect it being specifically a MEM-AP function.
129 * @param dap The DAP connected to the MEM-AP.
130 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
131 * matches the cached value, the register is not changed.
132 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
133 * matches the cached address, the register is not changed.
135 * @return ERROR_OK if the transaction was properly queued, else a fault code.
137 int dap_setup_accessport(struct adiv5_dap
*dap
, uint32_t csw
, uint32_t tar
)
141 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
;
142 if (csw
!= dap
->ap_csw_value
) {
143 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
144 retval
= dap_queue_ap_write(dap
, AP_REG_CSW
, csw
);
145 if (retval
!= ERROR_OK
)
147 dap
->ap_csw_value
= csw
;
149 if (tar
!= dap
->ap_tar_value
) {
150 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
151 retval
= dap_queue_ap_write(dap
, AP_REG_TAR
, tar
);
152 if (retval
!= ERROR_OK
)
154 dap
->ap_tar_value
= tar
;
156 /* Disable TAR cache when autoincrementing */
157 if (csw
& CSW_ADDRINC_MASK
)
158 dap
->ap_tar_value
= -1;
163 * Asynchronous (queued) read of a word from memory or a system register.
165 * @param dap The DAP connected to the MEM-AP performing the read.
166 * @param address Address of the 32-bit word to read; it must be
167 * readable by the currently selected MEM-AP.
168 * @param value points to where the word will be stored when the
169 * transaction queue is flushed (assuming no errors).
171 * @return ERROR_OK for success. Otherwise a fault code.
173 int mem_ap_read_u32(struct adiv5_dap
*dap
, uint32_t address
,
178 /* Use banked addressing (REG_BDx) to avoid some link traffic
179 * (updating TAR) when reading several consecutive addresses.
181 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
182 address
& 0xFFFFFFF0);
183 if (retval
!= ERROR_OK
)
186 return dap_queue_ap_read(dap
, AP_REG_BD0
| (address
& 0xC), value
);
190 * Synchronous read of a word from memory or a system register.
191 * As a side effect, this flushes any queued transactions.
193 * @param dap The DAP connected to the MEM-AP performing the read.
194 * @param address Address of the 32-bit word to read; it must be
195 * readable by the currently selected MEM-AP.
196 * @param value points to where the result will be stored.
198 * @return ERROR_OK for success; *value holds the result.
199 * Otherwise a fault code.
201 int mem_ap_read_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
206 retval
= mem_ap_read_u32(dap
, address
, value
);
207 if (retval
!= ERROR_OK
)
214 * Asynchronous (queued) write of a word to memory or a system register.
216 * @param dap The DAP connected to the MEM-AP.
217 * @param address Address to be written; it must be writable by
218 * the currently selected MEM-AP.
219 * @param value Word that will be written to the address when transaction
220 * queue is flushed (assuming no errors).
222 * @return ERROR_OK for success. Otherwise a fault code.
224 int mem_ap_write_u32(struct adiv5_dap
*dap
, uint32_t address
,
229 /* Use banked addressing (REG_BDx) to avoid some link traffic
230 * (updating TAR) when writing several consecutive addresses.
232 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
233 address
& 0xFFFFFFF0);
234 if (retval
!= ERROR_OK
)
237 return dap_queue_ap_write(dap
, AP_REG_BD0
| (address
& 0xC),
242 * Synchronous write of a word to memory or a system register.
243 * As a side effect, this flushes any queued transactions.
245 * @param dap The DAP connected to the MEM-AP.
246 * @param address Address to be written; it must be writable by
247 * the currently selected MEM-AP.
248 * @param value Word that will be written.
250 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
252 int mem_ap_write_atomic_u32(struct adiv5_dap
*dap
, uint32_t address
,
255 int retval
= mem_ap_write_u32(dap
, address
, value
);
257 if (retval
!= ERROR_OK
)
263 /*****************************************************************************
265 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
267 * Write a buffer in target order (little endian) *
269 *****************************************************************************/
270 int mem_ap_write_buf_u32(struct adiv5_dap
*dap
, const uint8_t *buffer
, int count
, uint32_t address
)
272 int wcount
, blocksize
, writecount
, errorcount
= 0, retval
= ERROR_OK
;
273 uint32_t adr
= address
;
274 const uint8_t *pBuffer
= buffer
;
279 /* if we have an unaligned access - reorder data */
281 for (writecount
= 0; writecount
< count
; writecount
++) {
284 memcpy(&outvalue
, pBuffer
, sizeof(uint32_t));
286 for (i
= 0; i
< 4; i
++) {
287 *((uint8_t *)pBuffer
+ (adr
& 0x3)) = outvalue
;
291 pBuffer
+= sizeof(uint32_t);
296 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
297 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
298 if (wcount
< blocksize
)
301 /* handle unaligned data at 4k boundary */
305 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_SINGLE
, address
);
306 if (retval
!= ERROR_OK
)
309 for (writecount
= 0; writecount
< blocksize
; writecount
++) {
311 tmp
= buf_get_u32(buffer
+ 4 * writecount
, 0, 32);
312 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, tmp
);
313 if (retval
!= ERROR_OK
)
317 retval
= dap_run(dap
);
318 if (retval
== ERROR_OK
) {
319 wcount
= wcount
- blocksize
;
320 address
= address
+ 4 * blocksize
;
321 buffer
= buffer
+ 4 * blocksize
;
325 if (errorcount
> 1) {
326 LOG_WARNING("Block write error address 0x%" PRIx32
", wcount 0x%x", address
, wcount
);
334 static int mem_ap_write_buf_packed_u16(struct adiv5_dap
*dap
,
335 const uint8_t *buffer
, int count
, uint32_t address
)
337 int retval
= ERROR_OK
;
338 int wcount
, blocksize
, writecount
, i
;
345 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
346 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
348 if (wcount
< blocksize
)
351 /* handle unaligned data at 4k boundary */
355 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
356 if (retval
!= ERROR_OK
)
358 writecount
= blocksize
;
361 nbytes
= MIN((writecount
<< 1), 4);
364 retval
= mem_ap_write_buf_u16(dap
, buffer
,
366 if (retval
!= ERROR_OK
) {
367 LOG_WARNING("Block write error address "
368 "0x%" PRIx32
", count 0x%x",
373 address
+= nbytes
>> 1;
376 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
378 for (i
= 0; i
< nbytes
; i
++) {
379 *((uint8_t *)buffer
+ (address
& 0x3)) = outvalue
;
384 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
385 retval
= dap_queue_ap_write(dap
,
386 AP_REG_DRW
, outvalue
);
387 if (retval
!= ERROR_OK
)
390 retval
= dap_run(dap
);
391 if (retval
!= ERROR_OK
) {
392 LOG_WARNING("Block write error address "
393 "0x%" PRIx32
", count 0x%x",
399 buffer
+= nbytes
>> 1;
400 writecount
-= nbytes
>> 1;
402 } while (writecount
);
409 int mem_ap_write_buf_u16(struct adiv5_dap
*dap
, const uint8_t *buffer
, int count
, uint32_t address
)
411 int retval
= ERROR_OK
;
414 return mem_ap_write_buf_packed_u16(dap
, buffer
, count
, address
);
417 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
418 if (retval
!= ERROR_OK
)
421 memcpy(&svalue
, buffer
, sizeof(uint16_t));
422 uint32_t outvalue
= (uint32_t)svalue
<< 8 * (address
& 0x3);
423 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, outvalue
);
424 if (retval
!= ERROR_OK
)
427 retval
= dap_run(dap
);
428 if (retval
!= ERROR_OK
)
439 static int mem_ap_write_buf_packed_u8(struct adiv5_dap
*dap
,
440 const uint8_t *buffer
, int count
, uint32_t address
)
442 int retval
= ERROR_OK
;
443 int wcount
, blocksize
, writecount
, i
;
450 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
451 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
453 if (wcount
< blocksize
)
456 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
457 if (retval
!= ERROR_OK
)
459 writecount
= blocksize
;
462 nbytes
= MIN(writecount
, 4);
465 retval
= mem_ap_write_buf_u8(dap
, buffer
, nbytes
, address
);
466 if (retval
!= ERROR_OK
) {
467 LOG_WARNING("Block write error address "
468 "0x%" PRIx32
", count 0x%x",
476 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
478 for (i
= 0; i
< nbytes
; i
++) {
479 *((uint8_t *)buffer
+ (address
& 0x3)) = outvalue
;
484 memcpy(&outvalue
, buffer
, sizeof(uint32_t));
485 retval
= dap_queue_ap_write(dap
,
486 AP_REG_DRW
, outvalue
);
487 if (retval
!= ERROR_OK
)
490 retval
= dap_run(dap
);
491 if (retval
!= ERROR_OK
) {
492 LOG_WARNING("Block write error address "
493 "0x%" PRIx32
", count 0x%x",
500 writecount
-= nbytes
;
502 } while (writecount
);
509 int mem_ap_write_buf_u8(struct adiv5_dap
*dap
, const uint8_t *buffer
, int count
, uint32_t address
)
511 int retval
= ERROR_OK
;
514 return mem_ap_write_buf_packed_u8(dap
, buffer
, count
, address
);
517 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
518 if (retval
!= ERROR_OK
)
520 uint32_t outvalue
= (uint32_t)*buffer
<< 8 * (address
& 0x3);
521 retval
= dap_queue_ap_write(dap
, AP_REG_DRW
, outvalue
);
522 if (retval
!= ERROR_OK
)
525 retval
= dap_run(dap
);
526 if (retval
!= ERROR_OK
)
537 /* FIXME don't import ... this is a temporary workaround for the
538 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
540 extern int adi_jtag_dp_scan(struct adiv5_dap
*dap
,
541 uint8_t instr
, uint8_t reg_addr
, uint8_t RnW
,
542 uint8_t *outvalue
, uint8_t *invalue
, uint8_t *ack
);
545 * Synchronously read a block of 32-bit words into a buffer
546 * @param dap The DAP connected to the MEM-AP.
547 * @param buffer where the words will be stored (in host byte order).
548 * @param count How many words to read.
549 * @param address Memory address from which to read words; all the
550 * words must be readable by the currently selected MEM-AP.
552 int mem_ap_read_buf_u32(struct adiv5_dap
*dap
, uint8_t *buffer
,
553 int count
, uint32_t address
)
555 int wcount
, blocksize
, readcount
, errorcount
= 0, retval
= ERROR_OK
;
556 uint32_t adr
= address
;
557 uint8_t *pBuffer
= buffer
;
563 /* Adjust to read blocks within boundaries aligned to the
564 * TAR autoincrement size (at least 2^10). Autoincrement
565 * mode avoids an extra per-word roundtrip to update TAR.
567 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
,
569 if (wcount
< blocksize
)
572 /* handle unaligned data at 4k boundary */
576 retval
= dap_setup_accessport(dap
, CSW_32BIT
| CSW_ADDRINC_SINGLE
,
578 if (retval
!= ERROR_OK
)
581 /* FIXME remove these three calls to adi_jtag_dp_scan(),
582 * so this routine becomes transport-neutral. Be careful
583 * not to cause performance problems with JTAG; would it
584 * suffice to loop over dap_queue_ap_read(), or would that
585 * be slower when JTAG is the chosen transport?
588 /* Scan out first read */
589 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, AP_REG_DRW
,
590 DPAP_READ
, 0, NULL
, NULL
);
591 if (retval
!= ERROR_OK
)
593 for (readcount
= 0; readcount
< blocksize
- 1; readcount
++) {
594 /* Scan out next read; scan in posted value for the
595 * previous one. Assumes read is acked "OK/FAULT",
596 * and CTRL_STAT says that meant "OK".
598 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_APACC
, AP_REG_DRW
,
599 DPAP_READ
, 0, buffer
+ 4 * readcount
,
601 if (retval
!= ERROR_OK
)
605 /* Scan in last posted value; RDBUFF has no other effect,
606 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
608 retval
= adi_jtag_dp_scan(dap
, JTAG_DP_DPACC
, DP_RDBUFF
,
609 DPAP_READ
, 0, buffer
+ 4 * readcount
,
611 if (retval
!= ERROR_OK
)
614 retval
= dap_run(dap
);
615 if (retval
!= ERROR_OK
) {
617 if (errorcount
<= 1) {
621 LOG_WARNING("Block read error address 0x%" PRIx32
, address
);
624 wcount
= wcount
- blocksize
;
625 address
+= 4 * blocksize
;
626 buffer
+= 4 * blocksize
;
629 /* if we have an unaligned access - reorder data */
631 for (readcount
= 0; readcount
< count
; readcount
++) {
634 memcpy(&data
, pBuffer
, sizeof(uint32_t));
636 for (i
= 0; i
< 4; i
++) {
637 *((uint8_t *)pBuffer
) =
638 (data
>> 8 * (adr
& 0x3));
648 static int mem_ap_read_buf_packed_u16(struct adiv5_dap
*dap
,
649 uint8_t *buffer
, int count
, uint32_t address
)
652 int retval
= ERROR_OK
;
653 int wcount
, blocksize
, readcount
, i
;
660 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
661 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
662 if (wcount
< blocksize
)
665 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_PACKED
, address
);
666 if (retval
!= ERROR_OK
)
669 /* handle unaligned data at 4k boundary */
672 readcount
= blocksize
;
675 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
676 if (retval
!= ERROR_OK
)
678 retval
= dap_run(dap
);
679 if (retval
!= ERROR_OK
) {
680 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
684 nbytes
= MIN((readcount
<< 1), 4);
686 for (i
= 0; i
< nbytes
; i
++) {
687 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
692 readcount
-= (nbytes
>> 1);
701 * Synchronously read a block of 16-bit halfwords into a buffer
702 * @param dap The DAP connected to the MEM-AP.
703 * @param buffer where the halfwords will be stored (in host byte order).
704 * @param count How many halfwords to read.
705 * @param address Memory address from which to read words; all the
706 * words must be readable by the currently selected MEM-AP.
708 int mem_ap_read_buf_u16(struct adiv5_dap
*dap
, uint8_t *buffer
,
709 int count
, uint32_t address
)
712 int retval
= ERROR_OK
;
715 return mem_ap_read_buf_packed_u16(dap
, buffer
, count
, address
);
718 retval
= dap_setup_accessport(dap
, CSW_16BIT
| CSW_ADDRINC_SINGLE
, address
);
719 if (retval
!= ERROR_OK
)
721 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
722 if (retval
!= ERROR_OK
)
725 retval
= dap_run(dap
);
726 if (retval
!= ERROR_OK
)
730 for (i
= 0; i
< 2; i
++) {
731 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
736 uint16_t svalue
= (invalue
>> 8 * (address
& 0x3));
737 memcpy(buffer
, &svalue
, sizeof(uint16_t));
747 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
748 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
750 * The solution is to arrange for a large out/in scan in this loop and
751 * and convert data afterwards.
753 static int mem_ap_read_buf_packed_u8(struct adiv5_dap
*dap
,
754 uint8_t *buffer
, int count
, uint32_t address
)
757 int retval
= ERROR_OK
;
758 int wcount
, blocksize
, readcount
, i
;
765 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
766 blocksize
= max_tar_block_size(dap
->tar_autoincr_block
, address
);
768 if (wcount
< blocksize
)
771 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, address
);
772 if (retval
!= ERROR_OK
)
774 readcount
= blocksize
;
777 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
778 if (retval
!= ERROR_OK
)
780 retval
= dap_run(dap
);
781 if (retval
!= ERROR_OK
) {
782 LOG_WARNING("Block read error address 0x%" PRIx32
", count 0x%x", address
, count
);
786 nbytes
= MIN(readcount
, 4);
788 for (i
= 0; i
< nbytes
; i
++) {
789 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
803 * Synchronously read a block of bytes into a buffer
804 * @param dap The DAP connected to the MEM-AP.
805 * @param buffer where the bytes will be stored.
806 * @param count How many bytes to read.
807 * @param address Memory address from which to read data; all the
808 * data must be readable by the currently selected MEM-AP.
810 int mem_ap_read_buf_u8(struct adiv5_dap
*dap
, uint8_t *buffer
,
811 int count
, uint32_t address
)
814 int retval
= ERROR_OK
;
817 return mem_ap_read_buf_packed_u8(dap
, buffer
, count
, address
);
820 retval
= dap_setup_accessport(dap
, CSW_8BIT
| CSW_ADDRINC_SINGLE
, address
);
821 if (retval
!= ERROR_OK
)
823 retval
= dap_queue_ap_read(dap
, AP_REG_DRW
, &invalue
);
824 if (retval
!= ERROR_OK
)
826 retval
= dap_run(dap
);
827 if (retval
!= ERROR_OK
)
830 *((uint8_t *)buffer
) = (invalue
>> 8 * (address
& 0x3));
839 /*--------------------------------------------------------------------*/
840 /* Wrapping function with selection of AP */
841 /*--------------------------------------------------------------------*/
842 int mem_ap_sel_read_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
843 uint32_t address
, uint32_t *value
)
845 dap_ap_select(swjdp
, ap
);
846 return mem_ap_read_u32(swjdp
, address
, value
);
849 int mem_ap_sel_write_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
850 uint32_t address
, uint32_t value
)
852 dap_ap_select(swjdp
, ap
);
853 return mem_ap_write_u32(swjdp
, address
, value
);
856 int mem_ap_sel_read_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
857 uint32_t address
, uint32_t *value
)
859 dap_ap_select(swjdp
, ap
);
860 return mem_ap_read_atomic_u32(swjdp
, address
, value
);
863 int mem_ap_sel_write_atomic_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
864 uint32_t address
, uint32_t value
)
866 dap_ap_select(swjdp
, ap
);
867 return mem_ap_write_atomic_u32(swjdp
, address
, value
);
870 int mem_ap_sel_read_buf_u8(struct adiv5_dap
*swjdp
, uint8_t ap
,
871 uint8_t *buffer
, int count
, uint32_t address
)
873 dap_ap_select(swjdp
, ap
);
874 return mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
877 int mem_ap_sel_read_buf_u16(struct adiv5_dap
*swjdp
, uint8_t ap
,
878 uint8_t *buffer
, int count
, uint32_t address
)
880 dap_ap_select(swjdp
, ap
);
881 return mem_ap_read_buf_u16(swjdp
, buffer
, count
, address
);
884 int mem_ap_sel_read_buf_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
885 uint8_t *buffer
, int count
, uint32_t address
)
887 dap_ap_select(swjdp
, ap
);
888 return mem_ap_read_buf_u32(swjdp
, buffer
, count
, address
);
891 int mem_ap_sel_write_buf_u8(struct adiv5_dap
*swjdp
, uint8_t ap
,
892 const uint8_t *buffer
, int count
, uint32_t address
)
894 dap_ap_select(swjdp
, ap
);
895 return mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
898 int mem_ap_sel_write_buf_u16(struct adiv5_dap
*swjdp
, uint8_t ap
,
899 const uint8_t *buffer
, int count
, uint32_t address
)
901 dap_ap_select(swjdp
, ap
);
902 return mem_ap_write_buf_u16(swjdp
, buffer
, count
, address
);
905 int mem_ap_sel_write_buf_u32(struct adiv5_dap
*swjdp
, uint8_t ap
,
906 const uint8_t *buffer
, int count
, uint32_t address
)
908 dap_ap_select(swjdp
, ap
);
909 return mem_ap_write_buf_u32(swjdp
, buffer
, count
, address
);
912 #define MDM_REG_STAT 0x00
913 #define MDM_REG_CTRL 0x04
914 #define MDM_REG_ID 0xfc
916 #define MDM_STAT_FMEACK (1<<0)
917 #define MDM_STAT_FREADY (1<<1)
918 #define MDM_STAT_SYSSEC (1<<2)
919 #define MDM_STAT_SYSRES (1<<3)
920 #define MDM_STAT_FMEEN (1<<5)
921 #define MDM_STAT_BACKDOOREN (1<<6)
922 #define MDM_STAT_LPEN (1<<7)
923 #define MDM_STAT_VLPEN (1<<8)
924 #define MDM_STAT_LLSMODEXIT (1<<9)
925 #define MDM_STAT_VLLSXMODEXIT (1<<10)
926 #define MDM_STAT_CORE_HALTED (1<<16)
927 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
928 #define MDM_STAT_CORESLEEPING (1<<18)
930 #define MEM_CTRL_FMEIP (1<<0)
931 #define MEM_CTRL_DBG_DIS (1<<1)
932 #define MEM_CTRL_DBG_REQ (1<<2)
933 #define MEM_CTRL_SYS_RES_REQ (1<<3)
934 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
935 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
936 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
937 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
942 int dap_syssec_kinetis_mdmap(struct adiv5_dap
*dap
)
946 enum reset_types jtag_reset_config
= jtag_get_reset_config();
948 dap_ap_select(dap
, 1);
950 /* first check mdm-ap id register */
951 retval
= dap_queue_ap_read(dap
, MDM_REG_ID
, &val
);
952 if (retval
!= ERROR_OK
)
956 if (val
!= 0x001C0000) {
957 LOG_DEBUG("id doesn't match %08X != 0x001C0000", val
);
958 dap_ap_select(dap
, 0);
962 /* read and parse status register
963 * it's important that the device is out of
966 retval
= dap_queue_ap_read(dap
, MDM_REG_STAT
, &val
);
967 if (retval
!= ERROR_OK
)
971 LOG_DEBUG("MDM_REG_STAT %08X", val
);
973 if ((val
& (MDM_STAT_SYSSEC
|MDM_STAT_FREADY
)) != (MDM_STAT_FREADY
)) {
974 LOG_DEBUG("MDMAP: system is secured, masserase needed");
976 if (!(val
& MDM_STAT_FMEEN
))
977 LOG_DEBUG("MDMAP: masserase is disabled");
979 /* we need to assert reset */
980 if (jtag_reset_config
& RESET_HAS_SRST
) {
981 /* default to asserting srst */
982 adapter_assert_reset();
984 LOG_DEBUG("SRST not configured");
985 dap_ap_select(dap
, 0);
990 retval
= dap_queue_ap_write(dap
, MDM_REG_CTRL
, MEM_CTRL_FMEIP
);
991 if (retval
!= ERROR_OK
)
994 /* read status register and wait for ready */
995 retval
= dap_queue_ap_read(dap
, MDM_REG_STAT
, &val
);
996 if (retval
!= ERROR_OK
)
999 LOG_DEBUG("MDM_REG_STAT %08X", val
);
1006 retval
= dap_queue_ap_write(dap
, MDM_REG_CTRL
, 0);
1007 if (retval
!= ERROR_OK
)
1010 /* read status register */
1011 retval
= dap_queue_ap_read(dap
, MDM_REG_STAT
, &val
);
1012 if (retval
!= ERROR_OK
)
1015 LOG_DEBUG("MDM_REG_STAT %08X", val
);
1016 /* read control register and wait for ready */
1017 retval
= dap_queue_ap_read(dap
, MDM_REG_CTRL
, &val
);
1018 if (retval
!= ERROR_OK
)
1021 LOG_DEBUG("MDM_REG_CTRL %08X", val
);
1029 dap_ap_select(dap
, 0);
1035 struct dap_syssec_filter
{
1039 int (*dap_init
)(struct adiv5_dap
*dap
);
1043 static struct dap_syssec_filter dap_syssec_filter_data
[] = {
1044 { 0x4BA00477, dap_syssec_kinetis_mdmap
}
1050 int dap_syssec(struct adiv5_dap
*dap
)
1053 struct jtag_tap
*tap
;
1055 for (i
= 0; i
< sizeof(dap_syssec_filter_data
); i
++) {
1056 tap
= dap
->jtag_info
->tap
;
1058 while (tap
!= NULL
) {
1059 if (tap
->hasidcode
&& (dap_syssec_filter_data
[i
].idcode
== tap
->idcode
)) {
1060 LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap
->idcode
);
1061 dap_syssec_filter_data
[i
].dap_init(dap
);
1063 tap
= tap
->next_tap
;
1070 /*--------------------------------------------------------------------------*/
1073 /* FIXME don't import ... just initialize as
1074 * part of DAP transport setup
1076 extern const struct dap_ops jtag_dp_ops
;
1078 /*--------------------------------------------------------------------------*/
1081 * Initialize a DAP. This sets up the power domains, prepares the DP
1082 * for further use, and arranges to use AP #0 for all AP operations
1083 * until dap_ap-select() changes that policy.
1085 * @param dap The DAP being initialized.
1087 * @todo Rename this. We also need an initialization scheme which account
1088 * for SWD transports not just JTAG; that will need to address differences
1089 * in layering. (JTAG is useful without any debug target; but not SWD.)
1090 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1092 int ahbap_debugport_init(struct adiv5_dap
*dap
)
1100 /* JTAG-DP or SWJ-DP, in JTAG mode
1101 * ... for SWD mode this is patched as part
1102 * of link switchover
1105 dap
->ops
= &jtag_dp_ops
;
1107 /* Default MEM-AP setup.
1109 * REVISIT AP #0 may be an inappropriate default for this.
1110 * Should we probe, or take a hint from the caller?
1111 * Presumably we can ignore the possibility of multiple APs.
1113 dap
->ap_current
= !0;
1114 dap_ap_select(dap
, 0);
1116 /* DP initialization */
1118 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1119 if (retval
!= ERROR_OK
)
1122 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, SSTICKYERR
);
1123 if (retval
!= ERROR_OK
)
1126 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1127 if (retval
!= ERROR_OK
)
1130 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
1131 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
1132 if (retval
!= ERROR_OK
)
1135 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
1136 if (retval
!= ERROR_OK
)
1138 retval
= dap_run(dap
);
1139 if (retval
!= ERROR_OK
)
1142 /* Check that we have debug power domains activated */
1143 while (!(ctrlstat
& CDBGPWRUPACK
) && (cnt
++ < 10)) {
1144 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1145 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
1146 if (retval
!= ERROR_OK
)
1148 retval
= dap_run(dap
);
1149 if (retval
!= ERROR_OK
)
1154 while (!(ctrlstat
& CSYSPWRUPACK
) && (cnt
++ < 10)) {
1155 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1156 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, &ctrlstat
);
1157 if (retval
!= ERROR_OK
)
1159 retval
= dap_run(dap
);
1160 if (retval
!= ERROR_OK
)
1165 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1166 if (retval
!= ERROR_OK
)
1168 /* With debug power on we can activate OVERRUN checking */
1169 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
1170 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
1171 if (retval
!= ERROR_OK
)
1173 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
1174 if (retval
!= ERROR_OK
)
1182 /* CID interpretation -- see ARM IHI 0029B section 3
1183 * and ARM IHI 0031A table 13-3.
1185 static const char *class_description
[16] = {
1186 "Reserved", "ROM table", "Reserved", "Reserved",
1187 "Reserved", "Reserved", "Reserved", "Reserved",
1188 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1189 "Reserved", "OptimoDE DESS",
1190 "Generic IP component", "PrimeCell or System component"
1193 static bool is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
1195 return cid3
== 0xb1 && cid2
== 0x05
1196 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
1199 int dap_get_debugbase(struct adiv5_dap
*dap
, int ap
,
1200 uint32_t *out_dbgbase
, uint32_t *out_apid
)
1204 uint32_t dbgbase
, apid
;
1206 /* AP address is in bits 31:24 of DP_SELECT */
1208 return ERROR_COMMAND_SYNTAX_ERROR
;
1210 ap_old
= dap
->ap_current
;
1211 dap_ap_select(dap
, ap
);
1213 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &dbgbase
);
1214 if (retval
!= ERROR_OK
)
1216 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1217 if (retval
!= ERROR_OK
)
1219 retval
= dap_run(dap
);
1220 if (retval
!= ERROR_OK
)
1223 /* Excavate the device ID code */
1224 struct jtag_tap
*tap
= dap
->jtag_info
->tap
;
1225 while (tap
!= NULL
) {
1228 tap
= tap
->next_tap
;
1230 if (tap
== NULL
|| !tap
->hasidcode
)
1233 dap_ap_select(dap
, ap_old
);
1235 /* The asignment happens only here to prevent modification of these
1236 * values before they are certain. */
1237 *out_dbgbase
= dbgbase
;
1243 int dap_lookup_cs_component(struct adiv5_dap
*dap
, int ap
,
1244 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
)
1247 uint32_t romentry
, entry_offset
= 0, component_base
, devtype
;
1248 int retval
= ERROR_FAIL
;
1251 return ERROR_COMMAND_SYNTAX_ERROR
;
1253 ap_old
= dap
->ap_current
;
1254 dap_ap_select(dap
, ap
);
1257 retval
= mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) |
1258 entry_offset
, &romentry
);
1259 if (retval
!= ERROR_OK
)
1262 component_base
= (dbgbase
& 0xFFFFF000)
1263 + (romentry
& 0xFFFFF000);
1265 if (romentry
& 0x1) {
1266 retval
= mem_ap_read_atomic_u32(dap
,
1267 (component_base
& 0xfffff000) | 0xfcc,
1269 if (retval
!= ERROR_OK
)
1271 if ((devtype
& 0xff) == type
) {
1272 *addr
= component_base
;
1278 } while (romentry
> 0);
1280 dap_ap_select(dap
, ap_old
);
1285 static int dap_info_command(struct command_context
*cmd_ctx
,
1286 struct adiv5_dap
*dap
, int ap
)
1289 uint32_t dbgbase
= 0, apid
= 0; /* Silence gcc by initializing */
1290 int romtable_present
= 0;
1294 retval
= dap_get_debugbase(dap
, ap
, &dbgbase
, &apid
);
1295 if (retval
!= ERROR_OK
)
1298 ap_old
= dap
->ap_current
;
1299 dap_ap_select(dap
, ap
);
1301 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1302 mem_ap
= ((apid
&0x10000) && ((apid
&0x0F) != 0));
1303 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1305 switch (apid
&0x0F) {
1307 command_print(cmd_ctx
, "\tType is JTAG-AP");
1310 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1313 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1316 command_print(cmd_ctx
, "\tUnknown AP type");
1320 /* NOTE: a MEM-AP may have a single CoreSight component that's
1321 * not a ROM table ... or have no such components at all.
1324 command_print(cmd_ctx
, "AP BASE 0x%8.8" PRIx32
, dbgbase
);
1326 command_print(cmd_ctx
, "No AP found at this ap 0x%x", ap
);
1328 romtable_present
= ((mem_ap
) && (dbgbase
!= 0xFFFFFFFF));
1329 if (romtable_present
) {
1330 uint32_t cid0
, cid1
, cid2
, cid3
, memtype
, romentry
;
1331 uint16_t entry_offset
;
1333 /* bit 16 of apid indicates a memory access port */
1335 command_print(cmd_ctx
, "\tValid ROM table present");
1337 command_print(cmd_ctx
, "\tROM table in legacy format");
1339 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1340 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
1341 if (retval
!= ERROR_OK
)
1343 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
1344 if (retval
!= ERROR_OK
)
1346 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
1347 if (retval
!= ERROR_OK
)
1349 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
1350 if (retval
!= ERROR_OK
)
1352 retval
= mem_ap_read_u32(dap
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
1353 if (retval
!= ERROR_OK
)
1355 retval
= dap_run(dap
);
1356 if (retval
!= ERROR_OK
)
1359 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1360 command_print(cmd_ctx
, "\tCID3 0x%2.2x"
1364 (unsigned) cid3
, (unsigned)cid2
,
1365 (unsigned) cid1
, (unsigned) cid0
);
1367 command_print(cmd_ctx
, "\tMEMTYPE system memory present on bus");
1369 command_print(cmd_ctx
, "\tMEMTYPE System memory not present. "
1370 "Dedicated debug bus.");
1372 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1375 retval
= mem_ap_read_atomic_u32(dap
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
1376 if (retval
!= ERROR_OK
)
1378 command_print(cmd_ctx
, "\tROMTABLE[0x%x] = 0x%" PRIx32
"", entry_offset
, romentry
);
1379 if (romentry
& 0x01) {
1380 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
1381 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
1382 uint32_t component_base
;
1386 component_base
= (dbgbase
& 0xFFFFF000) + (romentry
& 0xFFFFF000);
1388 /* IDs are in last 4K section */
1389 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE0, &c_pid0
);
1390 if (retval
!= ERROR_OK
)
1393 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE4, &c_pid1
);
1394 if (retval
!= ERROR_OK
)
1397 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFE8, &c_pid2
);
1398 if (retval
!= ERROR_OK
)
1401 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFEC, &c_pid3
);
1402 if (retval
!= ERROR_OK
)
1405 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFD0, &c_pid4
);
1406 if (retval
!= ERROR_OK
)
1410 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF0, &c_cid0
);
1411 if (retval
!= ERROR_OK
)
1414 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF4, &c_cid1
);
1415 if (retval
!= ERROR_OK
)
1418 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFF8, &c_cid2
);
1419 if (retval
!= ERROR_OK
)
1422 retval
= mem_ap_read_atomic_u32(dap
, component_base
+ 0xFFC, &c_cid3
);
1423 if (retval
!= ERROR_OK
)
1427 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
","
1428 "start address 0x%" PRIx32
, component_base
,
1429 /* component may take multiple 4K pages */
1430 component_base
- 0x1000*(c_pid4
>> 4));
1431 command_print(cmd_ctx
, "\t\tComponent class is 0x%x, %s",
1432 (int) (c_cid1
>> 4) & 0xf,
1433 /* See ARM IHI 0029B Table 3-3 */
1434 class_description
[(c_cid1
>> 4) & 0xf]);
1436 /* CoreSight component? */
1437 if (((c_cid1
>> 4) & 0x0f) == 9) {
1440 char *major
= "Reserved", *subtype
= "Reserved";
1442 retval
= mem_ap_read_atomic_u32(dap
,
1443 (component_base
& 0xfffff000) | 0xfcc,
1445 if (retval
!= ERROR_OK
)
1447 minor
= (devtype
>> 4) & 0x0f;
1448 switch (devtype
& 0x0f) {
1450 major
= "Miscellaneous";
1456 subtype
= "Validation component";
1461 major
= "Trace Sink";
1475 major
= "Trace Link";
1481 subtype
= "Funnel, router";
1487 subtype
= "FIFO, buffer";
1492 major
= "Trace Source";
1498 subtype
= "Processor";
1504 subtype
= "Engine/Coprocessor";
1512 major
= "Debug Control";
1518 subtype
= "Trigger Matrix";
1521 subtype
= "Debug Auth";
1526 major
= "Debug Logic";
1532 subtype
= "Processor";
1538 subtype
= "Engine/Coprocessor";
1543 command_print(cmd_ctx
, "\t\tType is 0x%2.2x, %s, %s",
1544 (unsigned) (devtype
& 0xff),
1546 /* REVISIT also show 0xfc8 DevId */
1549 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1550 command_print(cmd_ctx
,
1559 command_print(cmd_ctx
,
1560 "\t\tPeripheral ID[4..0] = hex "
1561 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1562 (int) c_pid4
, (int) c_pid3
, (int) c_pid2
,
1563 (int) c_pid1
, (int) c_pid0
);
1565 /* Part number interpretations are from Cortex
1566 * core specs, the CoreSight components TRM
1567 * (ARM DDI 0314H), CoreSight System Design
1568 * Guide (ARM DGI 0012D) and ETM specs; also
1569 * from chip observation (e.g. TI SDTI).
1571 part_num
= (c_pid0
& 0xff);
1572 part_num
|= (c_pid1
& 0x0f) << 8;
1575 type
= "Cortex-M3 NVIC";
1576 full
= "(Interrupt Controller)";
1579 type
= "Cortex-M3 ITM";
1580 full
= "(Instrumentation Trace Module)";
1583 type
= "Cortex-M3 DWT";
1584 full
= "(Data Watchpoint and Trace)";
1587 type
= "Cortex-M3 FBP";
1588 full
= "(Flash Patch and Breakpoint)";
1591 type
= "Cortex-M4 SCS";
1592 full
= "(System Control Space)";
1595 type
= "CoreSight ETM11";
1596 full
= "(Embedded Trace)";
1598 /* case 0x113: what? */
1599 case 0x120: /* from OMAP3 memmap */
1601 full
= "(System Debug Trace Interface)";
1603 case 0x343: /* from OMAP3 memmap */
1608 type
= "Coresight CTI";
1609 full
= "(Cross Trigger)";
1612 type
= "Coresight ETB";
1613 full
= "(Trace Buffer)";
1616 type
= "Coresight CSTF";
1617 full
= "(Trace Funnel)";
1620 type
= "CoreSight ETM9";
1621 full
= "(Embedded Trace)";
1624 type
= "Coresight TPIU";
1625 full
= "(Trace Port Interface Unit)";
1628 type
= "Cortex-A8 ETM";
1629 full
= "(Embedded Trace)";
1632 type
= "Cortex-A8 CTI";
1633 full
= "(Cross Trigger)";
1636 type
= "Cortex-M3 TPIU";
1637 full
= "(Trace Port Interface Unit)";
1640 type
= "Cortex-M3 ETM";
1641 full
= "(Embedded Trace)";
1644 type
= "Cortex-M4 ETM";
1645 full
= "(Embedded Trace)";
1648 type
= "Cortex-R4 ETM";
1649 full
= "(Embedded Trace)";
1652 type
= "Cortex-M4 TPUI";
1653 full
= "(Trace Port Interface Unit)";
1656 type
= "Cortex-A8 Debug";
1657 full
= "(Debug Unit)";
1660 type
= "-*- unrecognized -*-";
1664 command_print(cmd_ctx
, "\t\tPart is %s %s",
1668 command_print(cmd_ctx
, "\t\tComponent not present");
1670 command_print(cmd_ctx
, "\t\tEnd of ROM table");
1673 } while (romentry
> 0);
1675 command_print(cmd_ctx
, "\tNo ROM table present");
1676 dap_ap_select(dap
, ap_old
);
1681 COMMAND_HANDLER(handle_dap_info_command
)
1683 struct target
*target
= get_current_target(CMD_CTX
);
1684 struct arm
*arm
= target_to_arm(target
);
1685 struct adiv5_dap
*dap
= arm
->dap
;
1693 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1696 return ERROR_COMMAND_SYNTAX_ERROR
;
1699 return dap_info_command(CMD_CTX
, dap
, apsel
);
1702 COMMAND_HANDLER(dap_baseaddr_command
)
1704 struct target
*target
= get_current_target(CMD_CTX
);
1705 struct arm
*arm
= target_to_arm(target
);
1706 struct adiv5_dap
*dap
= arm
->dap
;
1708 uint32_t apsel
, baseaddr
;
1716 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1717 /* AP address is in bits 31:24 of DP_SELECT */
1719 return ERROR_COMMAND_SYNTAX_ERROR
;
1722 return ERROR_COMMAND_SYNTAX_ERROR
;
1725 dap_ap_select(dap
, apsel
);
1727 /* NOTE: assumes we're talking to a MEM-AP, which
1728 * has a base address. There are other kinds of AP,
1729 * though they're not common for now. This should
1730 * use the ID register to verify it's a MEM-AP.
1732 retval
= dap_queue_ap_read(dap
, AP_REG_BASE
, &baseaddr
);
1733 if (retval
!= ERROR_OK
)
1735 retval
= dap_run(dap
);
1736 if (retval
!= ERROR_OK
)
1739 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1744 COMMAND_HANDLER(dap_memaccess_command
)
1746 struct target
*target
= get_current_target(CMD_CTX
);
1747 struct arm
*arm
= target_to_arm(target
);
1748 struct adiv5_dap
*dap
= arm
->dap
;
1750 uint32_t memaccess_tck
;
1754 memaccess_tck
= dap
->memaccess_tck
;
1757 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1760 return ERROR_COMMAND_SYNTAX_ERROR
;
1762 dap
->memaccess_tck
= memaccess_tck
;
1764 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1765 dap
->memaccess_tck
);
1770 COMMAND_HANDLER(dap_apsel_command
)
1772 struct target
*target
= get_current_target(CMD_CTX
);
1773 struct arm
*arm
= target_to_arm(target
);
1774 struct adiv5_dap
*dap
= arm
->dap
;
1776 uint32_t apsel
, apid
;
1784 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1785 /* AP address is in bits 31:24 of DP_SELECT */
1787 return ERROR_COMMAND_SYNTAX_ERROR
;
1790 return ERROR_COMMAND_SYNTAX_ERROR
;
1794 dap_ap_select(dap
, apsel
);
1796 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1797 if (retval
!= ERROR_OK
)
1799 retval
= dap_run(dap
);
1800 if (retval
!= ERROR_OK
)
1803 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1809 COMMAND_HANDLER(dap_apid_command
)
1811 struct target
*target
= get_current_target(CMD_CTX
);
1812 struct arm
*arm
= target_to_arm(target
);
1813 struct adiv5_dap
*dap
= arm
->dap
;
1815 uint32_t apsel
, apid
;
1823 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1824 /* AP address is in bits 31:24 of DP_SELECT */
1826 return ERROR_COMMAND_SYNTAX_ERROR
;
1829 return ERROR_COMMAND_SYNTAX_ERROR
;
1832 dap_ap_select(dap
, apsel
);
1834 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1835 if (retval
!= ERROR_OK
)
1837 retval
= dap_run(dap
);
1838 if (retval
!= ERROR_OK
)
1841 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1846 static const struct command_registration dap_commands
[] = {
1849 .handler
= handle_dap_info_command
,
1850 .mode
= COMMAND_EXEC
,
1851 .help
= "display ROM table for MEM-AP "
1852 "(default currently selected AP)",
1853 .usage
= "[ap_num]",
1857 .handler
= dap_apsel_command
,
1858 .mode
= COMMAND_EXEC
,
1859 .help
= "Set the currently selected AP (default 0) "
1860 "and display the result",
1861 .usage
= "[ap_num]",
1865 .handler
= dap_apid_command
,
1866 .mode
= COMMAND_EXEC
,
1867 .help
= "return ID register from AP "
1868 "(default currently selected AP)",
1869 .usage
= "[ap_num]",
1873 .handler
= dap_baseaddr_command
,
1874 .mode
= COMMAND_EXEC
,
1875 .help
= "return debug base address from MEM-AP "
1876 "(default currently selected AP)",
1877 .usage
= "[ap_num]",
1880 .name
= "memaccess",
1881 .handler
= dap_memaccess_command
,
1882 .mode
= COMMAND_EXEC
,
1883 .help
= "set/get number of extra tck for MEM-AP memory "
1884 "bus access [0-255]",
1885 .usage
= "[cycles]",
1887 COMMAND_REGISTRATION_DONE
1890 const struct command_registration dap_command_handlers
[] = {
1893 .mode
= COMMAND_EXEC
,
1894 .help
= "DAP command group",
1896 .chain
= dap_commands
,
1898 COMMAND_REGISTRATION_DONE
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