1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block
, uint32_t address
)
88 return tar_autoincr_block
- ((tar_autoincr_block
- 1) & address
);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
106 void dap_ap_select(struct adiv5_dap
*dap
, uint8_t ap
)
108 uint32_t new_ap
= (ap
<< 24) & 0xFF000000;
110 if (new_ap
!= dap
->ap_current
) {
111 dap
->ap_current
= new_ap
;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
115 dap
->ap_bank_value
= -1;
119 static int mem_ap_setup_csw(struct adiv5_ap
*ap
, uint32_t csw
)
121 csw
= csw
| CSW_DBGSWENABLE
| CSW_MASTER_DEBUG
| CSW_HPROT
|
124 if (csw
!= ap
->csw_value
) {
125 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
126 int retval
= dap_queue_ap_write(ap
->dap
, MEM_AP_REG_CSW
, csw
);
127 if (retval
!= ERROR_OK
)
134 static int mem_ap_setup_tar(struct adiv5_ap
*ap
, uint32_t tar
)
136 if (tar
!= ap
->tar_value
||
137 (ap
->csw_value
& CSW_ADDRINC_MASK
)) {
138 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
139 int retval
= dap_queue_ap_write(ap
->dap
, MEM_AP_REG_TAR
, tar
);
140 if (retval
!= ERROR_OK
)
148 * Queue transactions setting up transfer parameters for the
149 * currently selected MEM-AP.
151 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
152 * initiate data reads or writes using memory or peripheral addresses.
153 * If the CSW is configured for it, the TAR may be automatically
154 * incremented after each transfer.
156 * @param ap The MEM-AP.
157 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
158 * matches the cached value, the register is not changed.
159 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
160 * matches the cached address, the register is not changed.
162 * @return ERROR_OK if the transaction was properly queued, else a fault code.
164 static int mem_ap_setup_transfer(struct adiv5_ap
*ap
, uint32_t csw
, uint32_t tar
)
167 retval
= mem_ap_setup_csw(ap
, csw
);
168 if (retval
!= ERROR_OK
)
170 retval
= mem_ap_setup_tar(ap
, tar
);
171 if (retval
!= ERROR_OK
)
177 * Asynchronous (queued) read of a word from memory or a system register.
179 * @param ap The MEM-AP to access.
180 * @param address Address of the 32-bit word to read; it must be
181 * readable by the currently selected MEM-AP.
182 * @param value points to where the word will be stored when the
183 * transaction queue is flushed (assuming no errors).
185 * @return ERROR_OK for success. Otherwise a fault code.
187 int mem_ap_read_u32(struct adiv5_ap
*ap
, uint32_t address
,
192 dap_ap_select(ap
->dap
, ap
->ap_num
);
194 /* Use banked addressing (REG_BDx) to avoid some link traffic
195 * (updating TAR) when reading several consecutive addresses.
197 retval
= mem_ap_setup_transfer(ap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
198 address
& 0xFFFFFFF0);
199 if (retval
!= ERROR_OK
)
202 return dap_queue_ap_read(ap
->dap
, MEM_AP_REG_BD0
| (address
& 0xC), value
);
206 * Synchronous read of a word from memory or a system register.
207 * As a side effect, this flushes any queued transactions.
209 * @param ap The MEM-AP to access.
210 * @param address Address of the 32-bit word to read; it must be
211 * readable by the currently selected MEM-AP.
212 * @param value points to where the result will be stored.
214 * @return ERROR_OK for success; *value holds the result.
215 * Otherwise a fault code.
217 int mem_ap_read_atomic_u32(struct adiv5_ap
*ap
, uint32_t address
,
222 retval
= mem_ap_read_u32(ap
, address
, value
);
223 if (retval
!= ERROR_OK
)
226 return dap_run(ap
->dap
);
230 * Asynchronous (queued) write of a word to memory or a system register.
232 * @param ap The MEM-AP to access.
233 * @param address Address to be written; it must be writable by
234 * the currently selected MEM-AP.
235 * @param value Word that will be written to the address when transaction
236 * queue is flushed (assuming no errors).
238 * @return ERROR_OK for success. Otherwise a fault code.
240 int mem_ap_write_u32(struct adiv5_ap
*ap
, uint32_t address
,
245 dap_ap_select(ap
->dap
, ap
->ap_num
);
247 /* Use banked addressing (REG_BDx) to avoid some link traffic
248 * (updating TAR) when writing several consecutive addresses.
250 retval
= mem_ap_setup_transfer(ap
, CSW_32BIT
| CSW_ADDRINC_OFF
,
251 address
& 0xFFFFFFF0);
252 if (retval
!= ERROR_OK
)
255 return dap_queue_ap_write(ap
->dap
, MEM_AP_REG_BD0
| (address
& 0xC),
260 * Synchronous write of a word to memory or a system register.
261 * As a side effect, this flushes any queued transactions.
263 * @param ap The MEM-AP to access.
264 * @param address Address to be written; it must be writable by
265 * the currently selected MEM-AP.
266 * @param value Word that will be written.
268 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
270 int mem_ap_write_atomic_u32(struct adiv5_ap
*ap
, uint32_t address
,
273 int retval
= mem_ap_write_u32(ap
, address
, value
);
275 if (retval
!= ERROR_OK
)
278 return dap_run(ap
->dap
);
282 * Synchronous write of a block of memory, using a specific access size.
284 * @param ap The MEM-AP to access.
285 * @param buffer The data buffer to write. No particular alignment is assumed.
286 * @param size Which access size to use, in bytes. 1, 2 or 4.
287 * @param count The number of writes to do (in size units, not bytes).
288 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
289 * @param addrinc Whether the target address should be increased for each write or not. This
290 * should normally be true, except when writing to e.g. a FIFO.
291 * @return ERROR_OK on success, otherwise an error code.
293 static int mem_ap_write(struct adiv5_ap
*ap
, const uint8_t *buffer
, uint32_t size
, uint32_t count
,
294 uint32_t address
, bool addrinc
)
296 struct adiv5_dap
*dap
= ap
->dap
;
297 size_t nbytes
= size
* count
;
298 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
303 /* TI BE-32 Quirks mode:
304 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
305 * size write address bytes written in order
306 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
307 * 2 TAR ^ 2 (val >> 8), (val)
309 * For example, if you attempt to write a single byte to address 0, the processor
310 * will actually write a byte to address 3.
312 * To make writes of size < 4 work as expected, we xor a value with the address before
313 * setting the TAP, and we set the TAP after every transfer rather then relying on
314 * address increment. */
317 csw_size
= CSW_32BIT
;
319 } else if (size
== 2) {
320 csw_size
= CSW_16BIT
;
321 addr_xor
= dap
->ti_be_32_quirks
? 2 : 0;
322 } else if (size
== 1) {
324 addr_xor
= dap
->ti_be_32_quirks
? 3 : 0;
326 return ERROR_TARGET_UNALIGNED_ACCESS
;
329 if (ap
->unaligned_access_bad
&& (address
% size
!= 0))
330 return ERROR_TARGET_UNALIGNED_ACCESS
;
332 dap_ap_select(ap
->dap
, ap
->ap_num
);
334 retval
= mem_ap_setup_tar(ap
, address
^ addr_xor
);
335 if (retval
!= ERROR_OK
)
339 uint32_t this_size
= size
;
341 /* Select packed transfer if possible */
342 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
343 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
345 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
347 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
350 if (retval
!= ERROR_OK
)
353 /* How many source bytes each transfer will consume, and their location in the DRW,
354 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
355 uint32_t outvalue
= 0;
356 if (dap
->ti_be_32_quirks
) {
359 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
360 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
361 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
362 outvalue
|= (uint32_t)*buffer
++ << 8 * (3 ^ (address
++ & 3) ^ addr_xor
);
365 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (address
++ & 3) ^ addr_xor
);
366 outvalue
|= (uint32_t)*buffer
++ << 8 * (1 ^ (address
++ & 3) ^ addr_xor
);
369 outvalue
|= (uint32_t)*buffer
++ << 8 * (0 ^ (address
++ & 3) ^ addr_xor
);
375 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
376 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
378 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
380 outvalue
|= (uint32_t)*buffer
++ << 8 * (address
++ & 3);
386 retval
= dap_queue_ap_write(dap
, MEM_AP_REG_DRW
, outvalue
);
387 if (retval
!= ERROR_OK
)
390 /* Rewrite TAR if it wrapped or we're xoring addresses */
391 if (addrinc
&& (addr_xor
|| (address
% ap
->tar_autoincr_block
< size
&& nbytes
> 0))) {
392 retval
= mem_ap_setup_tar(ap
, address
^ addr_xor
);
393 if (retval
!= ERROR_OK
)
398 /* REVISIT: Might want to have a queued version of this function that does not run. */
399 if (retval
== ERROR_OK
)
400 retval
= dap_run(dap
);
402 if (retval
!= ERROR_OK
) {
404 if (dap_queue_ap_read(dap
, MEM_AP_REG_TAR
, &tar
) == ERROR_OK
405 && dap_run(dap
) == ERROR_OK
)
406 LOG_ERROR("Failed to write memory at 0x%08"PRIx32
, tar
);
408 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
415 * Synchronous read of a block of memory, using a specific access size.
417 * @param ap The MEM-AP to access.
418 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
419 * @param size Which access size to use, in bytes. 1, 2 or 4.
420 * @param count The number of reads to do (in size units, not bytes).
421 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
422 * @param addrinc Whether the target address should be increased after each read or not. This
423 * should normally be true, except when reading from e.g. a FIFO.
424 * @return ERROR_OK on success, otherwise an error code.
426 static int mem_ap_read(struct adiv5_ap
*ap
, uint8_t *buffer
, uint32_t size
, uint32_t count
,
427 uint32_t adr
, bool addrinc
)
429 struct adiv5_dap
*dap
= ap
->dap
;
430 size_t nbytes
= size
* count
;
431 const uint32_t csw_addrincr
= addrinc
? CSW_ADDRINC_SINGLE
: CSW_ADDRINC_OFF
;
433 uint32_t address
= adr
;
436 /* TI BE-32 Quirks mode:
437 * Reads on big-endian TMS570 behave strangely differently than writes.
438 * They read from the physical address requested, but with DRW byte-reversed.
439 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
440 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
444 csw_size
= CSW_32BIT
;
446 csw_size
= CSW_16BIT
;
450 return ERROR_TARGET_UNALIGNED_ACCESS
;
452 if (ap
->unaligned_access_bad
&& (adr
% size
!= 0))
453 return ERROR_TARGET_UNALIGNED_ACCESS
;
455 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
456 * over-allocation if packed transfers are going to be used, but determining the real need at
457 * this point would be messy. */
458 uint32_t *read_buf
= malloc(count
* sizeof(uint32_t));
459 uint32_t *read_ptr
= read_buf
;
460 if (read_buf
== NULL
) {
461 LOG_ERROR("Failed to allocate read buffer");
465 dap_ap_select(ap
->dap
, ap
->ap_num
);
467 retval
= mem_ap_setup_tar(ap
, address
);
468 if (retval
!= ERROR_OK
) {
473 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
474 * useful bytes it contains, and their location in the word, depends on the type of transfer
477 uint32_t this_size
= size
;
479 /* Select packed transfer if possible */
480 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
481 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
483 retval
= mem_ap_setup_csw(ap
, csw_size
| CSW_ADDRINC_PACKED
);
485 retval
= mem_ap_setup_csw(ap
, csw_size
| csw_addrincr
);
487 if (retval
!= ERROR_OK
)
490 retval
= dap_queue_ap_read(dap
, MEM_AP_REG_DRW
, read_ptr
++);
491 if (retval
!= ERROR_OK
)
495 address
+= this_size
;
497 /* Rewrite TAR if it wrapped */
498 if (addrinc
&& address
% ap
->tar_autoincr_block
< size
&& nbytes
> 0) {
499 retval
= mem_ap_setup_tar(ap
, address
);
500 if (retval
!= ERROR_OK
)
505 if (retval
== ERROR_OK
)
506 retval
= dap_run(dap
);
510 nbytes
= size
* count
;
513 /* If something failed, read TAR to find out how much data was successfully read, so we can
514 * at least give the caller what we have. */
515 if (retval
!= ERROR_OK
) {
517 if (dap_queue_ap_read(dap
, MEM_AP_REG_TAR
, &tar
) == ERROR_OK
518 && dap_run(dap
) == ERROR_OK
) {
519 LOG_ERROR("Failed to read memory at 0x%08"PRIx32
, tar
);
520 if (nbytes
> tar
- address
)
521 nbytes
= tar
- address
;
523 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
528 /* Replay loop to populate caller's buffer from the correct word and byte lane */
530 uint32_t this_size
= size
;
532 if (addrinc
&& ap
->packed_transfers
&& nbytes
>= 4
533 && max_tar_block_size(ap
->tar_autoincr_block
, address
) >= 4) {
537 if (dap
->ti_be_32_quirks
) {
540 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
541 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
543 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
545 *buffer
++ = *read_ptr
>> 8 * (3 - (address
++ & 3));
550 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
551 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
553 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
555 *buffer
++ = *read_ptr
>> 8 * (address
++ & 3);
567 int mem_ap_read_buf(struct adiv5_ap
*ap
,
568 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
570 return mem_ap_read(ap
, buffer
, size
, count
, address
, true);
573 int mem_ap_write_buf(struct adiv5_ap
*ap
,
574 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
576 return mem_ap_write(ap
, buffer
, size
, count
, address
, true);
579 int mem_ap_read_buf_noincr(struct adiv5_ap
*ap
,
580 uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
582 return mem_ap_read(ap
, buffer
, size
, count
, address
, false);
585 int mem_ap_write_buf_noincr(struct adiv5_ap
*ap
,
586 const uint8_t *buffer
, uint32_t size
, uint32_t count
, uint32_t address
)
588 return mem_ap_write(ap
, buffer
, size
, count
, address
, false);
591 /*--------------------------------------------------------------------------*/
594 #define DAP_POWER_DOMAIN_TIMEOUT (10)
596 /* FIXME don't import ... just initialize as
597 * part of DAP transport setup
599 extern const struct dap_ops jtag_dp_ops
;
601 /*--------------------------------------------------------------------------*/
606 struct adiv5_dap
*dap_init(void)
608 struct adiv5_dap
*dap
= calloc(1, sizeof(struct adiv5_dap
));
610 /* Set up with safe defaults */
611 for (i
= 0; i
<= 255; i
++) {
612 dap
->ap
[i
].dap
= dap
;
613 dap
->ap
[i
].ap_num
= i
;
614 /* memaccess_tck max is 255 */
615 dap
->ap
[i
].memaccess_tck
= 255;
616 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
617 dap
->ap
[i
].tar_autoincr_block
= (1<<10);
619 dap
->ap_current
= -1;
620 dap
->ap_bank_value
= -1;
621 dap
->dp_bank_value
= -1;
626 * Initialize a DAP. This sets up the power domains, prepares the DP
627 * for further use and activates overrun checking.
629 * @param dap The DAP being initialized.
631 int dap_dp_init(struct adiv5_dap
*dap
)
636 /* JTAG-DP or SWJ-DP, in JTAG mode
637 * ... for SWD mode this is patched as part
639 * FIXME: This should already be setup by the respective transport specific DAP creation.
642 dap
->ops
= &jtag_dp_ops
;
644 dap
->ap_current
= -1;
645 dap
->ap_bank_value
= -1;
646 dap
->last_read
= NULL
;
648 for (size_t i
= 0; i
< 10; i
++) {
649 /* DP initialization */
651 dap
->dp_bank_value
= 0;
653 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
654 if (retval
!= ERROR_OK
)
657 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, SSTICKYERR
);
658 if (retval
!= ERROR_OK
)
661 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
662 if (retval
!= ERROR_OK
)
665 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
;
666 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
667 if (retval
!= ERROR_OK
)
670 /* Check that we have debug power domains activated */
671 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
672 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
673 CDBGPWRUPACK
, CDBGPWRUPACK
,
674 DAP_POWER_DOMAIN_TIMEOUT
);
675 if (retval
!= ERROR_OK
)
678 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
679 retval
= dap_dp_poll_register(dap
, DP_CTRL_STAT
,
680 CSYSPWRUPACK
, CSYSPWRUPACK
,
681 DAP_POWER_DOMAIN_TIMEOUT
);
682 if (retval
!= ERROR_OK
)
685 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
686 if (retval
!= ERROR_OK
)
689 /* With debug power on we can activate OVERRUN checking */
690 dap
->dp_ctrl_stat
= CDBGPWRUPREQ
| CSYSPWRUPREQ
| CORUNDETECT
;
691 retval
= dap_queue_dp_write(dap
, DP_CTRL_STAT
, dap
->dp_ctrl_stat
);
692 if (retval
!= ERROR_OK
)
694 retval
= dap_queue_dp_read(dap
, DP_CTRL_STAT
, NULL
);
695 if (retval
!= ERROR_OK
)
698 retval
= dap_run(dap
);
699 if (retval
!= ERROR_OK
)
709 * Initialize a DAP. This sets up the power domains, prepares the DP
710 * for further use, and arranges to use AP #0 for all AP operations
711 * until dap_ap-select() changes that policy.
713 * @param ap The MEM-AP being initialized.
715 int mem_ap_init(struct adiv5_ap
*ap
)
717 /* check that we support packed transfers */
720 struct adiv5_dap
*dap
= ap
->dap
;
722 dap_ap_select(dap
, ap
->ap_num
);
724 retval
= mem_ap_setup_transfer(ap
, CSW_8BIT
| CSW_ADDRINC_PACKED
, 0);
725 if (retval
!= ERROR_OK
)
728 retval
= dap_queue_ap_read(dap
, MEM_AP_REG_CSW
, &csw
);
729 if (retval
!= ERROR_OK
)
732 retval
= dap_queue_ap_read(dap
, MEM_AP_REG_CFG
, &cfg
);
733 if (retval
!= ERROR_OK
)
736 retval
= dap_run(dap
);
737 if (retval
!= ERROR_OK
)
740 if (csw
& CSW_ADDRINC_PACKED
)
741 ap
->packed_transfers
= true;
743 ap
->packed_transfers
= false;
745 /* Packed transfers on TI BE-32 processors do not work correctly in
747 if (dap
->ti_be_32_quirks
)
748 ap
->packed_transfers
= false;
750 LOG_DEBUG("MEM_AP Packed Transfers: %s",
751 ap
->packed_transfers
? "enabled" : "disabled");
753 /* The ARM ADI spec leaves implementation-defined whether unaligned
754 * memory accesses work, only work partially, or cause a sticky error.
755 * On TI BE-32 processors, reads seem to return garbage in some bytes
756 * and unaligned writes seem to cause a sticky error.
757 * TODO: it would be nice to have a way to detect whether unaligned
758 * operations are supported on other processors. */
759 ap
->unaligned_access_bad
= dap
->ti_be_32_quirks
;
761 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
762 !!(cfg
& 0x04), !!(cfg
& 0x02), !!(cfg
& 0x01));
767 /* CID interpretation -- see ARM IHI 0029B section 3
768 * and ARM IHI 0031A table 13-3.
770 static const char *class_description
[16] = {
771 "Reserved", "ROM table", "Reserved", "Reserved",
772 "Reserved", "Reserved", "Reserved", "Reserved",
773 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
774 "Reserved", "OptimoDE DESS",
775 "Generic IP component", "PrimeCell or System component"
778 static bool is_dap_cid_ok(uint32_t cid3
, uint32_t cid2
, uint32_t cid1
, uint32_t cid0
)
780 return cid3
== 0xb1 && cid2
== 0x05
781 && ((cid1
& 0x0f) == 0) && cid0
== 0x0d;
785 * This function checks the ID for each access port to find the requested Access Port type
787 int dap_find_ap(struct adiv5_dap
*dap
, enum ap_type type_to_find
, struct adiv5_ap
**ap_out
)
791 /* Maximum AP number is 255 since the SELECT register is 8 bits */
792 for (ap_num
= 0; ap_num
<= 255; ap_num
++) {
794 /* read the IDR register of the Access Port */
796 dap_ap_select(dap
, ap_num
);
798 int retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &id_val
);
799 if (retval
!= ERROR_OK
)
802 retval
= dap_run(dap
);
806 * 27-24 : JEDEC bank (0x4 for ARM)
807 * 23-17 : JEDEC code (0x3B for ARM)
808 * 16-13 : Class (0b1000=Mem-AP)
810 * 7-4 : AP Variant (non-zero for JTAG-AP)
811 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
814 /* Reading register for a non-existant AP should not cause an error,
815 * but just to be sure, try to continue searching if an error does happen.
817 if ((retval
== ERROR_OK
) && /* Register read success */
818 ((id_val
& IDR_JEP106
) == IDR_JEP106_ARM
) && /* Jedec codes match */
819 ((id_val
& IDR_TYPE
) == type_to_find
)) { /* type matches*/
821 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32
")",
822 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
823 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
824 (type_to_find
== AP_TYPE_AXI_AP
) ? "AXI-AP" :
825 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown",
828 *ap_out
= &dap
->ap
[ap_num
];
833 LOG_DEBUG("No %s found",
834 (type_to_find
== AP_TYPE_AHB_AP
) ? "AHB-AP" :
835 (type_to_find
== AP_TYPE_APB_AP
) ? "APB-AP" :
836 (type_to_find
== AP_TYPE_AXI_AP
) ? "AXI-AP" :
837 (type_to_find
== AP_TYPE_JTAG_AP
) ? "JTAG-AP" : "Unknown");
841 int dap_get_debugbase(struct adiv5_ap
*ap
,
842 uint32_t *dbgbase
, uint32_t *apid
)
844 struct adiv5_dap
*dap
= ap
->dap
;
848 ap_old
= dap_ap_get_select(dap
);
849 dap_ap_select(dap
, ap
->ap_num
);
851 retval
= dap_queue_ap_read(dap
, MEM_AP_REG_BASE
, dbgbase
);
852 if (retval
!= ERROR_OK
)
854 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, apid
);
855 if (retval
!= ERROR_OK
)
857 retval
= dap_run(dap
);
858 if (retval
!= ERROR_OK
)
861 dap_ap_select(dap
, ap_old
);
866 int dap_lookup_cs_component(struct adiv5_ap
*ap
,
867 uint32_t dbgbase
, uint8_t type
, uint32_t *addr
, int32_t *idx
)
869 struct adiv5_dap
*dap
= ap
->dap
;
871 uint32_t romentry
, entry_offset
= 0, component_base
, devtype
;
875 ap_old
= dap_ap_get_select(dap
);
878 retval
= mem_ap_read_atomic_u32(ap
, (dbgbase
&0xFFFFF000) |
879 entry_offset
, &romentry
);
880 if (retval
!= ERROR_OK
)
883 component_base
= (dbgbase
& 0xFFFFF000)
884 + (romentry
& 0xFFFFF000);
886 if (romentry
& 0x1) {
888 retval
= mem_ap_read_atomic_u32(ap
, component_base
| 0xff4, &c_cid1
);
889 if (retval
!= ERROR_OK
) {
890 LOG_ERROR("Can't read component with base address 0x%" PRIx32
891 ", the corresponding core might be turned off", component_base
);
894 if (((c_cid1
>> 4) & 0x0f) == 1) {
895 retval
= dap_lookup_cs_component(ap
, component_base
,
897 if (retval
== ERROR_OK
)
899 if (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
903 retval
= mem_ap_read_atomic_u32(ap
,
904 (component_base
& 0xfffff000) | 0xfcc,
906 if (retval
!= ERROR_OK
)
908 if ((devtype
& 0xff) == type
) {
910 *addr
= component_base
;
917 } while (romentry
> 0);
919 dap_ap_select(dap
, ap_old
);
922 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
927 static int dap_rom_display(struct command_context
*cmd_ctx
,
928 struct adiv5_ap
*ap
, uint32_t dbgbase
, int depth
)
930 struct adiv5_dap
*dap
= ap
->dap
;
932 uint32_t cid0
, cid1
, cid2
, cid3
, memtype
, romentry
;
933 uint16_t entry_offset
;
937 command_print(cmd_ctx
, "\tTables too deep");
942 snprintf(tabs
, sizeof(tabs
), "[L%02d] ", depth
);
944 /* bit 16 of apid indicates a memory access port */
946 command_print(cmd_ctx
, "\t%sValid ROM table present", tabs
);
948 command_print(cmd_ctx
, "\t%sROM table in legacy format", tabs
);
950 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
951 retval
= mem_ap_read_u32(ap
, (dbgbase
&0xFFFFF000) | 0xFF0, &cid0
);
952 if (retval
!= ERROR_OK
)
954 retval
= mem_ap_read_u32(ap
, (dbgbase
&0xFFFFF000) | 0xFF4, &cid1
);
955 if (retval
!= ERROR_OK
)
957 retval
= mem_ap_read_u32(ap
, (dbgbase
&0xFFFFF000) | 0xFF8, &cid2
);
958 if (retval
!= ERROR_OK
)
960 retval
= mem_ap_read_u32(ap
, (dbgbase
&0xFFFFF000) | 0xFFC, &cid3
);
961 if (retval
!= ERROR_OK
)
963 retval
= mem_ap_read_u32(ap
, (dbgbase
&0xFFFFF000) | 0xFCC, &memtype
);
964 if (retval
!= ERROR_OK
)
966 retval
= dap_run(dap
);
967 if (retval
!= ERROR_OK
)
970 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
971 command_print(cmd_ctx
, "\t%sCID3 0x%02x"
976 (unsigned)cid3
, (unsigned)cid2
,
977 (unsigned)cid1
, (unsigned)cid0
);
979 command_print(cmd_ctx
, "\t%sMEMTYPE system memory present on bus", tabs
);
981 command_print(cmd_ctx
, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs
);
983 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
984 for (entry_offset
= 0; ; entry_offset
+= 4) {
985 retval
= mem_ap_read_atomic_u32(ap
, (dbgbase
&0xFFFFF000) | entry_offset
, &romentry
);
986 if (retval
!= ERROR_OK
)
988 command_print(cmd_ctx
, "\t%sROMTABLE[0x%x] = 0x%" PRIx32
"",
989 tabs
, entry_offset
, romentry
);
990 if (romentry
& 0x01) {
991 uint32_t c_cid0
, c_cid1
, c_cid2
, c_cid3
;
992 uint32_t c_pid0
, c_pid1
, c_pid2
, c_pid3
, c_pid4
;
993 uint32_t component_base
;
995 const char *type
, *full
;
997 component_base
= (dbgbase
& 0xFFFFF000) + (romentry
& 0xFFFFF000);
999 /* IDs are in last 4K section */
1000 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFE0, &c_pid0
);
1001 if (retval
!= ERROR_OK
) {
1002 command_print(cmd_ctx
, "\t%s\tCan't read component with base address 0x%" PRIx32
1003 ", the corresponding core might be turned off", tabs
, component_base
);
1007 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFE4, &c_pid1
);
1008 if (retval
!= ERROR_OK
)
1011 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFE8, &c_pid2
);
1012 if (retval
!= ERROR_OK
)
1015 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFEC, &c_pid3
);
1016 if (retval
!= ERROR_OK
)
1019 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFD0, &c_pid4
);
1020 if (retval
!= ERROR_OK
)
1024 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFF0, &c_cid0
);
1025 if (retval
!= ERROR_OK
)
1028 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFF4, &c_cid1
);
1029 if (retval
!= ERROR_OK
)
1032 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFF8, &c_cid2
);
1033 if (retval
!= ERROR_OK
)
1036 retval
= mem_ap_read_atomic_u32(ap
, component_base
+ 0xFFC, &c_cid3
);
1037 if (retval
!= ERROR_OK
)
1041 command_print(cmd_ctx
, "\t\tComponent base address 0x%" PRIx32
", "
1042 "start address 0x%" PRIx32
, component_base
,
1043 /* component may take multiple 4K pages */
1044 (uint32_t)(component_base
- 0x1000*(c_pid4
>> 4)));
1045 command_print(cmd_ctx
, "\t\tComponent class is 0x%" PRIx8
", %s",
1046 (uint8_t)((c_cid1
>> 4) & 0xf),
1047 /* See ARM IHI 0029B Table 3-3 */
1048 class_description
[(c_cid1
>> 4) & 0xf]);
1050 /* CoreSight component? */
1051 if (((c_cid1
>> 4) & 0x0f) == 9) {
1054 const char *major
= "Reserved", *subtype
= "Reserved";
1056 retval
= mem_ap_read_atomic_u32(ap
,
1057 (component_base
& 0xfffff000) | 0xfcc,
1059 if (retval
!= ERROR_OK
)
1061 minor
= (devtype
>> 4) & 0x0f;
1062 switch (devtype
& 0x0f) {
1064 major
= "Miscellaneous";
1070 subtype
= "Validation component";
1075 major
= "Trace Sink";
1092 major
= "Trace Link";
1098 subtype
= "Funnel, router";
1104 subtype
= "FIFO, buffer";
1109 major
= "Trace Source";
1115 subtype
= "Processor";
1121 subtype
= "Engine/Coprocessor";
1127 subtype
= "Software";
1132 major
= "Debug Control";
1138 subtype
= "Trigger Matrix";
1141 subtype
= "Debug Auth";
1144 subtype
= "Power Requestor";
1149 major
= "Debug Logic";
1155 subtype
= "Processor";
1161 subtype
= "Engine/Coprocessor";
1172 major
= "Perfomance Monitor";
1178 subtype
= "Processor";
1184 subtype
= "Engine/Coprocessor";
1195 command_print(cmd_ctx
, "\t\tType is 0x%02" PRIx8
", %s, %s",
1196 (uint8_t)(devtype
& 0xff),
1198 /* REVISIT also show 0xfc8 DevId */
1201 if (!is_dap_cid_ok(cid3
, cid2
, cid1
, cid0
))
1202 command_print(cmd_ctx
,
1211 command_print(cmd_ctx
,
1212 "\t\tPeripheral ID[4..0] = hex "
1213 "%02x %02x %02x %02x %02x",
1214 (int)c_pid4
, (int)c_pid3
, (int)c_pid2
,
1215 (int)c_pid1
, (int)c_pid0
);
1217 /* Part number interpretations are from Cortex
1218 * core specs, the CoreSight components TRM
1219 * (ARM DDI 0314H), CoreSight System Design
1220 * Guide (ARM DGI 0012D) and ETM specs; also
1221 * from chip observation (e.g. TI SDTI).
1223 part_num
= (c_pid0
& 0xff);
1224 part_num
|= (c_pid1
& 0x0f) << 8;
1227 type
= "Cortex-M3 NVIC";
1228 full
= "(Interrupt Controller)";
1231 type
= "Cortex-M3 ITM";
1232 full
= "(Instrumentation Trace Module)";
1235 type
= "Cortex-M3 DWT";
1236 full
= "(Data Watchpoint and Trace)";
1239 type
= "Cortex-M3 FBP";
1240 full
= "(Flash Patch and Breakpoint)";
1243 type
= "Cortex-M0 SCS";
1244 full
= "(System Control Space)";
1247 type
= "Cortex-M0 DWT";
1248 full
= "(Data Watchpoint and Trace)";
1251 type
= "Cortex-M0 BPU";
1252 full
= "(Breakpoint Unit)";
1255 type
= "Cortex-M4 SCS";
1256 full
= "(System Control Space)";
1259 type
= "CoreSight ETM11";
1260 full
= "(Embedded Trace)";
1262 /* case 0x113: what? */
1263 case 0x120: /* from OMAP3 memmap */
1265 full
= "(System Debug Trace Interface)";
1267 case 0x343: /* from OMAP3 memmap */
1272 type
= "Coresight CTI";
1273 full
= "(Cross Trigger)";
1276 type
= "Coresight ETB";
1277 full
= "(Trace Buffer)";
1280 type
= "Coresight CSTF";
1281 full
= "(Trace Funnel)";
1284 type
= "CoreSight ETM9";
1285 full
= "(Embedded Trace)";
1288 type
= "Coresight TPIU";
1289 full
= "(Trace Port Interface Unit)";
1292 type
= "Coresight ITM";
1293 full
= "(Instrumentation Trace Macrocell)";
1296 type
= "Coresight SWO";
1297 full
= "(Single Wire Output)";
1300 type
= "Coresight HTM";
1301 full
= "(AHB Trace Macrocell)";
1304 type
= "CoreSight ETM11";
1305 full
= "(Embedded Trace)";
1308 type
= "Cortex-A8 ETM";
1309 full
= "(Embedded Trace)";
1312 type
= "Cortex-A8 CTI";
1313 full
= "(Cross Trigger)";
1316 type
= "Cortex-M3 TPIU";
1317 full
= "(Trace Port Interface Unit)";
1320 type
= "Cortex-M3 ETM";
1321 full
= "(Embedded Trace)";
1324 type
= "Cortex-M4 ETM";
1325 full
= "(Embedded Trace)";
1328 type
= "Cortex-R4 ETM";
1329 full
= "(Embedded Trace)";
1332 type
= "CoreSight Component";
1333 full
= "(unidentified Cortex-A9 component)";
1336 type
= "CoreSight TMC";
1337 full
= "(Trace Memory Controller)";
1340 type
= "CoreSight STM";
1341 full
= "(System Trace Macrocell)";
1344 type
= "CoreSight PMU";
1345 full
= "(Performance Monitoring Unit)";
1348 type
= "Cortex-M4 TPUI";
1349 full
= "(Trace Port Interface Unit)";
1352 type
= "Cortex-A5 ETM";
1353 full
= "(Embedded Trace)";
1356 type
= "Cortex-A5 Debug";
1357 full
= "(Debug Unit)";
1360 type
= "Cortex-A8 Debug";
1361 full
= "(Debug Unit)";
1364 type
= "Cortex-A9 Debug";
1365 full
= "(Debug Unit)";
1368 type
= "Cortex-A15 Debug";
1369 full
= "(Debug Unit)";
1372 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32
, part_num
);
1373 type
= "-*- unrecognized -*-";
1377 command_print(cmd_ctx
, "\t\tPart is %s %s",
1381 if (((c_cid1
>> 4) & 0x0f) == 1) {
1382 retval
= dap_rom_display(cmd_ctx
, ap
, component_base
, depth
+ 1);
1383 if (retval
!= ERROR_OK
)
1388 command_print(cmd_ctx
, "\t\tComponent not present");
1393 command_print(cmd_ctx
, "\t%s\tEnd of ROM table", tabs
);
1397 static int dap_info_command(struct command_context
*cmd_ctx
,
1398 struct adiv5_ap
*ap
)
1401 uint32_t dbgbase
, apid
;
1402 int romtable_present
= 0;
1405 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1406 retval
= dap_get_debugbase(ap
, &dbgbase
, &apid
);
1407 if (retval
!= ERROR_OK
)
1410 command_print(cmd_ctx
, "AP ID register 0x%8.8" PRIx32
, apid
);
1412 command_print(cmd_ctx
, "No AP found at this ap 0x%x", ap
->ap_num
);
1416 switch (apid
& (IDR_JEP106
| IDR_TYPE
)) {
1417 case IDR_JEP106_ARM
| AP_TYPE_JTAG_AP
:
1418 command_print(cmd_ctx
, "\tType is JTAG-AP");
1420 case IDR_JEP106_ARM
| AP_TYPE_AHB_AP
:
1421 command_print(cmd_ctx
, "\tType is MEM-AP AHB");
1423 case IDR_JEP106_ARM
| AP_TYPE_APB_AP
:
1424 command_print(cmd_ctx
, "\tType is MEM-AP APB");
1426 case IDR_JEP106_ARM
| AP_TYPE_AXI_AP
:
1427 command_print(cmd_ctx
, "\tType is MEM-AP AXI");
1430 command_print(cmd_ctx
, "\tUnknown AP type");
1434 /* NOTE: a MEM-AP may have a single CoreSight component that's
1435 * not a ROM table ... or have no such components at all.
1437 mem_ap
= (apid
& IDR_CLASS
) == AP_CLASS_MEM_AP
;
1439 command_print(cmd_ctx
, "MEM-AP BASE 0x%8.8" PRIx32
, dbgbase
);
1441 romtable_present
= dbgbase
!= 0xFFFFFFFF;
1442 if (romtable_present
)
1443 dap_rom_display(cmd_ctx
, ap
, dbgbase
, 0);
1445 command_print(cmd_ctx
, "\tNo ROM table present");
1451 COMMAND_HANDLER(handle_dap_info_command
)
1453 struct target
*target
= get_current_target(CMD_CTX
);
1454 struct arm
*arm
= target_to_arm(target
);
1455 struct adiv5_dap
*dap
= arm
->dap
;
1463 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1465 return ERROR_COMMAND_SYNTAX_ERROR
;
1468 return ERROR_COMMAND_SYNTAX_ERROR
;
1471 return dap_info_command(CMD_CTX
, &dap
->ap
[apsel
]);
1474 COMMAND_HANDLER(dap_baseaddr_command
)
1476 struct target
*target
= get_current_target(CMD_CTX
);
1477 struct arm
*arm
= target_to_arm(target
);
1478 struct adiv5_dap
*dap
= arm
->dap
;
1480 uint32_t apsel
, baseaddr
;
1488 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1489 /* AP address is in bits 31:24 of DP_SELECT */
1491 return ERROR_COMMAND_SYNTAX_ERROR
;
1494 return ERROR_COMMAND_SYNTAX_ERROR
;
1497 dap_ap_select(dap
, apsel
);
1499 /* NOTE: assumes we're talking to a MEM-AP, which
1500 * has a base address. There are other kinds of AP,
1501 * though they're not common for now. This should
1502 * use the ID register to verify it's a MEM-AP.
1504 retval
= dap_queue_ap_read(dap
, MEM_AP_REG_BASE
, &baseaddr
);
1505 if (retval
!= ERROR_OK
)
1507 retval
= dap_run(dap
);
1508 if (retval
!= ERROR_OK
)
1511 command_print(CMD_CTX
, "0x%8.8" PRIx32
, baseaddr
);
1516 COMMAND_HANDLER(dap_memaccess_command
)
1518 struct target
*target
= get_current_target(CMD_CTX
);
1519 struct arm
*arm
= target_to_arm(target
);
1520 struct adiv5_dap
*dap
= arm
->dap
;
1522 uint32_t memaccess_tck
;
1526 memaccess_tck
= dap
->ap
[dap
->apsel
].memaccess_tck
;
1529 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], memaccess_tck
);
1532 return ERROR_COMMAND_SYNTAX_ERROR
;
1534 dap
->ap
[dap
->apsel
].memaccess_tck
= memaccess_tck
;
1536 command_print(CMD_CTX
, "memory bus access delay set to %" PRIi32
" tck",
1537 dap
->ap
[dap
->apsel
].memaccess_tck
);
1542 COMMAND_HANDLER(dap_apsel_command
)
1544 struct target
*target
= get_current_target(CMD_CTX
);
1545 struct arm
*arm
= target_to_arm(target
);
1546 struct adiv5_dap
*dap
= arm
->dap
;
1548 uint32_t apsel
, apid
;
1556 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1557 /* AP address is in bits 31:24 of DP_SELECT */
1559 return ERROR_COMMAND_SYNTAX_ERROR
;
1562 return ERROR_COMMAND_SYNTAX_ERROR
;
1566 dap_ap_select(dap
, apsel
);
1568 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1569 if (retval
!= ERROR_OK
)
1571 retval
= dap_run(dap
);
1572 if (retval
!= ERROR_OK
)
1575 command_print(CMD_CTX
, "ap %" PRIi32
" selected, identification register 0x%8.8" PRIx32
,
1581 COMMAND_HANDLER(dap_apcsw_command
)
1583 struct target
*target
= get_current_target(CMD_CTX
);
1584 struct arm
*arm
= target_to_arm(target
);
1585 struct adiv5_dap
*dap
= arm
->dap
;
1587 uint32_t apcsw
= dap
->ap
[dap
->apsel
].csw_default
, sprot
= 0;
1591 command_print(CMD_CTX
, "apsel %" PRIi32
" selected, csw 0x%8.8" PRIx32
,
1592 (dap
->apsel
), apcsw
);
1595 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], sprot
);
1596 /* AP address is in bits 31:24 of DP_SELECT */
1598 return ERROR_COMMAND_SYNTAX_ERROR
;
1602 apcsw
&= ~CSW_SPROT
;
1605 return ERROR_COMMAND_SYNTAX_ERROR
;
1607 dap
->ap
[dap
->apsel
].csw_default
= apcsw
;
1614 COMMAND_HANDLER(dap_apid_command
)
1616 struct target
*target
= get_current_target(CMD_CTX
);
1617 struct arm
*arm
= target_to_arm(target
);
1618 struct adiv5_dap
*dap
= arm
->dap
;
1620 uint32_t apsel
, apid
;
1628 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
1629 /* AP address is in bits 31:24 of DP_SELECT */
1631 return ERROR_COMMAND_SYNTAX_ERROR
;
1634 return ERROR_COMMAND_SYNTAX_ERROR
;
1637 dap_ap_select(dap
, apsel
);
1639 retval
= dap_queue_ap_read(dap
, AP_REG_IDR
, &apid
);
1640 if (retval
!= ERROR_OK
)
1642 retval
= dap_run(dap
);
1643 if (retval
!= ERROR_OK
)
1646 command_print(CMD_CTX
, "0x%8.8" PRIx32
, apid
);
1651 COMMAND_HANDLER(dap_ti_be_32_quirks_command
)
1653 struct target
*target
= get_current_target(CMD_CTX
);
1654 struct arm
*arm
= target_to_arm(target
);
1655 struct adiv5_dap
*dap
= arm
->dap
;
1657 uint32_t enable
= dap
->ti_be_32_quirks
;
1663 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], enable
);
1665 return ERROR_COMMAND_SYNTAX_ERROR
;
1668 return ERROR_COMMAND_SYNTAX_ERROR
;
1670 dap
->ti_be_32_quirks
= enable
;
1671 command_print(CMD_CTX
, "TI BE-32 quirks mode %s",
1672 enable
? "enabled" : "disabled");
1677 static const struct command_registration dap_commands
[] = {
1680 .handler
= handle_dap_info_command
,
1681 .mode
= COMMAND_EXEC
,
1682 .help
= "display ROM table for MEM-AP "
1683 "(default currently selected AP)",
1684 .usage
= "[ap_num]",
1688 .handler
= dap_apsel_command
,
1689 .mode
= COMMAND_EXEC
,
1690 .help
= "Set the currently selected AP (default 0) "
1691 "and display the result",
1692 .usage
= "[ap_num]",
1696 .handler
= dap_apcsw_command
,
1697 .mode
= COMMAND_EXEC
,
1698 .help
= "Set csw access bit ",
1704 .handler
= dap_apid_command
,
1705 .mode
= COMMAND_EXEC
,
1706 .help
= "return ID register from AP "
1707 "(default currently selected AP)",
1708 .usage
= "[ap_num]",
1712 .handler
= dap_baseaddr_command
,
1713 .mode
= COMMAND_EXEC
,
1714 .help
= "return debug base address from MEM-AP "
1715 "(default currently selected AP)",
1716 .usage
= "[ap_num]",
1719 .name
= "memaccess",
1720 .handler
= dap_memaccess_command
,
1721 .mode
= COMMAND_EXEC
,
1722 .help
= "set/get number of extra tck for MEM-AP memory "
1723 "bus access [0-255]",
1724 .usage
= "[cycles]",
1727 .name
= "ti_be_32_quirks",
1728 .handler
= dap_ti_be_32_quirks_command
,
1729 .mode
= COMMAND_CONFIG
,
1730 .help
= "set/get quirks mode for TI TMS450/TMS570 processors",
1731 .usage
= "[enable]",
1733 COMMAND_REGISTRATION_DONE
1736 const struct command_registration dap_command_handlers
[] = {
1739 .mode
= COMMAND_EXEC
,
1740 .help
= "DAP command group",
1742 .chain
= dap_commands
,
1744 COMMAND_REGISTRATION_DONE
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