arm_adi_v5: do not deactivate power domains while trying to clear sticky error
[openocd.git] / src / target / arm_adi_v5.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
3 * lundin@mlu.mine.nu *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2009-2010 by David Brownell *
12 * *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
29
30 /**
31 * @file
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
37 *
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 *
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
57 */
58
59 /*
60 * Relevant specifications from ARM include:
61 *
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 *
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
67 */
68
69 #ifdef HAVE_CONFIG_H
70 #include "config.h"
71 #endif
72
73 #include "jtag/interface.h"
74 #include "arm.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
79 #include <helper/jim-nvp.h>
80
81 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
82
83 /*
84 uint32_t tar_block_size(uint32_t address)
85 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 */
87 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 {
89 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
90 }
91
92 /***************************************************************************
93 * *
94 * DP and MEM-AP register access through APACC and DPACC *
95 * *
96 ***************************************************************************/
97
98 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 {
100 csw |= ap->csw_default;
101
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK) {
106 ap->csw_value = 0;
107 return retval;
108 }
109 ap->csw_value = csw;
110 }
111 return ERROR_OK;
112 }
113
114 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
115 {
116 if (!ap->tar_valid || tar != ap->tar_value) {
117 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
118 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
119 if (retval != ERROR_OK) {
120 ap->tar_valid = false;
121 return retval;
122 }
123 ap->tar_value = tar;
124 ap->tar_valid = true;
125 }
126 return ERROR_OK;
127 }
128
129 static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
130 {
131 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
132 if (retval != ERROR_OK) {
133 ap->tar_valid = false;
134 return retval;
135 }
136
137 retval = dap_run(ap->dap);
138 if (retval != ERROR_OK) {
139 ap->tar_valid = false;
140 return retval;
141 }
142
143 ap->tar_value = *tar;
144 ap->tar_valid = true;
145 return ERROR_OK;
146 }
147
148 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
149 {
150 switch (ap->csw_value & CSW_ADDRINC_MASK) {
151 case CSW_ADDRINC_SINGLE:
152 switch (ap->csw_value & CSW_SIZE_MASK) {
153 case CSW_8BIT:
154 return 1;
155 case CSW_16BIT:
156 return 2;
157 case CSW_32BIT:
158 return 4;
159 default:
160 return 0;
161 }
162 case CSW_ADDRINC_PACKED:
163 return 4;
164 }
165 return 0;
166 }
167
168 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
169 */
170 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
171 {
172 if (!ap->tar_valid)
173 return;
174
175 uint32_t inc = mem_ap_get_tar_increment(ap);
176 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
177 ap->tar_valid = false;
178 else
179 ap->tar_value += inc;
180 }
181
182 /**
183 * Queue transactions setting up transfer parameters for the
184 * currently selected MEM-AP.
185 *
186 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
187 * initiate data reads or writes using memory or peripheral addresses.
188 * If the CSW is configured for it, the TAR may be automatically
189 * incremented after each transfer.
190 *
191 * @param ap The MEM-AP.
192 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
193 * matches the cached value, the register is not changed.
194 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
195 * matches the cached address, the register is not changed.
196 *
197 * @return ERROR_OK if the transaction was properly queued, else a fault code.
198 */
199 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
200 {
201 int retval;
202 retval = mem_ap_setup_csw(ap, csw);
203 if (retval != ERROR_OK)
204 return retval;
205 retval = mem_ap_setup_tar(ap, tar);
206 if (retval != ERROR_OK)
207 return retval;
208 return ERROR_OK;
209 }
210
211 /**
212 * Asynchronous (queued) read of a word from memory or a system register.
213 *
214 * @param ap The MEM-AP to access.
215 * @param address Address of the 32-bit word to read; it must be
216 * readable by the currently selected MEM-AP.
217 * @param value points to where the word will be stored when the
218 * transaction queue is flushed (assuming no errors).
219 *
220 * @return ERROR_OK for success. Otherwise a fault code.
221 */
222 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
223 uint32_t *value)
224 {
225 int retval;
226
227 /* Use banked addressing (REG_BDx) to avoid some link traffic
228 * (updating TAR) when reading several consecutive addresses.
229 */
230 retval = mem_ap_setup_transfer(ap,
231 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
232 address & 0xFFFFFFF0);
233 if (retval != ERROR_OK)
234 return retval;
235
236 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
237 }
238
239 /**
240 * Synchronous read of a word from memory or a system register.
241 * As a side effect, this flushes any queued transactions.
242 *
243 * @param ap The MEM-AP to access.
244 * @param address Address of the 32-bit word to read; it must be
245 * readable by the currently selected MEM-AP.
246 * @param value points to where the result will be stored.
247 *
248 * @return ERROR_OK for success; *value holds the result.
249 * Otherwise a fault code.
250 */
251 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
252 uint32_t *value)
253 {
254 int retval;
255
256 retval = mem_ap_read_u32(ap, address, value);
257 if (retval != ERROR_OK)
258 return retval;
259
260 return dap_run(ap->dap);
261 }
262
263 /**
264 * Asynchronous (queued) write of a word to memory or a system register.
265 *
266 * @param ap The MEM-AP to access.
267 * @param address Address to be written; it must be writable by
268 * the currently selected MEM-AP.
269 * @param value Word that will be written to the address when transaction
270 * queue is flushed (assuming no errors).
271 *
272 * @return ERROR_OK for success. Otherwise a fault code.
273 */
274 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
275 uint32_t value)
276 {
277 int retval;
278
279 /* Use banked addressing (REG_BDx) to avoid some link traffic
280 * (updating TAR) when writing several consecutive addresses.
281 */
282 retval = mem_ap_setup_transfer(ap,
283 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
284 address & 0xFFFFFFF0);
285 if (retval != ERROR_OK)
286 return retval;
287
288 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
289 value);
290 }
291
292 /**
293 * Synchronous write of a word to memory or a system register.
294 * As a side effect, this flushes any queued transactions.
295 *
296 * @param ap The MEM-AP to access.
297 * @param address Address to be written; it must be writable by
298 * the currently selected MEM-AP.
299 * @param value Word that will be written.
300 *
301 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
302 */
303 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
304 uint32_t value)
305 {
306 int retval = mem_ap_write_u32(ap, address, value);
307
308 if (retval != ERROR_OK)
309 return retval;
310
311 return dap_run(ap->dap);
312 }
313
314 /**
315 * Synchronous write of a block of memory, using a specific access size.
316 *
317 * @param ap The MEM-AP to access.
318 * @param buffer The data buffer to write. No particular alignment is assumed.
319 * @param size Which access size to use, in bytes. 1, 2 or 4.
320 * @param count The number of writes to do (in size units, not bytes).
321 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
322 * @param addrinc Whether the target address should be increased for each write or not. This
323 * should normally be true, except when writing to e.g. a FIFO.
324 * @return ERROR_OK on success, otherwise an error code.
325 */
326 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
327 uint32_t address, bool addrinc)
328 {
329 struct adiv5_dap *dap = ap->dap;
330 size_t nbytes = size * count;
331 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
332 uint32_t csw_size;
333 uint32_t addr_xor;
334 int retval = ERROR_OK;
335
336 /* TI BE-32 Quirks mode:
337 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
338 * size write address bytes written in order
339 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
340 * 2 TAR ^ 2 (val >> 8), (val)
341 * 1 TAR ^ 3 (val)
342 * For example, if you attempt to write a single byte to address 0, the processor
343 * will actually write a byte to address 3.
344 *
345 * To make writes of size < 4 work as expected, we xor a value with the address before
346 * setting the TAP, and we set the TAP after every transfer rather then relying on
347 * address increment. */
348
349 if (size == 4) {
350 csw_size = CSW_32BIT;
351 addr_xor = 0;
352 } else if (size == 2) {
353 csw_size = CSW_16BIT;
354 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
355 } else if (size == 1) {
356 csw_size = CSW_8BIT;
357 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
358 } else {
359 return ERROR_TARGET_UNALIGNED_ACCESS;
360 }
361
362 if (ap->unaligned_access_bad && (address % size != 0))
363 return ERROR_TARGET_UNALIGNED_ACCESS;
364
365 while (nbytes > 0) {
366 uint32_t this_size = size;
367
368 /* Select packed transfer if possible */
369 if (addrinc && ap->packed_transfers && nbytes >= 4
370 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
371 this_size = 4;
372 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
373 } else {
374 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
375 }
376
377 if (retval != ERROR_OK)
378 break;
379
380 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
381 if (retval != ERROR_OK)
382 return retval;
383
384 /* How many source bytes each transfer will consume, and their location in the DRW,
385 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
386 uint32_t outvalue = 0;
387 uint32_t drw_byte_idx = address;
388 if (dap->ti_be_32_quirks) {
389 switch (this_size) {
390 case 4:
391 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
392 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
393 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
394 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
395 break;
396 case 2:
397 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
398 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
399 break;
400 case 1:
401 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
402 break;
403 }
404 } else {
405 switch (this_size) {
406 case 4:
407 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
408 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
409 /* fallthrough */
410 case 2:
411 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
412 /* fallthrough */
413 case 1:
414 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
415 }
416 }
417
418 nbytes -= this_size;
419
420 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
421 if (retval != ERROR_OK)
422 break;
423
424 mem_ap_update_tar_cache(ap);
425 if (addrinc)
426 address += this_size;
427 }
428
429 /* REVISIT: Might want to have a queued version of this function that does not run. */
430 if (retval == ERROR_OK)
431 retval = dap_run(dap);
432
433 if (retval != ERROR_OK) {
434 uint32_t tar;
435 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
436 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
437 else
438 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
439 }
440
441 return retval;
442 }
443
444 /**
445 * Synchronous read of a block of memory, using a specific access size.
446 *
447 * @param ap The MEM-AP to access.
448 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
449 * @param size Which access size to use, in bytes. 1, 2 or 4.
450 * @param count The number of reads to do (in size units, not bytes).
451 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
452 * @param addrinc Whether the target address should be increased after each read or not. This
453 * should normally be true, except when reading from e.g. a FIFO.
454 * @return ERROR_OK on success, otherwise an error code.
455 */
456 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
457 uint32_t adr, bool addrinc)
458 {
459 struct adiv5_dap *dap = ap->dap;
460 size_t nbytes = size * count;
461 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
462 uint32_t csw_size;
463 uint32_t address = adr;
464 int retval = ERROR_OK;
465
466 /* TI BE-32 Quirks mode:
467 * Reads on big-endian TMS570 behave strangely differently than writes.
468 * They read from the physical address requested, but with DRW byte-reversed.
469 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
470 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
471 * so avoid them. */
472
473 if (size == 4)
474 csw_size = CSW_32BIT;
475 else if (size == 2)
476 csw_size = CSW_16BIT;
477 else if (size == 1)
478 csw_size = CSW_8BIT;
479 else
480 return ERROR_TARGET_UNALIGNED_ACCESS;
481
482 if (ap->unaligned_access_bad && (adr % size != 0))
483 return ERROR_TARGET_UNALIGNED_ACCESS;
484
485 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
486 * over-allocation if packed transfers are going to be used, but determining the real need at
487 * this point would be messy. */
488 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
489 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
490 uint32_t *read_ptr = read_buf;
491 if (read_buf == NULL) {
492 LOG_ERROR("Failed to allocate read buffer");
493 return ERROR_FAIL;
494 }
495
496 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
497 * useful bytes it contains, and their location in the word, depends on the type of transfer
498 * and alignment. */
499 while (nbytes > 0) {
500 uint32_t this_size = size;
501
502 /* Select packed transfer if possible */
503 if (addrinc && ap->packed_transfers && nbytes >= 4
504 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
505 this_size = 4;
506 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
507 } else {
508 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
509 }
510 if (retval != ERROR_OK)
511 break;
512
513 retval = mem_ap_setup_tar(ap, address);
514 if (retval != ERROR_OK)
515 break;
516
517 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
518 if (retval != ERROR_OK)
519 break;
520
521 nbytes -= this_size;
522 if (addrinc)
523 address += this_size;
524
525 mem_ap_update_tar_cache(ap);
526 }
527
528 if (retval == ERROR_OK)
529 retval = dap_run(dap);
530
531 /* Restore state */
532 address = adr;
533 nbytes = size * count;
534 read_ptr = read_buf;
535
536 /* If something failed, read TAR to find out how much data was successfully read, so we can
537 * at least give the caller what we have. */
538 if (retval != ERROR_OK) {
539 uint32_t tar;
540 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
541 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
542 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
543 if (nbytes > tar - address)
544 nbytes = tar - address;
545 } else {
546 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
547 nbytes = 0;
548 }
549 }
550
551 /* Replay loop to populate caller's buffer from the correct word and byte lane */
552 while (nbytes > 0) {
553 uint32_t this_size = size;
554
555 if (addrinc && ap->packed_transfers && nbytes >= 4
556 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
557 this_size = 4;
558 }
559
560 if (dap->ti_be_32_quirks) {
561 switch (this_size) {
562 case 4:
563 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
564 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
565 /* fallthrough */
566 case 2:
567 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
568 /* fallthrough */
569 case 1:
570 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
571 }
572 } else {
573 switch (this_size) {
574 case 4:
575 *buffer++ = *read_ptr >> 8 * (address++ & 3);
576 *buffer++ = *read_ptr >> 8 * (address++ & 3);
577 /* fallthrough */
578 case 2:
579 *buffer++ = *read_ptr >> 8 * (address++ & 3);
580 /* fallthrough */
581 case 1:
582 *buffer++ = *read_ptr >> 8 * (address++ & 3);
583 }
584 }
585
586 read_ptr++;
587 nbytes -= this_size;
588 }
589
590 free(read_buf);
591 return retval;
592 }
593
594 int mem_ap_read_buf(struct adiv5_ap *ap,
595 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
596 {
597 return mem_ap_read(ap, buffer, size, count, address, true);
598 }
599
600 int mem_ap_write_buf(struct adiv5_ap *ap,
601 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
602 {
603 return mem_ap_write(ap, buffer, size, count, address, true);
604 }
605
606 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
607 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
608 {
609 return mem_ap_read(ap, buffer, size, count, address, false);
610 }
611
612 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
613 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
614 {
615 return mem_ap_write(ap, buffer, size, count, address, false);
616 }
617
618 /*--------------------------------------------------------------------------*/
619
620
621 #define DAP_POWER_DOMAIN_TIMEOUT (10)
622
623 /*--------------------------------------------------------------------------*/
624
625 /**
626 * Invalidate cached DP select and cached TAR and CSW of all APs
627 */
628 void dap_invalidate_cache(struct adiv5_dap *dap)
629 {
630 dap->select = DP_SELECT_INVALID;
631 dap->last_read = NULL;
632
633 int i;
634 for (i = 0; i <= 255; i++) {
635 /* force csw and tar write on the next mem-ap access */
636 dap->ap[i].tar_valid = false;
637 dap->ap[i].csw_value = 0;
638 }
639 }
640
641 /**
642 * Initialize a DAP. This sets up the power domains, prepares the DP
643 * for further use and activates overrun checking.
644 *
645 * @param dap The DAP being initialized.
646 */
647 int dap_dp_init(struct adiv5_dap *dap)
648 {
649 int retval;
650
651 LOG_DEBUG("%s", adiv5_dap_name(dap));
652
653 dap_invalidate_cache(dap);
654
655 /*
656 * Early initialize dap->dp_ctrl_stat.
657 * In jtag mode only, if the following atomic reads fail and set the
658 * sticky error, it will trigger the clearing of the sticky. Without this
659 * initialization system and debug power would be disabled while clearing
660 * the sticky error bit.
661 */
662 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
663
664 for (size_t i = 0; i < 30; i++) {
665 /* DP initialization */
666
667 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
668 if (retval == ERROR_OK)
669 break;
670 }
671
672 /*
673 * This write operation clears the sticky error bit in jtag mode only and
674 * is ignored in swd mode. It also powers-up system and debug domains in
675 * both jtag and swd modes, if not done before.
676 * Actually we do not need to clear the sticky error here because it has
677 * been already cleared (if it was set) in the previous atomic read. This
678 * write could be removed, but this initial part of dap_dp_init() is the
679 * result of years of fine tuning and there are strong concerns about any
680 * unnecessary code change. It doesn't harm, so let's keep it here and
681 * preserve the historical sequence of read/write operations!
682 */
683 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat | SSTICKYERR);
684 if (retval != ERROR_OK)
685 return retval;
686
687 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
688 if (retval != ERROR_OK)
689 return retval;
690
691 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
692 if (retval != ERROR_OK)
693 return retval;
694
695 /* Check that we have debug power domains activated */
696 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
697 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
698 CDBGPWRUPACK, CDBGPWRUPACK,
699 DAP_POWER_DOMAIN_TIMEOUT);
700 if (retval != ERROR_OK)
701 return retval;
702
703 if (!dap->ignore_syspwrupack) {
704 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
705 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
706 CSYSPWRUPACK, CSYSPWRUPACK,
707 DAP_POWER_DOMAIN_TIMEOUT);
708 if (retval != ERROR_OK)
709 return retval;
710 }
711
712 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
713 if (retval != ERROR_OK)
714 return retval;
715
716 /* With debug power on we can activate OVERRUN checking */
717 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
718 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
719 if (retval != ERROR_OK)
720 return retval;
721 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
722 if (retval != ERROR_OK)
723 return retval;
724
725 retval = dap_run(dap);
726 if (retval != ERROR_OK)
727 return retval;
728
729 return retval;
730 }
731
732 /**
733 * Initialize a DAP. This sets up the power domains, prepares the DP
734 * for further use, and arranges to use AP #0 for all AP operations
735 * until dap_ap-select() changes that policy.
736 *
737 * @param ap The MEM-AP being initialized.
738 */
739 int mem_ap_init(struct adiv5_ap *ap)
740 {
741 /* check that we support packed transfers */
742 uint32_t csw, cfg;
743 int retval;
744 struct adiv5_dap *dap = ap->dap;
745
746 ap->tar_valid = false;
747 ap->csw_value = 0; /* force csw and tar write */
748 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
749 if (retval != ERROR_OK)
750 return retval;
751
752 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
753 if (retval != ERROR_OK)
754 return retval;
755
756 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
757 if (retval != ERROR_OK)
758 return retval;
759
760 retval = dap_run(dap);
761 if (retval != ERROR_OK)
762 return retval;
763
764 if (csw & CSW_ADDRINC_PACKED)
765 ap->packed_transfers = true;
766 else
767 ap->packed_transfers = false;
768
769 /* Packed transfers on TI BE-32 processors do not work correctly in
770 * many cases. */
771 if (dap->ti_be_32_quirks)
772 ap->packed_transfers = false;
773
774 LOG_DEBUG("MEM_AP Packed Transfers: %s",
775 ap->packed_transfers ? "enabled" : "disabled");
776
777 /* The ARM ADI spec leaves implementation-defined whether unaligned
778 * memory accesses work, only work partially, or cause a sticky error.
779 * On TI BE-32 processors, reads seem to return garbage in some bytes
780 * and unaligned writes seem to cause a sticky error.
781 * TODO: it would be nice to have a way to detect whether unaligned
782 * operations are supported on other processors. */
783 ap->unaligned_access_bad = dap->ti_be_32_quirks;
784
785 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
786 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
787
788 return ERROR_OK;
789 }
790
791 /* CID interpretation -- see ARM IHI 0029B section 3
792 * and ARM IHI 0031A table 13-3.
793 */
794 static const char *class_description[16] = {
795 "Reserved", "ROM table", "Reserved", "Reserved",
796 "Reserved", "Reserved", "Reserved", "Reserved",
797 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
798 "Reserved", "OptimoDE DESS",
799 "Generic IP component", "PrimeCell or System component"
800 };
801
802 static bool is_dap_cid_ok(uint32_t cid)
803 {
804 return (cid & 0xffff0fff) == 0xb105000d;
805 }
806
807 /*
808 * This function checks the ID for each access port to find the requested Access Port type
809 */
810 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
811 {
812 int ap_num;
813
814 /* Maximum AP number is 255 since the SELECT register is 8 bits */
815 for (ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
816
817 /* read the IDR register of the Access Port */
818 uint32_t id_val = 0;
819
820 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
821 if (retval != ERROR_OK)
822 return retval;
823
824 retval = dap_run(dap);
825
826 /* IDR bits:
827 * 31-28 : Revision
828 * 27-24 : JEDEC bank (0x4 for ARM)
829 * 23-17 : JEDEC code (0x3B for ARM)
830 * 16-13 : Class (0b1000=Mem-AP)
831 * 12-8 : Reserved
832 * 7-4 : AP Variant (non-zero for JTAG-AP)
833 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
834 */
835
836 /* Reading register for a non-existant AP should not cause an error,
837 * but just to be sure, try to continue searching if an error does happen.
838 */
839 if ((retval == ERROR_OK) && /* Register read success */
840 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
841 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
842
843 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
844 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
845 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
846 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
847 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
848 ap_num, id_val);
849
850 *ap_out = &dap->ap[ap_num];
851 return ERROR_OK;
852 }
853 }
854
855 LOG_DEBUG("No %s found",
856 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
857 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
858 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
859 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
860 return ERROR_FAIL;
861 }
862
863 int dap_get_debugbase(struct adiv5_ap *ap,
864 uint32_t *dbgbase, uint32_t *apid)
865 {
866 struct adiv5_dap *dap = ap->dap;
867 int retval;
868
869 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
870 if (retval != ERROR_OK)
871 return retval;
872 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
873 if (retval != ERROR_OK)
874 return retval;
875 retval = dap_run(dap);
876 if (retval != ERROR_OK)
877 return retval;
878
879 return ERROR_OK;
880 }
881
882 int dap_lookup_cs_component(struct adiv5_ap *ap,
883 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
884 {
885 uint32_t romentry, entry_offset = 0, component_base, devtype;
886 int retval;
887
888 *addr = 0;
889
890 do {
891 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
892 entry_offset, &romentry);
893 if (retval != ERROR_OK)
894 return retval;
895
896 component_base = (dbgbase & 0xFFFFF000)
897 + (romentry & 0xFFFFF000);
898
899 if (romentry & 0x1) {
900 uint32_t c_cid1;
901 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
902 if (retval != ERROR_OK) {
903 LOG_ERROR("Can't read component with base address 0x%" PRIx32
904 ", the corresponding core might be turned off", component_base);
905 return retval;
906 }
907 if (((c_cid1 >> 4) & 0x0f) == 1) {
908 retval = dap_lookup_cs_component(ap, component_base,
909 type, addr, idx);
910 if (retval == ERROR_OK)
911 break;
912 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
913 return retval;
914 }
915
916 retval = mem_ap_read_atomic_u32(ap,
917 (component_base & 0xfffff000) | 0xfcc,
918 &devtype);
919 if (retval != ERROR_OK)
920 return retval;
921 if ((devtype & 0xff) == type) {
922 if (!*idx) {
923 *addr = component_base;
924 break;
925 } else
926 (*idx)--;
927 }
928 }
929 entry_offset += 4;
930 } while (romentry > 0);
931
932 if (!*addr)
933 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
934
935 return ERROR_OK;
936 }
937
938 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
939 {
940 assert((component_base & 0xFFF) == 0);
941 assert(ap != NULL && cid != NULL && pid != NULL);
942
943 uint32_t cid0, cid1, cid2, cid3;
944 uint32_t pid0, pid1, pid2, pid3, pid4;
945 int retval;
946
947 /* IDs are in last 4K section */
948 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
949 if (retval != ERROR_OK)
950 return retval;
951 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
952 if (retval != ERROR_OK)
953 return retval;
954 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
955 if (retval != ERROR_OK)
956 return retval;
957 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
958 if (retval != ERROR_OK)
959 return retval;
960 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
961 if (retval != ERROR_OK)
962 return retval;
963 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
964 if (retval != ERROR_OK)
965 return retval;
966 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
967 if (retval != ERROR_OK)
968 return retval;
969 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
970 if (retval != ERROR_OK)
971 return retval;
972 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
973 if (retval != ERROR_OK)
974 return retval;
975
976 retval = dap_run(ap->dap);
977 if (retval != ERROR_OK)
978 return retval;
979
980 *cid = (cid3 & 0xff) << 24
981 | (cid2 & 0xff) << 16
982 | (cid1 & 0xff) << 8
983 | (cid0 & 0xff);
984 *pid = (uint64_t)(pid4 & 0xff) << 32
985 | (pid3 & 0xff) << 24
986 | (pid2 & 0xff) << 16
987 | (pid1 & 0xff) << 8
988 | (pid0 & 0xff);
989
990 return ERROR_OK;
991 }
992
993 /* The designer identity code is encoded as:
994 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
995 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
996 * a legacy ASCII Identity Code.
997 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
998 * JEP106 is a standard available from jedec.org
999 */
1000
1001 /* Part number interpretations are from Cortex
1002 * core specs, the CoreSight components TRM
1003 * (ARM DDI 0314H), CoreSight System Design
1004 * Guide (ARM DGI 0012D) and ETM specs; also
1005 * from chip observation (e.g. TI SDTI).
1006 */
1007
1008 /* The legacy code only used the part number field to identify CoreSight peripherals.
1009 * This meant that the same part number from two different manufacturers looked the same.
1010 * It is desirable for all future additions to identify with both part number and JEP106.
1011 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
1012 */
1013
1014 #define ANY_ID 0x1000
1015
1016 #define ARM_ID 0x4BB
1017
1018 static const struct {
1019 uint16_t designer_id;
1020 uint16_t part_num;
1021 const char *type;
1022 const char *full;
1023 } dap_partnums[] = {
1024 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1025 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1026 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1027 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1028 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1029 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1030 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1031 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1032 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1033 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1034 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1035 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1036 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1037 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1038 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1039 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1040 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1041 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1042 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1043 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1044 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1045 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1046 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1047 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1048 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1049 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1050 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1051 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1052 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1053 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1054 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1055 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1056 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1057 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1058 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1059 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1060 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1061 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1062 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1063 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1064 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1065 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1066 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1067 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1068 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1069 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1070 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1071 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1072 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1073 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1074 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1075 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1076 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1077 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1078 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1079 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1080 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1081 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1082 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1083 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1084 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1085 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1086 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1087 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1088 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1089 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1090 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1091 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1092 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1093 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1094 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1095 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1096 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1097 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1098 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1099 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1100 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1101 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1102 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1103 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1104 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1105 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1106 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1107 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1108 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1109 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1110 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1111 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1112 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1113 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1114 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1115 /* legacy comment: 0x113: what? */
1116 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1117 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1118 };
1119
1120 static int dap_rom_display(struct command_context *cmd_ctx,
1121 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1122 {
1123 int retval;
1124 uint64_t pid;
1125 uint32_t cid;
1126 char tabs[16] = "";
1127
1128 if (depth > 16) {
1129 command_print(cmd_ctx, "\tTables too deep");
1130 return ERROR_FAIL;
1131 }
1132
1133 if (depth)
1134 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1135
1136 uint32_t base_addr = dbgbase & 0xFFFFF000;
1137 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1138
1139 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1140 if (retval != ERROR_OK) {
1141 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1142 return ERROR_OK; /* Don't abort recursion */
1143 }
1144
1145 if (!is_dap_cid_ok(cid)) {
1146 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1147 return ERROR_OK; /* Don't abort recursion */
1148 }
1149
1150 /* component may take multiple 4K pages */
1151 uint32_t size = (pid >> 36) & 0xf;
1152 if (size > 0)
1153 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1154
1155 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1156
1157 uint8_t class = (cid >> 12) & 0xf;
1158 uint16_t part_num = pid & 0xfff;
1159 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1160
1161 if (designer_id & 0x80) {
1162 /* JEP106 code */
1163 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1164 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1165 } else {
1166 /* Legacy ASCII ID, clear invalid bits */
1167 designer_id &= 0x7f;
1168 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1169 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1170 }
1171
1172 /* default values to be overwritten upon finding a match */
1173 const char *type = "Unrecognized";
1174 const char *full = "";
1175
1176 /* search dap_partnums[] array for a match */
1177 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1178
1179 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1180 continue;
1181
1182 if (dap_partnums[entry].part_num != part_num)
1183 continue;
1184
1185 type = dap_partnums[entry].type;
1186 full = dap_partnums[entry].full;
1187 break;
1188 }
1189
1190 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1191 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1192
1193 if (class == 1) { /* ROM Table */
1194 uint32_t memtype;
1195 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1196 if (retval != ERROR_OK)
1197 return retval;
1198
1199 if (memtype & 0x01)
1200 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1201 else
1202 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1203
1204 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1205 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1206 uint32_t romentry;
1207 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1208 if (retval != ERROR_OK)
1209 return retval;
1210 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1211 tabs, entry_offset, romentry);
1212 if (romentry & 0x01) {
1213 /* Recurse */
1214 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1215 if (retval != ERROR_OK)
1216 return retval;
1217 } else if (romentry != 0) {
1218 command_print(cmd_ctx, "\t\tComponent not present");
1219 } else {
1220 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1221 break;
1222 }
1223 }
1224 } else if (class == 9) { /* CoreSight component */
1225 const char *major = "Reserved", *subtype = "Reserved";
1226
1227 uint32_t devtype;
1228 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1229 if (retval != ERROR_OK)
1230 return retval;
1231 unsigned minor = (devtype >> 4) & 0x0f;
1232 switch (devtype & 0x0f) {
1233 case 0:
1234 major = "Miscellaneous";
1235 switch (minor) {
1236 case 0:
1237 subtype = "other";
1238 break;
1239 case 4:
1240 subtype = "Validation component";
1241 break;
1242 }
1243 break;
1244 case 1:
1245 major = "Trace Sink";
1246 switch (minor) {
1247 case 0:
1248 subtype = "other";
1249 break;
1250 case 1:
1251 subtype = "Port";
1252 break;
1253 case 2:
1254 subtype = "Buffer";
1255 break;
1256 case 3:
1257 subtype = "Router";
1258 break;
1259 }
1260 break;
1261 case 2:
1262 major = "Trace Link";
1263 switch (minor) {
1264 case 0:
1265 subtype = "other";
1266 break;
1267 case 1:
1268 subtype = "Funnel, router";
1269 break;
1270 case 2:
1271 subtype = "Filter";
1272 break;
1273 case 3:
1274 subtype = "FIFO, buffer";
1275 break;
1276 }
1277 break;
1278 case 3:
1279 major = "Trace Source";
1280 switch (minor) {
1281 case 0:
1282 subtype = "other";
1283 break;
1284 case 1:
1285 subtype = "Processor";
1286 break;
1287 case 2:
1288 subtype = "DSP";
1289 break;
1290 case 3:
1291 subtype = "Engine/Coprocessor";
1292 break;
1293 case 4:
1294 subtype = "Bus";
1295 break;
1296 case 6:
1297 subtype = "Software";
1298 break;
1299 }
1300 break;
1301 case 4:
1302 major = "Debug Control";
1303 switch (minor) {
1304 case 0:
1305 subtype = "other";
1306 break;
1307 case 1:
1308 subtype = "Trigger Matrix";
1309 break;
1310 case 2:
1311 subtype = "Debug Auth";
1312 break;
1313 case 3:
1314 subtype = "Power Requestor";
1315 break;
1316 }
1317 break;
1318 case 5:
1319 major = "Debug Logic";
1320 switch (minor) {
1321 case 0:
1322 subtype = "other";
1323 break;
1324 case 1:
1325 subtype = "Processor";
1326 break;
1327 case 2:
1328 subtype = "DSP";
1329 break;
1330 case 3:
1331 subtype = "Engine/Coprocessor";
1332 break;
1333 case 4:
1334 subtype = "Bus";
1335 break;
1336 case 5:
1337 subtype = "Memory";
1338 break;
1339 }
1340 break;
1341 case 6:
1342 major = "Perfomance Monitor";
1343 switch (minor) {
1344 case 0:
1345 subtype = "other";
1346 break;
1347 case 1:
1348 subtype = "Processor";
1349 break;
1350 case 2:
1351 subtype = "DSP";
1352 break;
1353 case 3:
1354 subtype = "Engine/Coprocessor";
1355 break;
1356 case 4:
1357 subtype = "Bus";
1358 break;
1359 case 5:
1360 subtype = "Memory";
1361 break;
1362 }
1363 break;
1364 }
1365 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1366 (uint8_t)(devtype & 0xff),
1367 major, subtype);
1368 /* REVISIT also show 0xfc8 DevId */
1369 }
1370
1371 return ERROR_OK;
1372 }
1373
1374 int dap_info_command(struct command_context *cmd_ctx,
1375 struct adiv5_ap *ap)
1376 {
1377 int retval;
1378 uint32_t dbgbase, apid;
1379 uint8_t mem_ap;
1380
1381 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1382 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1383 if (retval != ERROR_OK)
1384 return retval;
1385
1386 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1387 if (apid == 0) {
1388 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1389 return ERROR_FAIL;
1390 }
1391
1392 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1393 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1394 command_print(cmd_ctx, "\tType is JTAG-AP");
1395 break;
1396 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1397 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1398 break;
1399 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1400 command_print(cmd_ctx, "\tType is MEM-AP APB");
1401 break;
1402 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1403 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1404 break;
1405 default:
1406 command_print(cmd_ctx, "\tUnknown AP type");
1407 break;
1408 }
1409
1410 /* NOTE: a MEM-AP may have a single CoreSight component that's
1411 * not a ROM table ... or have no such components at all.
1412 */
1413 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1414 if (mem_ap) {
1415 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1416
1417 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1418 command_print(cmd_ctx, "\tNo ROM table present");
1419 } else {
1420 if (dbgbase & 0x01)
1421 command_print(cmd_ctx, "\tValid ROM table present");
1422 else
1423 command_print(cmd_ctx, "\tROM table in legacy format");
1424
1425 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1426 }
1427 }
1428
1429 return ERROR_OK;
1430 }
1431
1432 enum adiv5_cfg_param {
1433 CFG_DAP,
1434 CFG_AP_NUM
1435 };
1436
1437 static const Jim_Nvp nvp_config_opts[] = {
1438 { .name = "-dap", .value = CFG_DAP },
1439 { .name = "-ap-num", .value = CFG_AP_NUM },
1440 { .name = NULL, .value = -1 }
1441 };
1442
1443 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1444 {
1445 struct adiv5_private_config *pc;
1446 int e;
1447
1448 pc = (struct adiv5_private_config *)target->private_config;
1449 if (pc == NULL) {
1450 pc = calloc(1, sizeof(struct adiv5_private_config));
1451 pc->ap_num = DP_APSEL_INVALID;
1452 target->private_config = pc;
1453 }
1454
1455 target->has_dap = true;
1456
1457 if (goi->argc > 0) {
1458 Jim_Nvp *n;
1459
1460 Jim_SetEmptyResult(goi->interp);
1461
1462 /* check first if topmost item is for us */
1463 e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts,
1464 goi->argv[0], &n);
1465 if (e != JIM_OK)
1466 return JIM_CONTINUE;
1467
1468 e = Jim_GetOpt_Obj(goi, NULL);
1469 if (e != JIM_OK)
1470 return e;
1471
1472 switch (n->value) {
1473 case CFG_DAP:
1474 if (goi->isconfigure) {
1475 Jim_Obj *o_t;
1476 struct adiv5_dap *dap;
1477 e = Jim_GetOpt_Obj(goi, &o_t);
1478 if (e != JIM_OK)
1479 return e;
1480 dap = dap_instance_by_jim_obj(goi->interp, o_t);
1481 if (dap == NULL) {
1482 Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
1483 return JIM_ERR;
1484 }
1485 if (pc->dap != NULL && pc->dap != dap) {
1486 Jim_SetResultString(goi->interp,
1487 "DAP assignment cannot be changed after target was created!", -1);
1488 return JIM_ERR;
1489 }
1490 if (target->tap_configured) {
1491 Jim_SetResultString(goi->interp,
1492 "-chain-position and -dap configparams are mutually exclusive!", -1);
1493 return JIM_ERR;
1494 }
1495 pc->dap = dap;
1496 target->tap = dap->tap;
1497 target->dap_configured = true;
1498 } else {
1499 if (goi->argc != 0) {
1500 Jim_WrongNumArgs(goi->interp,
1501 goi->argc, goi->argv,
1502 "NO PARAMS");
1503 return JIM_ERR;
1504 }
1505
1506 if (pc->dap == NULL) {
1507 Jim_SetResultString(goi->interp, "DAP not configured", -1);
1508 return JIM_ERR;
1509 }
1510 Jim_SetResultString(goi->interp, adiv5_dap_name(pc->dap), -1);
1511 }
1512 break;
1513
1514 case CFG_AP_NUM:
1515 if (goi->isconfigure) {
1516 jim_wide ap_num;
1517 e = Jim_GetOpt_Wide(goi, &ap_num);
1518 if (e != JIM_OK)
1519 return e;
1520 if (ap_num < 0 || ap_num > DP_APSEL_MAX) {
1521 Jim_SetResultString(goi->interp, "Invalid AP number!", -1);
1522 return JIM_ERR;
1523 }
1524 pc->ap_num = ap_num;
1525 } else {
1526 if (goi->argc != 0) {
1527 Jim_WrongNumArgs(goi->interp,
1528 goi->argc, goi->argv,
1529 "NO PARAMS");
1530 return JIM_ERR;
1531 }
1532
1533 if (pc->ap_num == DP_APSEL_INVALID) {
1534 Jim_SetResultString(goi->interp, "AP number not configured", -1);
1535 return JIM_ERR;
1536 }
1537 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, pc->ap_num));
1538 }
1539 break;
1540 }
1541 }
1542
1543 return JIM_OK;
1544 }
1545
1546 int adiv5_verify_config(struct adiv5_private_config *pc)
1547 {
1548 if (pc == NULL)
1549 return ERROR_FAIL;
1550
1551 if (pc->dap == NULL)
1552 return ERROR_FAIL;
1553
1554 return ERROR_OK;
1555 }
1556
1557
1558 COMMAND_HANDLER(handle_dap_info_command)
1559 {
1560 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1561 uint32_t apsel;
1562
1563 switch (CMD_ARGC) {
1564 case 0:
1565 apsel = dap->apsel;
1566 break;
1567 case 1:
1568 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1569 if (apsel > DP_APSEL_MAX)
1570 return ERROR_COMMAND_SYNTAX_ERROR;
1571 break;
1572 default:
1573 return ERROR_COMMAND_SYNTAX_ERROR;
1574 }
1575
1576 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1577 }
1578
1579 COMMAND_HANDLER(dap_baseaddr_command)
1580 {
1581 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1582 uint32_t apsel, baseaddr;
1583 int retval;
1584
1585 switch (CMD_ARGC) {
1586 case 0:
1587 apsel = dap->apsel;
1588 break;
1589 case 1:
1590 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1591 /* AP address is in bits 31:24 of DP_SELECT */
1592 if (apsel > DP_APSEL_MAX)
1593 return ERROR_COMMAND_SYNTAX_ERROR;
1594 break;
1595 default:
1596 return ERROR_COMMAND_SYNTAX_ERROR;
1597 }
1598
1599 /* NOTE: assumes we're talking to a MEM-AP, which
1600 * has a base address. There are other kinds of AP,
1601 * though they're not common for now. This should
1602 * use the ID register to verify it's a MEM-AP.
1603 */
1604 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1605 if (retval != ERROR_OK)
1606 return retval;
1607 retval = dap_run(dap);
1608 if (retval != ERROR_OK)
1609 return retval;
1610
1611 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1612
1613 return retval;
1614 }
1615
1616 COMMAND_HANDLER(dap_memaccess_command)
1617 {
1618 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1619 uint32_t memaccess_tck;
1620
1621 switch (CMD_ARGC) {
1622 case 0:
1623 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1624 break;
1625 case 1:
1626 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1627 break;
1628 default:
1629 return ERROR_COMMAND_SYNTAX_ERROR;
1630 }
1631 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1632
1633 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1634 dap->ap[dap->apsel].memaccess_tck);
1635
1636 return ERROR_OK;
1637 }
1638
1639 COMMAND_HANDLER(dap_apsel_command)
1640 {
1641 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1642 uint32_t apsel;
1643
1644 switch (CMD_ARGC) {
1645 case 0:
1646 command_print(CMD_CTX, "%" PRIi32, dap->apsel);
1647 return ERROR_OK;
1648 case 1:
1649 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1650 /* AP address is in bits 31:24 of DP_SELECT */
1651 if (apsel > DP_APSEL_MAX)
1652 return ERROR_COMMAND_SYNTAX_ERROR;
1653 break;
1654 default:
1655 return ERROR_COMMAND_SYNTAX_ERROR;
1656 }
1657
1658 dap->apsel = apsel;
1659 return ERROR_OK;
1660 }
1661
1662 COMMAND_HANDLER(dap_apcsw_command)
1663 {
1664 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1665 uint32_t apcsw = dap->ap[dap->apsel].csw_default;
1666 uint32_t csw_val, csw_mask;
1667
1668 switch (CMD_ARGC) {
1669 case 0:
1670 command_print(CMD_CTX, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1671 dap->apsel, apcsw);
1672 return ERROR_OK;
1673 case 1:
1674 if (strcmp(CMD_ARGV[0], "default") == 0)
1675 csw_val = CSW_DEFAULT;
1676 else
1677 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1678
1679 if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1680 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
1681 return ERROR_COMMAND_SYNTAX_ERROR;
1682 }
1683 apcsw = csw_val;
1684 break;
1685 case 2:
1686 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1687 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
1688 if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1689 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
1690 return ERROR_COMMAND_SYNTAX_ERROR;
1691 }
1692 apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
1693 break;
1694 default:
1695 return ERROR_COMMAND_SYNTAX_ERROR;
1696 }
1697 dap->ap[dap->apsel].csw_default = apcsw;
1698
1699 return 0;
1700 }
1701
1702
1703
1704 COMMAND_HANDLER(dap_apid_command)
1705 {
1706 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1707 uint32_t apsel, apid;
1708 int retval;
1709
1710 switch (CMD_ARGC) {
1711 case 0:
1712 apsel = dap->apsel;
1713 break;
1714 case 1:
1715 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1716 /* AP address is in bits 31:24 of DP_SELECT */
1717 if (apsel > DP_APSEL_MAX)
1718 return ERROR_COMMAND_SYNTAX_ERROR;
1719 break;
1720 default:
1721 return ERROR_COMMAND_SYNTAX_ERROR;
1722 }
1723
1724 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1725 if (retval != ERROR_OK)
1726 return retval;
1727 retval = dap_run(dap);
1728 if (retval != ERROR_OK)
1729 return retval;
1730
1731 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1732
1733 return retval;
1734 }
1735
1736 COMMAND_HANDLER(dap_apreg_command)
1737 {
1738 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1739 uint32_t apsel, reg, value;
1740 struct adiv5_ap *ap;
1741 int retval;
1742
1743 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1744 return ERROR_COMMAND_SYNTAX_ERROR;
1745
1746 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1747 /* AP address is in bits 31:24 of DP_SELECT */
1748 if (apsel > DP_APSEL_MAX)
1749 return ERROR_COMMAND_SYNTAX_ERROR;
1750 ap = dap_ap(dap, apsel);
1751
1752 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1753 if (reg >= 256 || (reg & 3))
1754 return ERROR_COMMAND_SYNTAX_ERROR;
1755
1756 if (CMD_ARGC == 3) {
1757 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1758 switch (reg) {
1759 case MEM_AP_REG_CSW:
1760 ap->csw_value = 0; /* invalid, in case write fails */
1761 retval = dap_queue_ap_write(ap, reg, value);
1762 if (retval == ERROR_OK)
1763 ap->csw_value = value;
1764 break;
1765 case MEM_AP_REG_TAR:
1766 ap->tar_valid = false; /* invalid, force write */
1767 retval = mem_ap_setup_tar(ap, value);
1768 break;
1769 default:
1770 retval = dap_queue_ap_write(ap, reg, value);
1771 break;
1772 }
1773 } else {
1774 retval = dap_queue_ap_read(ap, reg, &value);
1775 }
1776 if (retval == ERROR_OK)
1777 retval = dap_run(dap);
1778
1779 if (retval != ERROR_OK)
1780 return retval;
1781
1782 if (CMD_ARGC == 2)
1783 command_print(CMD_CTX, "0x%08" PRIx32, value);
1784
1785 return retval;
1786 }
1787
1788 COMMAND_HANDLER(dap_dpreg_command)
1789 {
1790 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1791 uint32_t reg, value;
1792 int retval;
1793
1794 if (CMD_ARGC < 1 || CMD_ARGC > 2)
1795 return ERROR_COMMAND_SYNTAX_ERROR;
1796
1797 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg);
1798 if (reg >= 256 || (reg & 3))
1799 return ERROR_COMMAND_SYNTAX_ERROR;
1800
1801 if (CMD_ARGC == 2) {
1802 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1803 retval = dap_queue_dp_write(dap, reg, value);
1804 } else {
1805 retval = dap_queue_dp_read(dap, reg, &value);
1806 }
1807 if (retval == ERROR_OK)
1808 retval = dap_run(dap);
1809
1810 if (retval != ERROR_OK)
1811 return retval;
1812
1813 if (CMD_ARGC == 1)
1814 command_print(CMD_CTX, "0x%08" PRIx32, value);
1815
1816 return retval;
1817 }
1818
1819 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1820 {
1821 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1822 uint32_t enable = dap->ti_be_32_quirks;
1823
1824 switch (CMD_ARGC) {
1825 case 0:
1826 break;
1827 case 1:
1828 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1829 if (enable > 1)
1830 return ERROR_COMMAND_SYNTAX_ERROR;
1831 break;
1832 default:
1833 return ERROR_COMMAND_SYNTAX_ERROR;
1834 }
1835 dap->ti_be_32_quirks = enable;
1836 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1837 enable ? "enabled" : "disabled");
1838
1839 return 0;
1840 }
1841
1842 const struct command_registration dap_instance_commands[] = {
1843 {
1844 .name = "info",
1845 .handler = handle_dap_info_command,
1846 .mode = COMMAND_EXEC,
1847 .help = "display ROM table for MEM-AP "
1848 "(default currently selected AP)",
1849 .usage = "[ap_num]",
1850 },
1851 {
1852 .name = "apsel",
1853 .handler = dap_apsel_command,
1854 .mode = COMMAND_ANY,
1855 .help = "Set the currently selected AP (default 0) "
1856 "and display the result",
1857 .usage = "[ap_num]",
1858 },
1859 {
1860 .name = "apcsw",
1861 .handler = dap_apcsw_command,
1862 .mode = COMMAND_ANY,
1863 .help = "Set CSW default bits",
1864 .usage = "[value [mask]]",
1865 },
1866
1867 {
1868 .name = "apid",
1869 .handler = dap_apid_command,
1870 .mode = COMMAND_EXEC,
1871 .help = "return ID register from AP "
1872 "(default currently selected AP)",
1873 .usage = "[ap_num]",
1874 },
1875 {
1876 .name = "apreg",
1877 .handler = dap_apreg_command,
1878 .mode = COMMAND_EXEC,
1879 .help = "read/write a register from AP "
1880 "(reg is byte address of a word register, like 0 4 8...)",
1881 .usage = "ap_num reg [value]",
1882 },
1883 {
1884 .name = "dpreg",
1885 .handler = dap_dpreg_command,
1886 .mode = COMMAND_EXEC,
1887 .help = "read/write a register from DP "
1888 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
1889 .usage = "reg [value]",
1890 },
1891 {
1892 .name = "baseaddr",
1893 .handler = dap_baseaddr_command,
1894 .mode = COMMAND_EXEC,
1895 .help = "return debug base address from MEM-AP "
1896 "(default currently selected AP)",
1897 .usage = "[ap_num]",
1898 },
1899 {
1900 .name = "memaccess",
1901 .handler = dap_memaccess_command,
1902 .mode = COMMAND_EXEC,
1903 .help = "set/get number of extra tck for MEM-AP memory "
1904 "bus access [0-255]",
1905 .usage = "[cycles]",
1906 },
1907 {
1908 .name = "ti_be_32_quirks",
1909 .handler = dap_ti_be_32_quirks_command,
1910 .mode = COMMAND_CONFIG,
1911 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1912 .usage = "[enable]",
1913 },
1914 COMMAND_REGISTRATION_DONE
1915 };