1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Hongtao Zheng *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
34 #define _DEBUG_INSTRUCTION_EXECUTION_
38 int handle_arm9tdmi_catch_vectors_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 /* forward declarations */
41 int arm9tdmi_target_create( struct target_s
*target
, Jim_Interp
*interp
);
43 int arm9tdmi_quit(void);
45 target_type_t arm9tdmi_target
=
50 .arch_state
= armv4_5_arch_state
,
52 .target_request_data
= arm7_9_target_request_data
,
55 .resume
= arm7_9_resume
,
58 .assert_reset
= arm7_9_assert_reset
,
59 .deassert_reset
= arm7_9_deassert_reset
,
60 .soft_reset_halt
= arm7_9_soft_reset_halt
,
62 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
64 .read_memory
= arm7_9_read_memory
,
65 .write_memory
= arm7_9_write_memory
,
66 .bulk_write_memory
= arm7_9_bulk_write_memory
,
67 .checksum_memory
= arm7_9_checksum_memory
,
68 .blank_check_memory
= arm7_9_blank_check_memory
,
70 .run_algorithm
= armv4_5_run_algorithm
,
72 .add_breakpoint
= arm7_9_add_breakpoint
,
73 .remove_breakpoint
= arm7_9_remove_breakpoint
,
74 .add_watchpoint
= arm7_9_add_watchpoint
,
75 .remove_watchpoint
= arm7_9_remove_watchpoint
,
77 .register_commands
= arm9tdmi_register_commands
,
78 .target_create
= arm9tdmi_target_create
,
79 .init_target
= arm9tdmi_init_target
,
80 .examine
= arm9tdmi_examine
,
84 arm9tdmi_vector_t arm9tdmi_vectors
[] =
86 {"reset", ARM9TDMI_RESET_VECTOR
},
87 {"undef", ARM9TDMI_UNDEF_VECTOR
},
88 {"swi", ARM9TDMI_SWI_VECTOR
},
89 {"pabt", ARM9TDMI_PABT_VECTOR
},
90 {"dabt", ARM9TDMI_DABT_VECTOR
},
91 {"reserved", ARM9TDMI_RESERVED_VECTOR
},
92 {"irq", ARM9TDMI_IRQ_VECTOR
},
93 {"fiq", ARM9TDMI_FIQ_VECTOR
},
97 int arm9tdmi_examine_debug_reason(target_t
*target
)
99 int retval
= ERROR_OK
;
100 /* get pointers to arch-specific information */
101 armv4_5_common_t
*armv4_5
= target
->arch_info
;
102 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
104 /* only check the debug reason if we don't know it already */
105 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
106 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
))
108 scan_field_t fields
[3];
110 u8 instructionbus
[4];
113 jtag_add_end_state(TAP_DRPAUSE
);
115 fields
[0].tap
= arm7_9
->jtag_info
.tap
;
116 fields
[0].num_bits
= 32;
117 fields
[0].out_value
= NULL
;
118 fields
[0].in_value
= databus
;
120 fields
[1].tap
= arm7_9
->jtag_info
.tap
;
121 fields
[1].num_bits
= 3;
122 fields
[1].out_value
= NULL
;
123 fields
[1].in_value
= &debug_reason
;
125 fields
[2].tap
= arm7_9
->jtag_info
.tap
;
126 fields
[2].num_bits
= 32;
127 fields
[2].out_value
= NULL
;
128 fields
[2].in_value
= instructionbus
;
130 if ((retval
= arm_jtag_scann(&arm7_9
->jtag_info
, 0x1)) != ERROR_OK
)
134 arm_jtag_set_instr(&arm7_9
->jtag_info
, arm7_9
->jtag_info
.intest_instr
, NULL
);
136 jtag_add_dr_scan(3, fields
, TAP_DRPAUSE
);
137 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
142 fields
[0].in_value
= NULL
;
143 fields
[0].out_value
= databus
;
144 fields
[1].in_value
= NULL
;
145 fields
[1].out_value
= &debug_reason
;
146 fields
[2].in_value
= NULL
;
147 fields
[2].out_value
= instructionbus
;
149 jtag_add_dr_scan(3, fields
, TAP_DRPAUSE
);
151 if (debug_reason
& 0x4)
152 if (debug_reason
& 0x2)
153 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
155 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
157 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
163 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
164 int arm9tdmi_clock_out(arm_jtag_t
*jtag_info
, u32 instr
, u32 out
, u32
*in
, int sysspeed
)
166 int retval
= ERROR_OK
;
167 scan_field_t fields
[3];
170 u8 sysspeed_buf
= 0x0;
173 buf_set_u32(out_buf
, 0, 32, out
);
175 buf_set_u32(instr_buf
, 0, 32, flip_u32(instr
, 32));
178 buf_set_u32(&sysspeed_buf
, 2, 1, 1);
180 jtag_add_end_state(TAP_DRPAUSE
);
181 if ((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
186 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
188 fields
[0].tap
= jtag_info
->tap
;
189 fields
[0].num_bits
= 32;
190 fields
[0].out_value
= out_buf
;
191 fields
[0].in_value
= NULL
;
193 fields
[1].tap
= jtag_info
->tap
;
194 fields
[1].num_bits
= 3;
195 fields
[1].out_value
= &sysspeed_buf
;
196 fields
[1].in_value
= NULL
;
198 fields
[2].tap
= jtag_info
->tap
;
199 fields
[2].num_bits
= 32;
200 fields
[2].out_value
= instr_buf
;
201 fields
[2].in_value
= NULL
;
205 fields
[0].in_value
=(u8
*)in
;
206 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
208 jtag_add_callback(arm_le_to_h_u32
, (u8
*)in
);
212 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
215 jtag_add_runtest(0, TAP_INVALID
);
217 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
219 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
226 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr
, out
, *in
);
229 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr
, out
);
236 /* just read data (instruction and data-out = don't care) */
237 int arm9tdmi_clock_data_in(arm_jtag_t
*jtag_info
, u32
*in
)
239 int retval
= ERROR_OK
;;
240 scan_field_t fields
[3];
242 jtag_add_end_state(TAP_DRPAUSE
);
243 if ((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
248 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
250 fields
[0].tap
= jtag_info
->tap
;
251 fields
[0].num_bits
= 32;
252 fields
[0].out_value
= NULL
;
253 fields
[0].in_value
= (u8
*)in
;
255 fields
[1].tap
= jtag_info
->tap
;
256 fields
[1].num_bits
= 3;
257 fields
[1].out_value
= NULL
;
258 fields
[1].in_value
= NULL
;
260 fields
[2].tap
= jtag_info
->tap
;
261 fields
[2].num_bits
= 32;
262 fields
[2].out_value
= NULL
;
263 fields
[2].in_value
= NULL
;
265 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
267 jtag_add_callback(arm_le_to_h_u32
, (u8
*)in
);
269 jtag_add_runtest(0, TAP_INVALID
);
271 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
273 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
280 LOG_DEBUG("in: 0x%8.8x", *in
);
284 LOG_ERROR("BUG: called with in == NULL");
292 extern void arm_endianness(u8
*tmp
, void *in
, int size
, int be
, int flip
);
294 static int arm9endianness(u8
*in
, jtag_callback_data_t size
, jtag_callback_data_t be
, jtag_callback_data_t captured
)
296 arm_endianness((u8
*)captured
, in
, (int)size
, (int)be
, 0);
300 /* clock the target, and read the databus
301 * the *in pointer points to a buffer where elements of 'size' bytes
302 * are stored in big (be==1) or little (be==0) endianness
304 int arm9tdmi_clock_data_in_endianness(arm_jtag_t
*jtag_info
, void *in
, int size
, int be
)
306 int retval
= ERROR_OK
;
307 scan_field_t fields
[3];
309 jtag_add_end_state(TAP_DRPAUSE
);
310 if ((retval
= arm_jtag_scann(jtag_info
, 0x1)) != ERROR_OK
)
315 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
317 fields
[0].tap
= jtag_info
->tap
;
318 fields
[0].num_bits
= 32;
319 fields
[0].out_value
= NULL
;
320 jtag_alloc_in_value32(&fields
[0]);
322 fields
[1].tap
= jtag_info
->tap
;
323 fields
[1].num_bits
= 3;
324 fields
[1].out_value
= NULL
;
325 fields
[1].in_value
= NULL
;
327 fields
[2].tap
= jtag_info
->tap
;
328 fields
[2].num_bits
= 32;
329 fields
[2].out_value
= NULL
;
330 fields
[2].in_value
= NULL
;
332 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
334 jtag_add_callback4(arm9endianness
, in
, (jtag_callback_data_t
)size
, (jtag_callback_data_t
)be
, (jtag_callback_data_t
)fields
[0].in_value
);
336 jtag_add_runtest(0, TAP_INVALID
);
338 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
340 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
347 LOG_DEBUG("in: 0x%8.8x", *(u32
*)in
);
351 LOG_ERROR("BUG: called with in == NULL");
359 void arm9tdmi_change_to_arm(target_t
*target
, u32
*r0
, u32
*pc
)
361 int retval
= ERROR_OK
;
362 /* get pointers to arch-specific information */
363 armv4_5_common_t
*armv4_5
= target
->arch_info
;
364 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
365 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
367 /* save r0 before using it and put system in ARM state
368 * to allow common handling of ARM and THUMB debugging */
370 /* fetch STR r0, [r0] */
371 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
372 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
373 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
374 /* STR r0, [r0] in Memory */
375 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, r0
, 0);
377 /* MOV r0, r15 fetched, STR in Decode */
378 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_MOV(0, 15), 0, NULL
, 0);
379 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
380 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_STR(0, 0), 0, NULL
, 0);
381 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
382 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
383 /* nothing fetched, STR r0, [r0] in Memory */
384 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, pc
, 0);
386 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
387 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
389 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
391 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
392 /* LDR in Memory (to account for interlock) */
393 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
396 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_BX(0), 0, NULL
, 0);
397 /* NOP fetched, BX in Decode, MOV in Execute */
398 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
399 /* NOP fetched, BX in Execute (1) */
400 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
402 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
407 /* fix program counter:
408 * MOV r0, r15 was the 5th instruction (+8)
409 * reading PC in Thumb state gives address of instruction + 4
414 void arm9tdmi_read_core_regs(target_t
*target
, u32 mask
, u32
* core_regs
[16])
417 /* get pointers to arch-specific information */
418 armv4_5_common_t
*armv4_5
= target
->arch_info
;
419 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
420 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
422 /* STMIA r0-15, [r0] at debug speed
423 * register values will start to appear on 4th DCLK
425 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
427 /* fetch NOP, STM in DECODE stage */
428 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
429 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
430 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
432 for (i
= 0; i
<= 15; i
++)
435 /* nothing fetched, STM in MEMORY (i'th cycle) */
436 arm9tdmi_clock_data_in(jtag_info
, core_regs
[i
]);
440 void arm9tdmi_read_core_regs_target_buffer(target_t
*target
, u32 mask
, void* buffer
, int size
)
443 /* get pointers to arch-specific information */
444 armv4_5_common_t
*armv4_5
= target
->arch_info
;
445 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
446 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
447 int be
= (target
->endianness
== TARGET_BIG_ENDIAN
) ? 1 : 0;
448 u32
*buf_u32
= buffer
;
449 u16
*buf_u16
= buffer
;
452 /* STMIA r0-15, [r0] at debug speed
453 * register values will start to appear on 4th DCLK
455 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
457 /* fetch NOP, STM in DECODE stage */
458 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
459 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
460 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
462 for (i
= 0; i
<= 15; i
++)
465 /* nothing fetched, STM in MEMORY (i'th cycle) */
469 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u32
++, 4, be
);
472 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u16
++, 2, be
);
475 arm9tdmi_clock_data_in_endianness(jtag_info
, buf_u8
++, 1, be
);
481 void arm9tdmi_read_xpsr(target_t
*target
, u32
*xpsr
, int spsr
)
483 /* get pointers to arch-specific information */
484 armv4_5_common_t
*armv4_5
= target
->arch_info
;
485 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
486 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
489 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MRS(0, spsr
& 1), 0, NULL
, 0);
490 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
491 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
492 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
493 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
496 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STR(0, 15), 0, NULL
, 0);
497 /* fetch NOP, STR in DECODE stage */
498 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
499 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
500 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
501 /* nothing fetched, STR in MEMORY */
502 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, xpsr
, 0);
505 void arm9tdmi_write_xpsr(target_t
*target
, u32 xpsr
, int spsr
)
507 /* get pointers to arch-specific information */
508 armv4_5_common_t
*armv4_5
= target
->arch_info
;
509 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
510 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
512 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr
, spsr
);
515 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr
& 0xff, 0, 1, spsr
), 0, NULL
, 0);
516 /* MSR2 fetched, MSR1 in DECODE */
517 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff00) >> 8, 0xc, 2, spsr
), 0, NULL
, 0);
518 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
519 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff0000) >> 16, 0x8, 4, spsr
), 0, NULL
, 0);
520 /* nothing fetched, MSR1 in EXECUTE (2) */
521 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
522 /* nothing fetched, MSR1 in EXECUTE (3) */
523 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
524 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
525 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM((xpsr
& 0xff000000) >> 24, 0x4, 8, spsr
), 0, NULL
, 0);
526 /* nothing fetched, MSR2 in EXECUTE (2) */
527 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
528 /* nothing fetched, MSR2 in EXECUTE (3) */
529 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
530 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
531 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
532 /* nothing fetched, MSR3 in EXECUTE (2) */
533 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
534 /* nothing fetched, MSR3 in EXECUTE (3) */
535 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
536 /* NOP fetched, MSR4 in EXECUTE (1) */
537 /* last MSR writes flags, which takes only one cycle */
538 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
541 void arm9tdmi_write_xpsr_im8(target_t
*target
, u8 xpsr_im
, int rot
, int spsr
)
543 /* get pointers to arch-specific information */
544 armv4_5_common_t
*armv4_5
= target
->arch_info
;
545 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
546 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
548 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im
, rot
, spsr
);
551 arm9tdmi_clock_out(jtag_info
, ARMV4_5_MSR_IM(xpsr_im
, rot
, 1, spsr
), 0, NULL
, 0);
552 /* NOP fetched, MSR in DECODE */
553 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
554 /* NOP fetched, MSR in EXECUTE (1) */
555 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
557 /* rot == 4 writes flags, which takes only one cycle */
560 /* nothing fetched, MSR in EXECUTE (2) */
561 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
562 /* nothing fetched, MSR in EXECUTE (3) */
563 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
567 void arm9tdmi_write_core_regs(target_t
*target
, u32 mask
, u32 core_regs
[16])
570 /* get pointers to arch-specific information */
571 armv4_5_common_t
*armv4_5
= target
->arch_info
;
572 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
573 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
575 /* LDMIA r0-15, [r0] at debug speed
576 * register values will start to appear on 4th DCLK
578 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 0), 0, NULL
, 0);
580 /* fetch NOP, LDM in DECODE stage */
581 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
582 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
583 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
585 for (i
= 0; i
<= 15; i
++)
588 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
589 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, core_regs
[i
], NULL
, 0);
591 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
594 void arm9tdmi_load_word_regs(target_t
*target
, u32 mask
)
596 /* get pointers to arch-specific information */
597 armv4_5_common_t
*armv4_5
= target
->arch_info
;
598 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
599 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
601 /* put system-speed load-multiple into the pipeline */
602 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, mask
& 0xffff, 0, 1), 0, NULL
, 0);
603 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
606 void arm9tdmi_load_hword_reg(target_t
*target
, int num
)
608 /* get pointers to arch-specific information */
609 armv4_5_common_t
*armv4_5
= target
->arch_info
;
610 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
611 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
613 /* put system-speed load half-word into the pipeline */
614 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRH_IP(num
, 0), 0, NULL
, 0);
615 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
618 void arm9tdmi_load_byte_reg(target_t
*target
, int num
)
620 /* get pointers to arch-specific information */
621 armv4_5_common_t
*armv4_5
= target
->arch_info
;
622 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
623 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
625 /* put system-speed load byte into the pipeline */
626 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDRB_IP(num
, 0), 0, NULL
, 0);
627 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
630 void arm9tdmi_store_word_regs(target_t
*target
, u32 mask
)
632 /* get pointers to arch-specific information */
633 armv4_5_common_t
*armv4_5
= target
->arch_info
;
634 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
635 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
637 /* put system-speed store-multiple into the pipeline */
638 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STMIA(0, mask
, 0, 1), 0, NULL
, 0);
639 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
642 void arm9tdmi_store_hword_reg(target_t
*target
, int num
)
644 /* get pointers to arch-specific information */
645 armv4_5_common_t
*armv4_5
= target
->arch_info
;
646 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
647 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
649 /* put system-speed store half-word into the pipeline */
650 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRH_IP(num
, 0), 0, NULL
, 0);
651 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
654 void arm9tdmi_store_byte_reg(target_t
*target
, int num
)
656 /* get pointers to arch-specific information */
657 armv4_5_common_t
*armv4_5
= target
->arch_info
;
658 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
659 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
661 /* put system-speed store byte into the pipeline */
662 arm9tdmi_clock_out(jtag_info
, ARMV4_5_STRB_IP(num
, 0), 0, NULL
, 0);
663 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
666 void arm9tdmi_write_pc(target_t
*target
, u32 pc
)
668 /* get pointers to arch-specific information */
669 armv4_5_common_t
*armv4_5
= target
->arch_info
;
670 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
671 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
673 /* LDMIA r0-15, [r0] at debug speed
674 * register values will start to appear on 4th DCLK
676 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL
, 0);
678 /* fetch NOP, LDM in DECODE stage */
679 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
680 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
681 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
682 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
683 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, pc
, NULL
, 0);
684 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
685 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
686 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
687 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
688 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
689 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
692 void arm9tdmi_branch_resume(target_t
*target
)
694 /* get pointers to arch-specific information */
695 armv4_5_common_t
*armv4_5
= target
->arch_info
;
696 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
697 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
699 arm9tdmi_clock_out(jtag_info
, ARMV4_5_B(0xfffffc, 0), 0, NULL
, 0);
700 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
703 void arm9tdmi_branch_resume_thumb(target_t
*target
)
707 /* get pointers to arch-specific information */
708 armv4_5_common_t
*armv4_5
= target
->arch_info
;
709 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
710 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
711 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
713 /* LDMIA r0-15, [r0] at debug speed
714 * register values will start to appear on 4th DCLK
716 arm9tdmi_clock_out(jtag_info
, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL
, 0);
718 /* fetch NOP, LDM in DECODE stage */
719 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
720 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
721 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
722 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
723 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) | 1, NULL
, 0);
724 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
725 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
727 /* Branch and eXchange */
728 arm9tdmi_clock_out(jtag_info
, ARMV4_5_BX(0), 0, NULL
, 0);
730 embeddedice_read_reg(dbg_stat
);
732 /* fetch NOP, BX in DECODE stage */
733 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
735 embeddedice_read_reg(dbg_stat
);
737 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
738 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 0);
740 /* target is now in Thumb state */
741 embeddedice_read_reg(dbg_stat
);
743 /* load r0 value, MOV_IM in Decode*/
744 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_LDR_PCREL(0), 0, NULL
, 0);
745 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
746 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
747 /* fetch NOP, LDR in Execute */
748 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
749 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
750 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, buf_get_u32(armv4_5
->core_cache
->reg_list
[0].value
, 0, 32), NULL
, 0);
751 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
752 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
754 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
755 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
757 embeddedice_read_reg(dbg_stat
);
759 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_B(0x7f7), 0, NULL
, 1);
760 arm9tdmi_clock_out(jtag_info
, ARMV4_5_T_NOP
, 0, NULL
, 0);
763 void arm9tdmi_enable_single_step(target_t
*target
, u32 next_pc
)
765 /* get pointers to arch-specific information */
766 armv4_5_common_t
*armv4_5
= target
->arch_info
;
767 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
769 if (arm7_9
->has_single_step
)
771 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 1);
772 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
776 arm7_9_enable_eice_step(target
, next_pc
);
780 void arm9tdmi_disable_single_step(target_t
*target
)
782 /* get pointers to arch-specific information */
783 armv4_5_common_t
*armv4_5
= target
->arch_info
;
784 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
786 if (arm7_9
->has_single_step
)
788 buf_set_u32(arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
].value
, 3, 1, 0);
789 embeddedice_store_reg(&arm7_9
->eice_cache
->reg_list
[EICE_DBG_CTRL
]);
793 arm7_9_disable_eice_step(target
);
797 void arm9tdmi_build_reg_cache(target_t
*target
)
799 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
800 /* get pointers to arch-specific information */
801 armv4_5_common_t
*armv4_5
= target
->arch_info
;
803 (*cache_p
) = armv4_5_build_reg_cache(target
, armv4_5
);
804 armv4_5
->core_cache
= (*cache_p
);
807 int arm9tdmi_examine(struct target_s
*target
)
809 /* get pointers to arch-specific information */
811 armv4_5_common_t
*armv4_5
= target
->arch_info
;
812 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
813 if (!target
->type
->examined
)
815 reg_cache_t
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
817 /* one extra register (vector catch) */
818 t
=embeddedice_build_reg_cache(target
, arm7_9
);
822 arm7_9
->eice_cache
= (*cache_p
);
826 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
827 (*cache_p
)->next
= etm_build_reg_cache(target
, jtag_info
, arm7_9
->etm_ctx
);
828 arm7_9
->etm_ctx
->reg_cache
= (*cache_p
)->next
;
830 target
->type
->examined
= 1;
832 if ((retval
=embeddedice_setup(target
))!=ERROR_OK
)
834 if ((retval
=arm7_9_setup(target
))!=ERROR_OK
)
838 if ((retval
=etm_setup(target
))!=ERROR_OK
)
844 int arm9tdmi_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
847 arm9tdmi_build_reg_cache(target
);
852 int arm9tdmi_quit(void)
857 int arm9tdmi_init_arch_info(target_t
*target
, arm9tdmi_common_t
*arm9tdmi
, jtag_tap_t
*tap
)
859 armv4_5_common_t
*armv4_5
;
860 arm7_9_common_t
*arm7_9
;
862 arm7_9
= &arm9tdmi
->arm7_9_common
;
863 armv4_5
= &arm7_9
->armv4_5_common
;
865 /* prepare JTAG information for the new target */
866 arm7_9
->jtag_info
.tap
= tap
;
867 arm7_9
->jtag_info
.scann_size
= 5;
869 /* register arch-specific functions */
870 arm7_9
->examine_debug_reason
= arm9tdmi_examine_debug_reason
;
871 arm7_9
->change_to_arm
= arm9tdmi_change_to_arm
;
872 arm7_9
->read_core_regs
= arm9tdmi_read_core_regs
;
873 arm7_9
->read_core_regs_target_buffer
= arm9tdmi_read_core_regs_target_buffer
;
874 arm7_9
->read_xpsr
= arm9tdmi_read_xpsr
;
876 arm7_9
->write_xpsr
= arm9tdmi_write_xpsr
;
877 arm7_9
->write_xpsr_im8
= arm9tdmi_write_xpsr_im8
;
878 arm7_9
->write_core_regs
= arm9tdmi_write_core_regs
;
880 arm7_9
->load_word_regs
= arm9tdmi_load_word_regs
;
881 arm7_9
->load_hword_reg
= arm9tdmi_load_hword_reg
;
882 arm7_9
->load_byte_reg
= arm9tdmi_load_byte_reg
;
884 arm7_9
->store_word_regs
= arm9tdmi_store_word_regs
;
885 arm7_9
->store_hword_reg
= arm9tdmi_store_hword_reg
;
886 arm7_9
->store_byte_reg
= arm9tdmi_store_byte_reg
;
888 arm7_9
->write_pc
= arm9tdmi_write_pc
;
889 arm7_9
->branch_resume
= arm9tdmi_branch_resume
;
890 arm7_9
->branch_resume_thumb
= arm9tdmi_branch_resume_thumb
;
892 arm7_9
->enable_single_step
= arm9tdmi_enable_single_step
;
893 arm7_9
->disable_single_step
= arm9tdmi_disable_single_step
;
895 arm7_9
->pre_debug_entry
= NULL
;
896 arm7_9
->post_debug_entry
= NULL
;
898 arm7_9
->pre_restore_context
= NULL
;
899 arm7_9
->post_restore_context
= NULL
;
901 /* initialize arch-specific breakpoint handling */
902 arm7_9
->arm_bkpt
= 0xdeeedeee;
903 arm7_9
->thumb_bkpt
= 0xdeee;
905 arm7_9
->dbgreq_adjust_pc
= 3;
906 arm7_9
->arch_info
= arm9tdmi
;
908 arm9tdmi
->common_magic
= ARM9TDMI_COMMON_MAGIC
;
909 arm9tdmi
->arch_info
= NULL
;
911 arm7_9_init_arch_info(target
, arm7_9
);
913 /* override use of DBGRQ, this is safe on ARM9TDMI */
914 arm7_9
->use_dbgrq
= 1;
916 /* all ARM9s have the vector catch register */
917 arm7_9
->has_vector_catch
= 1;
922 int arm9tdmi_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
)
924 armv4_5_common_t
*armv4_5
= target
->arch_info
;
925 arm7_9_common_t
*arm7_9
;
926 arm9tdmi_common_t
*arm9tdmi
;
928 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
933 arm7_9
= armv4_5
->arch_info
;
934 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
939 arm9tdmi
= arm7_9
->arch_info
;
940 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
945 *armv4_5_p
= armv4_5
;
947 *arm9tdmi_p
= arm9tdmi
;
952 int arm9tdmi_target_create(struct target_s
*target
, Jim_Interp
*interp
)
954 arm9tdmi_common_t
*arm9tdmi
= calloc(1,sizeof(arm9tdmi_common_t
));
956 arm9tdmi_init_arch_info(target
, arm9tdmi
, target
->tap
);
961 int arm9tdmi_register_commands(struct command_context_s
*cmd_ctx
)
964 command_t
*arm9tdmi_cmd
;
966 retval
= arm7_9_register_commands(cmd_ctx
);
967 arm9tdmi_cmd
= register_command(cmd_ctx
, NULL
, "arm9tdmi", NULL
, COMMAND_ANY
, "arm9tdmi specific commands");
968 register_command(cmd_ctx
, arm9tdmi_cmd
, "vector_catch", handle_arm9tdmi_catch_vectors_command
, COMMAND_EXEC
, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
973 int handle_arm9tdmi_catch_vectors_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
975 target_t
*target
= get_current_target(cmd_ctx
);
976 armv4_5_common_t
*armv4_5
;
977 arm7_9_common_t
*arm7_9
;
978 arm9tdmi_common_t
*arm9tdmi
;
980 u32 vector_catch_value
;
983 if (arm9tdmi_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
) != ERROR_OK
)
985 command_print(cmd_ctx
, "current target isn't an ARM9TDMI based target");
989 vector_catch
= &arm7_9
->eice_cache
->reg_list
[EICE_VEC_CATCH
];
991 /* read the vector catch register if necessary */
992 if (!vector_catch
->valid
)
993 embeddedice_read_reg(vector_catch
);
995 /* get the current setting */
996 vector_catch_value
= buf_get_u32(vector_catch
->value
, 0, 32);
1000 vector_catch_value
= 0x0;
1001 if (strcmp(args
[0], "all") == 0)
1003 vector_catch_value
= 0xdf;
1005 else if (strcmp(args
[0], "none") == 0)
1011 for (i
= 0; i
< argc
; i
++)
1013 /* go through list of vectors */
1014 for (j
= 0; arm9tdmi_vectors
[j
].name
; j
++)
1016 if (strcmp(args
[i
], arm9tdmi_vectors
[j
].name
) == 0)
1018 vector_catch_value
|= arm9tdmi_vectors
[j
].value
;
1023 /* complain if vector wasn't found */
1024 if (!arm9tdmi_vectors
[j
].name
)
1026 command_print(cmd_ctx
, "vector '%s' not found, leaving current setting unchanged", args
[i
]);
1028 /* reread current setting */
1029 vector_catch_value
= buf_get_u32(vector_catch
->value
, 0, 32);
1036 /* store new settings */
1037 buf_set_u32(vector_catch
->value
, 0, 32, vector_catch_value
);
1038 embeddedice_store_reg(vector_catch
);
1041 /* output current settings (skip RESERVED vector) */
1042 for (i
= 0; i
< 8; i
++)
1046 command_print(cmd_ctx
, "%s: %s", arm9tdmi_vectors
[i
].name
,
1047 (vector_catch_value
& (1 << i
)) ? "catch" : "don't catch");
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1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)