1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
25 #include "time_support.h"
29 #define _DEBUG_INSTRUCTION_EXECUTION_
33 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
34 int arm926ejs_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
35 int arm926ejs_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
36 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
37 int arm926ejs_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
38 int arm926ejs_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm926ejs_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm926ejs_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 /* forward declarations */
44 int arm926ejs_target_create(struct target_s
*target
, Jim_Interp
*interp
);
45 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
46 int arm926ejs_quit(void);
47 int arm926ejs_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
49 static int arm926ejs_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
);
50 static int arm926ejs_mmu(struct target_s
*target
, int *enabled
);
52 target_type_t arm926ejs_target
=
57 .arch_state
= arm926ejs_arch_state
,
59 .target_request_data
= arm7_9_target_request_data
,
62 .resume
= arm7_9_resume
,
65 .assert_reset
= arm7_9_assert_reset
,
66 .deassert_reset
= arm7_9_deassert_reset
,
67 .soft_reset_halt
= arm926ejs_soft_reset_halt
,
69 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
71 .read_memory
= arm7_9_read_memory
,
72 .write_memory
= arm926ejs_write_memory
,
73 .bulk_write_memory
= arm7_9_bulk_write_memory
,
74 .checksum_memory
= arm7_9_checksum_memory
,
75 .blank_check_memory
= arm7_9_blank_check_memory
,
77 .run_algorithm
= armv4_5_run_algorithm
,
79 .add_breakpoint
= arm7_9_add_breakpoint
,
80 .remove_breakpoint
= arm7_9_remove_breakpoint
,
81 .add_watchpoint
= arm7_9_add_watchpoint
,
82 .remove_watchpoint
= arm7_9_remove_watchpoint
,
84 .register_commands
= arm926ejs_register_commands
,
85 .target_create
= arm926ejs_target_create
,
86 .init_target
= arm926ejs_init_target
,
87 .examine
= arm9tdmi_examine
,
88 .quit
= arm926ejs_quit
,
89 .virt2phys
= arm926ejs_virt2phys
,
93 int arm926ejs_catch_broken_irscan(u8
*captured
, void *priv
, scan_field_t
*field
)
95 /* FIX!!!! this code should be reenabled. For now it does not check
99 /* The ARM926EJ-S' instruction register is 4 bits wide */
100 u8 t
= *captured
& 0xf;
101 u8 t2
= *field
->in_check_value
& 0xf;
106 else if ((t
== 0x0f) || (t
== 0x00))
108 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
111 return ERROR_JTAG_QUEUE_FAILED
;;
115 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
117 int arm926ejs_cp15_read(target_t
*target
, u32 op1
, u32 op2
, u32 CRn
, u32 CRm
, u32
*value
)
119 int retval
= ERROR_OK
;
120 armv4_5_common_t
*armv4_5
= target
->arch_info
;
121 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
122 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
123 u32 address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
124 scan_field_t fields
[4];
129 buf_set_u32(address_buf
, 0, 14, address
);
131 jtag_add_end_state(TAP_IDLE
);
132 if ((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
136 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
138 fields
[0].tap
= jtag_info
->tap
;
139 fields
[0].num_bits
= 32;
140 fields
[0].out_value
= NULL
;
141 fields
[0].in_value
= (u8
*)value
;
144 fields
[1].tap
= jtag_info
->tap
;
145 fields
[1].num_bits
= 1;
146 fields
[1].out_value
= &access
;
147 fields
[1].in_value
= &access
;
149 fields
[2].tap
= jtag_info
->tap
;
150 fields
[2].num_bits
= 14;
151 fields
[2].out_value
= address_buf
;
152 fields
[2].in_value
= NULL
;
154 fields
[3].tap
= jtag_info
->tap
;
155 fields
[3].num_bits
= 1;
156 fields
[3].out_value
= &nr_w_buf
;
157 fields
[3].in_value
= NULL
;
159 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
161 /*TODO: add timeout*/
164 /* rescan with NOP, to wait for the access to complete */
167 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
169 jtag_add_callback(arm_le_to_h_u32
, (u8
*)value
);
171 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
175 } while (buf_get_u32(&access
, 0, 1) != 1);
177 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
178 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, *value
);
181 arm_jtag_set_instr(jtag_info
, 0xc, &arm926ejs_catch_broken_irscan
);
186 int arm926ejs_cp15_write(target_t
*target
, u32 op1
, u32 op2
, u32 CRn
, u32 CRm
, u32 value
)
188 int retval
= ERROR_OK
;
189 armv4_5_common_t
*armv4_5
= target
->arch_info
;
190 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
191 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
192 u32 address
= ARM926EJS_CP15_ADDR(op1
, op2
, CRn
, CRm
);
193 scan_field_t fields
[4];
199 buf_set_u32(address_buf
, 0, 14, address
);
200 buf_set_u32(value_buf
, 0, 32, value
);
202 jtag_add_end_state(TAP_IDLE
);
203 if ((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
207 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
209 fields
[0].tap
= jtag_info
->tap
;
210 fields
[0].num_bits
= 32;
211 fields
[0].out_value
= value_buf
;
212 fields
[0].in_value
= NULL
;
214 fields
[1].tap
= jtag_info
->tap
;
215 fields
[1].num_bits
= 1;
216 fields
[1].out_value
= &access
;
217 fields
[1].in_value
= &access
;
219 fields
[2].tap
= jtag_info
->tap
;
220 fields
[2].num_bits
= 14;
221 fields
[2].out_value
= address_buf
;
222 fields
[2].in_value
= NULL
;
224 fields
[3].tap
= jtag_info
->tap
;
225 fields
[3].num_bits
= 1;
226 fields
[3].out_value
= &nr_w_buf
;
227 fields
[3].in_value
= NULL
;
229 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
230 /*TODO: add timeout*/
233 /* rescan with NOP, to wait for the access to complete */
236 jtag_add_dr_scan(4, fields
, TAP_INVALID
);
237 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
241 } while (buf_get_u32(&access
, 0, 1) != 1);
243 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
244 LOG_DEBUG("addr: 0x%x value: %8.8x", address
, value
);
247 arm_jtag_set_instr(jtag_info
, 0xf, &arm926ejs_catch_broken_irscan
);
252 int arm926ejs_examine_debug_reason(target_t
*target
)
254 armv4_5_common_t
*armv4_5
= target
->arch_info
;
255 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
256 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
260 embeddedice_read_reg(dbg_stat
);
261 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
264 debug_reason
= buf_get_u32(dbg_stat
->value
, 6, 4);
266 switch (debug_reason
)
269 LOG_DEBUG("breakpoint from EICE unit 0");
270 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
273 LOG_DEBUG("breakpoint from EICE unit 1");
274 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
277 LOG_DEBUG("soft breakpoint (BKPT instruction)");
278 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
281 LOG_DEBUG("vector catch breakpoint");
282 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
285 LOG_DEBUG("external breakpoint");
286 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
289 LOG_DEBUG("watchpoint from EICE unit 0");
290 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
293 LOG_DEBUG("watchpoint from EICE unit 1");
294 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
297 LOG_DEBUG("external watchpoint");
298 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
301 LOG_DEBUG("internal debug request");
302 target
->debug_reason
= DBG_REASON_DBGRQ
;
305 LOG_DEBUG("external debug request");
306 target
->debug_reason
= DBG_REASON_DBGRQ
;
309 LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
312 /* FIX!!!! here be dragons!!! We need to fail here so
313 * the target will interpreted as halted but we won't
314 * try to talk to it right now... a resume + halt seems
315 * to sync things up again. Please send an email to
316 * openocd development mailing list if you have hardware
317 * to donate to look into this problem....
319 LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
320 target
->debug_reason
= DBG_REASON_DBGRQ
;
321 retval
= ERROR_TARGET_FAILURE
;
324 LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason
);
325 target
->debug_reason
= DBG_REASON_DBGRQ
;
326 /* if we fail here, we won't talk to the target and it will
327 * be reported to be in the halted state */
328 retval
= ERROR_TARGET_FAILURE
;
335 u32
arm926ejs_get_ttb(target_t
*target
)
337 armv4_5_common_t
*armv4_5
= target
->arch_info
;
338 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
339 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
340 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
344 if ((retval
= arm926ejs
->read_cp15(target
, 0, 0, 2, 0, &ttb
)) != ERROR_OK
)
350 void arm926ejs_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
352 armv4_5_common_t
*armv4_5
= target
->arch_info
;
353 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
354 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
355 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
358 /* read cp15 control register */
359 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
360 jtag_execute_queue();
365 arm926ejs
->write_cp15(target
, 0, 0, 8, 7, 0x0);
367 cp15_control
&= ~0x1U
;
373 /* read-modify-write CP15 debug override register
374 * to enable "test and clean all" */
375 arm926ejs
->read_cp15(target
, 0, 0, 15, 0, &debug_override
);
376 debug_override
|= 0x80000;
377 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
379 /* clean and invalidate DCache */
380 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
382 /* write CP15 debug override register
383 * to disable "test and clean all" */
384 debug_override
&= ~0x80000;
385 arm926ejs
->write_cp15(target
, 0, 0, 15, 0, debug_override
);
387 cp15_control
&= ~0x4U
;
392 /* invalidate ICache */
393 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, 0x0);
395 cp15_control
&= ~0x1000U
;
398 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
401 void arm926ejs_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
403 armv4_5_common_t
*armv4_5
= target
->arch_info
;
404 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
405 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
406 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
409 /* read cp15 control register */
410 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &cp15_control
);
411 jtag_execute_queue();
414 cp15_control
|= 0x1U
;
417 cp15_control
|= 0x4U
;
420 cp15_control
|= 0x1000U
;
422 arm926ejs
->write_cp15(target
, 0, 0, 1, 0, cp15_control
);
425 void arm926ejs_post_debug_entry(target_t
*target
)
427 armv4_5_common_t
*armv4_5
= target
->arch_info
;
428 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
429 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
430 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
432 /* examine cp15 control reg */
433 arm926ejs
->read_cp15(target
, 0, 0, 1, 0, &arm926ejs
->cp15_control_reg
);
434 jtag_execute_queue();
435 LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs
->cp15_control_reg
);
437 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
440 /* identify caches */
441 arm926ejs
->read_cp15(target
, 0, 1, 0, 0, &cache_type_reg
);
442 jtag_execute_queue();
443 armv4_5_identify_cache(cache_type_reg
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
446 arm926ejs
->armv4_5_mmu
.mmu_enabled
= (arm926ejs
->cp15_control_reg
& 0x1U
) ? 1 : 0;
447 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x4U
) ? 1 : 0;
448 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm926ejs
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
450 /* save i/d fault status and address register */
451 arm926ejs
->read_cp15(target
, 0, 0, 5, 0, &arm926ejs
->d_fsr
);
452 arm926ejs
->read_cp15(target
, 0, 1, 5, 0, &arm926ejs
->i_fsr
);
453 arm926ejs
->read_cp15(target
, 0, 0, 6, 0, &arm926ejs
->d_far
);
455 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
456 arm926ejs
->d_fsr
, arm926ejs
->d_far
, arm926ejs
->i_fsr
);
460 /* read-modify-write CP15 cache debug control register
461 * to disable I/D-cache linefills and force WT */
462 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
463 cache_dbg_ctrl
|= 0x7;
464 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
467 void arm926ejs_pre_restore_context(target_t
*target
)
469 armv4_5_common_t
*armv4_5
= target
->arch_info
;
470 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
471 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
472 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
474 /* restore i/d fault status and address register */
475 arm926ejs
->write_cp15(target
, 0, 0, 5, 0, arm926ejs
->d_fsr
);
476 arm926ejs
->write_cp15(target
, 0, 1, 5, 0, arm926ejs
->i_fsr
);
477 arm926ejs
->write_cp15(target
, 0, 0, 6, 0, arm926ejs
->d_far
);
481 /* read-modify-write CP15 cache debug control register
482 * to reenable I/D-cache linefills and disable WT */
483 arm926ejs
->read_cp15(target
, 7, 0, 15, 0, &cache_dbg_ctrl
);
484 cache_dbg_ctrl
&= ~0x7;
485 arm926ejs
->write_cp15(target
, 7, 0, 15, 0, cache_dbg_ctrl
);
488 int arm926ejs_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm926ejs_common_t
**arm926ejs_p
)
490 armv4_5_common_t
*armv4_5
= target
->arch_info
;
491 arm7_9_common_t
*arm7_9
;
492 arm9tdmi_common_t
*arm9tdmi
;
493 arm926ejs_common_t
*arm926ejs
;
495 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
500 arm7_9
= armv4_5
->arch_info
;
501 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
506 arm9tdmi
= arm7_9
->arch_info
;
507 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
512 arm926ejs
= arm9tdmi
->arch_info
;
513 if (arm926ejs
->common_magic
!= ARM926EJS_COMMON_MAGIC
)
518 *armv4_5_p
= armv4_5
;
520 *arm9tdmi_p
= arm9tdmi
;
521 *arm926ejs_p
= arm926ejs
;
526 int arm926ejs_arch_state(struct target_s
*target
)
528 armv4_5_common_t
*armv4_5
= target
->arch_info
;
529 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
530 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
531 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
535 "disabled", "enabled"
538 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
540 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
545 "target halted in %s state due to %s, current mode: %s\n"
546 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
547 "MMU: %s, D-Cache: %s, I-Cache: %s",
548 armv4_5_state_strings
[armv4_5
->core_state
],
549 Jim_Nvp_value2name_simple( nvp_target_debug_reason
,target
->debug_reason
)->name
,
550 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
551 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
552 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
553 state
[arm926ejs
->armv4_5_mmu
.mmu_enabled
],
554 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
555 state
[arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
560 int arm926ejs_soft_reset_halt(struct target_s
*target
)
562 int retval
= ERROR_OK
;
563 armv4_5_common_t
*armv4_5
= target
->arch_info
;
564 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
565 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
566 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
567 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
569 if ((retval
= target_halt(target
)) != ERROR_OK
)
574 long long then
=timeval_ms();
576 while (!(timeout
=((timeval_ms()-then
)>1000)))
578 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
580 embeddedice_read_reg(dbg_stat
);
581 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
591 /* do not eat all CPU, time out after 1 se*/
600 LOG_ERROR("Failed to halt CPU after 1 sec");
601 return ERROR_TARGET_TIMEOUT
;
604 target
->state
= TARGET_HALTED
;
606 /* SVC, ARM state, IRQ and FIQ disabled */
607 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
608 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
609 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
611 /* start fetching from 0x0 */
612 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
613 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
614 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
616 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
617 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
619 arm926ejs_disable_mmu_caches(target
, 1, 1, 1);
620 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
621 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
622 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
624 return target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
627 int arm926ejs_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
630 armv4_5_common_t
*armv4_5
= target
->arch_info
;
631 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
632 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
633 arm926ejs_common_t
*arm926ejs
= arm9tdmi
->arch_info
;
635 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
638 /* If ICache is enabled, we have to invalidate affected ICache lines
639 * the DCache is forced to write-through, so we don't have to clean it here
641 if (arm926ejs
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
645 /* invalidate ICache single entry with MVA */
646 arm926ejs
->write_cp15(target
, 0, 1, 7, 5, address
);
650 /* invalidate ICache */
651 arm926ejs
->write_cp15(target
, 0, 0, 7, 5, address
);
658 int arm926ejs_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
660 arm9tdmi_init_target(cmd_ctx
, target
);
665 int arm926ejs_quit(void)
670 int arm926ejs_init_arch_info(target_t
*target
, arm926ejs_common_t
*arm926ejs
, jtag_tap_t
*tap
)
672 arm9tdmi_common_t
*arm9tdmi
= &arm926ejs
->arm9tdmi_common
;
673 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
675 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
677 arm9tdmi_init_arch_info(target
, arm9tdmi
, tap
);
679 arm9tdmi
->arch_info
= arm926ejs
;
680 arm926ejs
->common_magic
= ARM926EJS_COMMON_MAGIC
;
682 arm7_9
->post_debug_entry
= arm926ejs_post_debug_entry
;
683 arm7_9
->pre_restore_context
= arm926ejs_pre_restore_context
;
685 arm926ejs
->read_cp15
= arm926ejs_cp15_read
;
686 arm926ejs
->write_cp15
= arm926ejs_cp15_write
;
687 arm926ejs
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
688 arm926ejs
->armv4_5_mmu
.get_ttb
= arm926ejs_get_ttb
;
689 arm926ejs
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
690 arm926ejs
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
691 arm926ejs
->armv4_5_mmu
.disable_mmu_caches
= arm926ejs_disable_mmu_caches
;
692 arm926ejs
->armv4_5_mmu
.enable_mmu_caches
= arm926ejs_enable_mmu_caches
;
693 arm926ejs
->armv4_5_mmu
.has_tiny_pages
= 1;
694 arm926ejs
->armv4_5_mmu
.mmu_enabled
= 0;
696 arm7_9
->examine_debug_reason
= arm926ejs_examine_debug_reason
;
698 /* The ARM926EJ-S implements the ARMv5TE architecture which
699 * has the BKPT instruction, so we don't have to use a watchpoint comparator
701 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
702 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
707 int arm926ejs_target_create(struct target_s
*target
, Jim_Interp
*interp
)
709 arm926ejs_common_t
*arm926ejs
= calloc(1,sizeof(arm926ejs_common_t
));
711 arm926ejs_init_arch_info(target
, arm926ejs
, target
->tap
);
716 int arm926ejs_register_commands(struct command_context_s
*cmd_ctx
)
719 command_t
*arm926ejs_cmd
;
722 retval
= arm9tdmi_register_commands(cmd_ctx
);
724 arm926ejs_cmd
= register_command(cmd_ctx
, NULL
, "arm926ejs", NULL
, COMMAND_ANY
, "arm926ejs specific commands");
726 register_command(cmd_ctx
, arm926ejs_cmd
, "cp15", arm926ejs_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
728 register_command(cmd_ctx
, arm926ejs_cmd
, "cache_info", arm926ejs_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
729 register_command(cmd_ctx
, arm926ejs_cmd
, "virt2phys", arm926ejs_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
731 register_command(cmd_ctx
, arm926ejs_cmd
, "mdw_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
732 register_command(cmd_ctx
, arm926ejs_cmd
, "mdh_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
733 register_command(cmd_ctx
, arm926ejs_cmd
, "mdb_phys", arm926ejs_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
735 register_command(cmd_ctx
, arm926ejs_cmd
, "mww_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
736 register_command(cmd_ctx
, arm926ejs_cmd
, "mwh_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
737 register_command(cmd_ctx
, arm926ejs_cmd
, "mwb_phys", arm926ejs_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
742 int arm926ejs_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
745 target_t
*target
= get_current_target(cmd_ctx
);
746 armv4_5_common_t
*armv4_5
;
747 arm7_9_common_t
*arm7_9
;
748 arm9tdmi_common_t
*arm9tdmi
;
749 arm926ejs_common_t
*arm926ejs
;
755 if ((argc
< 4) || (argc
> 5))
757 command_print(cmd_ctx
, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
761 opcode_1
= strtoul(args
[0], NULL
, 0);
762 opcode_2
= strtoul(args
[1], NULL
, 0);
763 CRn
= strtoul(args
[2], NULL
, 0);
764 CRm
= strtoul(args
[3], NULL
, 0);
766 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
768 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
772 if (target
->state
!= TARGET_HALTED
)
774 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
781 if ((retval
= arm926ejs
->read_cp15(target
, opcode_1
, opcode_2
, CRn
, CRm
, &value
)) != ERROR_OK
)
783 command_print(cmd_ctx
, "couldn't access register");
786 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
791 command_print(cmd_ctx
, "%i %i %i %i: %8.8x", opcode_1
, opcode_2
, CRn
, CRm
, value
);
795 u32 value
= strtoul(args
[4], NULL
, 0);
796 if ((retval
= arm926ejs
->write_cp15(target
, opcode_1
, opcode_2
, CRn
, CRm
, value
)) != ERROR_OK
)
798 command_print(cmd_ctx
, "couldn't access register");
801 command_print(cmd_ctx
, "%i %i %i %i: %8.8x", opcode_1
, opcode_2
, CRn
, CRm
, value
);
807 int arm926ejs_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
809 target_t
*target
= get_current_target(cmd_ctx
);
810 armv4_5_common_t
*armv4_5
;
811 arm7_9_common_t
*arm7_9
;
812 arm9tdmi_common_t
*arm9tdmi
;
813 arm926ejs_common_t
*arm926ejs
;
815 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
817 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
821 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm926ejs
->armv4_5_mmu
.armv4_5_cache
);
824 int arm926ejs_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
826 target_t
*target
= get_current_target(cmd_ctx
);
827 armv4_5_common_t
*armv4_5
;
828 arm7_9_common_t
*arm7_9
;
829 arm9tdmi_common_t
*arm9tdmi
;
830 arm926ejs_common_t
*arm926ejs
;
831 arm_jtag_t
*jtag_info
;
833 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
835 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
839 jtag_info
= &arm7_9
->jtag_info
;
841 if (target
->state
!= TARGET_HALTED
)
843 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
847 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
850 int arm926ejs_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
852 target_t
*target
= get_current_target(cmd_ctx
);
853 armv4_5_common_t
*armv4_5
;
854 arm7_9_common_t
*arm7_9
;
855 arm9tdmi_common_t
*arm9tdmi
;
856 arm926ejs_common_t
*arm926ejs
;
857 arm_jtag_t
*jtag_info
;
859 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
861 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
865 jtag_info
= &arm7_9
->jtag_info
;
867 if (target
->state
!= TARGET_HALTED
)
869 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
873 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
876 int arm926ejs_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
878 target_t
*target
= get_current_target(cmd_ctx
);
879 armv4_5_common_t
*armv4_5
;
880 arm7_9_common_t
*arm7_9
;
881 arm9tdmi_common_t
*arm9tdmi
;
882 arm926ejs_common_t
*arm926ejs
;
883 arm_jtag_t
*jtag_info
;
885 if (arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
) != ERROR_OK
)
887 command_print(cmd_ctx
, "current target isn't an ARM926EJ-S target");
891 jtag_info
= &arm7_9
->jtag_info
;
893 if (target
->state
!= TARGET_HALTED
)
895 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
899 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm926ejs
->armv4_5_mmu
);
902 static int arm926ejs_virt2phys(struct target_s
*target
, u32
virtual, u32
*physical
)
910 armv4_5_common_t
*armv4_5
;
911 arm7_9_common_t
*arm7_9
;
912 arm9tdmi_common_t
*arm9tdmi
;
913 arm926ejs_common_t
*arm926ejs
;
914 retval
= arm926ejs_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm926ejs
);
915 if (retval
!= ERROR_OK
)
919 u32 ret
= armv4_5_mmu_translate_va(target
, &arm926ejs
->armv4_5_mmu
, virtual, &type
, &cb
, &domain
, &ap
);
928 static int arm926ejs_mmu(struct target_s
*target
, int *enabled
)
930 armv4_5_common_t
*armv4_5
= target
->arch_info
;
931 arm926ejs_common_t
*arm926ejs
= armv4_5
->arch_info
;
933 if (target
->state
!= TARGET_HALTED
)
935 LOG_ERROR("Target not halted");
936 return ERROR_TARGET_INVALID
;
938 *enabled
= arm926ejs
->armv4_5_mmu
.mmu_enabled
;
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