1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm920t_register_commands(struct command_context_s
*cmd_ctx
);
38 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
39 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm920t_handle_virt2phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
42 int arm920t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 int arm920t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
45 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
46 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
48 /* forward declarations */
49 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
);
50 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
52 int arm920t_arch_state(struct target_s
*target
);
53 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
54 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
55 int arm920t_soft_reset_halt(struct target_s
*target
);
57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
59 target_type_t arm920t_target
=
64 .arch_state
= arm920t_arch_state
,
66 .target_request_data
= arm7_9_target_request_data
,
69 .resume
= arm7_9_resume
,
72 .assert_reset
= arm7_9_assert_reset
,
73 .deassert_reset
= arm7_9_deassert_reset
,
74 .soft_reset_halt
= arm920t_soft_reset_halt
,
75 .prepare_reset_halt
= arm7_9_prepare_reset_halt
,
77 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
79 .read_memory
= arm920t_read_memory
,
80 .write_memory
= arm920t_write_memory
,
81 .bulk_write_memory
= arm7_9_bulk_write_memory
,
82 .checksum_memory
= arm7_9_checksum_memory
,
84 .run_algorithm
= armv4_5_run_algorithm
,
86 .add_breakpoint
= arm7_9_add_breakpoint
,
87 .remove_breakpoint
= arm7_9_remove_breakpoint
,
88 .add_watchpoint
= arm7_9_add_watchpoint
,
89 .remove_watchpoint
= arm7_9_remove_watchpoint
,
91 .register_commands
= arm920t_register_commands
,
92 .target_command
= arm920t_target_command
,
93 .init_target
= arm920t_init_target
,
97 int arm920t_read_cp15_physical(target_t
*target
, int reg_addr
, u32
*value
)
99 armv4_5_common_t
*armv4_5
= target
->arch_info
;
100 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
101 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
102 scan_field_t fields
[4];
103 u8 access_type_buf
= 1;
104 u8 reg_addr_buf
= reg_addr
& 0x3f;
107 jtag_add_end_state(TAP_RTI
);
108 arm_jtag_scann(jtag_info
, 0xf);
109 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
111 fields
[0].device
= jtag_info
->chain_pos
;
112 fields
[0].num_bits
= 1;
113 fields
[0].out_value
= &access_type_buf
;
114 fields
[0].out_mask
= NULL
;
115 fields
[0].in_value
= NULL
;
116 fields
[0].in_check_value
= NULL
;
117 fields
[0].in_check_mask
= NULL
;
118 fields
[0].in_handler
= NULL
;
119 fields
[0].in_handler_priv
= NULL
;
121 fields
[1].device
= jtag_info
->chain_pos
;
122 fields
[1].num_bits
= 32;
123 fields
[1].out_value
= NULL
;
124 fields
[1].out_mask
= NULL
;
125 fields
[1].in_value
= NULL
;
126 fields
[1].in_check_value
= NULL
;
127 fields
[1].in_check_mask
= NULL
;
128 fields
[1].in_handler
= NULL
;
129 fields
[1].in_handler_priv
= NULL
;
131 fields
[2].device
= jtag_info
->chain_pos
;
132 fields
[2].num_bits
= 6;
133 fields
[2].out_value
= ®_addr_buf
;
134 fields
[2].out_mask
= NULL
;
135 fields
[2].in_value
= NULL
;
136 fields
[2].in_check_value
= NULL
;
137 fields
[2].in_check_mask
= NULL
;
138 fields
[2].in_handler
= NULL
;
139 fields
[2].in_handler_priv
= NULL
;
141 fields
[3].device
= jtag_info
->chain_pos
;
142 fields
[3].num_bits
= 1;
143 fields
[3].out_value
= &nr_w_buf
;
144 fields
[3].out_mask
= NULL
;
145 fields
[3].in_value
= NULL
;
146 fields
[3].in_check_value
= NULL
;
147 fields
[3].in_check_mask
= NULL
;
148 fields
[3].in_handler
= NULL
;
149 fields
[3].in_handler_priv
= NULL
;
151 jtag_add_dr_scan(4, fields
, -1);
153 fields
[1].in_handler_priv
= value
;
154 fields
[1].in_handler
= arm_jtag_buf_to_u32
;
156 jtag_add_dr_scan(4, fields
, -1);
158 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
159 jtag_execute_queue();
160 DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
166 int arm920t_write_cp15_physical(target_t
*target
, int reg_addr
, u32 value
)
168 armv4_5_common_t
*armv4_5
= target
->arch_info
;
169 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
170 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
171 scan_field_t fields
[4];
172 u8 access_type_buf
= 1;
173 u8 reg_addr_buf
= reg_addr
& 0x3f;
177 buf_set_u32(value_buf
, 0, 32, value
);
179 jtag_add_end_state(TAP_RTI
);
180 arm_jtag_scann(jtag_info
, 0xf);
181 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
183 fields
[0].device
= jtag_info
->chain_pos
;
184 fields
[0].num_bits
= 1;
185 fields
[0].out_value
= &access_type_buf
;
186 fields
[0].out_mask
= NULL
;
187 fields
[0].in_value
= NULL
;
188 fields
[0].in_check_value
= NULL
;
189 fields
[0].in_check_mask
= NULL
;
190 fields
[0].in_handler
= NULL
;
191 fields
[0].in_handler_priv
= NULL
;
193 fields
[1].device
= jtag_info
->chain_pos
;
194 fields
[1].num_bits
= 32;
195 fields
[1].out_value
= value_buf
;
196 fields
[1].out_mask
= NULL
;
197 fields
[1].in_value
= NULL
;
198 fields
[1].in_check_value
= NULL
;
199 fields
[1].in_check_mask
= NULL
;
200 fields
[1].in_handler
= NULL
;
201 fields
[1].in_handler_priv
= NULL
;
203 fields
[2].device
= jtag_info
->chain_pos
;
204 fields
[2].num_bits
= 6;
205 fields
[2].out_value
= ®_addr_buf
;
206 fields
[2].out_mask
= NULL
;
207 fields
[2].in_value
= NULL
;
208 fields
[2].in_check_value
= NULL
;
209 fields
[2].in_check_mask
= NULL
;
210 fields
[2].in_handler
= NULL
;
211 fields
[2].in_handler_priv
= NULL
;
213 fields
[3].device
= jtag_info
->chain_pos
;
214 fields
[3].num_bits
= 1;
215 fields
[3].out_value
= &nr_w_buf
;
216 fields
[3].out_mask
= NULL
;
217 fields
[3].in_value
= NULL
;
218 fields
[3].in_check_value
= NULL
;
219 fields
[3].in_check_mask
= NULL
;
220 fields
[3].in_handler
= NULL
;
221 fields
[3].in_handler_priv
= NULL
;
223 jtag_add_dr_scan(4, fields
, -1);
225 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
226 DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
232 int arm920t_execute_cp15(target_t
*target
, u32 cp15_opcode
, u32 arm_opcode
)
234 armv4_5_common_t
*armv4_5
= target
->arch_info
;
235 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
236 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
237 scan_field_t fields
[4];
238 u8 access_type_buf
= 0; /* interpreted access */
239 u8 reg_addr_buf
= 0x0;
241 u8 cp15_opcode_buf
[4];
243 jtag_add_end_state(TAP_RTI
);
244 arm_jtag_scann(jtag_info
, 0xf);
245 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
247 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
249 fields
[0].device
= jtag_info
->chain_pos
;
250 fields
[0].num_bits
= 1;
251 fields
[0].out_value
= &access_type_buf
;
252 fields
[0].out_mask
= NULL
;
253 fields
[0].in_value
= NULL
;
254 fields
[0].in_check_value
= NULL
;
255 fields
[0].in_check_mask
= NULL
;
256 fields
[0].in_handler
= NULL
;
257 fields
[0].in_handler_priv
= NULL
;
259 fields
[1].device
= jtag_info
->chain_pos
;
260 fields
[1].num_bits
= 32;
261 fields
[1].out_value
= cp15_opcode_buf
;
262 fields
[1].out_mask
= NULL
;
263 fields
[1].in_value
= NULL
;
264 fields
[1].in_check_value
= NULL
;
265 fields
[1].in_check_mask
= NULL
;
266 fields
[1].in_handler
= NULL
;
267 fields
[1].in_handler_priv
= NULL
;
269 fields
[2].device
= jtag_info
->chain_pos
;
270 fields
[2].num_bits
= 6;
271 fields
[2].out_value
= ®_addr_buf
;
272 fields
[2].out_mask
= NULL
;
273 fields
[2].in_value
= NULL
;
274 fields
[2].in_check_value
= NULL
;
275 fields
[2].in_check_mask
= NULL
;
276 fields
[2].in_handler
= NULL
;
277 fields
[2].in_handler_priv
= NULL
;
279 fields
[3].device
= jtag_info
->chain_pos
;
280 fields
[3].num_bits
= 1;
281 fields
[3].out_value
= &nr_w_buf
;
282 fields
[3].out_mask
= NULL
;
283 fields
[3].in_value
= NULL
;
284 fields
[3].in_check_value
= NULL
;
285 fields
[3].in_check_mask
= NULL
;
286 fields
[3].in_handler
= NULL
;
287 fields
[3].in_handler_priv
= NULL
;
289 jtag_add_dr_scan(4, fields
, -1);
291 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
292 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
293 arm7_9_execute_sys_speed(target
);
295 if (jtag_execute_queue() != ERROR_OK
)
297 ERROR("failed executing JTAG queue, exiting");
304 int arm920t_read_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 address
, u32
*value
)
306 armv4_5_common_t
*armv4_5
= target
->arch_info
;
311 /* load address into R1 */
313 arm9tdmi_write_core_regs(target
, 0x2, regs
);
315 /* read-modify-write CP15 test state register
316 * to enable interpreted access mode */
317 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
318 jtag_execute_queue();
319 cp15c15
|= 1; /* set interpret mode */
320 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
322 /* execute CP15 instruction and ARM load (reading from coprocessor) */
323 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
325 /* disable interpreted access mode */
326 cp15c15
&= ~1U; /* clear interpret mode */
327 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
329 /* retrieve value from R0 */
331 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
332 jtag_execute_queue();
334 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
335 DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode
, address
, *value
);
338 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
339 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
344 int arm920t_write_cp15_interpreted(target_t
*target
, u32 cp15_opcode
, u32 value
, u32 address
)
347 armv4_5_common_t
*armv4_5
= target
->arch_info
;
350 /* load value, address into R0, R1 */
353 arm9tdmi_write_core_regs(target
, 0x3, regs
);
355 /* read-modify-write CP15 test state register
356 * to enable interpreted access mode */
357 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
358 jtag_execute_queue();
359 cp15c15
|= 1; /* set interpret mode */
360 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
362 /* execute CP15 instruction and ARM store (writing to coprocessor) */
363 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
365 /* disable interpreted access mode */
366 cp15c15
&= ~1U; /* set interpret mode */
367 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
369 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
370 DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode
, value
, address
);
373 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
374 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
379 u32
arm920t_get_ttb(target_t
*target
)
384 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
390 void arm920t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
394 /* read cp15 control register */
395 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
396 jtag_execute_queue();
399 cp15_control
&= ~0x1U
;
402 cp15_control
&= ~0x4U
;
405 cp15_control
&= ~0x1000U
;
407 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
410 void arm920t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
414 /* read cp15 control register */
415 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
416 jtag_execute_queue();
419 cp15_control
|= 0x1U
;
422 cp15_control
|= 0x4U
;
425 cp15_control
|= 0x1000U
;
427 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
430 void arm920t_post_debug_entry(target_t
*target
)
433 armv4_5_common_t
*armv4_5
= target
->arch_info
;
434 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
435 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
436 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
438 /* examine cp15 control reg */
439 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
440 jtag_execute_queue();
441 DEBUG("cp15_control_reg: %8.8x", arm920t
->cp15_control_reg
);
443 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
446 /* identify caches */
447 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
448 jtag_execute_queue();
449 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
452 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
453 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
454 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
456 /* save i/d fault status and address register */
457 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
458 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
459 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
460 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
462 DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
463 arm920t
->d_fsr
, arm920t
->d_far
, arm920t
->i_fsr
, arm920t
->i_far
);
465 if (arm920t
->preserve_cache
)
467 /* read-modify-write CP15 test state register
468 * to disable I/D-cache linefills */
469 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
470 jtag_execute_queue();
472 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
476 void arm920t_pre_restore_context(target_t
*target
)
479 armv4_5_common_t
*armv4_5
= target
->arch_info
;
480 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
481 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
482 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
484 /* restore i/d fault status and address register */
485 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
486 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
487 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
488 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
490 /* read-modify-write CP15 test state register
491 * to reenable I/D-cache linefills */
492 if (arm920t
->preserve_cache
)
494 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
495 jtag_execute_queue();
497 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
501 int arm920t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm920t_common_t
**arm920t_p
)
503 armv4_5_common_t
*armv4_5
= target
->arch_info
;
504 arm7_9_common_t
*arm7_9
;
505 arm9tdmi_common_t
*arm9tdmi
;
506 arm920t_common_t
*arm920t
;
508 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
513 arm7_9
= armv4_5
->arch_info
;
514 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
519 arm9tdmi
= arm7_9
->arch_info
;
520 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
525 arm920t
= arm9tdmi
->arch_info
;
526 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
531 *armv4_5_p
= armv4_5
;
533 *arm9tdmi_p
= arm9tdmi
;
534 *arm920t_p
= arm920t
;
539 int arm920t_arch_state(struct target_s
*target
)
541 armv4_5_common_t
*armv4_5
= target
->arch_info
;
542 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
543 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
544 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
548 "disabled", "enabled"
551 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
553 ERROR("BUG: called for a non-ARMv4/5 target");
557 USER( "target halted in %s state due to %s, current mode: %s\n"
558 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
559 "MMU: %s, D-Cache: %s, I-Cache: %s",
560 armv4_5_state_strings
[armv4_5
->core_state
],
561 target_debug_reason_strings
[target
->debug_reason
],
562 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
563 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
564 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
565 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
566 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
567 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
572 int arm920t_read_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
576 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
581 int arm920t_write_memory(struct target_s
*target
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
584 armv4_5_common_t
*armv4_5
= target
->arch_info
;
585 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
586 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
587 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
589 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
592 if (((size
== 4) || (size
== 2)) && (count
== 1))
594 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
596 DEBUG("D-Cache enabled, writing through to main memory");
600 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
, address
, &type
, &cb
, &domain
, &ap
);
603 /* cacheable & bufferable means write-back region */
605 armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
, pa
, size
, count
, buffer
);
608 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
610 DEBUG("I-Cache enabled, invalidating affected I-Cache line");
611 arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
618 int arm920t_soft_reset_halt(struct target_s
*target
)
620 armv4_5_common_t
*armv4_5
= target
->arch_info
;
621 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
622 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
623 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
624 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
626 if (target
->state
== TARGET_RUNNING
)
628 target
->type
->halt(target
);
631 while (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
633 embeddedice_read_reg(dbg_stat
);
634 jtag_execute_queue();
637 target
->state
= TARGET_HALTED
;
639 /* SVC, ARM state, IRQ and FIQ disabled */
640 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
641 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
642 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
644 /* start fetching from 0x0 */
645 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
646 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
647 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
649 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
650 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
652 arm920t_disable_mmu_caches(target
, 1, 1, 1);
653 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
654 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
655 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
657 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
662 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
664 arm9tdmi_init_target(cmd_ctx
, target
);
676 int arm920t_init_arch_info(target_t
*target
, arm920t_common_t
*arm920t
, int chain_pos
, char *variant
)
678 arm9tdmi_common_t
*arm9tdmi
= &arm920t
->arm9tdmi_common
;
679 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
681 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
683 arm9tdmi_init_arch_info(target
, arm9tdmi
, chain_pos
, variant
);
685 arm9tdmi
->arch_info
= arm920t
;
686 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
688 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
689 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
691 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
692 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
693 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
694 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
695 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
696 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
697 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
698 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
700 /* disabling linefills leads to lockups, so keep them enabled for now
701 * this doesn't affect correctness, but might affect timing issues, if
702 * important data is evicted from the cache during the debug session
704 arm920t
->preserve_cache
= 0;
706 /* override hw single-step capability from ARM9TDMI */
707 arm7_9
->has_single_step
= 1;
712 int arm920t_target_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct target_s
*target
)
715 char *variant
= NULL
;
716 arm920t_common_t
*arm920t
= malloc(sizeof(arm920t_common_t
));
720 ERROR("'target arm920t' requires at least one additional argument");
724 chain_pos
= strtoul(args
[3], NULL
, 0);
729 DEBUG("chain_pos: %i, variant: %s", chain_pos
, variant
);
731 arm920t_init_arch_info(target
, arm920t
, chain_pos
, variant
);
736 int arm920t_register_commands(struct command_context_s
*cmd_ctx
)
739 command_t
*arm920t_cmd
;
742 retval
= arm9tdmi_register_commands(cmd_ctx
);
744 arm920t_cmd
= register_command(cmd_ctx
, NULL
, "arm920t", NULL
, COMMAND_ANY
, "arm920t specific commands");
746 register_command(cmd_ctx
, arm920t_cmd
, "cp15", arm920t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <num> [value]");
747 register_command(cmd_ctx
, arm920t_cmd
, "cp15i", arm920t_handle_cp15i_command
, COMMAND_EXEC
, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
748 register_command(cmd_ctx
, arm920t_cmd
, "cache_info", arm920t_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
749 register_command(cmd_ctx
, arm920t_cmd
, "virt2phys", arm920t_handle_virt2phys_command
, COMMAND_EXEC
, "translate va to pa <va>");
751 register_command(cmd_ctx
, arm920t_cmd
, "mdw_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
752 register_command(cmd_ctx
, arm920t_cmd
, "mdh_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
753 register_command(cmd_ctx
, arm920t_cmd
, "mdb_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
755 register_command(cmd_ctx
, arm920t_cmd
, "mww_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
756 register_command(cmd_ctx
, arm920t_cmd
, "mwh_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
757 register_command(cmd_ctx
, arm920t_cmd
, "mwb_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
759 register_command(cmd_ctx
, arm920t_cmd
, "read_cache", arm920t_handle_read_cache_command
, COMMAND_EXEC
, "display I/D cache content");
760 register_command(cmd_ctx
, arm920t_cmd
, "read_mmu", arm920t_handle_read_mmu_command
, COMMAND_EXEC
, "display I/D mmu content");
765 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
767 target_t
*target
= get_current_target(cmd_ctx
);
768 armv4_5_common_t
*armv4_5
;
769 arm7_9_common_t
*arm7_9
;
770 arm9tdmi_common_t
*arm9tdmi
;
771 arm920t_common_t
*arm920t
;
772 arm_jtag_t
*jtag_info
;
774 u32 cp15_ctrl
, cp15_ctrl_saved
;
777 u32 C15_C_D_Ind
, C15_C_I_Ind
;
780 arm920t_cache_line_t d_cache
[8][64], i_cache
[8][64];
785 command_print(cmd_ctx
, "usage: arm920t read_cache <filename>");
789 if ((output
= fopen(args
[0], "w")) == NULL
)
791 DEBUG("error opening cache content file");
795 for (i
= 0; i
< 16; i
++)
796 regs_p
[i
] = ®s
[i
];
798 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
800 command_print(cmd_ctx
, "current target isn't an ARM920t target");
804 jtag_info
= &arm7_9
->jtag_info
;
806 /* disable MMU and Caches */
807 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
808 jtag_execute_queue();
809 cp15_ctrl_saved
= cp15_ctrl
;
810 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
811 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
813 /* read CP15 test state register */
814 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
815 jtag_execute_queue();
817 /* read DCache content */
818 fprintf(output
, "DCache:\n");
820 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
821 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
823 fprintf(output
, "\nsegment: %i\n----------", segment
);
825 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
826 regs
[0] = 0x0 | (segment
<< 5);
827 arm9tdmi_write_core_regs(target
, 0x1, regs
);
829 /* set interpret mode */
831 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
833 /* D CAM Read, loads current victim into C15.C.D.Ind */
834 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
836 /* read current victim */
837 arm920t_read_cp15_physical(target
, 0x3d, &C15_C_D_Ind
);
839 /* clear interpret mode */
841 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
843 for (index
= 0; index
< 64; index
++)
845 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
846 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
847 arm9tdmi_write_core_regs(target
, 0x1, regs
);
849 /* set interpret mode */
851 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
853 /* Write DCache victim */
854 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
857 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
860 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
862 /* clear interpret mode */
864 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
866 /* read D RAM and CAM content */
867 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
868 jtag_execute_queue();
870 d_cache
[segment
][index
].cam
= regs
[9];
873 regs
[9] &= 0xfffffffe;
874 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
876 for (i
= 1; i
< 9; i
++)
878 d_cache
[segment
][index
].data
[i
] = regs
[i
];
879 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
884 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
885 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
886 arm9tdmi_write_core_regs(target
, 0x1, regs
);
888 /* set interpret mode */
890 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
892 /* Write DCache victim */
893 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
895 /* clear interpret mode */
897 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
900 /* read ICache content */
901 fprintf(output
, "ICache:\n");
903 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
904 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
906 fprintf(output
, "segment: %i\n----------", segment
);
908 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
909 regs
[0] = 0x0 | (segment
<< 5);
910 arm9tdmi_write_core_regs(target
, 0x1, regs
);
912 /* set interpret mode */
914 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
916 /* I CAM Read, loads current victim into C15.C.I.Ind */
917 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
919 /* read current victim */
920 arm920t_read_cp15_physical(target
, 0x3b, &C15_C_I_Ind
);
922 /* clear interpret mode */
924 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
926 for (index
= 0; index
< 64; index
++)
928 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
929 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
930 arm9tdmi_write_core_regs(target
, 0x1, regs
);
932 /* set interpret mode */
934 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
936 /* Write ICache victim */
937 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
940 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
943 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
945 /* clear interpret mode */
947 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
949 /* read I RAM and CAM content */
950 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
951 jtag_execute_queue();
953 i_cache
[segment
][index
].cam
= regs
[9];
956 regs
[9] &= 0xfffffffe;
957 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
959 for (i
= 1; i
< 9; i
++)
961 i_cache
[segment
][index
].data
[i
] = regs
[i
];
962 fprintf(output
, "%i: 0x%8.8x\n", i
-1, regs
[i
]);
968 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
969 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
970 arm9tdmi_write_core_regs(target
, 0x1, regs
);
972 /* set interpret mode */
974 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
976 /* Write ICache victim */
977 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
979 /* clear interpret mode */
981 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
984 /* restore CP15 MMU and Cache settings */
985 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
987 command_print(cmd_ctx
, "cache content successfully output to %s", args
[0]);
991 /* mark registers dirty. */
992 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
993 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
994 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
995 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
996 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
997 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
998 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
999 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1000 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1001 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1006 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1008 target_t
*target
= get_current_target(cmd_ctx
);
1009 armv4_5_common_t
*armv4_5
;
1010 arm7_9_common_t
*arm7_9
;
1011 arm9tdmi_common_t
*arm9tdmi
;
1012 arm920t_common_t
*arm920t
;
1013 arm_jtag_t
*jtag_info
;
1015 u32 cp15_ctrl
, cp15_ctrl_saved
;
1020 u32 Dlockdown
, Ilockdown
;
1021 arm920t_tlb_entry_t d_tlb
[64], i_tlb
[64];
1026 command_print(cmd_ctx
, "usage: arm920t read_mmu <filename>");
1030 if ((output
= fopen(args
[0], "w")) == NULL
)
1032 DEBUG("error opening mmu content file");
1036 for (i
= 0; i
< 16; i
++)
1037 regs_p
[i
] = ®s
[i
];
1039 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1041 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1045 jtag_info
= &arm7_9
->jtag_info
;
1047 /* disable MMU and Caches */
1048 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
1049 jtag_execute_queue();
1050 cp15_ctrl_saved
= cp15_ctrl
;
1051 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
1052 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
1054 /* read CP15 test state register */
1055 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
1056 jtag_execute_queue();
1058 /* prepare reading D TLB content
1061 /* set interpret mode */
1063 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1065 /* Read D TLB lockdown */
1066 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1068 /* clear interpret mode */
1070 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1072 /* read D TLB lockdown stored to r1 */
1073 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1074 jtag_execute_queue();
1075 Dlockdown
= regs
[1];
1077 for (victim
= 0; victim
< 64; victim
+= 8)
1079 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1080 * base remains unchanged, victim goes through entries 0 to 63 */
1081 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1082 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1084 /* set interpret mode */
1086 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1088 /* Write D TLB lockdown */
1089 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1091 /* Read D TLB CAM */
1092 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1094 /* clear interpret mode */
1096 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1098 /* read D TLB CAM content stored to r2-r9 */
1099 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1100 jtag_execute_queue();
1102 for (i
= 0; i
< 8; i
++)
1103 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1106 for (victim
= 0; victim
< 64; victim
++)
1108 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1109 * base remains unchanged, victim goes through entries 0 to 63 */
1110 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1111 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1113 /* set interpret mode */
1115 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1117 /* Write D TLB lockdown */
1118 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1120 /* Read D TLB RAM1 */
1121 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1123 /* Read D TLB RAM2 */
1124 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1126 /* clear interpret mode */
1128 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1130 /* read D TLB RAM content stored to r2 and r3 */
1131 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1132 jtag_execute_queue();
1134 d_tlb
[victim
].ram1
= regs
[2];
1135 d_tlb
[victim
].ram2
= regs
[3];
1138 /* restore D TLB lockdown */
1139 regs
[1] = Dlockdown
;
1140 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1142 /* Write D TLB lockdown */
1143 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1145 /* prepare reading I TLB content
1148 /* set interpret mode */
1150 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1152 /* Read I TLB lockdown */
1153 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1155 /* clear interpret mode */
1157 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1159 /* read I TLB lockdown stored to r1 */
1160 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1161 jtag_execute_queue();
1162 Ilockdown
= regs
[1];
1164 for (victim
= 0; victim
< 64; victim
+= 8)
1166 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1167 * base remains unchanged, victim goes through entries 0 to 63 */
1168 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1169 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1171 /* set interpret mode */
1173 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1175 /* Write I TLB lockdown */
1176 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1178 /* Read I TLB CAM */
1179 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1181 /* clear interpret mode */
1183 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1185 /* read I TLB CAM content stored to r2-r9 */
1186 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1187 jtag_execute_queue();
1189 for (i
= 0; i
< 8; i
++)
1190 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1193 for (victim
= 0; victim
< 64; victim
++)
1195 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1196 * base remains unchanged, victim goes through entries 0 to 63 */
1197 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1198 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1200 /* set interpret mode */
1202 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1204 /* Write I TLB lockdown */
1205 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1207 /* Read I TLB RAM1 */
1208 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1210 /* Read I TLB RAM2 */
1211 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1213 /* clear interpret mode */
1215 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1217 /* read I TLB RAM content stored to r2 and r3 */
1218 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1219 jtag_execute_queue();
1221 i_tlb
[victim
].ram1
= regs
[2];
1222 i_tlb
[victim
].ram2
= regs
[3];
1225 /* restore I TLB lockdown */
1226 regs
[1] = Ilockdown
;
1227 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1229 /* Write I TLB lockdown */
1230 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1232 /* restore CP15 MMU and Cache settings */
1233 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1235 /* output data to file */
1236 fprintf(output
, "D TLB content:\n");
1237 for (i
= 0; i
< 64; i
++)
1239 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
, (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1242 fprintf(output
, "\n\nI TLB content:\n");
1243 for (i
= 0; i
< 64; i
++)
1245 fprintf(output
, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
, (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1248 command_print(cmd_ctx
, "mmu content successfully output to %s", args
[0]);
1252 /* mark registers dirty */
1253 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1254 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
1255 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
1256 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
1257 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
1258 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
1259 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
1260 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1261 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1262 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1266 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1269 target_t
*target
= get_current_target(cmd_ctx
);
1270 armv4_5_common_t
*armv4_5
;
1271 arm7_9_common_t
*arm7_9
;
1272 arm9tdmi_common_t
*arm9tdmi
;
1273 arm920t_common_t
*arm920t
;
1274 arm_jtag_t
*jtag_info
;
1276 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1278 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1282 jtag_info
= &arm7_9
->jtag_info
;
1284 if (target
->state
!= TARGET_HALTED
)
1286 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1290 /* one or more argument, access a single register (write if second argument is given */
1293 int address
= strtoul(args
[0], NULL
, 0);
1298 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
1300 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1303 jtag_execute_queue();
1305 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1309 u32 value
= strtoul(args
[1], NULL
, 0);
1310 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
1312 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1315 command_print(cmd_ctx
, "%i: %8.8x", address
, value
);
1322 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1325 target_t
*target
= get_current_target(cmd_ctx
);
1326 armv4_5_common_t
*armv4_5
;
1327 arm7_9_common_t
*arm7_9
;
1328 arm9tdmi_common_t
*arm9tdmi
;
1329 arm920t_common_t
*arm920t
;
1330 arm_jtag_t
*jtag_info
;
1332 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1334 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1338 jtag_info
= &arm7_9
->jtag_info
;
1340 if (target
->state
!= TARGET_HALTED
)
1342 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1346 /* one or more argument, access a single register (write if second argument is given */
1349 u32 opcode
= strtoul(args
[0], NULL
, 0);
1354 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, 0x0, &value
)) != ERROR_OK
)
1356 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1360 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1364 u32 value
= strtoul(args
[1], NULL
, 0);
1365 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
1367 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1370 command_print(cmd_ctx
, "%8.8x: %8.8x", opcode
, value
);
1374 u32 value
= strtoul(args
[1], NULL
, 0);
1375 u32 address
= strtoul(args
[2], NULL
, 0);
1376 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
1378 command_print(cmd_ctx
, "couldn't execute %8.8x", opcode
);
1381 command_print(cmd_ctx
, "%8.8x: %8.8x %8.8x", opcode
, value
, address
);
1386 command_print(cmd_ctx
, "usage: arm920t cp15i <opcode> [value] [address]");
1392 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1394 target_t
*target
= get_current_target(cmd_ctx
);
1395 armv4_5_common_t
*armv4_5
;
1396 arm7_9_common_t
*arm7_9
;
1397 arm9tdmi_common_t
*arm9tdmi
;
1398 arm920t_common_t
*arm920t
;
1400 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1402 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1406 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1409 int arm920t_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1411 target_t
*target
= get_current_target(cmd_ctx
);
1412 armv4_5_common_t
*armv4_5
;
1413 arm7_9_common_t
*arm7_9
;
1414 arm9tdmi_common_t
*arm9tdmi
;
1415 arm920t_common_t
*arm920t
;
1416 arm_jtag_t
*jtag_info
;
1418 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1420 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1424 jtag_info
= &arm7_9
->jtag_info
;
1426 if (target
->state
!= TARGET_HALTED
)
1428 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1432 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1435 int arm920t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1437 target_t
*target
= get_current_target(cmd_ctx
);
1438 armv4_5_common_t
*armv4_5
;
1439 arm7_9_common_t
*arm7_9
;
1440 arm9tdmi_common_t
*arm9tdmi
;
1441 arm920t_common_t
*arm920t
;
1442 arm_jtag_t
*jtag_info
;
1444 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1446 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1450 jtag_info
= &arm7_9
->jtag_info
;
1452 if (target
->state
!= TARGET_HALTED
)
1454 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1458 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1461 int arm920t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1463 target_t
*target
= get_current_target(cmd_ctx
);
1464 armv4_5_common_t
*armv4_5
;
1465 arm7_9_common_t
*arm7_9
;
1466 arm9tdmi_common_t
*arm9tdmi
;
1467 arm920t_common_t
*arm920t
;
1468 arm_jtag_t
*jtag_info
;
1470 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1472 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1476 jtag_info
= &arm7_9
->jtag_info
;
1478 if (target
->state
!= TARGET_HALTED
)
1480 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1484 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
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then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)