737cbae5559c04491c8c17c85cb3582d64861734
[openocd.git] / src / target / arm7_9_common.h
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2007,2008 √ėyvind Harboe *
6 * oyvind.harboe@zylin.com *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2008 by Hongtao Zheng *
12 * hontor@126.com *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
28 ***************************************************************************/
29
30 #ifndef ARM7_9_COMMON_H
31 #define ARM7_9_COMMON_H
32
33 #include "arm.h"
34 #include "arm_jtag.h"
35
36 #define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
37
38 /**
39 * Structure for items that are common between both ARM7 and ARM9 targets.
40 */
41 struct arm7_9_common {
42 struct arm arm;
43 uint32_t common_magic;
44
45 struct arm_jtag jtag_info; /**< JTAG information for target */
46 struct reg_cache *eice_cache; /**< Embedded ICE register cache */
47
48 uint32_t arm_bkpt; /**< ARM breakpoint instruction */
49 uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
50
51 int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
52 int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
53 int breakpoint_count; /**< Current number of set breakpoints */
54 int wp_available; /**< Current number of available watchpoint units */
55 int wp_available_max; /**< Maximum number of available watchpoint units */
56 int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
57 int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
58 int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
59 int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
60 bool use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
61 bool need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
62
63 bool has_single_step;
64 bool has_monitor_mode;
65 bool has_vector_catch; /**< Specifies if the target has a reset vector catch */
66
67 bool debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
68
69 bool fast_memory_access;
70 bool dcc_downloads;
71
72 struct working_area *dcc_working_area;
73
74 int (*examine_debug_reason)(struct target *target);
75 /**< Function for determining why debug state was entered */
76
77 void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc);
78 /**< Function for changing from Thumb to ARM mode */
79
80 void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]);
81 /**< Function for reading the core registers */
82
83 void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask,
84 void *buffer, int size);
85 void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr);
86 /**< Function for reading CPSR or SPSR */
87
88 void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr);
89 /**< Function for writing to CPSR or SPSR */
90
91 void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr);
92 /**< Function for writing an immediate value to CPSR or SPSR */
93
94 void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]);
95
96 void (*load_word_regs)(struct target *target, uint32_t mask);
97 void (*load_hword_reg)(struct target *target, int num);
98 void (*load_byte_reg)(struct target *target, int num);
99
100 void (*store_word_regs)(struct target *target, uint32_t mask);
101 void (*store_hword_reg)(struct target *target, int num);
102 void (*store_byte_reg)(struct target *target, int num);
103
104 void (*write_pc)(struct target *target, uint32_t pc);
105 /**< Function for writing to the program counter */
106
107 void (*branch_resume)(struct target *target);
108 void (*branch_resume_thumb)(struct target *target);
109
110 void (*enable_single_step)(struct target *target, uint32_t next_pc);
111 void (*disable_single_step)(struct target *target);
112
113 void (*set_special_dbgrq)(struct target *target);
114 /**< Function for setting DBGRQ if the normal way won't work */
115
116 int (*post_debug_entry)(struct target *target);
117 /**< Callback function called after entering debug mode */
118
119 void (*pre_restore_context)(struct target *target);
120 /**< Callback function called before restoring the processor context */
121 };
122
123 static inline struct arm7_9_common *target_to_arm7_9(struct target *target)
124 {
125 return container_of(target->arch_info, struct arm7_9_common, arm);
126 }
127
128 static inline bool is_arm7_9(struct arm7_9_common *arm7_9)
129 {
130 return arm7_9->common_magic == ARM7_9_COMMON_MAGIC;
131 }
132
133 extern const struct command_registration arm7_9_command_handlers[];
134
135 int arm7_9_poll(struct target *target);
136
137 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer);
138
139 int arm7_9_assert_reset(struct target *target);
140 int arm7_9_deassert_reset(struct target *target);
141 int arm7_9_reset_request_halt(struct target *target);
142 int arm7_9_early_halt(struct target *target);
143 int arm7_9_soft_reset_halt(struct target *target);
144
145 int arm7_9_halt(struct target *target);
146 int arm7_9_resume(struct target *target, int current, uint32_t address,
147 int handle_breakpoints, int debug_execution);
148 int arm7_9_step(struct target *target, int current, uint32_t address,
149 int handle_breakpoints);
150 int arm7_9_read_memory(struct target *target, uint32_t address,
151 uint32_t size, uint32_t count, uint8_t *buffer);
152 int arm7_9_write_memory(struct target *target, uint32_t address,
153 uint32_t size, uint32_t count, const uint8_t *buffer);
154 int arm7_9_bulk_write_memory(struct target *target, uint32_t address,
155 uint32_t count, const uint8_t *buffer);
156
157 int arm7_9_run_algorithm(struct target *target, int num_mem_params,
158 struct mem_param *mem_params, int num_reg_prams,
159 struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
160
161 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
162 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
163 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
164 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
165
166 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc);
167 void arm7_9_disable_eice_step(struct target *target);
168
169 int arm7_9_execute_sys_speed(struct target *target);
170
171 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9);
172 int arm7_9_examine(struct target *target);
173 int arm7_9_check_reset(struct target *target);
174
175 int arm7_9_endianness_callback(jtag_callback_data_t pu8_in,
176 jtag_callback_data_t i_size, jtag_callback_data_t i_be,
177 jtag_callback_data_t i_flip);
178
179 #endif /* ARM7_9_COMMON_H */