a3ef8dea8b85dea94f46410604bf6434261ac464
[openocd.git] / src / target / arm7_9_common.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "embeddedice.h"
27 #include "target.h"
28 #include "armv4_5.h"
29 #include "arm_jtag.h"
30 #include "jtag.h"
31 #include "log.h"
32 #include "arm7_9_common.h"
33 #include "breakpoints.h"
34
35 #include <stdlib.h>
36 #include <string.h>
37 #include <unistd.h>
38
39 #include <sys/types.h>
40 #include <sys/stat.h>
41 #include <sys/time.h>
42 #include <errno.h>
43
44 int arm7_9_debug_entry(target_t *target);
45 int arm7_9_enable_sw_bkpts(struct target_s *target);
46
47 /* command handler forward declarations */
48 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58
59 int arm7_9_reinit_embeddedice(target_t *target)
60 {
61 armv4_5_common_t *armv4_5 = target->arch_info;
62 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
63
64 breakpoint_t *breakpoint = target->breakpoints;
65
66 arm7_9->wp_available = 2;
67 arm7_9->wp0_used = 0;
68 arm7_9->wp1_used = 0;
69
70 /* mark all hardware breakpoints as unset */
71 while (breakpoint)
72 {
73 if (breakpoint->type == BKPT_HARD)
74 {
75 breakpoint->set = 0;
76 }
77 breakpoint = breakpoint->next;
78 }
79
80 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
81 {
82 arm7_9->sw_bkpts_enabled = 0;
83 arm7_9_enable_sw_bkpts(target);
84 }
85
86 arm7_9->reinit_embeddedice = 0;
87
88 return ERROR_OK;
89 }
90
91 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
92 {
93 target_t *target = priv;
94 armv4_5_common_t *armv4_5 = target->arch_info;
95 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
96
97 /* a test-logic reset occured
98 * the EmbeddedICE registers have been reset
99 * hardware breakpoints have been cleared
100 */
101 if (event == JTAG_TRST_ASSERTED)
102 {
103 arm7_9->reinit_embeddedice = 1;
104 }
105
106 return ERROR_OK;
107 }
108
109 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
110 {
111 armv4_5_common_t *armv4_5 = target->arch_info;
112 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
113
114 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
115 {
116 return -1;
117 }
118
119 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
120 {
121 return -1;
122 }
123
124 *armv4_5_p = armv4_5;
125 *arm7_9_p = arm7_9;
126
127 return ERROR_OK;
128 }
129
130 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
131 {
132 armv4_5_common_t *armv4_5 = target->arch_info;
133 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
134
135 if (target->state != TARGET_HALTED)
136 {
137 WARNING("target not halted");
138 return ERROR_TARGET_NOT_HALTED;
139 }
140
141 if (arm7_9->force_hw_bkpts)
142 breakpoint->type = BKPT_HARD;
143
144 if (breakpoint->set)
145 {
146 WARNING("breakpoint already set");
147 return ERROR_OK;
148 }
149
150 if (breakpoint->type == BKPT_HARD)
151 {
152 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
153 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
154 if (!arm7_9->wp0_used)
155 {
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
161
162 jtag_execute_queue();
163 arm7_9->wp0_used = 1;
164 breakpoint->set = 1;
165 }
166 else if (!arm7_9->wp1_used)
167 {
168 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
172 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
173
174 jtag_execute_queue();
175 arm7_9->wp1_used = 1;
176 breakpoint->set = 2;
177 }
178 else
179 {
180 ERROR("BUG: no hardware comparator available");
181 return ERROR_OK;
182 }
183 }
184 else if (breakpoint->type == BKPT_SOFT)
185 {
186 if (breakpoint->length == 4)
187 {
188 /* keep the original instruction in target endianness */
189 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
190 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
191 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
192 }
193 else
194 {
195 /* keep the original instruction in target endianness */
196 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
197 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
198 target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt);
199 }
200 breakpoint->set = 1;
201 }
202
203 return ERROR_OK;
204
205 }
206
207 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
208 {
209 armv4_5_common_t *armv4_5 = target->arch_info;
210 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
211
212 if (target->state != TARGET_HALTED)
213 {
214 WARNING("target not halted");
215 return ERROR_TARGET_NOT_HALTED;
216 }
217
218 if (!breakpoint->set)
219 {
220 WARNING("breakpoint not set");
221 return ERROR_OK;
222 }
223
224 if (breakpoint->type == BKPT_HARD)
225 {
226 if (breakpoint->set == 1)
227 {
228 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
229 jtag_execute_queue();
230 arm7_9->wp0_used = 0;
231 }
232 else if (breakpoint->set == 2)
233 {
234 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
235 jtag_execute_queue();
236 arm7_9->wp1_used = 0;
237 }
238 breakpoint->set = 0;
239 }
240 else
241 {
242 /* restore original instruction (kept in target endianness) */
243 if (breakpoint->length == 4)
244 {
245 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
246 }
247 else
248 {
249 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
250 }
251 breakpoint->set = 0;
252 }
253
254 return ERROR_OK;
255 }
256
257 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
258 {
259 armv4_5_common_t *armv4_5 = target->arch_info;
260 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
261
262 if (target->state != TARGET_HALTED)
263 {
264 WARNING("target not halted");
265 return ERROR_TARGET_NOT_HALTED;
266 }
267
268 if (arm7_9->force_hw_bkpts)
269 {
270 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
271 breakpoint->type = BKPT_HARD;
272 }
273
274 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
275 {
276 INFO("sw breakpoint requested, but software breakpoints not enabled");
277 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
278 }
279
280 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
281 {
282 INFO("no watchpoint unit available for hardware breakpoint");
283 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
284 }
285
286 if ((breakpoint->length != 2) && (breakpoint->length != 4))
287 {
288 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
289 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
290 }
291
292 if (breakpoint->type == BKPT_HARD)
293 arm7_9->wp_available--;
294
295 return ERROR_OK;
296 }
297
298 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
299 {
300 armv4_5_common_t *armv4_5 = target->arch_info;
301 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
302
303 if (target->state != TARGET_HALTED)
304 {
305 WARNING("target not halted");
306 return ERROR_TARGET_NOT_HALTED;
307 }
308
309 if (breakpoint->set)
310 {
311 arm7_9_unset_breakpoint(target, breakpoint);
312 }
313
314 if (breakpoint->type == BKPT_HARD)
315 arm7_9->wp_available++;
316
317 return ERROR_OK;
318 }
319
320 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
321 {
322 armv4_5_common_t *armv4_5 = target->arch_info;
323 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
324 int rw_mask = 1;
325 u32 mask;
326
327 mask = watchpoint->length - 1;
328
329 if (target->state != TARGET_HALTED)
330 {
331 WARNING("target not halted");
332 return ERROR_TARGET_NOT_HALTED;
333 }
334
335 if (watchpoint->rw == WPT_ACCESS)
336 rw_mask = 0;
337 else
338 rw_mask = 1;
339
340 if (!arm7_9->wp0_used)
341 {
342 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
343 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
344 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
345 if( watchpoint->mask != 0xffffffffu )
346 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
347 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
348 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
349
350 jtag_execute_queue();
351 watchpoint->set = 1;
352 arm7_9->wp0_used = 2;
353 }
354 else if (!arm7_9->wp1_used)
355 {
356 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
357 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
359 if( watchpoint->mask != 0xffffffffu )
360 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
361 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
363
364 jtag_execute_queue();
365 watchpoint->set = 2;
366 arm7_9->wp1_used = 2;
367 }
368 else
369 {
370 ERROR("BUG: no hardware comparator available");
371 return ERROR_OK;
372 }
373
374 return ERROR_OK;
375 }
376
377 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
378 {
379 armv4_5_common_t *armv4_5 = target->arch_info;
380 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
381
382 if (target->state != TARGET_HALTED)
383 {
384 WARNING("target not halted");
385 return ERROR_TARGET_NOT_HALTED;
386 }
387
388 if (!watchpoint->set)
389 {
390 WARNING("breakpoint not set");
391 return ERROR_OK;
392 }
393
394 if (watchpoint->set == 1)
395 {
396 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
397 jtag_execute_queue();
398 arm7_9->wp0_used = 0;
399 }
400 else if (watchpoint->set == 2)
401 {
402 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
403 jtag_execute_queue();
404 arm7_9->wp1_used = 0;
405 }
406 watchpoint->set = 0;
407
408 return ERROR_OK;
409 }
410
411 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
412 {
413 armv4_5_common_t *armv4_5 = target->arch_info;
414 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
415
416 if (target->state != TARGET_HALTED)
417 {
418 WARNING("target not halted");
419 return ERROR_TARGET_NOT_HALTED;
420 }
421
422 if (arm7_9->wp_available < 1)
423 {
424 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
425 }
426
427 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
428 {
429 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
430 }
431
432 arm7_9->wp_available--;
433
434 return ERROR_OK;
435 }
436
437 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
438 {
439 armv4_5_common_t *armv4_5 = target->arch_info;
440 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
441
442 if (target->state != TARGET_HALTED)
443 {
444 WARNING("target not halted");
445 return ERROR_TARGET_NOT_HALTED;
446 }
447
448 if (watchpoint->set)
449 {
450 arm7_9_unset_watchpoint(target, watchpoint);
451 }
452
453 arm7_9->wp_available++;
454
455 return ERROR_OK;
456 }
457
458 int arm7_9_enable_sw_bkpts(struct target_s *target)
459 {
460 armv4_5_common_t *armv4_5 = target->arch_info;
461 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
462 int retval;
463
464 if (arm7_9->sw_bkpts_enabled)
465 return ERROR_OK;
466
467 if (arm7_9->wp_available < 1)
468 {
469 WARNING("can't enable sw breakpoints with no watchpoint unit available");
470 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
471 }
472 arm7_9->wp_available--;
473
474 if (!arm7_9->wp0_used)
475 {
476 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
477 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
478 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
479 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
480 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
481 arm7_9->sw_bkpts_enabled = 1;
482 arm7_9->wp0_used = 3;
483 }
484 else if (!arm7_9->wp1_used)
485 {
486 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
487 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
488 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
489 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
490 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
491 arm7_9->sw_bkpts_enabled = 2;
492 arm7_9->wp1_used = 3;
493 }
494 else
495 {
496 ERROR("BUG: both watchpoints used, but wp_available >= 1");
497 exit(-1);
498 }
499
500 if ((retval = jtag_execute_queue()) != ERROR_OK)
501 {
502 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
503 exit(-1);
504 };
505
506 return ERROR_OK;
507 }
508
509 int arm7_9_disable_sw_bkpts(struct target_s *target)
510 {
511 armv4_5_common_t *armv4_5 = target->arch_info;
512 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
513
514 if (!arm7_9->sw_bkpts_enabled)
515 return ERROR_OK;
516
517 if (arm7_9->sw_bkpts_enabled == 1)
518 {
519 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
520 arm7_9->sw_bkpts_enabled = 0;
521 arm7_9->wp0_used = 0;
522 arm7_9->wp_available++;
523 }
524 else if (arm7_9->sw_bkpts_enabled == 2)
525 {
526 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
527 arm7_9->sw_bkpts_enabled = 0;
528 arm7_9->wp1_used = 0;
529 arm7_9->wp_available++;
530 }
531
532 return ERROR_OK;
533 }
534
535 int arm7_9_execute_sys_speed(struct target_s *target)
536 {
537 int timeout;
538 int retval;
539
540 armv4_5_common_t *armv4_5 = target->arch_info;
541 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
542 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
543 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
544
545 /* set RESTART instruction */
546 jtag_add_end_state(TAP_RTI);
547 arm_jtag_set_instr(jtag_info, 0x4);
548
549 for (timeout=0; timeout<50; timeout++)
550 {
551 /* read debug status register */
552 embeddedice_read_reg(dbg_stat);
553 if ((retval = jtag_execute_queue()) != ERROR_OK)
554 return retval;
555 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
556 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
557 break;
558 usleep(100000);
559 }
560 if (timeout == 50)
561 {
562 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
563 return ERROR_TARGET_TIMEOUT;
564 }
565
566 return ERROR_OK;
567 }
568
569 int arm7_9_execute_fast_sys_speed(struct target_s *target)
570 {
571 u8 check_value[4], check_mask[4];
572
573 armv4_5_common_t *armv4_5 = target->arch_info;
574 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
575 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
576 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
577
578 /* set RESTART instruction */
579 jtag_add_end_state(TAP_RTI);
580 arm_jtag_set_instr(jtag_info, 0x4);
581
582 /* check for DBGACK and SYSCOMP set (others don't care) */
583 buf_set_u32(check_value, 0, 32, 0x9);
584 buf_set_u32(check_mask, 0, 32, 0x9);
585
586 /* read debug status register */
587 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
588
589 return ERROR_OK;
590 }
591
592 enum target_state arm7_9_poll(target_t *target)
593 {
594 int retval;
595 armv4_5_common_t *armv4_5 = target->arch_info;
596 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
597 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
598
599 if (arm7_9->reinit_embeddedice)
600 {
601 arm7_9_reinit_embeddedice(target);
602 }
603
604 /* read debug status register */
605 embeddedice_read_reg(dbg_stat);
606 if ((retval = jtag_execute_queue()) != ERROR_OK)
607 {
608 switch (retval)
609 {
610 case ERROR_JTAG_QUEUE_FAILED:
611 ERROR("JTAG queue failed while reading EmbeddedICE status register");
612 exit(-1);
613 break;
614 default:
615 break;
616 }
617 }
618
619 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
620 {
621 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
622 if ((target->state == TARGET_UNKNOWN))
623 {
624 WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
625 target->state = TARGET_RUNNING;
626 }
627 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
628 {
629 target->state = TARGET_HALTED;
630 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
631 return retval;
632
633 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
634 }
635 if (target->state == TARGET_DEBUG_RUNNING)
636 {
637 target->state = TARGET_HALTED;
638 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
639 return retval;
640
641 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
642 }
643 }
644 else
645 {
646 if (target->state != TARGET_DEBUG_RUNNING)
647 target->state = TARGET_RUNNING;
648 }
649
650 return target->state;
651 }
652
653 int arm7_9_assert_reset(target_t *target)
654 {
655 int retval;
656
657 DEBUG("target->state: %s", target_state_strings[target->state]);
658
659 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
660 {
661 /* if the target wasn't running, there might be working areas allocated */
662 target_free_all_working_areas(target);
663
664 /* assert SRST and TRST */
665 /* system would get ouf sync if we didn't reset test-logic, too */
666 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
667 {
668 if (retval == ERROR_JTAG_RESET_CANT_SRST)
669 {
670 WARNING("can't assert srst");
671 return retval;
672 }
673 else
674 {
675 ERROR("unknown error");
676 exit(-1);
677 }
678 }
679 jtag_add_sleep(5000);
680 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
681 {
682 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
683 {
684 WARNING("srst resets test logic, too");
685 retval = jtag_add_reset(1, 1);
686 }
687 }
688 }
689 else
690 {
691 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
692 {
693 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
694 {
695 WARNING("srst resets test logic, too");
696 retval = jtag_add_reset(1, 1);
697 }
698
699 if (retval == ERROR_JTAG_RESET_CANT_SRST)
700 {
701 WARNING("can't assert srst");
702 return retval;
703 }
704 else if (retval != ERROR_OK)
705 {
706 ERROR("unknown error");
707 exit(-1);
708 }
709 }
710 }
711
712 target->state = TARGET_RESET;
713 jtag_add_sleep(50000);
714
715 armv4_5_invalidate_core_regs(target);
716
717 return ERROR_OK;
718
719 }
720
721 int arm7_9_deassert_reset(target_t *target)
722 {
723 DEBUG("target->state: %s", target_state_strings[target->state]);
724
725 /* deassert reset lines */
726 jtag_add_reset(0, 0);
727
728 return ERROR_OK;
729
730 }
731
732 int arm7_9_clear_halt(target_t *target)
733 {
734 armv4_5_common_t *armv4_5 = target->arch_info;
735 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
736 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
737
738 if (arm7_9->use_dbgrq)
739 {
740 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
741 */
742 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
743 embeddedice_store_reg(dbg_ctrl);
744 }
745 else
746 {
747 /* restore registers if watchpoint unit 0 was in use
748 */
749 if (arm7_9->wp0_used)
750 {
751 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
752 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
753 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
754 }
755 /* control value always has to be restored, as it was either disabled,
756 * or enabled with possibly different bits
757 */
758 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
759 }
760
761 return ERROR_OK;
762 }
763
764 int arm7_9_soft_reset_halt(struct target_s *target)
765 {
766 armv4_5_common_t *armv4_5 = target->arch_info;
767 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
768 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
769 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
770 int i;
771
772 if (target->state == TARGET_RUNNING)
773 {
774 target->type->halt(target);
775 }
776
777 while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
778 {
779 embeddedice_read_reg(dbg_stat);
780 jtag_execute_queue();
781 }
782 target->state = TARGET_HALTED;
783
784 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
785 * ensure that DBGRQ is cleared
786 */
787 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
788 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
789 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
790 embeddedice_store_reg(dbg_ctrl);
791
792 arm7_9_clear_halt(target);
793
794 /* if the target is in Thumb state, change to ARM state */
795 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
796 {
797 u32 r0_thumb, pc_thumb;
798 DEBUG("target entered debug from Thumb state, changing to ARM");
799 /* Entered debug from Thumb mode */
800 armv4_5->core_state = ARMV4_5_STATE_THUMB;
801 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
802 }
803
804 /* all register content is now invalid */
805 armv4_5_invalidate_core_regs(target);
806
807 /* SVC, ARM state, IRQ and FIQ disabled */
808 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
809 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
810 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
811
812 /* start fetching from 0x0 */
813 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
814 armv4_5->core_cache->reg_list[15].dirty = 1;
815 armv4_5->core_cache->reg_list[15].valid = 1;
816
817 armv4_5->core_mode = ARMV4_5_MODE_SVC;
818 armv4_5->core_state = ARMV4_5_STATE_ARM;
819
820 /* reset registers */
821 for (i = 0; i <= 14; i++)
822 {
823 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
824 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
825 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
826 }
827
828 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
829
830 return ERROR_OK;
831 }
832
833 int arm7_9_halt(target_t *target)
834 {
835 armv4_5_common_t *armv4_5 = target->arch_info;
836 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
837 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
838
839 DEBUG("target->state: %s", target_state_strings[target->state]);
840
841 if (target->state == TARGET_HALTED)
842 {
843 WARNING("target was already halted");
844 return ERROR_TARGET_ALREADY_HALTED;
845 }
846
847 if (target->state == TARGET_UNKNOWN)
848 {
849 WARNING("target was in unknown state when halt was requested");
850 }
851
852 if ((target->state == TARGET_RESET) && (jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_srst))
853 {
854 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
855 return ERROR_TARGET_FAILURE;
856 }
857
858 if (arm7_9->use_dbgrq)
859 {
860 /* program EmbeddedICE Debug Control Register to assert DBGRQ
861 */
862 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
863 embeddedice_store_reg(dbg_ctrl);
864 }
865 else
866 {
867 /* program watchpoint unit to match on any address
868 */
869 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
870 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
871 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
872 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
873 }
874
875 target->debug_reason = DBG_REASON_DBGRQ;
876
877 return ERROR_OK;
878 }
879
880 int arm7_9_debug_entry(target_t *target)
881 {
882 int i;
883 u32 context[16];
884 u32* context_p[16];
885 u32 r0_thumb, pc_thumb;
886 u32 cpsr;
887 int retval;
888 /* get pointers to arch-specific information */
889 armv4_5_common_t *armv4_5 = target->arch_info;
890 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
891 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
892 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
893
894 #ifdef _DEBUG_ARM7_9_
895 DEBUG("");
896 #endif
897
898 if (arm7_9->pre_debug_entry)
899 arm7_9->pre_debug_entry(target);
900
901 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
902 * ensure that DBGRQ is cleared
903 */
904 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
905 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
906 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
907 embeddedice_store_reg(dbg_ctrl);
908
909 arm7_9_clear_halt(target);
910
911 if ((retval = jtag_execute_queue()) != ERROR_OK)
912 {
913 switch (retval)
914 {
915 case ERROR_JTAG_QUEUE_FAILED:
916 ERROR("JTAG queue failed while writing EmbeddedICE control register");
917 exit(-1);
918 break;
919 default:
920 break;
921 }
922 }
923
924 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
925 return retval;
926
927
928 if (target->state != TARGET_HALTED)
929 {
930 WARNING("target not halted");
931 return ERROR_TARGET_NOT_HALTED;
932 }
933
934 /* if the target is in Thumb state, change to ARM state */
935 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
936 {
937 DEBUG("target entered debug from Thumb state");
938 /* Entered debug from Thumb mode */
939 armv4_5->core_state = ARMV4_5_STATE_THUMB;
940 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
941 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
942 }
943 else
944 {
945 DEBUG("target entered debug from ARM state");
946 /* Entered debug from ARM mode */
947 armv4_5->core_state = ARMV4_5_STATE_ARM;
948 }
949
950 for (i = 0; i < 16; i++)
951 context_p[i] = &context[i];
952 /* save core registers (r0 - r15 of current core mode) */
953 arm7_9->read_core_regs(target, 0xffff, context_p);
954
955 arm7_9->read_xpsr(target, &cpsr, 0);
956
957 if ((retval = jtag_execute_queue()) != ERROR_OK)
958 return retval;
959
960 /* if the core has been executing in Thumb state, set the T bit */
961 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
962 cpsr |= 0x20;
963
964 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
965 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
966 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
967
968 armv4_5->core_mode = cpsr & 0x1f;
969
970 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
971 {
972 target->state = TARGET_UNKNOWN;
973 ERROR("cpsr contains invalid mode value - communication failure");
974 return ERROR_TARGET_FAILURE;
975 }
976
977 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
978
979 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
980 {
981 DEBUG("thumb state, applying fixups");
982 context[0] = r0_thumb;
983 context[15] = pc_thumb;
984 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
985 {
986 /* adjust value stored by STM */
987 context[15] -= 3 * 4;
988 }
989
990 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
991 || (target->debug_reason == DBG_REASON_SINGLESTEP)
992 || (target->debug_reason == DBG_REASON_WATCHPOINT)
993 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
994 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
995 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
996 else if (target->debug_reason == DBG_REASON_DBGRQ)
997 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
998 else
999 {
1000 ERROR("unknown debug reason: %i", target->debug_reason);
1001 }
1002
1003
1004 for (i=0; i<=15; i++)
1005 {
1006 DEBUG("r%i: 0x%8.8x", i, context[i]);
1007 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1008 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1009 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1010 }
1011
1012 DEBUG("entered debug state at PC 0x%x", context[15]);
1013
1014 /* exceptions other than USR & SYS have a saved program status register */
1015 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1016 {
1017 u32 spsr;
1018 arm7_9->read_xpsr(target, &spsr, 1);
1019 jtag_execute_queue();
1020 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1021 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1022 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1023 }
1024
1025 /* r0 and r15 (pc) have to be restored later */
1026 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1027 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
1028
1029 if ((retval = jtag->execute_queue()) != ERROR_OK)
1030 return retval;
1031
1032 if (arm7_9->post_debug_entry)
1033 arm7_9->post_debug_entry(target);
1034
1035 return ERROR_OK;
1036 }
1037
1038 int arm7_9_full_context(target_t *target)
1039 {
1040 int i;
1041 int retval;
1042 armv4_5_common_t *armv4_5 = target->arch_info;
1043 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1044
1045 DEBUG("");
1046
1047 if (target->state != TARGET_HALTED)
1048 {
1049 WARNING("target not halted");
1050 return ERROR_TARGET_NOT_HALTED;
1051 }
1052
1053 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1054 * SYS shares registers with User, so we don't touch SYS
1055 */
1056 for(i = 0; i < 6; i++)
1057 {
1058 u32 mask = 0;
1059 u32* reg_p[16];
1060 int j;
1061 int valid = 1;
1062
1063 /* check if there are invalid registers in the current mode
1064 */
1065 for (j = 0; j <= 16; j++)
1066 {
1067 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1068 valid = 0;
1069 }
1070
1071 if (!valid)
1072 {
1073 u32 tmp_cpsr;
1074
1075 /* change processor mode (and mask T bit) */
1076 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1077 tmp_cpsr |= armv4_5_number_to_mode(i);
1078 tmp_cpsr &= ~0x20;
1079 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1080
1081 for (j = 0; j < 15; j++)
1082 {
1083 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1084 {
1085 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1086 mask |= 1 << j;
1087 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1088 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1089 }
1090 }
1091
1092 /* if only the PSR is invalid, mask is all zeroes */
1093 if (mask)
1094 arm7_9->read_core_regs(target, mask, reg_p);
1095
1096 /* check if the PSR has to be read */
1097 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1098 {
1099 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1100 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1101 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1102 }
1103 }
1104 }
1105
1106 /* restore processor mode (mask T bit) */
1107 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1108
1109 if ((retval = jtag_execute_queue()) != ERROR_OK)
1110 {
1111 ERROR("JTAG failure");
1112 exit(-1);
1113 }
1114 return ERROR_OK;
1115 }
1116
1117 int arm7_9_restore_context(target_t *target)
1118 {
1119 armv4_5_common_t *armv4_5 = target->arch_info;
1120 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1121 reg_t *reg;
1122 armv4_5_core_reg_t *reg_arch_info;
1123 enum armv4_5_mode current_mode = armv4_5->core_mode;
1124 int i, j;
1125 int dirty;
1126 int mode_change;
1127
1128 DEBUG("");
1129
1130 if (target->state != TARGET_HALTED)
1131 {
1132 WARNING("target not halted");
1133 return ERROR_TARGET_NOT_HALTED;
1134 }
1135
1136 if (arm7_9->pre_restore_context)
1137 arm7_9->pre_restore_context(target);
1138
1139 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1140 * SYS shares registers with User, so we don't touch SYS
1141 */
1142 for (i = 0; i < 6; i++)
1143 {
1144 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1145 dirty = 0;
1146 mode_change = 0;
1147 /* check if there are dirty registers in the current mode
1148 */
1149 for (j = 0; j <= 16; j++)
1150 {
1151 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1152 reg_arch_info = reg->arch_info;
1153 if (reg->dirty == 1)
1154 {
1155 if (reg->valid == 1)
1156 {
1157 dirty = 1;
1158 DEBUG("examining dirty reg: %s", reg->name);
1159 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1160 && (reg_arch_info->mode != current_mode)
1161 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1162 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1163 {
1164 mode_change = 1;
1165 DEBUG("require mode change");
1166 }
1167 }
1168 else
1169 {
1170 ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1171 exit(-1);
1172 }
1173 }
1174 }
1175
1176 if (dirty)
1177 {
1178 u32 mask = 0x0;
1179 int num_regs = 0;
1180 u32 regs[16];
1181
1182 if (mode_change)
1183 {
1184 u32 tmp_cpsr;
1185
1186 /* change processor mode (mask T bit) */
1187 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1188 tmp_cpsr |= armv4_5_number_to_mode(i);
1189 tmp_cpsr &= ~0x20;
1190 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1191 current_mode = armv4_5_number_to_mode(i);
1192 }
1193
1194 for (j = 0; j <= 14; j++)
1195 {
1196 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1197 reg_arch_info = reg->arch_info;
1198
1199
1200 if (reg->dirty == 1)
1201 {
1202 regs[j] = buf_get_u32(reg->value, 0, 32);
1203 mask |= 1 << j;
1204 num_regs++;
1205 reg->dirty = 0;
1206 reg->valid = 1;
1207 DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1208 }
1209 }
1210
1211 if (mask)
1212 {
1213 arm7_9->write_core_regs(target, mask, regs);
1214 }
1215
1216 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1217 reg_arch_info = reg->arch_info;
1218 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1219 {
1220 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1221 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1222 }
1223 }
1224 }
1225
1226 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1227 {
1228 /* restore processor mode (mask T bit) */
1229 u32 tmp_cpsr;
1230
1231 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1232 tmp_cpsr |= armv4_5_number_to_mode(i);
1233 tmp_cpsr &= ~0x20;
1234 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1235 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1236 }
1237 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1238 {
1239 /* CPSR has been changed, full restore necessary (mask T bit) */
1240 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1241 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1242 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1243 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1244 }
1245
1246 /* restore PC */
1247 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1248 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1249 armv4_5->core_cache->reg_list[15].dirty = 0;
1250
1251 if (arm7_9->post_restore_context)
1252 arm7_9->post_restore_context(target);
1253
1254 return ERROR_OK;
1255 }
1256
1257 int arm7_9_restart_core(struct target_s *target)
1258 {
1259 armv4_5_common_t *armv4_5 = target->arch_info;
1260 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1261 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1262
1263 /* set RESTART instruction */
1264 jtag_add_end_state(TAP_RTI);
1265 arm_jtag_set_instr(jtag_info, 0x4);
1266
1267 jtag_add_runtest(1, TAP_RTI);
1268 if ((jtag_execute_queue()) != ERROR_OK)
1269 {
1270 exit(-1);
1271 }
1272
1273 return ERROR_OK;
1274 }
1275
1276 void arm7_9_enable_watchpoints(struct target_s *target)
1277 {
1278 watchpoint_t *watchpoint = target->watchpoints;
1279
1280 while (watchpoint)
1281 {
1282 if (watchpoint->set == 0)
1283 arm7_9_set_watchpoint(target, watchpoint);
1284 watchpoint = watchpoint->next;
1285 }
1286 }
1287
1288 void arm7_9_enable_breakpoints(struct target_s *target)
1289 {
1290 breakpoint_t *breakpoint = target->breakpoints;
1291
1292 /* set any pending breakpoints */
1293 while (breakpoint)
1294 {
1295 if (breakpoint->set == 0)
1296 arm7_9_set_breakpoint(target, breakpoint);
1297 breakpoint = breakpoint->next;
1298 }
1299 }
1300
1301 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1302 {
1303 breakpoint_t *breakpoint = target->breakpoints;
1304 watchpoint_t *watchpoint = target->watchpoints;
1305
1306 /* set any pending breakpoints */
1307 while (breakpoint)
1308 {
1309 if (breakpoint->set != 0)
1310 arm7_9_unset_breakpoint(target, breakpoint);
1311 breakpoint = breakpoint->next;
1312 }
1313
1314 while (watchpoint)
1315 {
1316 if (watchpoint->set != 0)
1317 arm7_9_unset_watchpoint(target, watchpoint);
1318 watchpoint = watchpoint->next;
1319 }
1320 }
1321
1322 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1323 {
1324 armv4_5_common_t *armv4_5 = target->arch_info;
1325 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1326 breakpoint_t *breakpoint = target->breakpoints;
1327 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1328
1329 DEBUG("");
1330
1331 if (target->state != TARGET_HALTED)
1332 {
1333 WARNING("target not halted");
1334 return ERROR_TARGET_NOT_HALTED;
1335 }
1336
1337 if (!debug_execution)
1338 {
1339 target_free_all_working_areas(target);
1340 }
1341
1342 /* current = 1: continue on current pc, otherwise continue at <address> */
1343 if (!current)
1344 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1345
1346 /* the front-end may request us not to handle breakpoints */
1347 if (handle_breakpoints)
1348 {
1349 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1350 {
1351 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1352 arm7_9_unset_breakpoint(target, breakpoint);
1353
1354 DEBUG("enable single-step");
1355 arm7_9->enable_single_step(target);
1356
1357 target->debug_reason = DBG_REASON_SINGLESTEP;
1358
1359 arm7_9_restore_context(target);
1360
1361 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1362 arm7_9->branch_resume(target);
1363 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1364 {
1365 arm7_9->branch_resume_thumb(target);
1366 }
1367 else
1368 {
1369 ERROR("unhandled core state");
1370 exit(-1);
1371 }
1372
1373 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1374 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1375 arm7_9_execute_sys_speed(target);
1376
1377 DEBUG("disable single-step");
1378 arm7_9->disable_single_step(target);
1379
1380 arm7_9_debug_entry(target);
1381 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1382
1383 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1384 arm7_9_set_breakpoint(target, breakpoint);
1385 }
1386 }
1387
1388 /* enable any pending breakpoints and watchpoints */
1389 arm7_9_enable_breakpoints(target);
1390 arm7_9_enable_watchpoints(target);
1391
1392 arm7_9_restore_context(target);
1393
1394 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1395 {
1396 arm7_9->branch_resume(target);
1397 }
1398 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1399 {
1400 arm7_9->branch_resume_thumb(target);
1401 }
1402 else
1403 {
1404 ERROR("unhandled core state");
1405 exit(-1);
1406 }
1407
1408 /* deassert DBGACK and INTDIS */
1409 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1410 /* INTDIS only when we really resume, not during debug execution */
1411 if (!debug_execution)
1412 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1413 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1414
1415 arm7_9_restart_core(target);
1416
1417 target->debug_reason = DBG_REASON_NOTHALTED;
1418
1419 if (!debug_execution)
1420 {
1421 /* registers are now invalid */
1422 armv4_5_invalidate_core_regs(target);
1423 target->state = TARGET_RUNNING;
1424 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1425 }
1426 else
1427 {
1428 target->state = TARGET_DEBUG_RUNNING;
1429 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1430 }
1431
1432 DEBUG("target resumed");
1433
1434 return ERROR_OK;
1435 }
1436
1437 void arm7_9_enable_eice_step(target_t *target)
1438 {
1439 armv4_5_common_t *armv4_5 = target->arch_info;
1440 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1441
1442 /* setup an inverse breakpoint on the current PC
1443 * - comparator 1 matches the current address
1444 * - rangeout from comparator 1 is connected to comparator 0 rangein
1445 * - comparator 0 matches any address, as long as rangein is low */
1446 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1447 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1448 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1449 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1450 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1451 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1452 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1453 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1454 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1455 }
1456
1457 void arm7_9_disable_eice_step(target_t *target)
1458 {
1459 armv4_5_common_t *armv4_5 = target->arch_info;
1460 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1461
1462 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1463 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1464 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1465 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1466 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1467 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1468 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1469 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1470 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1471 }
1472
1473 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1474 {
1475 armv4_5_common_t *armv4_5 = target->arch_info;
1476 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1477 breakpoint_t *breakpoint = NULL;
1478
1479 if (target->state != TARGET_HALTED)
1480 {
1481 WARNING("target not halted");
1482 return ERROR_TARGET_NOT_HALTED;
1483 }
1484
1485 /* current = 1: continue on current pc, otherwise continue at <address> */
1486 if (!current)
1487 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1488
1489 /* the front-end may request us not to handle breakpoints */
1490 if (handle_breakpoints)
1491 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1492 arm7_9_unset_breakpoint(target, breakpoint);
1493
1494 target->debug_reason = DBG_REASON_SINGLESTEP;
1495
1496 arm7_9_restore_context(target);
1497
1498 arm7_9->enable_single_step(target);
1499
1500 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1501 {
1502 arm7_9->branch_resume(target);
1503 }
1504 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1505 {
1506 arm7_9->branch_resume_thumb(target);
1507 }
1508 else
1509 {
1510 ERROR("unhandled core state");
1511 exit(-1);
1512 }
1513
1514 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1515
1516 arm7_9_execute_sys_speed(target);
1517 arm7_9->disable_single_step(target);
1518
1519 /* registers are now invalid */
1520 armv4_5_invalidate_core_regs(target);
1521
1522 arm7_9_debug_entry(target);
1523
1524 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1525
1526 if (breakpoint)
1527 arm7_9_set_breakpoint(target, breakpoint);
1528
1529 DEBUG("target stepped");
1530
1531 return ERROR_OK;
1532
1533 }
1534
1535 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1536 {
1537 u32* reg_p[16];
1538 u32 value;
1539 int retval;
1540 armv4_5_common_t *armv4_5 = target->arch_info;
1541 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1542 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1543
1544 if ((num < 0) || (num > 16))
1545 return ERROR_INVALID_ARGUMENTS;
1546
1547 if ((mode != ARMV4_5_MODE_ANY)
1548 && (mode != armv4_5->core_mode)
1549 && (reg_mode != ARMV4_5_MODE_ANY))
1550 {
1551 u32 tmp_cpsr;
1552
1553 /* change processor mode (mask T bit) */
1554 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1555 tmp_cpsr |= mode;
1556 tmp_cpsr &= ~0x20;
1557 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1558 }
1559
1560 if ((num >= 0) && (num <= 15))
1561 {
1562 /* read a normal core register */
1563 reg_p[num] = &value;
1564
1565 arm7_9->read_core_regs(target, 1 << num, reg_p);
1566 }
1567 else
1568 {
1569 /* read a program status register
1570 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1571 */
1572 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1573 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1574
1575 arm7_9->read_xpsr(target, &value, spsr);
1576 }
1577
1578 if ((retval = jtag_execute_queue()) != ERROR_OK)
1579 {
1580 ERROR("JTAG failure");
1581 exit(-1);
1582 }
1583
1584 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1585 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1586 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1587
1588 if ((mode != ARMV4_5_MODE_ANY)
1589 && (mode != armv4_5->core_mode)
1590 && (reg_mode != ARMV4_5_MODE_ANY)) {
1591 /* restore processor mode (mask T bit) */
1592 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1593 }
1594
1595 return ERROR_OK;
1596
1597 }
1598
1599 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1600 {
1601 u32 reg[16];
1602 int retval;
1603 armv4_5_common_t *armv4_5 = target->arch_info;
1604 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1605 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1606
1607 if ((num < 0) || (num > 16))
1608 return ERROR_INVALID_ARGUMENTS;
1609
1610 if ((mode != ARMV4_5_MODE_ANY)
1611 && (mode != armv4_5->core_mode)
1612 && (reg_mode != ARMV4_5_MODE_ANY)) {
1613 u32 tmp_cpsr;
1614
1615 /* change processor mode (mask T bit) */
1616 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1617 tmp_cpsr |= mode;
1618 tmp_cpsr &= ~0x20;
1619 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1620 }
1621
1622 if ((num >= 0) && (num <= 15))
1623 {
1624 /* write a normal core register */
1625 reg[num] = value;
1626
1627 arm7_9->write_core_regs(target, 1 << num, reg);
1628 }
1629 else
1630 {
1631 /* write a program status register
1632 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1633 */
1634 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1635 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1636
1637 /* if we're writing the CPSR, mask the T bit */
1638 if (!spsr)
1639 value &= ~0x20;
1640
1641 arm7_9->write_xpsr(target, value, spsr);
1642 }
1643
1644 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1645 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1646
1647 if ((mode != ARMV4_5_MODE_ANY)
1648 && (mode != armv4_5->core_mode)
1649 && (reg_mode != ARMV4_5_MODE_ANY)) {
1650 /* restore processor mode (mask T bit) */
1651 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1652 }
1653
1654 if ((retval = jtag_execute_queue()) != ERROR_OK)
1655 {
1656 ERROR("JTAG failure");
1657 exit(-1);
1658 }
1659
1660 return ERROR_OK;
1661
1662 }
1663
1664 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1665 {
1666 armv4_5_common_t *armv4_5 = target->arch_info;
1667 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1668
1669 u32 reg[16];
1670 int num_accesses = 0;
1671 int thisrun_accesses;
1672 int i;
1673 u32 cpsr;
1674 int retval;
1675 int last_reg = 0;
1676
1677 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1678
1679 if (target->state != TARGET_HALTED)
1680 {
1681 WARNING("target not halted");
1682 return ERROR_TARGET_NOT_HALTED;
1683 }
1684
1685 /* sanitize arguments */
1686 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1687 return ERROR_INVALID_ARGUMENTS;
1688
1689 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1690 return ERROR_TARGET_UNALIGNED_ACCESS;
1691
1692 /* load the base register with the address of the first word */
1693 reg[0] = address;
1694 arm7_9->write_core_regs(target, 0x1, reg);
1695
1696 switch (size)
1697 {
1698 case 4:
1699 while (num_accesses < count)
1700 {
1701 u32 reg_list;
1702 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1703 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1704
1705 if (last_reg <= thisrun_accesses)
1706 last_reg = thisrun_accesses;
1707
1708 arm7_9->load_word_regs(target, reg_list);
1709
1710 /* fast memory reads are only safe when the target is running
1711 * from a sufficiently high clock (32 kHz is usually too slow)
1712 */
1713 if (arm7_9->fast_memory_access)
1714 arm7_9_execute_fast_sys_speed(target);
1715 else
1716 arm7_9_execute_sys_speed(target);
1717
1718 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1719
1720 /* advance buffer, count number of accesses */
1721 buffer += thisrun_accesses * 4;
1722 num_accesses += thisrun_accesses;
1723 }
1724 break;
1725 case 2:
1726 while (num_accesses < count)
1727 {
1728 u32 reg_list;
1729 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1730 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1731
1732 for (i = 1; i <= thisrun_accesses; i++)
1733 {
1734 if (i > last_reg)
1735 last_reg = i;
1736 arm7_9->load_hword_reg(target, i);
1737 /* fast memory reads are only safe when the target is running
1738 * from a sufficiently high clock (32 kHz is usually too slow)
1739 */
1740 if (arm7_9->fast_memory_access)
1741 arm7_9_execute_fast_sys_speed(target);
1742 else
1743 arm7_9_execute_sys_speed(target);
1744 }
1745
1746 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1747
1748 /* advance buffer, count number of accesses */
1749 buffer += thisrun_accesses * 2;
1750 num_accesses += thisrun_accesses;
1751 }
1752 break;
1753 case 1:
1754 while (num_accesses < count)
1755 {
1756 u32 reg_list;
1757 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1758 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1759
1760 for (i = 1; i <= thisrun_accesses; i++)
1761 {
1762 if (i > last_reg)
1763 last_reg = i;
1764 arm7_9->load_byte_reg(target, i);
1765 /* fast memory reads are only safe when the target is running
1766 * from a sufficiently high clock (32 kHz is usually too slow)
1767 */
1768 if (arm7_9->fast_memory_access)
1769 arm7_9_execute_fast_sys_speed(target);
1770 else
1771 arm7_9_execute_sys_speed(target);
1772 }
1773
1774 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1775
1776 /* advance buffer, count number of accesses */
1777 buffer += thisrun_accesses * 1;
1778 num_accesses += thisrun_accesses;
1779 }
1780 break;
1781 default:
1782 ERROR("BUG: we shouldn't get here");
1783 exit(-1);
1784 break;
1785 }
1786
1787 for (i=0; i<=last_reg; i++)
1788 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1789
1790 arm7_9->read_xpsr(target, &cpsr, 0);
1791 if ((retval = jtag_execute_queue()) != ERROR_OK)
1792 {
1793 ERROR("JTAG error while reading cpsr");
1794 exit(-1);
1795 }
1796
1797 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1798 {
1799 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1800
1801 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1802
1803 return ERROR_TARGET_DATA_ABORT;
1804 }
1805
1806 return ERROR_OK;
1807 }
1808
1809 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1810 {
1811 armv4_5_common_t *armv4_5 = target->arch_info;
1812 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1813 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1814
1815 u32 reg[16];
1816 int num_accesses = 0;
1817 int thisrun_accesses;
1818 int i;
1819 u32 cpsr;
1820 int retval;
1821 int last_reg = 0;
1822
1823 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1824
1825 if (target->state != TARGET_HALTED)
1826 {
1827 WARNING("target not halted");
1828 return ERROR_TARGET_NOT_HALTED;
1829 }
1830
1831 /* sanitize arguments */
1832 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1833 return ERROR_INVALID_ARGUMENTS;
1834
1835 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1836 return ERROR_TARGET_UNALIGNED_ACCESS;
1837
1838 /* load the base register with the address of the first word */
1839 reg[0] = address;
1840 arm7_9->write_core_regs(target, 0x1, reg);
1841
1842 /* Clear DBGACK, to make sure memory fetches work as expected */
1843 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1844 embeddedice_store_reg(dbg_ctrl);
1845
1846 switch (size)
1847 {
1848 case 4:
1849 while (num_accesses < count)
1850 {
1851 u32 reg_list;
1852 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1853 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1854
1855 for (i = 1; i <= thisrun_accesses; i++)
1856 {
1857 if (i > last_reg)
1858 last_reg = i;
1859 reg[i] = target_buffer_get_u32(target, buffer);
1860 buffer += 4;
1861 }
1862
1863 arm7_9->write_core_regs(target, reg_list, reg);
1864
1865 arm7_9->store_word_regs(target, reg_list);
1866
1867 /* fast memory writes are only safe when the target is running
1868 * from a sufficiently high clock (32 kHz is usually too slow)
1869 */
1870 if (arm7_9->fast_memory_access)
1871 arm7_9_execute_fast_sys_speed(target);
1872 else
1873 arm7_9_execute_sys_speed(target);
1874
1875 num_accesses += thisrun_accesses;
1876 }
1877 break;
1878 case 2:
1879 while (num_accesses < count)
1880 {
1881 u32 reg_list;
1882 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1883 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1884
1885 for (i = 1; i <= thisrun_accesses; i++)
1886 {
1887 if (i > last_reg)
1888 last_reg = i;
1889 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1890 buffer += 2;
1891 }
1892
1893 arm7_9->write_core_regs(target, reg_list, reg);
1894
1895 for (i = 1; i <= thisrun_accesses; i++)
1896 {
1897 arm7_9->store_hword_reg(target, i);
1898
1899 /* fast memory writes are only safe when the target is running
1900 * from a sufficiently high clock (32 kHz is usually too slow)
1901 */
1902 if (arm7_9->fast_memory_access)
1903 arm7_9_execute_fast_sys_speed(target);
1904 else
1905 arm7_9_execute_sys_speed(target);
1906 }
1907
1908 num_accesses += thisrun_accesses;
1909 }
1910 break;
1911 case 1:
1912 while (num_accesses < count)
1913 {
1914 u32 reg_list;
1915 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1916 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1917
1918 for (i = 1; i <= thisrun_accesses; i++)
1919 {
1920 if (i > last_reg)
1921 last_reg = i;
1922 reg[i] = *buffer++ & 0xff;
1923 }
1924
1925 arm7_9->write_core_regs(target, reg_list, reg);
1926
1927 for (i = 1; i <= thisrun_accesses; i++)
1928 {
1929 arm7_9->store_byte_reg(target, i);
1930 /* fast memory writes are only safe when the target is running
1931 * from a sufficiently high clock (32 kHz is usually too slow)
1932 */
1933 if (arm7_9->fast_memory_access)
1934 arm7_9_execute_fast_sys_speed(target);
1935 else
1936 arm7_9_execute_sys_speed(target);
1937 }
1938
1939 num_accesses += thisrun_accesses;
1940 }
1941 break;
1942 default:
1943 ERROR("BUG: we shouldn't get here");
1944 exit(-1);
1945 break;
1946 }
1947
1948 /* Re-Set DBGACK */
1949 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1950 embeddedice_store_reg(dbg_ctrl);
1951
1952 for (i=0; i<=last_reg; i++)
1953 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1954
1955 arm7_9->read_xpsr(target, &cpsr, 0);
1956 if ((retval = jtag_execute_queue()) != ERROR_OK)
1957 {
1958 ERROR("JTAG error while reading cpsr");
1959 exit(-1);
1960 }
1961
1962 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1963 {
1964 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1965
1966 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1967
1968 return ERROR_TARGET_DATA_ABORT;
1969 }
1970
1971 return ERROR_OK;
1972 }
1973
1974 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
1975 {
1976 armv4_5_common_t *armv4_5 = target->arch_info;
1977 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1978 enum armv4_5_state core_state = armv4_5->core_state;
1979 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
1980 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
1981 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1982 int i;
1983
1984 u32 dcc_code[] =
1985 {
1986 /* MRC TST BNE MRC STR B */
1987 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1988 };
1989
1990 if (!arm7_9->dcc_downloads)
1991 return target->type->write_memory(target, address, 4, count, buffer);
1992
1993 /* regrab previously allocated working_area, or allocate a new one */
1994 if (!arm7_9->dcc_working_area)
1995 {
1996 u8 dcc_code_buf[6 * 4];
1997
1998 /* make sure we have a working area */
1999 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2000 {
2001 INFO("no working area available, falling back to memory writes");
2002 return target->type->write_memory(target, address, 4, count, buffer);
2003 }
2004
2005 /* copy target instructions to target endianness */
2006 for (i = 0; i < 6; i++)
2007 {
2008 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2009 }
2010
2011 /* write DCC code to working area */
2012 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2013 }
2014
2015 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2016 armv4_5->core_cache->reg_list[0].valid = 1;
2017 armv4_5->core_cache->reg_list[0].dirty = 1;
2018 armv4_5->core_state = ARMV4_5_STATE_ARM;
2019
2020 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2021
2022 for (i = 0; i < count; i++)
2023 {
2024 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
2025 buffer += 4;
2026 }
2027
2028 target->type->halt(target);
2029
2030 while (target->state != TARGET_HALTED)
2031 target->type->poll(target);
2032
2033 /* restore target state */
2034 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2035 armv4_5->core_cache->reg_list[0].valid = 1;
2036 armv4_5->core_cache->reg_list[0].dirty = 1;
2037 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2038 armv4_5->core_cache->reg_list[1].valid = 1;
2039 armv4_5->core_cache->reg_list[1].dirty = 1;
2040 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2041 armv4_5->core_cache->reg_list[15].valid = 1;
2042 armv4_5->core_cache->reg_list[15].dirty = 1;
2043 armv4_5->core_state = core_state;
2044
2045 return ERROR_OK;
2046 }
2047
2048 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2049 {
2050 command_t *arm7_9_cmd;
2051
2052 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2053
2054 register_command(cmd_ctx, arm7_9_cmd, "etm", handle_arm7_9_etm_command, COMMAND_CONFIG, NULL);
2055
2056 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2057 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2058
2059 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2060
2061 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2062 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2063 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2064 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2065 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2066 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2067 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2068 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2069 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2070 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2071
2072 armv4_5_register_commands(cmd_ctx);
2073
2074 return ERROR_OK;
2075 }
2076
2077 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2078 {
2079 u32 value;
2080 int spsr;
2081 int retval;
2082 target_t *target = get_current_target(cmd_ctx);
2083 armv4_5_common_t *armv4_5;
2084 arm7_9_common_t *arm7_9;
2085
2086 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2087 {
2088 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2089 return ERROR_OK;
2090 }
2091
2092 if (target->state != TARGET_HALTED)
2093 {
2094 command_print(cmd_ctx, "can't write registers while running");
2095 return ERROR_OK;
2096 }
2097
2098 if (argc < 2)
2099 {
2100 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2101 return ERROR_OK;
2102 }
2103
2104 value = strtoul(args[0], NULL, 0);
2105 spsr = strtol(args[1], NULL, 0);
2106
2107 /* if we're writing the CPSR, mask the T bit */
2108 if (!spsr)
2109 value &= ~0x20;
2110
2111 arm7_9->write_xpsr(target, value, spsr);
2112 if ((retval = jtag_execute_queue()) != ERROR_OK)
2113 {
2114 ERROR("JTAG error while writing to xpsr");
2115 exit(-1);
2116 }
2117
2118 return ERROR_OK;
2119 }
2120
2121 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2122 {
2123 u32 value;
2124 int rotate;
2125 int spsr;
2126 int retval;
2127 target_t *target = get_current_target(cmd_ctx);
2128 armv4_5_common_t *armv4_5;
2129 arm7_9_common_t *arm7_9;
2130
2131 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2132 {
2133 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2134 return ERROR_OK;
2135 }
2136
2137 if (target->state != TARGET_HALTED)
2138 {
2139 command_print(cmd_ctx, "can't write registers while running");
2140 return ERROR_OK;
2141 }
2142
2143 if (argc < 3)
2144 {
2145 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2146 return ERROR_OK;
2147 }
2148
2149 value = strtoul(args[0], NULL, 0);
2150 rotate = strtol(args[1], NULL, 0);
2151 spsr = strtol(args[2], NULL, 0);
2152
2153 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2154 if ((retval = jtag_execute_queue()) != ERROR_OK)
2155 {
2156 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2157 exit(-1);
2158 }
2159
2160 return ERROR_OK;
2161 }
2162
2163 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2164 {
2165 u32 value;
2166 u32 mode;
2167 int num;
2168 target_t *target = get_current_target(cmd_ctx);
2169 armv4_5_common_t *armv4_5;
2170 arm7_9_common_t *arm7_9;
2171
2172 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2173 {
2174 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2175 return ERROR_OK;
2176 }
2177
2178 if (target->state != TARGET_HALTED)
2179 {
2180 command_print(cmd_ctx, "can't write registers while running");
2181 return ERROR_OK;
2182 }
2183
2184 if (argc < 3)
2185 {
2186 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2187 return ERROR_OK;
2188 }
2189
2190 num = strtol(args[0], NULL, 0);
2191 mode = strtoul(args[1], NULL, 0);
2192 value = strtoul(args[2], NULL, 0);
2193
2194 arm7_9_write_core_reg(target, num, mode, value);
2195
2196 return ERROR_OK;
2197 }
2198
2199 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2200 {
2201 target_t *target = get_current_target(cmd_ctx);
2202 armv4_5_common_t *armv4_5;
2203 arm7_9_common_t *arm7_9;
2204
2205 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2206 {
2207 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2208 return ERROR_OK;
2209 }
2210
2211 if (argc == 0)
2212 {
2213 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2214 return ERROR_OK;
2215 }
2216
2217 if (strcmp("enable", args[0]) == 0)
2218 {
2219 if (arm7_9->sw_bkpts_use_wp)
2220 {
2221 arm7_9_enable_sw_bkpts(target);
2222 }
2223 else
2224 {
2225 arm7_9->sw_bkpts_enabled = 1;
2226 }
2227 }
2228 else if (strcmp("disable", args[0]) == 0)
2229 {
2230 if (arm7_9->sw_bkpts_use_wp)
2231 {
2232 arm7_9_disable_sw_bkpts(target);
2233 }
2234 else
2235 {
2236 arm7_9->sw_bkpts_enabled = 0;
2237 }
2238 }
2239 else
2240 {
2241 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2242 }
2243
2244 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2245
2246 return ERROR_OK;
2247 }
2248
2249 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2250 {
2251 target_t *target = get_current_target(cmd_ctx);
2252 armv4_5_common_t *armv4_5;
2253 arm7_9_common_t *arm7_9;
2254
2255 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2256 {
2257 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2258 return ERROR_OK;
2259 }
2260
2261 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2262 {
2263 arm7_9->force_hw_bkpts = 1;
2264 if (arm7_9->sw_bkpts_use_wp)
2265 {
2266 arm7_9_disable_sw_bkpts(target);
2267 }
2268 }
2269 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2270 {
2271 arm7_9->force_hw_bkpts = 0;
2272 }
2273 else
2274 {
2275 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2276 }
2277
2278 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2279
2280 return ERROR_OK;
2281 }
2282
2283 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2284 {
2285 target_t *target = get_current_target(cmd_ctx);
2286 armv4_5_common_t *armv4_5;
2287 arm7_9_common_t *arm7_9;
2288
2289 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2290 {
2291 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2292 return ERROR_OK;
2293 }
2294
2295 if (argc > 0)
2296 {
2297 if (strcmp("enable", args[0]) == 0)
2298 {
2299 arm7_9->use_dbgrq = 1;
2300 }
2301 else if (strcmp("disable", args[0]) == 0)
2302 {
2303 arm7_9->use_dbgrq = 0;
2304 }
2305 else
2306 {
2307 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2308 }
2309 }
2310
2311 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2312
2313 return ERROR_OK;
2314 }
2315
2316 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2317 {
2318 target_t *target = get_current_target(cmd_ctx);
2319 armv4_5_common_t *armv4_5;
2320 arm7_9_common_t *arm7_9;
2321
2322 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2323 {
2324 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2325 return ERROR_OK;
2326 }
2327
2328 if (argc > 0)
2329 {
2330 if (strcmp("enable", args[0]) == 0)
2331 {
2332 arm7_9->fast_memory_access = 1;
2333 }
2334 else if (strcmp("disable", args[0]) == 0)
2335 {
2336 arm7_9->fast_memory_access = 0;
2337 }
2338 else
2339 {
2340 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2341 }
2342 }
2343
2344 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2345
2346 return ERROR_OK;
2347 }
2348
2349 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2350 {
2351 target_t *target = get_current_target(cmd_ctx);
2352 armv4_5_common_t *armv4_5;
2353 arm7_9_common_t *arm7_9;
2354
2355 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2356 {
2357 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2358 return ERROR_OK;
2359 }
2360
2361 if (argc > 0)
2362 {
2363 if (strcmp("enable", args[0]) == 0)
2364 {
2365 arm7_9->dcc_downloads = 1;
2366 }
2367 else if (strcmp("disable", args[0]) == 0)
2368 {
2369 arm7_9->dcc_downloads = 0;
2370 }
2371 else
2372 {
2373 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2374 }
2375 }
2376
2377 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2378
2379 return ERROR_OK;
2380 }
2381
2382 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2383 {
2384 target_t *target;
2385 armv4_5_common_t *armv4_5;
2386 arm7_9_common_t *arm7_9;
2387
2388 if (argc != 1)
2389 {
2390 ERROR("incomplete 'arm7_9 etm <target>' command");
2391 exit(-1);
2392 }
2393
2394 target = get_target_by_num(strtoul(args[0], NULL, 0));
2395
2396 if (!target)
2397 {
2398 ERROR("target number '%s' not defined", args[0]);
2399 exit(-1);
2400 }
2401
2402 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2403 {
2404 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2405 return ERROR_OK;
2406 }
2407
2408 arm7_9->has_etm = 1;
2409
2410 return ERROR_OK;
2411 }
2412
2413 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2414 {
2415 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2416
2417 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2418
2419 arm_jtag_setup_connection(&arm7_9->jtag_info);
2420 arm7_9->wp_available = 2;
2421 arm7_9->wp0_used = 0;
2422 arm7_9->wp1_used = 0;
2423 arm7_9->force_hw_bkpts = 0;
2424 arm7_9->use_dbgrq = 0;
2425
2426 arm7_9->has_etm = 0;
2427 arm7_9->has_single_step = 0;
2428 arm7_9->has_monitor_mode = 0;
2429 arm7_9->has_vector_catch = 0;
2430
2431 arm7_9->reinit_embeddedice = 0;
2432
2433 arm7_9->dcc_working_area = NULL;
2434
2435 arm7_9->fast_memory_access = 0;
2436 arm7_9->dcc_downloads = 0;
2437
2438 jtag_register_event_callback(arm7_9_jtag_callback, target);
2439
2440 armv4_5->arch_info = arm7_9;
2441 armv4_5->read_core_reg = arm7_9_read_core_reg;
2442 armv4_5->write_core_reg = arm7_9_write_core_reg;
2443 armv4_5->full_context = arm7_9_full_context;
2444
2445 armv4_5_init_arch_info(target, armv4_5);
2446
2447 return ERROR_OK;
2448 }