1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
26 #include <target/armv4_5.h>
27 #include <target/arm_dpm.h>
29 #define ARM11_TAP_DEFAULT TAP_INVALID
31 #define CHECK_RETVAL(action) \
33 int __retval = (action); \
34 if (__retval != ERROR_OK) { \
35 LOG_DEBUG("error while calling \"%s\"", \
41 enum arm11_debug_version
43 ARM11_DEBUG_V6
= 0x01,
44 ARM11_DEBUG_V61
= 0x02,
45 ARM11_DEBUG_V7
= 0x03,
46 ARM11_DEBUG_V7_CP14
= 0x04,
53 /** Debug module state. */
56 size_t brp
; /**< Number of Breakpoint Register Pairs from DIDR */
57 size_t wrp
; /**< Number of Watchpoint Register Pairs from DIDR */
58 size_t free_brps
; /**< Number of breakpoints allocated */
60 uint32_t dscr
; /**< Last retrieved DSCR value. */
68 bool simulate_reset_on_next_halt
; /**< Perform cleanups of the ARM state on next halt */
70 struct arm_jtag jtag_info
;
73 static inline struct arm11_common
*target_to_arm11(struct target
*target
)
75 return container_of(target
->arch_info
, struct arm11_common
,
80 * ARM11 DBGTAP instructions
82 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
84 enum arm11_instructions
98 ARM11_DSCR_CORE_HALTED
= 1 << 0,
99 ARM11_DSCR_CORE_RESTARTED
= 1 << 1,
101 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK
= 0x0F << 2,
102 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT
= 0x00 << 2,
103 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT
= 0x01 << 2,
104 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT
= 0x02 << 2,
105 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION
= 0x03 << 2,
106 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ
= 0x04 << 2,
107 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH
= 0x05 << 2,
109 ARM11_DSCR_STICKY_PRECISE_DATA_ABORT
= 1 << 6,
110 ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
= 1 << 7,
111 ARM11_DSCR_INTERRUPTS_DISABLE
= 1 << 11,
112 ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
= 1 << 13,
113 ARM11_DSCR_MODE_SELECT
= 1 << 14,
114 ARM11_DSCR_WDTR_FULL
= 1 << 29,
115 ARM11_DSCR_RDTR_FULL
= 1 << 30,
120 ARM11_CPSR_T
= 1 << 5,
121 ARM11_CPSR_J
= 1 << 24,
132 ARM11_SC7_WCR0
= 112,
135 struct arm11_reg_state
138 struct target
* target
;
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