1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
30 #include "breakpoints.h"
31 #include "arm11_dbgtap.h"
33 #include "arm_simulator.h"
34 #include "time_support.h"
35 #include "target_type.h"
39 #define _DEBUG_INSTRUCTION_EXECUTION_
43 #define FNC_INFO LOG_DEBUG("-")
49 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
51 #define FNC_INFO_NOTIMPLEMENTED
54 static bool arm11_config_memwrite_burst
= true;
55 static bool arm11_config_memwrite_error_fatal
= true;
56 static uint32_t arm11_vcr
= 0;
57 static bool arm11_config_step_irq_enable
= false;
58 static bool arm11_config_hardware_step
= false;
60 static int arm11_regs_arch_type
= -1;
77 ARM11_REGISTER_SPSR_FIQ
,
78 ARM11_REGISTER_SPSR_SVC
,
79 ARM11_REGISTER_SPSR_ABT
,
80 ARM11_REGISTER_SPSR_IRQ
,
81 ARM11_REGISTER_SPSR_UND
,
82 ARM11_REGISTER_SPSR_MON
,
96 enum arm11_regtype type
;
99 /* update arm11_regcache_ids when changing this */
100 static const struct arm11_reg_defs arm11_reg_defs
[] =
102 {"r0", 0, 0, ARM11_REGISTER_CORE
},
103 {"r1", 1, 1, ARM11_REGISTER_CORE
},
104 {"r2", 2, 2, ARM11_REGISTER_CORE
},
105 {"r3", 3, 3, ARM11_REGISTER_CORE
},
106 {"r4", 4, 4, ARM11_REGISTER_CORE
},
107 {"r5", 5, 5, ARM11_REGISTER_CORE
},
108 {"r6", 6, 6, ARM11_REGISTER_CORE
},
109 {"r7", 7, 7, ARM11_REGISTER_CORE
},
110 {"r8", 8, 8, ARM11_REGISTER_CORE
},
111 {"r9", 9, 9, ARM11_REGISTER_CORE
},
112 {"r10", 10, 10, ARM11_REGISTER_CORE
},
113 {"r11", 11, 11, ARM11_REGISTER_CORE
},
114 {"r12", 12, 12, ARM11_REGISTER_CORE
},
115 {"sp", 13, 13, ARM11_REGISTER_CORE
},
116 {"lr", 14, 14, ARM11_REGISTER_CORE
},
117 {"pc", 15, 15, ARM11_REGISTER_CORE
},
119 #if ARM11_REGCACHE_FREGS
120 {"f0", 0, 16, ARM11_REGISTER_FX
},
121 {"f1", 1, 17, ARM11_REGISTER_FX
},
122 {"f2", 2, 18, ARM11_REGISTER_FX
},
123 {"f3", 3, 19, ARM11_REGISTER_FX
},
124 {"f4", 4, 20, ARM11_REGISTER_FX
},
125 {"f5", 5, 21, ARM11_REGISTER_FX
},
126 {"f6", 6, 22, ARM11_REGISTER_FX
},
127 {"f7", 7, 23, ARM11_REGISTER_FX
},
128 {"fps", 0, 24, ARM11_REGISTER_FPS
},
131 {"cpsr", 0, 25, ARM11_REGISTER_CPSR
},
133 #if ARM11_REGCACHE_MODEREGS
134 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ
},
135 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ
},
136 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ
},
137 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ
},
138 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ
},
139 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ
},
140 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ
},
141 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ
},
143 {"r13_svc", 13, -1, ARM11_REGISTER_SVC
},
144 {"r14_svc", 14, -1, ARM11_REGISTER_SVC
},
145 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC
},
147 {"r13_abt", 13, -1, ARM11_REGISTER_ABT
},
148 {"r14_abt", 14, -1, ARM11_REGISTER_ABT
},
149 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT
},
151 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ
},
152 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ
},
153 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ
},
155 {"r13_und", 13, -1, ARM11_REGISTER_UND
},
156 {"r14_und", 14, -1, ARM11_REGISTER_UND
},
157 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND
},
160 {"r13_mon", 13, -1, ARM11_REGISTER_MON
},
161 {"r14_mon", 14, -1, ARM11_REGISTER_MON
},
162 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON
},
165 /* Debug Registers */
166 {"dscr", 0, -1, ARM11_REGISTER_DSCR
},
167 {"wdtr", 0, -1, ARM11_REGISTER_WDTR
},
168 {"rdtr", 0, -1, ARM11_REGISTER_RDTR
},
171 enum arm11_regcache_ids
174 ARM11_RC_RX
= ARM11_RC_R0
,
189 ARM11_RC_SP
= ARM11_RC_R13
,
191 ARM11_RC_LR
= ARM11_RC_R14
,
193 ARM11_RC_PC
= ARM11_RC_R15
,
195 #if ARM11_REGCACHE_FREGS
197 ARM11_RC_FX
= ARM11_RC_F0
,
210 #if ARM11_REGCACHE_MODEREGS
248 #define ARM11_GDB_REGISTER_COUNT 26
250 /* FIXME these are *identical* to the ARMv4_5 dummies ... except
251 * for their names, and being static vs global, and having different
252 * addresses. Ditto ARMv7a and ARMv7m dummies.
255 static uint8_t arm11_gdb_dummy_fp_value
[12];
257 static struct reg arm11_gdb_dummy_fp_reg
=
259 .name
= "GDB dummy floating-point register",
260 .value
= arm11_gdb_dummy_fp_value
,
268 static uint8_t arm11_gdb_dummy_fps_value
[4];
270 static struct reg arm11_gdb_dummy_fps_reg
=
272 .name
= "GDB dummy floating-point status register",
273 .value
= arm11_gdb_dummy_fps_value
,
282 static int arm11_on_enter_debug_state(struct arm11_common
*arm11
);
283 static int arm11_step(struct target
*target
, int current
,
284 uint32_t address
, int handle_breakpoints
);
286 static int arm11_build_reg_cache(struct target
*target
);
287 static int arm11_set_reg(struct reg
*reg
, uint8_t *buf
);
288 static int arm11_get_reg(struct reg
*reg
);
290 static void arm11_record_register_history(struct arm11_common
* arm11
);
291 static void arm11_dump_reg_changes(struct arm11_common
* arm11
);
294 /** Check and if necessary take control of the system
296 * \param arm11 Target state variable.
297 * \param dscr If the current DSCR content is
298 * available a pointer to a word holding the
299 * DSCR can be passed. Otherwise use NULL.
301 static int arm11_check_init(struct arm11_common
*arm11
, uint32_t *dscr
)
305 uint32_t dscr_local_tmp_copy
;
309 dscr
= &dscr_local_tmp_copy
;
311 CHECK_RETVAL(arm11_read_DSCR(arm11
, dscr
));
314 if (!(*dscr
& ARM11_DSCR_MODE_SELECT
))
316 LOG_DEBUG("Bringing target into debug mode");
318 *dscr
|= ARM11_DSCR_MODE_SELECT
; /* Halt debug-mode */
319 arm11_write_DSCR(arm11
, *dscr
);
321 /* add further reset initialization here */
323 arm11
->simulate_reset_on_next_halt
= true;
325 if (*dscr
& ARM11_DSCR_CORE_HALTED
)
327 /** \todo TODO: this needs further scrutiny because
328 * arm11_on_enter_debug_state() never gets properly called.
329 * As a result we don't read the actual register states from
333 arm11
->target
->state
= TARGET_HALTED
;
334 arm11
->target
->debug_reason
= arm11_get_DSCR_debug_reason(*dscr
);
338 arm11
->target
->state
= TARGET_RUNNING
;
339 arm11
->target
->debug_reason
= DBG_REASON_NOTHALTED
;
342 arm11_sc7_clear_vbw(arm11
);
351 (arm11->reg_values[ARM11_RC_##x])
353 /** Save processor state.
355 * This is called when the HALT instruction has succeeded
356 * or on other occasions that stop the processor.
359 static int arm11_on_enter_debug_state(struct arm11_common
*arm11
)
364 for (size_t i
= 0; i
< asizeof(arm11
->reg_values
); i
++)
366 arm11
->reg_list
[i
].valid
= 1;
367 arm11
->reg_list
[i
].dirty
= 0;
371 CHECK_RETVAL(arm11_read_DSCR(arm11
, &R(DSCR
)));
375 if (R(DSCR
) & ARM11_DSCR_WDTR_FULL
)
377 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
379 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
381 struct scan_field chain5_fields
[3];
383 arm11_setup_field(arm11
, 32, NULL
, &R(WDTR
), chain5_fields
+ 0);
384 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
385 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
387 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
391 arm11
->reg_list
[ARM11_RC_WDTR
].valid
= 0;
395 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
396 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
397 ARM1136 seems to require this to issue ITR's as well */
399 uint32_t new_dscr
= R(DSCR
) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
;
401 /* this executes JTAG queue: */
403 arm11_write_DSCR(arm11
, new_dscr
);
407 Before executing any instruction in debug state you have to drain the write buffer.
408 This ensures that no imprecise Data Aborts can return at a later point:*/
410 /** \todo TODO: Test drain write buffer. */
415 /* MRC p14,0,R0,c5,c10,0 */
416 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
418 /* mcr 15, 0, r0, cr7, cr10, {4} */
419 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
421 uint32_t dscr
= arm11_read_DSCR(arm11
);
423 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
425 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
)
427 arm11_run_instr_no_data1(arm11
, 0xe320f000);
429 dscr
= arm11_read_DSCR(arm11
);
431 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
438 retval
= arm11_run_instr_data_prepare(arm11
);
439 if (retval
!= ERROR_OK
)
444 /** \todo TODO: handle other mode registers */
446 for (size_t i
= 0; i
< 15; i
++)
448 /* MCR p14,0,R?,c0,c5,0 */
449 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15 | (i
<< 12), &R(RX
+ i
), 1);
450 if (retval
!= ERROR_OK
)
456 /* check rDTRfull in DSCR */
458 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
)
460 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
461 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xEE100E15, &R(RDTR
));
462 if (retval
!= ERROR_OK
)
467 arm11
->reg_list
[ARM11_RC_RDTR
].valid
= 0;
472 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
473 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE10F0000, &R(CPSR
));
474 if (retval
!= ERROR_OK
)
479 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
480 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, 0xE1A0000F, &R(PC
));
481 if (retval
!= ERROR_OK
)
484 /* adjust PC depending on ARM state */
486 if (R(CPSR
) & ARM11_CPSR_J
) /* Java state */
488 arm11
->reg_values
[ARM11_RC_PC
] -= 0;
490 else if (R(CPSR
) & ARM11_CPSR_T
) /* Thumb state */
492 arm11
->reg_values
[ARM11_RC_PC
] -= 4;
496 arm11
->reg_values
[ARM11_RC_PC
] -= 8;
499 if (arm11
->simulate_reset_on_next_halt
)
501 arm11
->simulate_reset_on_next_halt
= false;
503 LOG_DEBUG("Reset c1 Control Register");
505 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
507 /* MCR p15,0,R0,c1,c0,0 */
508 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
509 if (retval
!= ERROR_OK
)
514 retval
= arm11_run_instr_data_finish(arm11
);
515 if (retval
!= ERROR_OK
)
518 arm11_dump_reg_changes(arm11
);
523 void arm11_dump_reg_changes(struct arm11_common
* arm11
)
526 if (!(debug_level
>= LOG_LVL_DEBUG
))
531 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
533 if (!arm11
->reg_list
[i
].valid
)
535 if (arm11
->reg_history
[i
].valid
)
536 LOG_DEBUG("%8s INVALID (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_history
[i
].value
);
540 if (arm11
->reg_history
[i
].valid
)
542 if (arm11
->reg_history
[i
].value
!= arm11
->reg_values
[i
])
543 LOG_DEBUG("%8s %08" PRIx32
" (%08" PRIx32
")", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
], arm11
->reg_history
[i
].value
);
547 LOG_DEBUG("%8s %08" PRIx32
" (INVALID)", arm11_reg_defs
[i
].name
, arm11
->reg_values
[i
]);
553 /** Restore processor state
555 * This is called in preparation for the RESTART function.
558 static int arm11_leave_debug_state(struct arm11_common
*arm11
)
563 retval
= arm11_run_instr_data_prepare(arm11
);
564 if (retval
!= ERROR_OK
)
567 /** \todo TODO: handle other mode registers */
569 /* restore R1 - R14 */
571 for (size_t i
= 1; i
< 15; i
++)
573 if (!arm11
->reg_list
[ARM11_RC_RX
+ i
].dirty
)
576 /* MRC p14,0,r?,c0,c5,0 */
577 arm11_run_instr_data_to_core1(arm11
, 0xee100e15 | (i
<< 12), R(RX
+ i
));
579 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
582 retval
= arm11_run_instr_data_finish(arm11
);
583 if (retval
!= ERROR_OK
)
586 /* spec says clear wDTR and rDTR; we assume they are clear as
587 otherwise our programming would be sloppy */
591 CHECK_RETVAL(arm11_read_DSCR(arm11
, &DSCR
));
593 if (DSCR
& (ARM11_DSCR_RDTR_FULL
| ARM11_DSCR_WDTR_FULL
))
596 The wDTR/rDTR two registers that are used to send/receive data to/from
597 the core in tandem with corresponding instruction codes that are
598 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
599 registers hold data that was written by one side (CPU or JTAG) and not
600 read out by the other side.
602 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32
")", DSCR
);
607 retval
= arm11_run_instr_data_prepare(arm11
);
608 if (retval
!= ERROR_OK
)
611 /* restore original wDTR */
613 if ((R(DSCR
) & ARM11_DSCR_WDTR_FULL
) || arm11
->reg_list
[ARM11_RC_WDTR
].dirty
)
615 /* MCR p14,0,R0,c0,c5,0 */
616 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee000e15, R(WDTR
));
617 if (retval
!= ERROR_OK
)
624 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xe129f000, R(CPSR
));
625 if (retval
!= ERROR_OK
)
632 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xe1a0f000, R(PC
));
633 if (retval
!= ERROR_OK
)
639 /* MRC p14,0,r0,c0,c5,0 */
640 arm11_run_instr_data_to_core1(arm11
, 0xee100e15, R(R0
));
642 retval
= arm11_run_instr_data_finish(arm11
);
643 if (retval
!= ERROR_OK
)
648 arm11_write_DSCR(arm11
, R(DSCR
));
652 if (R(DSCR
) & ARM11_DSCR_RDTR_FULL
|| arm11
->reg_list
[ARM11_RC_RDTR
].dirty
)
654 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
656 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
658 struct scan_field chain5_fields
[3];
660 uint8_t Ready
= 0; /* ignored */
661 uint8_t Valid
= 0; /* ignored */
663 arm11_setup_field(arm11
, 32, &R(RDTR
), NULL
, chain5_fields
+ 0);
664 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
665 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
667 arm11_add_dr_scan_vc(asizeof(chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
670 arm11_record_register_history(arm11
);
675 static void arm11_record_register_history(struct arm11_common
*arm11
)
677 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
679 arm11
->reg_history
[i
].value
= arm11
->reg_values
[i
];
680 arm11
->reg_history
[i
].valid
= arm11
->reg_list
[i
].valid
;
682 arm11
->reg_list
[i
].valid
= 0;
683 arm11
->reg_list
[i
].dirty
= 0;
688 /* poll current target status */
689 static int arm11_poll(struct target
*target
)
693 struct arm11_common
*arm11
= target_to_arm11(target
);
696 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
698 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
700 CHECK_RETVAL(arm11_check_init(arm11
, &dscr
));
702 if (dscr
& ARM11_DSCR_CORE_HALTED
)
704 if (target
->state
!= TARGET_HALTED
)
706 enum target_state old_state
= target
->state
;
708 LOG_DEBUG("enter TARGET_HALTED");
709 target
->state
= TARGET_HALTED
;
710 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
711 retval
= arm11_on_enter_debug_state(arm11
);
712 if (retval
!= ERROR_OK
)
715 target_call_event_callbacks(target
,
716 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
);
721 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
)
723 LOG_DEBUG("enter TARGET_RUNNING");
724 target
->state
= TARGET_RUNNING
;
725 target
->debug_reason
= DBG_REASON_NOTHALTED
;
731 /* architecture specific status reply */
732 static int arm11_arch_state(struct target
*target
)
734 struct arm11_common
*arm11
= target_to_arm11(target
);
736 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"",
737 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
744 /* target request support */
745 static int arm11_target_request_data(struct target
*target
,
746 uint32_t size
, uint8_t *buffer
)
748 FNC_INFO_NOTIMPLEMENTED
;
753 /* target execution control */
754 static int arm11_halt(struct target
*target
)
757 struct arm11_common
*arm11
= target_to_arm11(target
);
759 LOG_DEBUG("target->state: %s",
760 target_state_name(target
));
762 if (target
->state
== TARGET_UNKNOWN
)
764 arm11
->simulate_reset_on_next_halt
= true;
767 if (target
->state
== TARGET_HALTED
)
769 LOG_DEBUG("target was already halted");
773 arm11_add_IR(arm11
, ARM11_HALT
, TAP_IDLE
);
775 CHECK_RETVAL(jtag_execute_queue());
782 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
784 if (dscr
& ARM11_DSCR_CORE_HALTED
)
795 if ((timeval_ms()-then
) > 1000)
797 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
804 arm11_on_enter_debug_state(arm11
);
806 enum target_state old_state
= target
->state
;
808 target
->state
= TARGET_HALTED
;
809 target
->debug_reason
= arm11_get_DSCR_debug_reason(dscr
);
812 target_call_event_callbacks(target
,
813 old_state
== TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
));
818 static int arm11_resume(struct target
*target
, int current
,
819 uint32_t address
, int handle_breakpoints
, int debug_execution
)
823 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
824 // current, address, handle_breakpoints, debug_execution);
826 struct arm11_common
*arm11
= target_to_arm11(target
);
828 LOG_DEBUG("target->state: %s",
829 target_state_name(target
));
832 if (target
->state
!= TARGET_HALTED
)
834 LOG_ERROR("Target not halted");
835 return ERROR_TARGET_NOT_HALTED
;
841 LOG_DEBUG("RESUME PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
843 /* clear breakpoints/watchpoints and VCR*/
844 arm11_sc7_clear_vbw(arm11
);
846 /* Set up breakpoints */
847 if (!debug_execution
)
849 /* check if one matches PC and step over it if necessary */
851 struct breakpoint
* bp
;
853 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
855 if (bp
->address
== R(PC
))
857 LOG_DEBUG("must step over %08" PRIx32
"", bp
->address
);
858 arm11_step(target
, 1, 0, 0);
863 /* set all breakpoints */
867 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
)
869 struct arm11_sc7_action brp
[2];
872 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
873 brp
[0].value
= bp
->address
;
875 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
876 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
878 arm11_sc7_run(arm11
, brp
, asizeof(brp
));
880 LOG_DEBUG("Add BP " ZU
" at %08" PRIx32
"", brp_num
, bp
->address
);
885 arm11_sc7_set_vcr(arm11
, arm11_vcr
);
888 arm11_leave_debug_state(arm11
);
890 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
892 CHECK_RETVAL(jtag_execute_queue());
899 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
901 LOG_DEBUG("DSCR %08" PRIx32
"", dscr
);
903 if (dscr
& ARM11_DSCR_CORE_RESTARTED
)
914 if ((timeval_ms()-then
) > 1000)
916 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
923 if (!debug_execution
)
925 target
->state
= TARGET_RUNNING
;
926 target
->debug_reason
= DBG_REASON_NOTHALTED
;
928 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
932 target
->state
= TARGET_DEBUG_RUNNING
;
933 target
->debug_reason
= DBG_REASON_NOTHALTED
;
935 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
942 static int armv4_5_to_arm11(int reg
)
949 return ARM11_RC_CPSR
;
951 /* FIX!!! handle thumb better! */
952 return ARM11_RC_CPSR
;
954 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg
);
960 static uint32_t arm11_sim_get_reg(struct arm_sim_interface
*sim
, int reg
)
962 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
964 reg
=armv4_5_to_arm11(reg
);
966 return buf_get_u32(arm11
->reg_list
[reg
].value
, 0, 32);
969 static void arm11_sim_set_reg(struct arm_sim_interface
*sim
,
970 int reg
, uint32_t value
)
972 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
974 reg
=armv4_5_to_arm11(reg
);
976 buf_set_u32(arm11
->reg_list
[reg
].value
, 0, 32, value
);
979 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface
*sim
,
982 struct arm11_common
* arm11
= (struct arm11_common
*)sim
->user_data
;
984 return buf_get_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, pos
, bits
);
987 static enum armv4_5_state
arm11_sim_get_state(struct arm_sim_interface
*sim
)
989 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
991 /* FIX!!!! we should implement thumb for arm11 */
992 return ARMV4_5_STATE_ARM
;
995 static void arm11_sim_set_state(struct arm_sim_interface
*sim
,
996 enum armv4_5_state mode
)
998 // struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
1000 /* FIX!!!! we should implement thumb for arm11 */
1001 LOG_ERROR("Not implemetned!");
1005 static enum armv4_5_mode
arm11_sim_get_mode(struct arm_sim_interface
*sim
)
1007 //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
1009 /* FIX!!!! we should implement something that returns the current mode here!!! */
1010 return ARMV4_5_MODE_USR
;
1013 static int arm11_simulate_step(struct target
*target
, uint32_t *dry_run_pc
)
1015 struct arm_sim_interface sim
;
1017 sim
.user_data
=target
->arch_info
;
1018 sim
.get_reg
=&arm11_sim_get_reg
;
1019 sim
.set_reg
=&arm11_sim_set_reg
;
1020 sim
.get_reg_mode
=&arm11_sim_get_reg
;
1021 sim
.set_reg_mode
=&arm11_sim_set_reg
;
1022 sim
.get_cpsr
=&arm11_sim_get_cpsr
;
1023 sim
.get_mode
=&arm11_sim_get_mode
;
1024 sim
.get_state
=&arm11_sim_get_state
;
1025 sim
.set_state
=&arm11_sim_set_state
;
1027 return arm_simulate_step_core(target
, dry_run_pc
, &sim
);
1031 static int arm11_step(struct target
*target
, int current
,
1032 uint32_t address
, int handle_breakpoints
)
1036 LOG_DEBUG("target->state: %s",
1037 target_state_name(target
));
1039 if (target
->state
!= TARGET_HALTED
)
1041 LOG_WARNING("target was not halted");
1042 return ERROR_TARGET_NOT_HALTED
;
1045 struct arm11_common
*arm11
= target_to_arm11(target
);
1050 LOG_DEBUG("STEP PC %08" PRIx32
"%s", R(PC
), !current
? "!" : "");
1053 /** \todo TODO: Thumb not supported here */
1055 uint32_t next_instruction
;
1057 CHECK_RETVAL(arm11_read_memory_word(arm11
, R(PC
), &next_instruction
));
1059 /* skip over BKPT */
1060 if ((next_instruction
& 0xFFF00070) == 0xe1200070)
1063 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1064 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1065 LOG_DEBUG("Skipping BKPT");
1067 /* skip over Wait for interrupt / Standby */
1068 /* mcr 15, 0, r?, cr7, cr0, {4} */
1069 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90)
1072 arm11
->reg_list
[ARM11_RC_PC
].valid
= 1;
1073 arm11
->reg_list
[ARM11_RC_PC
].dirty
= 0;
1074 LOG_DEBUG("Skipping WFI");
1076 /* ignore B to self */
1077 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
1079 LOG_DEBUG("Not stepping jump to self");
1083 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1086 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1087 * the VCR might be something worth looking into. */
1090 /* Set up breakpoint for stepping */
1092 struct arm11_sc7_action brp
[2];
1095 brp
[0].address
= ARM11_SC7_BVR0
;
1097 brp
[1].address
= ARM11_SC7_BCR0
;
1099 if (arm11_config_hardware_step
)
1101 /* hardware single stepping be used if possible or is it better to
1102 * always use the same code path? Hardware single stepping is not supported
1105 brp
[0].value
= R(PC
);
1106 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1109 /* sets a breakpoint on the next PC(calculated by simulation),
1113 retval
= arm11_simulate_step(target
, &next_pc
);
1114 if (retval
!= ERROR_OK
)
1117 brp
[0].value
= next_pc
;
1118 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1121 CHECK_RETVAL(arm11_sc7_run(arm11
, brp
, asizeof(brp
)));
1126 if (arm11_config_step_irq_enable
)
1127 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
; /* should be redundant */
1129 R(DSCR
) |= ARM11_DSCR_INTERRUPTS_DISABLE
;
1132 CHECK_RETVAL(arm11_leave_debug_state(arm11
));
1134 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
1136 CHECK_RETVAL(jtag_execute_queue());
1144 CHECK_RETVAL(arm11_read_DSCR(arm11
, &dscr
));
1146 LOG_DEBUG("DSCR %08" PRIx32
"e", dscr
);
1148 if ((dscr
& (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
)) ==
1149 (ARM11_DSCR_CORE_RESTARTED
| ARM11_DSCR_CORE_HALTED
))
1155 then
= timeval_ms();
1159 if ((timeval_ms()-then
) > 1000)
1161 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1168 /* clear breakpoint */
1169 arm11_sc7_clear_vbw(arm11
);
1172 CHECK_RETVAL(arm11_on_enter_debug_state(arm11
));
1174 /* restore default state */
1175 R(DSCR
) &= ~ARM11_DSCR_INTERRUPTS_DISABLE
;
1179 // target->state = TARGET_HALTED;
1180 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1182 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
1187 static int arm11_assert_reset(struct target
*target
)
1191 struct arm11_common
*arm11
= target_to_arm11(target
);
1193 retval
= arm11_check_init(arm11
, NULL
);
1194 if (retval
!= ERROR_OK
)
1197 target
->state
= TARGET_UNKNOWN
;
1199 /* we would very much like to reset into the halted, state,
1200 * but resetting and halting is second best... */
1201 if (target
->reset_halt
)
1203 CHECK_RETVAL(target_halt(target
));
1207 /* srst is funny. We can not do *anything* else while it's asserted
1208 * and it has unkonwn side effects. Make sure no other code runs
1211 * Code below assumes srst:
1213 * - Causes power-on-reset (but of what parts of the system?). Bug
1216 * - Messes us TAP state without asserting trst.
1218 * - There is another bug in the arm11 core. When you generate an access to
1219 * external logic (for example ddr controller via AHB bus) and that block
1220 * is not configured (perhaps it is still held in reset), that transaction
1221 * will never complete. This will hang arm11 core but it will also hang
1222 * JTAG controller. Nothing, short of srst assertion will bring it out of
1227 * - What should the PC be after an srst reset when starting in the halted
1231 jtag_add_reset(0, 1);
1232 jtag_add_reset(0, 0);
1234 /* How long do we have to wait? */
1235 jtag_add_sleep(5000);
1237 /* un-mess up TAP state */
1240 retval
= jtag_execute_queue();
1241 if (retval
!= ERROR_OK
)
1249 static int arm11_deassert_reset(struct target
*target
)
1254 static int arm11_soft_reset_halt(struct target
*target
)
1256 FNC_INFO_NOTIMPLEMENTED
;
1261 /* target register access for gdb */
1262 static int arm11_get_gdb_reg_list(struct target
*target
,
1263 struct reg
**reg_list
[], int *reg_list_size
)
1266 struct arm11_common
*arm11
= target_to_arm11(target
);
1268 *reg_list_size
= ARM11_GDB_REGISTER_COUNT
;
1269 *reg_list
= malloc(sizeof(struct reg
*) * ARM11_GDB_REGISTER_COUNT
);
1271 for (size_t i
= 16; i
< 24; i
++)
1273 (*reg_list
)[i
] = &arm11_gdb_dummy_fp_reg
;
1276 (*reg_list
)[24] = &arm11_gdb_dummy_fps_reg
;
1278 for (size_t i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1280 if (arm11_reg_defs
[i
].gdb_num
== -1)
1283 (*reg_list
)[arm11_reg_defs
[i
].gdb_num
] = arm11
->reg_list
+ i
;
1289 /* target memory access
1290 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1291 * count: number of items of <size>
1293 * arm11_config_memrw_no_increment - in the future we may want to be able
1294 * to read/write a range of data to a "port". a "port" is an action on
1295 * read memory address for some peripheral.
1297 static int arm11_read_memory_inner(struct target
*target
,
1298 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
1299 bool arm11_config_memrw_no_increment
)
1301 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1306 if (target
->state
!= TARGET_HALTED
)
1308 LOG_WARNING("target was not halted");
1309 return ERROR_TARGET_NOT_HALTED
;
1312 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1314 struct arm11_common
*arm11
= target_to_arm11(target
);
1316 retval
= arm11_run_instr_data_prepare(arm11
);
1317 if (retval
!= ERROR_OK
)
1320 /* MRC p14,0,r0,c0,c5,0 */
1321 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1322 if (retval
!= ERROR_OK
)
1328 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1329 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1331 for (size_t i
= 0; i
< count
; i
++)
1333 /* ldrb r1, [r0], #1 */
1335 arm11_run_instr_no_data1(arm11
,
1336 !arm11_config_memrw_no_increment
? 0xe4d01001 : 0xe5d01000);
1339 /* MCR p14,0,R1,c0,c5,0 */
1340 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1349 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1351 for (size_t i
= 0; i
< count
; i
++)
1353 /* ldrh r1, [r0], #2 */
1354 arm11_run_instr_no_data1(arm11
,
1355 !arm11_config_memrw_no_increment
? 0xe0d010b2 : 0xe1d010b0);
1359 /* MCR p14,0,R1,c0,c5,0 */
1360 arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1);
1362 uint16_t svalue
= res
;
1363 memcpy(buffer
+ i
* sizeof(uint16_t), &svalue
, sizeof(uint16_t));
1371 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xecb05e01 : 0xed905e00;
1372 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1373 uint32_t *words
= (uint32_t *)buffer
;
1375 /* LDC p14,c5,[R0],#4 */
1376 /* LDC p14,c5,[R0] */
1377 arm11_run_instr_data_from_core(arm11
, instr
, words
, count
);
1382 return arm11_run_instr_data_finish(arm11
);
1385 static int arm11_read_memory(struct target
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1387 return arm11_read_memory_inner(target
, address
, size
, count
, buffer
, false);
1391 * arm11_config_memrw_no_increment - in the future we may want to be able
1392 * to read/write a range of data to a "port". a "port" is an action on
1393 * read memory address for some peripheral.
1395 static int arm11_write_memory_inner(struct target
*target
,
1396 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
1397 bool arm11_config_memrw_no_increment
)
1402 if (target
->state
!= TARGET_HALTED
)
1404 LOG_WARNING("target was not halted");
1405 return ERROR_TARGET_NOT_HALTED
;
1408 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"", address
, size
, count
);
1410 struct arm11_common
*arm11
= target_to_arm11(target
);
1412 retval
= arm11_run_instr_data_prepare(arm11
);
1413 if (retval
!= ERROR_OK
)
1416 /* MRC p14,0,r0,c0,c5,0 */
1417 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
1418 if (retval
!= ERROR_OK
)
1421 /* burst writes are not used for single words as those may well be
1422 * reset init script writes.
1424 * The other advantage is that as burst writes are default, we'll
1425 * now exercise both burst and non-burst code paths with the
1426 * default settings, increasing code coverage.
1428 bool burst
= arm11_config_memwrite_burst
&& (count
> 1);
1434 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1436 for (size_t i
= 0; i
< count
; i
++)
1438 /* MRC p14,0,r1,c0,c5,0 */
1439 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
1440 if (retval
!= ERROR_OK
)
1443 /* strb r1, [r0], #1 */
1445 retval
= arm11_run_instr_no_data1(arm11
,
1446 !arm11_config_memrw_no_increment
? 0xe4c01001 : 0xe5c01000);
1447 if (retval
!= ERROR_OK
)
1456 arm11
->reg_list
[ARM11_RC_R1
].dirty
= 1;
1458 for (size_t i
= 0; i
< count
; i
++)
1461 memcpy(&value
, buffer
+ i
* sizeof(uint16_t), sizeof(uint16_t));
1463 /* MRC p14,0,r1,c0,c5,0 */
1464 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, value
);
1465 if (retval
!= ERROR_OK
)
1468 /* strh r1, [r0], #2 */
1470 retval
= arm11_run_instr_no_data1(arm11
,
1471 !arm11_config_memrw_no_increment
? 0xe0c010b2 : 0xe1c010b0);
1472 if (retval
!= ERROR_OK
)
1480 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xeca05e01 : 0xed805e00;
1482 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1483 uint32_t *words
= (uint32_t*)buffer
;
1487 /* STC p14,c5,[R0],#4 */
1488 /* STC p14,c5,[R0]*/
1489 retval
= arm11_run_instr_data_to_core(arm11
, instr
, words
, count
);
1490 if (retval
!= ERROR_OK
)
1495 /* STC p14,c5,[R0],#4 */
1496 /* STC p14,c5,[R0]*/
1497 retval
= arm11_run_instr_data_to_core_noack(arm11
, instr
, words
, count
);
1498 if (retval
!= ERROR_OK
)
1506 /* r0 verification */
1507 if (!arm11_config_memrw_no_increment
)
1511 /* MCR p14,0,R0,c0,c5,0 */
1512 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1513 if (retval
!= ERROR_OK
)
1516 if (address
+ size
* count
!= r0
)
1518 LOG_ERROR("Data transfer failed. Expected end "
1519 "address 0x%08x, got 0x%08x",
1520 (unsigned) (address
+ size
* count
),
1524 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1526 if (arm11_config_memwrite_error_fatal
)
1531 return arm11_run_instr_data_finish(arm11
);
1534 static int arm11_write_memory(struct target
*target
,
1535 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
1537 return arm11_write_memory_inner(target
, address
, size
, count
, buffer
, false);
1540 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1541 static int arm11_bulk_write_memory(struct target
*target
,
1542 uint32_t address
, uint32_t count
, uint8_t *buffer
)
1546 if (target
->state
!= TARGET_HALTED
)
1548 LOG_WARNING("target was not halted");
1549 return ERROR_TARGET_NOT_HALTED
;
1552 return arm11_write_memory(target
, address
, 4, count
, buffer
);
1555 /* target break-/watchpoint control
1556 * rw: 0 = write, 1 = read, 2 = access
1558 static int arm11_add_breakpoint(struct target
*target
,
1559 struct breakpoint
*breakpoint
)
1562 struct arm11_common
*arm11
= target_to_arm11(target
);
1565 if (breakpoint
->type
== BKPT_SOFT
)
1567 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1568 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1572 if (!arm11
->free_brps
)
1574 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1575 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1578 if (breakpoint
->length
!= 4)
1580 LOG_DEBUG("only breakpoints of four bytes length supported");
1581 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1589 static int arm11_remove_breakpoint(struct target
*target
,
1590 struct breakpoint
*breakpoint
)
1593 struct arm11_common
*arm11
= target_to_arm11(target
);
1600 static int arm11_add_watchpoint(struct target
*target
,
1601 struct watchpoint
*watchpoint
)
1603 FNC_INFO_NOTIMPLEMENTED
;
1608 static int arm11_remove_watchpoint(struct target
*target
,
1609 struct watchpoint
*watchpoint
)
1611 FNC_INFO_NOTIMPLEMENTED
;
1616 // HACKHACKHACK - FIXME mode/state
1617 /* target algorithm support */
1618 static int arm11_run_algorithm(struct target
*target
,
1619 int num_mem_params
, struct mem_param
*mem_params
,
1620 int num_reg_params
, struct reg_param
*reg_params
,
1621 uint32_t entry_point
, uint32_t exit_point
,
1622 int timeout_ms
, void *arch_info
)
1624 struct arm11_common
*arm11
= target_to_arm11(target
);
1625 // enum armv4_5_state core_state = arm11->core_state;
1626 // enum armv4_5_mode core_mode = arm11->core_mode;
1627 uint32_t context
[16];
1629 int exit_breakpoint_size
= 0;
1630 int retval
= ERROR_OK
;
1631 LOG_DEBUG("Running algorithm");
1634 if (target
->state
!= TARGET_HALTED
)
1636 LOG_WARNING("target not halted");
1637 return ERROR_TARGET_NOT_HALTED
;
1641 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1642 // return ERROR_FAIL;
1645 for (unsigned i
= 0; i
< 16; i
++)
1647 context
[i
] = buf_get_u32((uint8_t*)(&arm11
->reg_values
[i
]),0,32);
1648 LOG_DEBUG("Save %u: 0x%" PRIx32
"", i
, context
[i
]);
1651 cpsr
= buf_get_u32((uint8_t*)(arm11
->reg_values
+ ARM11_RC_CPSR
),0,32);
1652 LOG_DEBUG("Save CPSR: 0x%" PRIx32
"", cpsr
);
1654 for (int i
= 0; i
< num_mem_params
; i
++)
1656 target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1659 // Set register parameters
1660 for (int i
= 0; i
< num_reg_params
; i
++)
1662 struct reg
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1665 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1669 if (reg
->size
!= reg_params
[i
].size
)
1671 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1674 arm11_set_reg(reg
,reg_params
[i
].value
);
1675 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1678 exit_breakpoint_size
= 4;
1680 /* arm11->core_state = arm11_algorithm_info->core_state;
1681 if (arm11->core_state == ARMV4_5_STATE_ARM)
1682 exit_breakpoint_size = 4;
1683 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1684 exit_breakpoint_size = 2;
1687 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1693 /* arm11 at this point only supports ARM not THUMB mode
1694 however if this test needs to be reactivated the current state can be read back
1697 if (arm11_algorithm_info
->core_mode
!= ARMV4_5_MODE_ANY
)
1699 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info
->core_mode
);
1700 buf_set_u32(arm11
->reg_list
[ARM11_RC_CPSR
].value
, 0, 5, arm11_algorithm_info
->core_mode
);
1701 arm11
->reg_list
[ARM11_RC_CPSR
].dirty
= 1;
1702 arm11
->reg_list
[ARM11_RC_CPSR
].valid
= 1;
1706 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_HARD
)) != ERROR_OK
)
1708 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1709 retval
= ERROR_TARGET_FAILURE
;
1713 // no debug, otherwise breakpoint is not set
1714 CHECK_RETVAL(target_resume(target
, 0, entry_point
, 1, 0));
1716 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, timeout_ms
));
1718 if (target
->state
!= TARGET_HALTED
)
1720 CHECK_RETVAL(target_halt(target
));
1722 CHECK_RETVAL(target_wait_state(target
, TARGET_HALTED
, 500));
1724 retval
= ERROR_TARGET_TIMEOUT
;
1726 goto del_breakpoint
;
1729 if (buf_get_u32(arm11
->reg_list
[15].value
, 0, 32) != exit_point
)
1731 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32
"",
1732 buf_get_u32(arm11
->reg_list
[15].value
, 0, 32));
1733 retval
= ERROR_TARGET_TIMEOUT
;
1734 goto del_breakpoint
;
1737 for (int i
= 0; i
< num_mem_params
; i
++)
1739 if (mem_params
[i
].direction
!= PARAM_OUT
)
1740 target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
);
1743 for (int i
= 0; i
< num_reg_params
; i
++)
1745 if (reg_params
[i
].direction
!= PARAM_OUT
)
1747 struct reg
*reg
= register_get_by_name(arm11
->core_cache
, reg_params
[i
].reg_name
, 0);
1750 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
1754 if (reg
->size
!= reg_params
[i
].size
)
1756 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
1760 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
1765 breakpoint_remove(target
, exit_point
);
1769 for (size_t i
= 0; i
< 16; i
++)
1771 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
"",
1772 arm11
->reg_list
[i
].name
, context
[i
]);
1773 arm11_set_reg(&arm11
->reg_list
[i
], (uint8_t*)&context
[i
]);
1775 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32
"", cpsr
);
1776 arm11_set_reg(&arm11
->reg_list
[ARM11_RC_CPSR
], (uint8_t*)&cpsr
);
1778 // arm11->core_state = core_state;
1779 // arm11->core_mode = core_mode;
1784 static int arm11_target_create(struct target
*target
, Jim_Interp
*interp
)
1788 NEW(struct arm11_common
, arm11
, 1);
1790 arm11
->target
= target
;
1792 if (target
->tap
== NULL
)
1795 if (target
->tap
->ir_length
!= 5)
1797 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1798 return ERROR_COMMAND_SYNTAX_ERROR
;
1801 armv4_5_init_arch_info(target
, &arm11
->arm
);
1803 arm11
->jtag_info
.tap
= target
->tap
;
1804 arm11
->jtag_info
.scann_size
= 5;
1805 arm11
->jtag_info
.scann_instr
= ARM11_SCAN_N
;
1806 /* cur_scan_chain == 0 */
1807 arm11
->jtag_info
.intest_instr
= ARM11_INTEST
;
1812 static int arm11_init_target(struct command_context
*cmd_ctx
,
1813 struct target
*target
)
1815 /* Initialize anything we can set up without talking to the target */
1816 return arm11_build_reg_cache(target
);
1819 /* talk to the target and set things up */
1820 static int arm11_examine(struct target
*target
)
1825 struct arm11_common
*arm11
= target_to_arm11(target
);
1829 arm11_add_IR(arm11
, ARM11_IDCODE
, ARM11_TAP_DEFAULT
);
1831 struct scan_field idcode_field
;
1833 arm11_setup_field(arm11
, 32, NULL
, &arm11
->device_id
, &idcode_field
);
1835 arm11_add_dr_scan_vc(1, &idcode_field
, TAP_DRPAUSE
);
1839 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
1841 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
1843 struct scan_field chain0_fields
[2];
1845 arm11_setup_field(arm11
, 32, NULL
, &arm11
->didr
, chain0_fields
+ 0);
1846 arm11_setup_field(arm11
, 8, NULL
, &arm11
->implementor
, chain0_fields
+ 1);
1848 arm11_add_dr_scan_vc(asizeof(chain0_fields
), chain0_fields
, TAP_IDLE
);
1850 CHECK_RETVAL(jtag_execute_queue());
1852 switch (arm11
->device_id
& 0x0FFFF000)
1854 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1855 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1856 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1858 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1862 arm11
->debug_version
= (arm11
->didr
>> 16) & 0x0F;
1864 if (arm11
->debug_version
!= ARM11_DEBUG_V6
&&
1865 arm11
->debug_version
!= ARM11_DEBUG_V61
)
1867 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1871 arm11
->brp
= ((arm11
->didr
>> 24) & 0x0F) + 1;
1872 arm11
->wrp
= ((arm11
->didr
>> 28) & 0x0F) + 1;
1874 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1875 arm11
->free_brps
= arm11
->brp
;
1876 arm11
->free_wrps
= arm11
->wrp
;
1878 LOG_DEBUG("IDCODE %08" PRIx32
" IMPLEMENTOR %02x DIDR %08" PRIx32
"",
1880 (int)(arm11
->implementor
),
1883 /* as a side-effect this reads DSCR and thus
1884 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1885 * as suggested by the spec.
1888 retval
= arm11_check_init(arm11
, NULL
);
1889 if (retval
!= ERROR_OK
)
1892 /* ETM on ARM11 still uses original scanchain 6 access mode */
1893 if (arm11
->arm
.etm
&& !target_was_examined(target
)) {
1894 *register_get_last_cache_p(&target
->reg_cache
) =
1895 etm_build_reg_cache(target
, &arm11
->jtag_info
,
1897 retval
= etm_setup(target
);
1900 target_set_examined(target
);
1906 /** Load a register that is marked !valid in the register cache */
1907 static int arm11_get_reg(struct reg
*reg
)
1911 struct target
* target
= ((struct arm11_reg_state
*)reg
->arch_info
)->target
;
1913 if (target
->state
!= TARGET_HALTED
)
1915 LOG_WARNING("target was not halted");
1916 return ERROR_TARGET_NOT_HALTED
;
1919 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1922 struct arm11_common
*arm11
= target_to_arm11(target
);
1923 const struct arm11_reg_defs
*arm11_reg_info
= arm11_reg_defs
+ ((struct arm11_reg_state
*)reg
->arch_info
)->def_index
;
1929 /** Change a value in the register cache */
1930 static int arm11_set_reg(struct reg
*reg
, uint8_t *buf
)
1934 struct target
*target
= ((struct arm11_reg_state
*)reg
->arch_info
)->target
;
1935 struct arm11_common
*arm11
= target_to_arm11(target
);
1936 // const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1938 arm11
->reg_values
[((struct arm11_reg_state
*)reg
->arch_info
)->def_index
] = buf_get_u32(buf
, 0, 32);
1945 static int arm11_build_reg_cache(struct target
*target
)
1947 struct arm11_common
*arm11
= target_to_arm11(target
);
1949 NEW(struct reg_cache
, cache
, 1);
1950 NEW(struct reg
, reg_list
, ARM11_REGCACHE_COUNT
);
1951 NEW(struct arm11_reg_state
, arm11_reg_states
, ARM11_REGCACHE_COUNT
);
1953 if (arm11_regs_arch_type
== -1)
1954 arm11_regs_arch_type
= register_reg_arch_type(arm11_get_reg
, arm11_set_reg
);
1956 register_init_dummy(&arm11_gdb_dummy_fp_reg
);
1957 register_init_dummy(&arm11_gdb_dummy_fps_reg
);
1959 arm11
->reg_list
= reg_list
;
1961 /* Build the process context cache */
1962 cache
->name
= "arm11 registers";
1964 cache
->reg_list
= reg_list
;
1965 cache
->num_regs
= ARM11_REGCACHE_COUNT
;
1967 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1970 arm11
->core_cache
= cache
;
1971 // armv7m->process_context = cache;
1975 /* Not very elegant assertion */
1976 if (ARM11_REGCACHE_COUNT
!= asizeof(arm11
->reg_values
) ||
1977 ARM11_REGCACHE_COUNT
!= asizeof(arm11_reg_defs
) ||
1978 ARM11_REGCACHE_COUNT
!= ARM11_RC_MAX
)
1980 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU
" " ZU
" %d)", ARM11_REGCACHE_COUNT
, asizeof(arm11
->reg_values
), asizeof(arm11_reg_defs
), ARM11_RC_MAX
);
1984 for (i
= 0; i
< ARM11_REGCACHE_COUNT
; i
++)
1986 struct reg
* r
= reg_list
+ i
;
1987 const struct arm11_reg_defs
* rd
= arm11_reg_defs
+ i
;
1988 struct arm11_reg_state
* rs
= arm11_reg_states
+ i
;
1992 r
->value
= (uint8_t *)(arm11
->reg_values
+ i
);
1995 r
->arch_type
= arm11_regs_arch_type
;
1999 rs
->target
= target
;
2005 static COMMAND_HELPER(arm11_handle_bool
, bool *var
, char *name
)
2009 LOG_INFO("%s is %s.", name
, *var
? "enabled" : "disabled");
2014 return ERROR_COMMAND_SYNTAX_ERROR
;
2019 case 'f': /* false */
2021 case 'd': /* disable */
2027 case 't': /* true */
2029 case 'e': /* enable */
2035 LOG_INFO("%s %s.", *var
? "Enabled" : "Disabled", name
);
2040 #define BOOL_WRAPPER(name, print_name) \
2041 COMMAND_HANDLER(arm11_handle_bool_##name) \
2043 return CALL_COMMAND_HANDLER(arm11_handle_bool, \
2044 &arm11_config_##name, print_name); \
2047 BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
2048 BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
2049 BOOL_WRAPPER(step_irq_enable
, "IRQs while stepping")
2050 BOOL_WRAPPER(hardware_step
, "hardware single step")
2052 COMMAND_HANDLER(arm11_handle_vcr
)
2058 COMMAND_PARSE_NUMBER(u32
, args
[0], arm11_vcr
);
2061 return ERROR_COMMAND_SYNTAX_ERROR
;
2064 LOG_INFO("VCR 0x%08" PRIx32
"", arm11_vcr
);
2068 static const uint32_t arm11_coproc_instruction_limits
[] =
2070 15, /* coprocessor */
2075 0xFFFFFFFF, /* value */
2078 static int arm11_mrc_inner(struct target
*target
, int cpnum
,
2079 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
,
2080 uint32_t *value
, bool read
)
2083 struct arm11_common
*arm11
= target_to_arm11(target
);
2085 if (target
->state
!= TARGET_HALTED
)
2087 LOG_ERROR("Target not halted");
2091 uint32_t instr
= 0xEE000010 |
2099 instr
|= 0x00100000;
2101 retval
= arm11_run_instr_data_prepare(arm11
);
2102 if (retval
!= ERROR_OK
)
2107 retval
= arm11_run_instr_data_from_core_via_r0(arm11
, instr
, value
);
2108 if (retval
!= ERROR_OK
)
2113 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, instr
, *value
);
2114 if (retval
!= ERROR_OK
)
2118 return arm11_run_instr_data_finish(arm11
);
2121 static int arm11_mrc(struct target
*target
, int cpnum
,
2122 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t *value
)
2124 return arm11_mrc_inner(target
, cpnum
, op1
, op2
, CRn
, CRm
, value
, true);
2127 static int arm11_mcr(struct target
*target
, int cpnum
,
2128 uint32_t op1
, uint32_t op2
, uint32_t CRn
, uint32_t CRm
, uint32_t value
)
2130 return arm11_mrc_inner(target
, cpnum
, op1
, op2
, CRn
, CRm
, &value
, false);
2133 static int arm11_register_commands(struct command_context
*cmd_ctx
)
2137 struct command
*top_cmd
, *mw_cmd
;
2139 top_cmd
= register_command(cmd_ctx
, NULL
, "arm11",
2140 NULL
, COMMAND_ANY
, NULL
);
2142 /* "hardware_step" is only here to check if the default
2143 * simulate + breakpoint implementation is broken.
2144 * TEMPORARY! NOT DOCUMENTED!
2146 register_command(cmd_ctx
, top_cmd
, "hardware_step",
2147 arm11_handle_bool_hardware_step
, COMMAND_ANY
,
2148 "DEBUG ONLY - Hardware single stepping"
2149 " (default: disabled)");
2151 mw_cmd
= register_command(cmd_ctx
, top_cmd
, "memwrite",
2152 NULL
, COMMAND_ANY
, NULL
);
2153 register_command(cmd_ctx
, mw_cmd
, "burst",
2154 arm11_handle_bool_memwrite_burst
, COMMAND_ANY
,
2155 "Enable/Disable non-standard but fast burst mode"
2156 " (default: enabled)");
2157 register_command(cmd_ctx
, mw_cmd
, "error_fatal",
2158 arm11_handle_bool_memwrite_error_fatal
, COMMAND_ANY
,
2159 "Terminate program if transfer error was found"
2160 " (default: enabled)");
2162 register_command(cmd_ctx
, top_cmd
, "step_irq_enable",
2163 arm11_handle_bool_step_irq_enable
, COMMAND_ANY
,
2164 "Enable interrupts while stepping"
2165 " (default: disabled)");
2166 register_command(cmd_ctx
, top_cmd
, "vcr",
2167 arm11_handle_vcr
, COMMAND_ANY
,
2168 "Control (Interrupt) Vector Catch Register");
2170 return etm_register_commands(cmd_ctx
);
2173 /** Holds methods for ARM11xx targets. */
2174 struct target_type arm11_target
= {
2178 .arch_state
= arm11_arch_state
,
2180 .target_request_data
= arm11_target_request_data
,
2183 .resume
= arm11_resume
,
2186 .assert_reset
= arm11_assert_reset
,
2187 .deassert_reset
= arm11_deassert_reset
,
2188 .soft_reset_halt
= arm11_soft_reset_halt
,
2190 .get_gdb_reg_list
= arm11_get_gdb_reg_list
,
2192 .read_memory
= arm11_read_memory
,
2193 .write_memory
= arm11_write_memory
,
2195 .bulk_write_memory
= arm11_bulk_write_memory
,
2197 .checksum_memory
= arm_checksum_memory
,
2198 .blank_check_memory
= arm_blank_check_memory
,
2200 .add_breakpoint
= arm11_add_breakpoint
,
2201 .remove_breakpoint
= arm11_remove_breakpoint
,
2202 .add_watchpoint
= arm11_add_watchpoint
,
2203 .remove_watchpoint
= arm11_remove_watchpoint
,
2205 .run_algorithm
= arm11_run_algorithm
,
2207 .register_commands
= arm11_register_commands
,
2208 .target_create
= arm11_target_create
,
2209 .init_target
= arm11_init_target
,
2210 .examine
= arm11_examine
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)