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add timeouts and fix syntax error handling of mrc/mcr commands.
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm11.h"
30 #include "armv4_5.h"
31 #include "arm_simulator.h"
32 #include "target_type.h"
33
34
35 #if 0
36 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #endif
38
39 #if 0
40 #define FNC_INFO LOG_DEBUG("-")
41 #else
42 #define FNC_INFO
43 #endif
44
45 #if 1
46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
47 #else
48 #define FNC_INFO_NOTIMPLEMENTED
49 #endif
50
51 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
52
53 bool arm11_config_memwrite_burst = true;
54 bool arm11_config_memwrite_error_fatal = true;
55 uint32_t arm11_vcr = 0;
56 bool arm11_config_memrw_no_increment = false;
57 bool arm11_config_step_irq_enable = false;
58 bool arm11_config_hardware_step = false;
59
60 #define ARM11_HANDLER(x) \
61 .x = arm11_##x
62
63 target_type_t arm11_target =
64 {
65 .name = "arm11",
66
67 ARM11_HANDLER(poll),
68 ARM11_HANDLER(arch_state),
69
70 ARM11_HANDLER(target_request_data),
71
72 ARM11_HANDLER(halt),
73 ARM11_HANDLER(resume),
74 ARM11_HANDLER(step),
75
76 ARM11_HANDLER(assert_reset),
77 ARM11_HANDLER(deassert_reset),
78 ARM11_HANDLER(soft_reset_halt),
79
80 ARM11_HANDLER(get_gdb_reg_list),
81
82 ARM11_HANDLER(read_memory),
83 ARM11_HANDLER(write_memory),
84
85 ARM11_HANDLER(bulk_write_memory),
86
87 ARM11_HANDLER(checksum_memory),
88
89 ARM11_HANDLER(add_breakpoint),
90 ARM11_HANDLER(remove_breakpoint),
91 ARM11_HANDLER(add_watchpoint),
92 ARM11_HANDLER(remove_watchpoint),
93
94 ARM11_HANDLER(run_algorithm),
95
96 ARM11_HANDLER(register_commands),
97 ARM11_HANDLER(target_create),
98 ARM11_HANDLER(init_target),
99 ARM11_HANDLER(examine),
100 ARM11_HANDLER(quit),
101 };
102
103 int arm11_regs_arch_type = -1;
104
105
106 enum arm11_regtype
107 {
108 ARM11_REGISTER_CORE,
109 ARM11_REGISTER_CPSR,
110
111 ARM11_REGISTER_FX,
112 ARM11_REGISTER_FPS,
113
114 ARM11_REGISTER_FIQ,
115 ARM11_REGISTER_SVC,
116 ARM11_REGISTER_ABT,
117 ARM11_REGISTER_IRQ,
118 ARM11_REGISTER_UND,
119 ARM11_REGISTER_MON,
120
121 ARM11_REGISTER_SPSR_FIQ,
122 ARM11_REGISTER_SPSR_SVC,
123 ARM11_REGISTER_SPSR_ABT,
124 ARM11_REGISTER_SPSR_IRQ,
125 ARM11_REGISTER_SPSR_UND,
126 ARM11_REGISTER_SPSR_MON,
127
128 /* debug regs */
129 ARM11_REGISTER_DSCR,
130 ARM11_REGISTER_WDTR,
131 ARM11_REGISTER_RDTR,
132 };
133
134
135 typedef struct arm11_reg_defs_s
136 {
137 char * name;
138 uint32_t num;
139 int gdb_num;
140 enum arm11_regtype type;
141 } arm11_reg_defs_t;
142
143 /* update arm11_regcache_ids when changing this */
144 static const arm11_reg_defs_t arm11_reg_defs[] =
145 {
146 {"r0", 0, 0, ARM11_REGISTER_CORE},
147 {"r1", 1, 1, ARM11_REGISTER_CORE},
148 {"r2", 2, 2, ARM11_REGISTER_CORE},
149 {"r3", 3, 3, ARM11_REGISTER_CORE},
150 {"r4", 4, 4, ARM11_REGISTER_CORE},
151 {"r5", 5, 5, ARM11_REGISTER_CORE},
152 {"r6", 6, 6, ARM11_REGISTER_CORE},
153 {"r7", 7, 7, ARM11_REGISTER_CORE},
154 {"r8", 8, 8, ARM11_REGISTER_CORE},
155 {"r9", 9, 9, ARM11_REGISTER_CORE},
156 {"r10", 10, 10, ARM11_REGISTER_CORE},
157 {"r11", 11, 11, ARM11_REGISTER_CORE},
158 {"r12", 12, 12, ARM11_REGISTER_CORE},
159 {"sp", 13, 13, ARM11_REGISTER_CORE},
160 {"lr", 14, 14, ARM11_REGISTER_CORE},
161 {"pc", 15, 15, ARM11_REGISTER_CORE},
162
163 #if ARM11_REGCACHE_FREGS
164 {"f0", 0, 16, ARM11_REGISTER_FX},
165 {"f1", 1, 17, ARM11_REGISTER_FX},
166 {"f2", 2, 18, ARM11_REGISTER_FX},
167 {"f3", 3, 19, ARM11_REGISTER_FX},
168 {"f4", 4, 20, ARM11_REGISTER_FX},
169 {"f5", 5, 21, ARM11_REGISTER_FX},
170 {"f6", 6, 22, ARM11_REGISTER_FX},
171 {"f7", 7, 23, ARM11_REGISTER_FX},
172 {"fps", 0, 24, ARM11_REGISTER_FPS},
173 #endif
174
175 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
176
177 #if ARM11_REGCACHE_MODEREGS
178 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
179 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
180 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
181 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
182 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
183 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
184 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
185 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
186
187 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
188 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
189 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
190
191 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
192 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
193 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
194
195 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
196 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
197 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
198
199 {"r13_und", 13, -1, ARM11_REGISTER_UND},
200 {"r14_und", 14, -1, ARM11_REGISTER_UND},
201 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
202
203 /* ARM1176 only */
204 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
205 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
206 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
207 #endif
208
209 /* Debug Registers */
210 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
211 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
212 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
213 };
214
215 enum arm11_regcache_ids
216 {
217 ARM11_RC_R0,
218 ARM11_RC_RX = ARM11_RC_R0,
219
220 ARM11_RC_R1,
221 ARM11_RC_R2,
222 ARM11_RC_R3,
223 ARM11_RC_R4,
224 ARM11_RC_R5,
225 ARM11_RC_R6,
226 ARM11_RC_R7,
227 ARM11_RC_R8,
228 ARM11_RC_R9,
229 ARM11_RC_R10,
230 ARM11_RC_R11,
231 ARM11_RC_R12,
232 ARM11_RC_R13,
233 ARM11_RC_SP = ARM11_RC_R13,
234 ARM11_RC_R14,
235 ARM11_RC_LR = ARM11_RC_R14,
236 ARM11_RC_R15,
237 ARM11_RC_PC = ARM11_RC_R15,
238
239 #if ARM11_REGCACHE_FREGS
240 ARM11_RC_F0,
241 ARM11_RC_FX = ARM11_RC_F0,
242 ARM11_RC_F1,
243 ARM11_RC_F2,
244 ARM11_RC_F3,
245 ARM11_RC_F4,
246 ARM11_RC_F5,
247 ARM11_RC_F6,
248 ARM11_RC_F7,
249 ARM11_RC_FPS,
250 #endif
251
252 ARM11_RC_CPSR,
253
254 #if ARM11_REGCACHE_MODEREGS
255 ARM11_RC_R8_FIQ,
256 ARM11_RC_R9_FIQ,
257 ARM11_RC_R10_FIQ,
258 ARM11_RC_R11_FIQ,
259 ARM11_RC_R12_FIQ,
260 ARM11_RC_R13_FIQ,
261 ARM11_RC_R14_FIQ,
262 ARM11_RC_SPSR_FIQ,
263
264 ARM11_RC_R13_SVC,
265 ARM11_RC_R14_SVC,
266 ARM11_RC_SPSR_SVC,
267
268 ARM11_RC_R13_ABT,
269 ARM11_RC_R14_ABT,
270 ARM11_RC_SPSR_ABT,
271
272 ARM11_RC_R13_IRQ,
273 ARM11_RC_R14_IRQ,
274 ARM11_RC_SPSR_IRQ,
275
276 ARM11_RC_R13_UND,
277 ARM11_RC_R14_UND,
278 ARM11_RC_SPSR_UND,
279
280 ARM11_RC_R13_MON,
281 ARM11_RC_R14_MON,
282 ARM11_RC_SPSR_MON,
283 #endif
284
285 ARM11_RC_DSCR,
286 ARM11_RC_WDTR,
287 ARM11_RC_RDTR,
288
289 ARM11_RC_MAX,
290 };
291
292 #define ARM11_GDB_REGISTER_COUNT 26
293
294 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
295
296 reg_t arm11_gdb_dummy_fp_reg =
297 {
298 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
299 };
300
301 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
302
303 reg_t arm11_gdb_dummy_fps_reg =
304 {
305 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
306 };
307
308
309
310 /** Check and if necessary take control of the system
311 *
312 * \param arm11 Target state variable.
313 * \param dscr If the current DSCR content is
314 * available a pointer to a word holding the
315 * DSCR can be passed. Otherwise use NULL.
316 */
317 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
318 {
319 FNC_INFO;
320
321 uint32_t dscr_local_tmp_copy;
322
323 if (!dscr)
324 {
325 dscr = &dscr_local_tmp_copy;
326
327 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
328 }
329
330 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
331 {
332 LOG_DEBUG("Bringing target into debug mode");
333
334 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
335 arm11_write_DSCR(arm11, *dscr);
336
337 /* add further reset initialization here */
338
339 arm11->simulate_reset_on_next_halt = true;
340
341 if (*dscr & ARM11_DSCR_CORE_HALTED)
342 {
343 /** \todo TODO: this needs further scrutiny because
344 * arm11_on_enter_debug_state() never gets properly called.
345 * As a result we don't read the actual register states from
346 * the target.
347 */
348
349 arm11->target->state = TARGET_HALTED;
350 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
351 }
352 else
353 {
354 arm11->target->state = TARGET_RUNNING;
355 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
356 }
357
358 arm11_sc7_clear_vbw(arm11);
359 }
360
361 return ERROR_OK;
362 }
363
364
365
366 #define R(x) \
367 (arm11->reg_values[ARM11_RC_##x])
368
369 /** Save processor state.
370 *
371 * This is called when the HALT instruction has succeeded
372 * or on other occasions that stop the processor.
373 *
374 */
375 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
376 {
377 int retval;
378 FNC_INFO;
379
380 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
381 {
382 arm11->reg_list[i].valid = 1;
383 arm11->reg_list[i].dirty = 0;
384 }
385
386 /* Save DSCR */
387 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
388
389 /* Save wDTR */
390
391 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
392 {
393 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
394
395 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
396
397 scan_field_t chain5_fields[3];
398
399 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
400 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
401 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
402
403 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
404 }
405 else
406 {
407 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
408 }
409
410
411 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
412 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
413 ARM1136 seems to require this to issue ITR's as well */
414
415 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
416
417 /* this executes JTAG queue: */
418
419 arm11_write_DSCR(arm11, new_dscr);
420
421
422 /* From the spec:
423 Before executing any instruction in debug state you have to drain the write buffer.
424 This ensures that no imprecise Data Aborts can return at a later point:*/
425
426 /** \todo TODO: Test drain write buffer. */
427
428 #if 0
429 while (1)
430 {
431 /* MRC p14,0,R0,c5,c10,0 */
432 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
433
434 /* mcr 15, 0, r0, cr7, cr10, {4} */
435 arm11_run_instr_no_data1(arm11, 0xee070f9a);
436
437 uint32_t dscr = arm11_read_DSCR(arm11);
438
439 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
440
441 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
442 {
443 arm11_run_instr_no_data1(arm11, 0xe320f000);
444
445 dscr = arm11_read_DSCR(arm11);
446
447 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
448
449 break;
450 }
451 }
452 #endif
453
454 arm11_run_instr_data_prepare(arm11);
455
456 /* save r0 - r14 */
457
458 /** \todo TODO: handle other mode registers */
459
460 for (size_t i = 0; i < 15; i++)
461 {
462 /* MCR p14,0,R?,c0,c5,0 */
463 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
464 if (retval != ERROR_OK)
465 return retval;
466 }
467
468 /* save rDTR */
469
470 /* check rDTRfull in DSCR */
471
472 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
473 {
474 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
475 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
476 }
477 else
478 {
479 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
480 }
481
482 /* save CPSR */
483
484 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
485 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
486
487 /* save PC */
488
489 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
490 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
491 if (retval != ERROR_OK)
492 return retval;
493
494 /* adjust PC depending on ARM state */
495
496 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
497 {
498 arm11->reg_values[ARM11_RC_PC] -= 0;
499 }
500 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
501 {
502 arm11->reg_values[ARM11_RC_PC] -= 4;
503 }
504 else /* ARM state */
505 {
506 arm11->reg_values[ARM11_RC_PC] -= 8;
507 }
508
509 if (arm11->simulate_reset_on_next_halt)
510 {
511 arm11->simulate_reset_on_next_halt = false;
512
513 LOG_DEBUG("Reset c1 Control Register");
514
515 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
516
517 /* MCR p15,0,R0,c1,c0,0 */
518 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
519
520 }
521
522 arm11_run_instr_data_finish(arm11);
523
524 arm11_dump_reg_changes(arm11);
525
526 return ERROR_OK;
527 }
528
529 void arm11_dump_reg_changes(arm11_common_t * arm11)
530 {
531
532 if (!(debug_level >= LOG_LVL_DEBUG))
533 {
534 return;
535 }
536
537 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
538 {
539 if (!arm11->reg_list[i].valid)
540 {
541 if (arm11->reg_history[i].valid)
542 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
543 }
544 else
545 {
546 if (arm11->reg_history[i].valid)
547 {
548 if (arm11->reg_history[i].value != arm11->reg_values[i])
549 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
550 }
551 else
552 {
553 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
554 }
555 }
556 }
557 }
558
559 /** Restore processor state
560 *
561 * This is called in preparation for the RESTART function.
562 *
563 */
564 int arm11_leave_debug_state(arm11_common_t * arm11)
565 {
566 FNC_INFO;
567
568 arm11_run_instr_data_prepare(arm11);
569
570 /** \todo TODO: handle other mode registers */
571
572 /* restore R1 - R14 */
573
574 for (size_t i = 1; i < 15; i++)
575 {
576 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
577 continue;
578
579 /* MRC p14,0,r?,c0,c5,0 */
580 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
581
582 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
583 }
584
585 arm11_run_instr_data_finish(arm11);
586
587 /* spec says clear wDTR and rDTR; we assume they are clear as
588 otherwise our programming would be sloppy */
589 {
590 uint32_t DSCR;
591
592 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
593
594 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
595 {
596 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
597 }
598 }
599
600 arm11_run_instr_data_prepare(arm11);
601
602 /* restore original wDTR */
603
604 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
605 {
606 /* MCR p14,0,R0,c0,c5,0 */
607 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
608 }
609
610 /* restore CPSR */
611
612 /* MSR CPSR,R0*/
613 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
614
615 /* restore PC */
616
617 /* MOV PC,R0 */
618 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
619
620 /* restore R0 */
621
622 /* MRC p14,0,r0,c0,c5,0 */
623 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
624
625 arm11_run_instr_data_finish(arm11);
626
627 /* restore DSCR */
628
629 arm11_write_DSCR(arm11, R(DSCR));
630
631 /* restore rDTR */
632
633 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
634 {
635 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
636
637 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
638
639 scan_field_t chain5_fields[3];
640
641 uint8_t Ready = 0; /* ignored */
642 uint8_t Valid = 0; /* ignored */
643
644 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
645 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
646 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
647
648 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
649 }
650
651 arm11_record_register_history(arm11);
652
653 return ERROR_OK;
654 }
655
656 void arm11_record_register_history(arm11_common_t * arm11)
657 {
658 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
659 {
660 arm11->reg_history[i].value = arm11->reg_values[i];
661 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
662
663 arm11->reg_list[i].valid = 0;
664 arm11->reg_list[i].dirty = 0;
665 }
666 }
667
668
669 /* poll current target status */
670 int arm11_poll(struct target_s *target)
671 {
672 FNC_INFO;
673 int retval;
674
675 arm11_common_t * arm11 = target->arch_info;
676
677 if (arm11->trst_active)
678 return ERROR_OK;
679
680 uint32_t dscr;
681
682 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
683
684 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
685
686 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
687
688 if (dscr & ARM11_DSCR_CORE_HALTED)
689 {
690 if (target->state != TARGET_HALTED)
691 {
692 enum target_state old_state = target->state;
693
694 LOG_DEBUG("enter TARGET_HALTED");
695 target->state = TARGET_HALTED;
696 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
697 retval = arm11_on_enter_debug_state(arm11);
698 if (retval != ERROR_OK)
699 return retval;
700
701 target_call_event_callbacks(target,
702 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
703 }
704 }
705 else
706 {
707 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
708 {
709 LOG_DEBUG("enter TARGET_RUNNING");
710 target->state = TARGET_RUNNING;
711 target->debug_reason = DBG_REASON_NOTHALTED;
712 }
713 }
714
715 return ERROR_OK;
716 }
717 /* architecture specific status reply */
718 int arm11_arch_state(struct target_s *target)
719 {
720 arm11_common_t * arm11 = target->arch_info;
721
722 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
723 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
724 R(CPSR),
725 R(PC));
726
727 return ERROR_OK;
728 }
729
730 /* target request support */
731 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
732 {
733 FNC_INFO_NOTIMPLEMENTED;
734
735 return ERROR_OK;
736 }
737
738 /* target execution control */
739 int arm11_halt(struct target_s *target)
740 {
741 FNC_INFO;
742
743 arm11_common_t * arm11 = target->arch_info;
744
745 LOG_DEBUG("target->state: %s",
746 target_state_name(target));
747
748 if (target->state == TARGET_UNKNOWN)
749 {
750 arm11->simulate_reset_on_next_halt = true;
751 }
752
753 if (target->state == TARGET_HALTED)
754 {
755 LOG_DEBUG("target was already halted");
756 return ERROR_OK;
757 }
758
759 if (arm11->trst_active)
760 {
761 arm11->halt_requested = true;
762 return ERROR_OK;
763 }
764
765 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
766
767 CHECK_RETVAL(jtag_execute_queue());
768
769 uint32_t dscr;
770
771 int i = 0;
772 while (1)
773 {
774 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
775
776 if (dscr & ARM11_DSCR_CORE_HALTED)
777 break;
778
779
780 long long then = 0;
781 if (i == 1000)
782 {
783 then = timeval_ms();
784 }
785 if (i >= 1000)
786 {
787 if ((timeval_ms()-then) > 1000)
788 {
789 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
790 return ERROR_FAIL;
791 }
792 }
793 i++;
794 }
795
796 arm11_on_enter_debug_state(arm11);
797
798 enum target_state old_state = target->state;
799
800 target->state = TARGET_HALTED;
801 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
802
803 CHECK_RETVAL(
804 target_call_event_callbacks(target,
805 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
806
807 return ERROR_OK;
808 }
809
810 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
811 {
812 FNC_INFO;
813
814 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
815 // current, address, handle_breakpoints, debug_execution);
816
817 arm11_common_t * arm11 = target->arch_info;
818
819 LOG_DEBUG("target->state: %s",
820 target_state_name(target));
821
822
823 if (target->state != TARGET_HALTED)
824 {
825 LOG_ERROR("Target not halted");
826 return ERROR_TARGET_NOT_HALTED;
827 }
828
829 if (!current)
830 R(PC) = address;
831
832 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
833
834 /* clear breakpoints/watchpoints and VCR*/
835 arm11_sc7_clear_vbw(arm11);
836
837 /* Set up breakpoints */
838 if (!debug_execution)
839 {
840 /* check if one matches PC and step over it if necessary */
841
842 breakpoint_t * bp;
843
844 for (bp = target->breakpoints; bp; bp = bp->next)
845 {
846 if (bp->address == R(PC))
847 {
848 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
849 arm11_step(target, 1, 0, 0);
850 break;
851 }
852 }
853
854 /* set all breakpoints */
855
856 size_t brp_num = 0;
857
858 for (bp = target->breakpoints; bp; bp = bp->next)
859 {
860 arm11_sc7_action_t brp[2];
861
862 brp[0].write = 1;
863 brp[0].address = ARM11_SC7_BVR0 + brp_num;
864 brp[0].value = bp->address;
865 brp[1].write = 1;
866 brp[1].address = ARM11_SC7_BCR0 + brp_num;
867 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
868
869 arm11_sc7_run(arm11, brp, asizeof(brp));
870
871 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
872
873 brp_num++;
874 }
875
876 arm11_sc7_set_vcr(arm11, arm11_vcr);
877 }
878
879 arm11_leave_debug_state(arm11);
880
881 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
882
883 CHECK_RETVAL(jtag_execute_queue());
884
885 int i = 0;
886 while (1)
887 {
888 uint32_t dscr;
889
890 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
891
892 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
893
894 if (dscr & ARM11_DSCR_CORE_RESTARTED)
895 break;
896
897
898 long long then = 0;
899 if (i == 1000)
900 {
901 then = timeval_ms();
902 }
903 if (i >= 1000)
904 {
905 if ((timeval_ms()-then) > 1000)
906 {
907 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
908 return ERROR_FAIL;
909 }
910 }
911 i++;
912 }
913
914 if (!debug_execution)
915 {
916 target->state = TARGET_RUNNING;
917 target->debug_reason = DBG_REASON_NOTHALTED;
918
919 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
920 }
921 else
922 {
923 target->state = TARGET_DEBUG_RUNNING;
924 target->debug_reason = DBG_REASON_NOTHALTED;
925
926 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
927 }
928
929 return ERROR_OK;
930 }
931
932
933 static int armv4_5_to_arm11(int reg)
934 {
935 if (reg < 16)
936 return reg;
937 switch (reg)
938 {
939 case ARMV4_5_CPSR:
940 return ARM11_RC_CPSR;
941 case 16:
942 /* FIX!!! handle thumb better! */
943 return ARM11_RC_CPSR;
944 default:
945 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
946 exit(-1);
947 }
948 }
949
950
951 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
952 {
953 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
954
955 reg=armv4_5_to_arm11(reg);
956
957 return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
958 }
959
960 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
961 {
962 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
963
964 reg=armv4_5_to_arm11(reg);
965
966 buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
967 }
968
969 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
970 {
971 arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
972
973 return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
974 }
975
976 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
977 {
978 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
979
980 /* FIX!!!! we should implement thumb for arm11 */
981 return ARMV4_5_STATE_ARM;
982 }
983
984 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
985 {
986 // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
987
988 /* FIX!!!! we should implement thumb for arm11 */
989 LOG_ERROR("Not implemetned!");
990 }
991
992
993 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
994 {
995 //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
996
997 /* FIX!!!! we should implement something that returns the current mode here!!! */
998 return ARMV4_5_MODE_USR;
999 }
1000
1001 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
1002 {
1003 struct arm_sim_interface sim;
1004
1005 sim.user_data=target->arch_info;
1006 sim.get_reg=&arm11_sim_get_reg;
1007 sim.set_reg=&arm11_sim_set_reg;
1008 sim.get_reg_mode=&arm11_sim_get_reg;
1009 sim.set_reg_mode=&arm11_sim_set_reg;
1010 sim.get_cpsr=&arm11_sim_get_cpsr;
1011 sim.get_mode=&arm11_sim_get_mode;
1012 sim.get_state=&arm11_sim_get_state;
1013 sim.set_state=&arm11_sim_set_state;
1014
1015 return arm_simulate_step_core(target, dry_run_pc, &sim);
1016
1017 }
1018
1019 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
1020 {
1021 FNC_INFO;
1022
1023 LOG_DEBUG("target->state: %s",
1024 target_state_name(target));
1025
1026 if (target->state != TARGET_HALTED)
1027 {
1028 LOG_WARNING("target was not halted");
1029 return ERROR_TARGET_NOT_HALTED;
1030 }
1031
1032 arm11_common_t * arm11 = target->arch_info;
1033
1034 if (!current)
1035 R(PC) = address;
1036
1037 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
1038
1039
1040 /** \todo TODO: Thumb not supported here */
1041
1042 uint32_t next_instruction;
1043
1044 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1045
1046 /* skip over BKPT */
1047 if ((next_instruction & 0xFFF00070) == 0xe1200070)
1048 {
1049 R(PC) += 4;
1050 arm11->reg_list[ARM11_RC_PC].valid = 1;
1051 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1052 LOG_DEBUG("Skipping BKPT");
1053 }
1054 /* skip over Wait for interrupt / Standby */
1055 /* mcr 15, 0, r?, cr7, cr0, {4} */
1056 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1057 {
1058 R(PC) += 4;
1059 arm11->reg_list[ARM11_RC_PC].valid = 1;
1060 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1061 LOG_DEBUG("Skipping WFI");
1062 }
1063 /* ignore B to self */
1064 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1065 {
1066 LOG_DEBUG("Not stepping jump to self");
1067 }
1068 else
1069 {
1070 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1071 * with this. */
1072
1073 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1074 * the VCR might be something worth looking into. */
1075
1076
1077 /* Set up breakpoint for stepping */
1078
1079 arm11_sc7_action_t brp[2];
1080
1081 brp[0].write = 1;
1082 brp[0].address = ARM11_SC7_BVR0;
1083 brp[1].write = 1;
1084 brp[1].address = ARM11_SC7_BCR0;
1085
1086 if (arm11_config_hardware_step)
1087 {
1088 /* hardware single stepping be used if possible or is it better to
1089 * always use the same code path? Hardware single stepping is not supported
1090 * on all hardware
1091 */
1092 brp[0].value = R(PC);
1093 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1094 } else
1095 {
1096 /* sets a breakpoint on the next PC(calculated by simulation),
1097 */
1098 uint32_t next_pc;
1099 int retval;
1100 retval = arm11_simulate_step(target, &next_pc);
1101 if (retval != ERROR_OK)
1102 return retval;
1103
1104 brp[0].value = next_pc;
1105 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
1106 }
1107
1108 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1109
1110 /* resume */
1111
1112
1113 if (arm11_config_step_irq_enable)
1114 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
1115 else
1116 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1117
1118
1119 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1120
1121 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1122
1123 CHECK_RETVAL(jtag_execute_queue());
1124
1125 /* wait for halt */
1126 int i = 0;
1127 while (1)
1128 {
1129 uint32_t dscr;
1130
1131 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1132
1133 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1134
1135 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1136 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1137 break;
1138
1139 long long then = 0;
1140 if (i == 1000)
1141 {
1142 then = timeval_ms();
1143 }
1144 if (i >= 1000)
1145 {
1146 if ((timeval_ms()-then) > 1000)
1147 {
1148 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
1149 return ERROR_FAIL;
1150 }
1151 }
1152 i++;
1153 }
1154
1155 /* clear breakpoint */
1156 arm11_sc7_clear_vbw(arm11);
1157
1158 /* save state */
1159 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1160
1161 /* restore default state */
1162 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1163
1164 }
1165
1166 // target->state = TARGET_HALTED;
1167 target->debug_reason = DBG_REASON_SINGLESTEP;
1168
1169 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1170
1171 return ERROR_OK;
1172 }
1173
1174 /* target reset control */
1175 int arm11_assert_reset(struct target_s *target)
1176 {
1177 FNC_INFO;
1178
1179 #if 0
1180 /* assert reset lines */
1181 /* resets only the DBGTAP, not the ARM */
1182
1183 jtag_add_reset(1, 0);
1184 jtag_add_sleep(5000);
1185
1186 arm11_common_t * arm11 = target->arch_info;
1187 arm11->trst_active = true;
1188 #endif
1189
1190 if (target->reset_halt)
1191 {
1192 CHECK_RETVAL(target_halt(target));
1193 }
1194
1195 return ERROR_OK;
1196 }
1197
1198 int arm11_deassert_reset(struct target_s *target)
1199 {
1200 FNC_INFO;
1201
1202 #if 0
1203 LOG_DEBUG("target->state: %s",
1204 target_state_name(target));
1205
1206
1207 /* deassert reset lines */
1208 jtag_add_reset(0, 0);
1209
1210 arm11_common_t * arm11 = target->arch_info;
1211 arm11->trst_active = false;
1212
1213 if (arm11->halt_requested)
1214 return arm11_halt(target);
1215 #endif
1216
1217 return ERROR_OK;
1218 }
1219
1220 int arm11_soft_reset_halt(struct target_s *target)
1221 {
1222 FNC_INFO_NOTIMPLEMENTED;
1223
1224 return ERROR_OK;
1225 }
1226
1227 /* target register access for gdb */
1228 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1229 {
1230 FNC_INFO;
1231
1232 arm11_common_t * arm11 = target->arch_info;
1233
1234 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1235 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1236
1237 for (size_t i = 16; i < 24; i++)
1238 {
1239 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1240 }
1241
1242 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1243
1244 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1245 {
1246 if (arm11_reg_defs[i].gdb_num == -1)
1247 continue;
1248
1249 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1250 }
1251
1252 return ERROR_OK;
1253 }
1254
1255 /* target memory access
1256 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1257 * count: number of items of <size>
1258 */
1259 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1260 {
1261 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1262
1263 FNC_INFO;
1264
1265 if (target->state != TARGET_HALTED)
1266 {
1267 LOG_WARNING("target was not halted");
1268 return ERROR_TARGET_NOT_HALTED;
1269 }
1270
1271 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1272
1273 arm11_common_t * arm11 = target->arch_info;
1274
1275 arm11_run_instr_data_prepare(arm11);
1276
1277 /* MRC p14,0,r0,c0,c5,0 */
1278 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1279
1280 switch (size)
1281 {
1282 case 1:
1283 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1284 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1285
1286 for (size_t i = 0; i < count; i++)
1287 {
1288 /* ldrb r1, [r0], #1 */
1289 /* ldrb r1, [r0] */
1290 arm11_run_instr_no_data1(arm11,
1291 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1292
1293 uint32_t res;
1294 /* MCR p14,0,R1,c0,c5,0 */
1295 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1296
1297 *buffer++ = res;
1298 }
1299
1300 break;
1301
1302 case 2:
1303 {
1304 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1305
1306 for (size_t i = 0; i < count; i++)
1307 {
1308 /* ldrh r1, [r0], #2 */
1309 arm11_run_instr_no_data1(arm11,
1310 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1311
1312 uint32_t res;
1313
1314 /* MCR p14,0,R1,c0,c5,0 */
1315 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1316
1317 uint16_t svalue = res;
1318 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1319 }
1320
1321 break;
1322 }
1323
1324 case 4:
1325 {
1326 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1327 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1328 uint32_t *words = (uint32_t *)buffer;
1329
1330 /* LDC p14,c5,[R0],#4 */
1331 /* LDC p14,c5,[R0] */
1332 arm11_run_instr_data_from_core(arm11, instr, words, count);
1333 break;
1334 }
1335 }
1336
1337 arm11_run_instr_data_finish(arm11);
1338
1339 return ERROR_OK;
1340 }
1341
1342 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1343 {
1344 FNC_INFO;
1345
1346 if (target->state != TARGET_HALTED)
1347 {
1348 LOG_WARNING("target was not halted");
1349 return ERROR_TARGET_NOT_HALTED;
1350 }
1351
1352 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1353
1354 arm11_common_t * arm11 = target->arch_info;
1355
1356 arm11_run_instr_data_prepare(arm11);
1357
1358 /* MRC p14,0,r0,c0,c5,0 */
1359 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1360
1361 switch (size)
1362 {
1363 case 1:
1364 {
1365 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1366
1367 for (size_t i = 0; i < count; i++)
1368 {
1369 /* MRC p14,0,r1,c0,c5,0 */
1370 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1371
1372 /* strb r1, [r0], #1 */
1373 /* strb r1, [r0] */
1374 arm11_run_instr_no_data1(arm11,
1375 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1376 }
1377
1378 break;
1379 }
1380
1381 case 2:
1382 {
1383 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1384
1385 for (size_t i = 0; i < count; i++)
1386 {
1387 uint16_t value;
1388 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1389
1390 /* MRC p14,0,r1,c0,c5,0 */
1391 arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1392
1393 /* strh r1, [r0], #2 */
1394 /* strh r1, [r0] */
1395 arm11_run_instr_no_data1(arm11,
1396 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1397 }
1398
1399 break;
1400 }
1401
1402 case 4: {
1403 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1404
1405 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1406 uint32_t *words = (uint32_t*)buffer;
1407
1408 if (!arm11_config_memwrite_burst)
1409 {
1410 /* STC p14,c5,[R0],#4 */
1411 /* STC p14,c5,[R0]*/
1412 arm11_run_instr_data_to_core(arm11, instr, words, count);
1413 }
1414 else
1415 {
1416 /* STC p14,c5,[R0],#4 */
1417 /* STC p14,c5,[R0]*/
1418 arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1419 }
1420
1421 break;
1422 }
1423 }
1424
1425 #if 1
1426 /* r0 verification */
1427 if (!arm11_config_memrw_no_increment)
1428 {
1429 uint32_t r0;
1430
1431 /* MCR p14,0,R0,c0,c5,0 */
1432 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1433
1434 if (address + size * count != r0)
1435 {
1436 LOG_ERROR("Data transfer failed. Expected end address 0x%08x, got 0x%08x",
1437 address + size * count, r0);
1438
1439 if (arm11_config_memwrite_burst)
1440 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1441
1442 if (arm11_config_memwrite_error_fatal)
1443 return ERROR_FAIL;
1444 }
1445 }
1446 #endif
1447
1448 arm11_run_instr_data_finish(arm11);
1449
1450 return ERROR_OK;
1451 }
1452
1453
1454 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1455 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1456 {
1457 FNC_INFO;
1458
1459 if (target->state != TARGET_HALTED)
1460 {
1461 LOG_WARNING("target was not halted");
1462 return ERROR_TARGET_NOT_HALTED;
1463 }
1464
1465 return arm11_write_memory(target, address, 4, count, buffer);
1466 }
1467
1468 /* here we have nothing target specific to contribute, so we fail and then the
1469 * fallback code will read data from the target and calculate the CRC on the
1470 * host.
1471 */
1472 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1473 {
1474 return ERROR_FAIL;
1475 }
1476
1477 /* target break-/watchpoint control
1478 * rw: 0 = write, 1 = read, 2 = access
1479 */
1480 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1481 {
1482 FNC_INFO;
1483
1484 arm11_common_t * arm11 = target->arch_info;
1485
1486 #if 0
1487 if (breakpoint->type == BKPT_SOFT)
1488 {
1489 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1490 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1491 }
1492 #endif
1493
1494 if (!arm11->free_brps)
1495 {
1496 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1497 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1498 }
1499
1500 if (breakpoint->length != 4)
1501 {
1502 LOG_DEBUG("only breakpoints of four bytes length supported");
1503 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1504 }
1505
1506 arm11->free_brps--;
1507
1508 return ERROR_OK;
1509 }
1510
1511 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1512 {
1513 FNC_INFO;
1514
1515 arm11_common_t * arm11 = target->arch_info;
1516
1517 arm11->free_brps++;
1518
1519 return ERROR_OK;
1520 }
1521
1522 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1523 {
1524 FNC_INFO_NOTIMPLEMENTED;
1525
1526 return ERROR_OK;
1527 }
1528
1529 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1530 {
1531 FNC_INFO_NOTIMPLEMENTED;
1532
1533 return ERROR_OK;
1534 }
1535
1536 // HACKHACKHACK - FIXME mode/state
1537 /* target algorithm support */
1538 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1539 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1540 int timeout_ms, void *arch_info)
1541 {
1542 arm11_common_t *arm11 = target->arch_info;
1543 // enum armv4_5_state core_state = arm11->core_state;
1544 // enum armv4_5_mode core_mode = arm11->core_mode;
1545 uint32_t context[16];
1546 uint32_t cpsr;
1547 int exit_breakpoint_size = 0;
1548 int retval = ERROR_OK;
1549 LOG_DEBUG("Running algorithm");
1550
1551
1552 if (target->state != TARGET_HALTED)
1553 {
1554 LOG_WARNING("target not halted");
1555 return ERROR_TARGET_NOT_HALTED;
1556 }
1557
1558 // FIXME
1559 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1560 // return ERROR_FAIL;
1561
1562 // Save regs
1563 for (size_t i = 0; i < 16; i++)
1564 {
1565 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1566 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1567 }
1568
1569 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1570 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1571
1572 for (int i = 0; i < num_mem_params; i++)
1573 {
1574 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1575 }
1576
1577 // Set register parameters
1578 for (int i = 0; i < num_reg_params; i++)
1579 {
1580 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1581 if (!reg)
1582 {
1583 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1584 exit(-1);
1585 }
1586
1587 if (reg->size != reg_params[i].size)
1588 {
1589 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1590 exit(-1);
1591 }
1592 arm11_set_reg(reg,reg_params[i].value);
1593 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1594 }
1595
1596 exit_breakpoint_size = 4;
1597
1598 /* arm11->core_state = arm11_algorithm_info->core_state;
1599 if (arm11->core_state == ARMV4_5_STATE_ARM)
1600 exit_breakpoint_size = 4;
1601 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1602 exit_breakpoint_size = 2;
1603 else
1604 {
1605 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1606 exit(-1);
1607 }
1608 */
1609
1610
1611 /* arm11 at this point only supports ARM not THUMB mode
1612 however if this test needs to be reactivated the current state can be read back
1613 from CPSR */
1614 #if 0
1615 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1616 {
1617 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1618 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1619 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1620 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1621 }
1622 #endif
1623
1624 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1625 {
1626 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1627 retval = ERROR_TARGET_FAILURE;
1628 goto restore;
1629 }
1630
1631 // no debug, otherwise breakpoint is not set
1632 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1633
1634 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1635
1636 if (target->state != TARGET_HALTED)
1637 {
1638 CHECK_RETVAL(target_halt(target));
1639
1640 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1641
1642 retval = ERROR_TARGET_TIMEOUT;
1643
1644 goto del_breakpoint;
1645 }
1646
1647 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1648 {
1649 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1650 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1651 retval = ERROR_TARGET_TIMEOUT;
1652 goto del_breakpoint;
1653 }
1654
1655 for (int i = 0; i < num_mem_params; i++)
1656 {
1657 if (mem_params[i].direction != PARAM_OUT)
1658 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1659 }
1660
1661 for (int i = 0; i < num_reg_params; i++)
1662 {
1663 if (reg_params[i].direction != PARAM_OUT)
1664 {
1665 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1666 if (!reg)
1667 {
1668 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1669 exit(-1);
1670 }
1671
1672 if (reg->size != reg_params[i].size)
1673 {
1674 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1675 exit(-1);
1676 }
1677
1678 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1679 }
1680 }
1681
1682 del_breakpoint:
1683 breakpoint_remove(target, exit_point);
1684
1685 restore:
1686 // Restore context
1687 for (size_t i = 0; i < 16; i++)
1688 {
1689 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1690 arm11->reg_list[i].name, context[i]);
1691 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1692 }
1693 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1694 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1695
1696 // arm11->core_state = core_state;
1697 // arm11->core_mode = core_mode;
1698
1699 return retval;
1700 }
1701
1702 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1703 {
1704 FNC_INFO;
1705
1706 NEW(arm11_common_t, arm11, 1);
1707
1708 arm11->target = target;
1709
1710 if (target->tap == NULL)
1711 return ERROR_FAIL;
1712
1713 if (target->tap->ir_length != 5)
1714 {
1715 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1716 return ERROR_COMMAND_SYNTAX_ERROR;
1717 }
1718
1719 target->arch_info = arm11;
1720
1721 return ERROR_OK;
1722 }
1723
1724 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1725 {
1726 /* Initialize anything we can set up without talking to the target */
1727 return arm11_build_reg_cache(target);
1728 }
1729
1730 /* talk to the target and set things up */
1731 int arm11_examine(struct target_s *target)
1732 {
1733 FNC_INFO;
1734
1735 arm11_common_t * arm11 = target->arch_info;
1736
1737 /* check IDCODE */
1738
1739 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1740
1741 scan_field_t idcode_field;
1742
1743 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1744
1745 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1746
1747 /* check DIDR */
1748
1749 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1750
1751 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1752
1753 scan_field_t chain0_fields[2];
1754
1755 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1756 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1757
1758 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1759
1760 CHECK_RETVAL(jtag_execute_queue());
1761
1762 switch (arm11->device_id & 0x0FFFF000)
1763 {
1764 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1765 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1766 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1767 default:
1768 {
1769 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1770 return ERROR_FAIL;
1771 }
1772 }
1773
1774 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1775
1776 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1777 arm11->debug_version != ARM11_DEBUG_V61)
1778 {
1779 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1780 return ERROR_FAIL;
1781 }
1782
1783 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1784 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1785
1786 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1787 arm11->free_brps = arm11->brp;
1788 arm11->free_wrps = arm11->wrp;
1789
1790 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1791 arm11->device_id,
1792 (int)(arm11->implementor),
1793 arm11->didr);
1794
1795 /* as a side-effect this reads DSCR and thus
1796 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1797 * as suggested by the spec.
1798 */
1799
1800 arm11_check_init(arm11, NULL);
1801
1802 target_set_examined(target);
1803
1804 return ERROR_OK;
1805 }
1806
1807 int arm11_quit(void)
1808 {
1809 FNC_INFO_NOTIMPLEMENTED;
1810
1811 return ERROR_OK;
1812 }
1813
1814 /** Load a register that is marked !valid in the register cache */
1815 int arm11_get_reg(reg_t *reg)
1816 {
1817 FNC_INFO;
1818
1819 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1820
1821 if (target->state != TARGET_HALTED)
1822 {
1823 LOG_WARNING("target was not halted");
1824 return ERROR_TARGET_NOT_HALTED;
1825 }
1826
1827 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1828
1829 #if 0
1830 arm11_common_t *arm11 = target->arch_info;
1831 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1832 #endif
1833
1834 return ERROR_OK;
1835 }
1836
1837 /** Change a value in the register cache */
1838 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1839 {
1840 FNC_INFO;
1841
1842 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1843 arm11_common_t *arm11 = target->arch_info;
1844 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1845
1846 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1847 reg->valid = 1;
1848 reg->dirty = 1;
1849
1850 return ERROR_OK;
1851 }
1852
1853 int arm11_build_reg_cache(target_t *target)
1854 {
1855 arm11_common_t *arm11 = target->arch_info;
1856
1857 NEW(reg_cache_t, cache, 1);
1858 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1859 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1860
1861 if (arm11_regs_arch_type == -1)
1862 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1863
1864 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1865 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1866
1867 arm11->reg_list = reg_list;
1868
1869 /* Build the process context cache */
1870 cache->name = "arm11 registers";
1871 cache->next = NULL;
1872 cache->reg_list = reg_list;
1873 cache->num_regs = ARM11_REGCACHE_COUNT;
1874
1875 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1876 (*cache_p) = cache;
1877
1878 arm11->core_cache = cache;
1879 // armv7m->process_context = cache;
1880
1881 size_t i;
1882
1883 /* Not very elegant assertion */
1884 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1885 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1886 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1887 {
1888 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1889 exit(-1);
1890 }
1891
1892 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1893 {
1894 reg_t * r = reg_list + i;
1895 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1896 arm11_reg_state_t * rs = arm11_reg_states + i;
1897
1898 r->name = rd->name;
1899 r->size = 32;
1900 r->value = (uint8_t *)(arm11->reg_values + i);
1901 r->dirty = 0;
1902 r->valid = 0;
1903 r->bitfield_desc = NULL;
1904 r->num_bitfields = 0;
1905 r->arch_type = arm11_regs_arch_type;
1906 r->arch_info = rs;
1907
1908 rs->def_index = i;
1909 rs->target = target;
1910 }
1911
1912 return ERROR_OK;
1913 }
1914
1915 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1916 {
1917 if (argc == 0)
1918 {
1919 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1920 return ERROR_OK;
1921 }
1922
1923 if (argc != 1)
1924 return ERROR_COMMAND_SYNTAX_ERROR;
1925
1926 switch (args[0][0])
1927 {
1928 case '0': /* 0 */
1929 case 'f': /* false */
1930 case 'F':
1931 case 'd': /* disable */
1932 case 'D':
1933 *var = false;
1934 break;
1935
1936 case '1': /* 1 */
1937 case 't': /* true */
1938 case 'T':
1939 case 'e': /* enable */
1940 case 'E':
1941 *var = true;
1942 break;
1943 }
1944
1945 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1946
1947 return ERROR_OK;
1948 }
1949
1950 #define BOOL_WRAPPER(name, print_name) \
1951 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1952 { \
1953 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1954 }
1955
1956 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1957 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1958 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
1959 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1960 BOOL_WRAPPER(hardware_step, "hardware single step")
1961
1962 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1963 {
1964 if (argc == 1)
1965 {
1966 arm11_vcr = strtoul(args[0], NULL, 0);
1967 }
1968 else if (argc != 0)
1969 {
1970 return ERROR_COMMAND_SYNTAX_ERROR;
1971 }
1972
1973 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1974 return ERROR_OK;
1975 }
1976
1977 const uint32_t arm11_coproc_instruction_limits[] =
1978 {
1979 15, /* coprocessor */
1980 7, /* opcode 1 */
1981 15, /* CRn */
1982 15, /* CRm */
1983 7, /* opcode 2 */
1984 0xFFFFFFFF, /* value */
1985 };
1986
1987 arm11_common_t * arm11_find_target(const char * arg)
1988 {
1989 jtag_tap_t * tap;
1990 target_t * t;
1991
1992 tap = jtag_tap_by_string(arg);
1993
1994 if (!tap)
1995 return 0;
1996
1997 for (t = all_targets; t; t = t->next)
1998 {
1999 if (t->tap != tap)
2000 continue;
2001
2002 /* if (t->type == arm11_target) */
2003 if (0 == strcmp(target_get_name(t), "arm11"))
2004 return t->arch_info;
2005 }
2006
2007 return 0;
2008 }
2009
2010 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
2011 {
2012 if (argc != (read ? 6 : 7))
2013 {
2014 LOG_ERROR("Invalid number of arguments.");
2015 return ERROR_COMMAND_SYNTAX_ERROR;
2016 }
2017
2018 arm11_common_t * arm11 = arm11_find_target(args[0]);
2019
2020 if (!arm11)
2021 {
2022 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
2023 return ERROR_COMMAND_SYNTAX_ERROR;
2024 }
2025
2026 if (arm11->target->state != TARGET_HALTED)
2027 {
2028 LOG_WARNING("target was not halted");
2029 return ERROR_TARGET_NOT_HALTED;
2030 }
2031
2032 uint32_t values[6];
2033
2034 for (size_t i = 0; i < (read ? 5 : 6); i++)
2035 {
2036 values[i] = strtoul(args[i + 1], NULL, 0);
2037
2038 if (values[i] > arm11_coproc_instruction_limits[i])
2039 {
2040 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
2041 (long)(i + 2),
2042 arm11_coproc_instruction_limits[i]);
2043 return ERROR_COMMAND_SYNTAX_ERROR;
2044 }
2045 }
2046
2047 uint32_t instr = 0xEE000010 |
2048 (values[0] << 8) |
2049 (values[1] << 21) |
2050 (values[2] << 16) |
2051 (values[3] << 0) |
2052 (values[4] << 5);
2053
2054 if (read)
2055 instr |= 0x00100000;
2056
2057 arm11_run_instr_data_prepare(arm11);
2058
2059 if (read)
2060 {
2061 uint32_t result;
2062 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2063
2064 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2065 (int)(values[0]),
2066 (int)(values[1]),
2067 (int)(values[2]),
2068 (int)(values[3]),
2069 (int)(values[4]), result, result);
2070 }
2071 else
2072 {
2073 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2074
2075 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2076 (int)(values[0]), (int)(values[1]),
2077 values[5],
2078 (int)(values[2]), (int)(values[3]), (int)(values[4]));
2079 }
2080
2081 arm11_run_instr_data_finish(arm11);
2082
2083
2084 return ERROR_OK;
2085 }
2086
2087 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2088 {
2089 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2090 }
2091
2092 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2093 {
2094 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2095 }
2096
2097 int arm11_register_commands(struct command_context_s *cmd_ctx)
2098 {
2099 FNC_INFO;
2100
2101 command_t *top_cmd, *mw_cmd;
2102
2103 top_cmd = register_command(cmd_ctx, NULL, "arm11",
2104 NULL, COMMAND_ANY, NULL);
2105
2106 /* "hardware_step" is only here to check if the default
2107 * simulate + breakpoint implementation is broken.
2108 * TEMPORARY! NOT DOCUMENTED!
2109 */
2110 register_command(cmd_ctx, top_cmd, "hardware_step",
2111 arm11_handle_bool_hardware_step, COMMAND_ANY,
2112 "DEBUG ONLY - Hardware single stepping"
2113 " (default: disabled)");
2114
2115 register_command(cmd_ctx, top_cmd, "mcr",
2116 arm11_handle_mcr, COMMAND_ANY,
2117 "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
2118
2119 mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
2120 NULL, COMMAND_ANY, NULL);
2121 register_command(cmd_ctx, mw_cmd, "burst",
2122 arm11_handle_bool_memwrite_burst, COMMAND_ANY,
2123 "Enable/Disable non-standard but fast burst mode"
2124 " (default: enabled)");
2125 register_command(cmd_ctx, mw_cmd, "error_fatal",
2126 arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
2127 "Terminate program if transfer error was found"
2128 " (default: enabled)");
2129
2130 register_command(cmd_ctx, top_cmd, "mrc",
2131 arm11_handle_mrc, COMMAND_ANY,
2132 "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
2133 register_command(cmd_ctx, top_cmd, "no_increment",
2134 arm11_handle_bool_memrw_no_increment, COMMAND_ANY,
2135 "Don't increment address on multi-read/-write"
2136 " (default: disabled)");
2137 register_command(cmd_ctx, top_cmd, "step_irq_enable",
2138 arm11_handle_bool_step_irq_enable, COMMAND_ANY,
2139 "Enable interrupts while stepping"
2140 " (default: disabled)");
2141 register_command(cmd_ctx, top_cmd, "vcr",
2142 arm11_handle_vcr, COMMAND_ANY,
2143 "Control (Interrupt) Vector Catch Register");
2144
2145 return ERROR_OK;
2146 }
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