1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
9 * Copyright (C) 2009 David Brownell *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include "breakpoints.h"
31 #include "arm11_dbgtap.h"
32 #include "arm_simulator.h"
33 #include <helper/time_support.h>
34 #include "target_type.h"
35 #include "algorithm.h"
37 #include "arm_opcodes.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
44 static int arm11_step(struct target
*target
, int current
,
45 uint32_t address
, int handle_breakpoints
);
48 /** Check and if necessary take control of the system
50 * \param arm11 Target state variable.
52 static int arm11_check_init(struct arm11_common
*arm11
)
54 CHECK_RETVAL(arm11_read_DSCR(arm11
));
56 if (!(arm11
->dscr
& DSCR_HALT_DBG_MODE
)) {
57 LOG_DEBUG("DSCR %08x", (unsigned) arm11
->dscr
);
58 LOG_DEBUG("Bringing target into debug mode");
60 arm11
->dscr
|= DSCR_HALT_DBG_MODE
;
61 CHECK_RETVAL(arm11_write_DSCR(arm11
, arm11
->dscr
));
63 /* add further reset initialization here */
65 arm11
->simulate_reset_on_next_halt
= true;
67 if (arm11
->dscr
& DSCR_CORE_HALTED
) {
68 /** \todo TODO: this needs further scrutiny because
69 * arm11_debug_entry() never gets called. (WHY NOT?)
70 * As a result we don't read the actual register states from
74 arm11
->arm
.target
->state
= TARGET_HALTED
;
75 arm_dpm_report_dscr(arm11
->arm
.dpm
, arm11
->dscr
);
77 arm11
->arm
.target
->state
= TARGET_RUNNING
;
78 arm11
->arm
.target
->debug_reason
= DBG_REASON_NOTHALTED
;
81 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11
));
88 * Save processor state. This is called after a HALT instruction
89 * succeeds, and on other occasions the processor enters debug mode
90 * (breakpoint, watchpoint, etc). Caller has updated arm11->dscr.
92 static int arm11_debug_entry(struct arm11_common
*arm11
)
96 arm11
->arm
.target
->state
= TARGET_HALTED
;
97 arm_dpm_report_dscr(arm11
->arm
.dpm
, arm11
->dscr
);
99 /* REVISIT entire cache should already be invalid !!! */
100 register_cache_invalidate(arm11
->arm
.core_cache
);
102 /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
104 /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
105 arm11
->is_wdtr_saved
= !!(arm11
->dscr
& DSCR_DTR_TX_FULL
);
106 if (arm11
->is_wdtr_saved
) {
107 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
109 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
111 struct scan_field chain5_fields
[3];
113 arm11_setup_field(arm11
, 32, NULL
,
114 &arm11
->saved_wdtr
, chain5_fields
+ 0);
115 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 1);
116 arm11_setup_field(arm11
, 1, NULL
, NULL
, chain5_fields
+ 2);
118 arm11_add_dr_scan_vc(arm11
->arm
.target
->tap
, ARRAY_SIZE(
119 chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
123 /* DSCR: set the Execute ARM instruction enable bit.
125 * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
126 * but not to issue ITRs(?). The ARMv7 arch spec says it's required
127 * for executing instructions via ITR.
129 CHECK_RETVAL(arm11_write_DSCR(arm11
, DSCR_ITR_EN
| arm11
->dscr
));
133 Before executing any instruction in debug state you have to drain the write buffer.
134 This ensures that no imprecise Data Aborts can return at a later point:*/
136 /** \todo TODO: Test drain write buffer. */
140 /* MRC p14,0,R0,c5,c10,0 */
141 /* arm11_run_instr_no_data1(arm11, / *0xee150e1a* /0xe320f000); */
143 /* mcr 15, 0, r0, cr7, cr10, {4} */
144 arm11_run_instr_no_data1(arm11
, 0xee070f9a);
146 uint32_t dscr
= arm11_read_DSCR(arm11
);
148 LOG_DEBUG("DRAIN, DSCR %08x", dscr
);
150 if (dscr
& ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT
) {
151 arm11_run_instr_no_data1(arm11
, 0xe320f000);
153 dscr
= arm11_read_DSCR(arm11
);
155 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr
);
164 * NOTE: ARM1136 TRM suggests saving just R0 here now, then
165 * CPSR and PC after the rDTR stuff. We do it all at once.
167 retval
= arm_dpm_read_current_registers(&arm11
->dpm
);
168 if (retval
!= ERROR_OK
)
169 LOG_ERROR("DPM REG READ -- fail");
171 retval
= arm11_run_instr_data_prepare(arm11
);
172 if (retval
!= ERROR_OK
)
175 /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
176 arm11
->is_rdtr_saved
= !!(arm11
->dscr
& DSCR_DTR_RX_FULL
);
177 if (arm11
->is_rdtr_saved
) {
178 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
179 retval
= arm11_run_instr_data_from_core_via_r0(arm11
,
180 0xEE100E15, &arm11
->saved_rdtr
);
181 if (retval
!= ERROR_OK
)
185 /* REVISIT Now that we've saved core state, there's may also
186 * be MMU and cache state to care about ...
189 if (arm11
->simulate_reset_on_next_halt
) {
190 arm11
->simulate_reset_on_next_halt
= false;
192 LOG_DEBUG("Reset c1 Control Register");
194 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
196 /* MCR p15,0,R0,c1,c0,0 */
197 retval
= arm11_run_instr_data_to_core_via_r0(arm11
, 0xee010f10, 0);
198 if (retval
!= ERROR_OK
)
203 if (arm11
->arm
.target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
206 /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
207 retval
= arm11_run_instr_data_from_core_via_r0(arm11
,
208 ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
210 if (retval
!= ERROR_OK
)
212 arm_dpm_report_wfar(arm11
->arm
.dpm
, wfar
);
216 retval
= arm11_run_instr_data_finish(arm11
);
217 if (retval
!= ERROR_OK
)
224 * Restore processor state. This is called in preparation for
225 * the RESTART function.
227 static int arm11_leave_debug_state(struct arm11_common
*arm11
, bool bpwp
)
231 /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
233 /* NOTE: the ARM1136 TRM suggests restoring all registers
234 * except R0/PC/CPSR right now. Instead, we do them all
235 * at once, just a bit later on.
238 /* REVISIT once we start caring about MMU and cache state,
239 * address it here ...
242 /* spec says clear wDTR and rDTR; we assume they are clear as
243 otherwise our programming would be sloppy */
245 CHECK_RETVAL(arm11_read_DSCR(arm11
));
247 if (arm11
->dscr
& (DSCR_DTR_RX_FULL
| DSCR_DTR_TX_FULL
)) {
249 The wDTR/rDTR two registers that are used to send/receive data to/from
250 the core in tandem with corresponding instruction codes that are
251 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
252 registers hold data that was written by one side (CPU or JTAG) and not
253 read out by the other side.
255 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
256 (unsigned) arm11
->dscr
);
261 /* maybe restore original wDTR */
262 if (arm11
->is_wdtr_saved
) {
263 retval
= arm11_run_instr_data_prepare(arm11
);
264 if (retval
!= ERROR_OK
)
267 /* MCR p14,0,R0,c0,c5,0 */
268 retval
= arm11_run_instr_data_to_core_via_r0(arm11
,
269 0xee000e15, arm11
->saved_wdtr
);
270 if (retval
!= ERROR_OK
)
273 retval
= arm11_run_instr_data_finish(arm11
);
274 if (retval
!= ERROR_OK
)
278 /* restore CPSR, PC, and R0 ... after flushing any modified
281 CHECK_RETVAL(arm_dpm_write_dirty_registers(&arm11
->dpm
, bpwp
));
283 CHECK_RETVAL(arm11_bpwp_flush(arm11
));
285 register_cache_invalidate(arm11
->arm
.core_cache
);
288 CHECK_RETVAL(arm11_write_DSCR(arm11
, arm11
->dscr
));
290 /* maybe restore rDTR */
291 if (arm11
->is_rdtr_saved
) {
292 arm11_add_debug_SCAN_N(arm11
, 0x05, ARM11_TAP_DEFAULT
);
294 arm11_add_IR(arm11
, ARM11_EXTEST
, ARM11_TAP_DEFAULT
);
296 struct scan_field chain5_fields
[3];
298 uint8_t Ready
= 0; /* ignored */
299 uint8_t Valid
= 0; /* ignored */
301 arm11_setup_field(arm11
, 32, &arm11
->saved_rdtr
,
302 NULL
, chain5_fields
+ 0);
303 arm11_setup_field(arm11
, 1, &Ready
, NULL
, chain5_fields
+ 1);
304 arm11_setup_field(arm11
, 1, &Valid
, NULL
, chain5_fields
+ 2);
306 arm11_add_dr_scan_vc(arm11
->arm
.target
->tap
, ARRAY_SIZE(
307 chain5_fields
), chain5_fields
, TAP_DRPAUSE
);
310 /* now processor is ready to RESTART */
315 /* poll current target status */
316 static int arm11_poll(struct target
*target
)
319 struct arm11_common
*arm11
= target_to_arm11(target
);
321 CHECK_RETVAL(arm11_check_init(arm11
));
323 if (arm11
->dscr
& DSCR_CORE_HALTED
) {
324 if (target
->state
!= TARGET_HALTED
) {
325 enum target_state old_state
= target
->state
;
327 LOG_DEBUG("enter TARGET_HALTED");
328 retval
= arm11_debug_entry(arm11
);
329 if (retval
!= ERROR_OK
)
332 target_call_event_callbacks(target
,
333 (old_state
== TARGET_DEBUG_RUNNING
)
334 ? TARGET_EVENT_DEBUG_HALTED
335 : TARGET_EVENT_HALTED
);
338 if (target
->state
!= TARGET_RUNNING
&& target
->state
!= TARGET_DEBUG_RUNNING
) {
339 LOG_DEBUG("enter TARGET_RUNNING");
340 target
->state
= TARGET_RUNNING
;
341 target
->debug_reason
= DBG_REASON_NOTHALTED
;
347 /* architecture specific status reply */
348 static int arm11_arch_state(struct target
*target
)
350 struct arm11_common
*arm11
= target_to_arm11(target
);
353 retval
= arm_arch_state(target
);
355 /* REVISIT also display ARM11-specific MMU and cache status ... */
357 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
)
358 LOG_USER("Watchpoint triggered at PC %#08x",
359 (unsigned) arm11
->dpm
.wp_pc
);
364 /* target execution control */
365 static int arm11_halt(struct target
*target
)
367 struct arm11_common
*arm11
= target_to_arm11(target
);
369 LOG_DEBUG("target->state: %s",
370 target_state_name(target
));
372 if (target
->state
== TARGET_UNKNOWN
)
373 arm11
->simulate_reset_on_next_halt
= true;
375 if (target
->state
== TARGET_HALTED
) {
376 LOG_DEBUG("target was already halted");
380 arm11_add_IR(arm11
, ARM11_HALT
, TAP_IDLE
);
382 CHECK_RETVAL(jtag_execute_queue());
387 CHECK_RETVAL(arm11_read_DSCR(arm11
));
389 if (arm11
->dscr
& DSCR_CORE_HALTED
)
397 if ((timeval_ms()-then
) > 1000) {
398 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
405 enum target_state old_state
= target
->state
;
407 CHECK_RETVAL(arm11_debug_entry(arm11
));
410 target_call_event_callbacks(target
,
412 TARGET_DEBUG_RUNNING
? TARGET_EVENT_DEBUG_HALTED
: TARGET_EVENT_HALTED
));
417 static uint32_t arm11_nextpc(struct arm11_common
*arm11
, int current
, uint32_t address
)
419 void *value
= arm11
->arm
.pc
->value
;
422 buf_set_u32(value
, 0, 32, address
);
424 address
= buf_get_u32(value
, 0, 32);
429 static int arm11_resume(struct target
*target
, int current
,
430 uint32_t address
, int handle_breakpoints
, int debug_execution
)
432 /* LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", */
433 /* current, address, handle_breakpoints, debug_execution); */
435 struct arm11_common
*arm11
= target_to_arm11(target
);
437 LOG_DEBUG("target->state: %s",
438 target_state_name(target
));
441 if (target
->state
!= TARGET_HALTED
) {
442 LOG_ERROR("Target not halted");
443 return ERROR_TARGET_NOT_HALTED
;
446 address
= arm11_nextpc(arm11
, current
, address
);
448 LOG_DEBUG("RESUME PC %08" PRIx32
"%s", address
, !current
? "!" : "");
450 /* clear breakpoints/watchpoints and VCR*/
451 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11
));
453 if (!debug_execution
)
454 target_free_all_working_areas(target
);
456 /* Should we skip over breakpoints matching the PC? */
457 if (handle_breakpoints
) {
458 struct breakpoint
*bp
;
460 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
) {
461 if (bp
->address
== address
) {
462 LOG_DEBUG("must step over %08" PRIx32
"", bp
->address
);
463 arm11_step(target
, 1, 0, 0);
469 /* activate all breakpoints */
471 struct breakpoint
*bp
;
472 unsigned brp_num
= 0;
474 for (bp
= target
->breakpoints
; bp
; bp
= bp
->next
) {
475 struct arm11_sc7_action brp
[2];
478 brp
[0].address
= ARM11_SC7_BVR0
+ brp_num
;
479 brp
[0].value
= bp
->address
;
481 brp
[1].address
= ARM11_SC7_BCR0
+ brp_num
;
484 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
486 CHECK_RETVAL(arm11_sc7_run(arm11
, brp
, ARRAY_SIZE(brp
)));
488 LOG_DEBUG("Add BP %d at %08" PRIx32
, brp_num
,
495 CHECK_RETVAL(arm11_sc7_set_vcr(arm11
, arm11
->vcr
));
498 /* activate all watchpoints and breakpoints */
499 CHECK_RETVAL(arm11_leave_debug_state(arm11
, true));
501 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
503 CHECK_RETVAL(jtag_execute_queue());
507 CHECK_RETVAL(arm11_read_DSCR(arm11
));
509 LOG_DEBUG("DSCR %08x", (unsigned) arm11
->dscr
);
511 if (arm11
->dscr
& DSCR_CORE_RESTARTED
)
519 if ((timeval_ms()-then
) > 1000) {
520 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
527 target
->debug_reason
= DBG_REASON_NOTHALTED
;
528 if (!debug_execution
)
529 target
->state
= TARGET_RUNNING
;
531 target
->state
= TARGET_DEBUG_RUNNING
;
532 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
));
537 static int arm11_step(struct target
*target
, int current
,
538 uint32_t address
, int handle_breakpoints
)
540 LOG_DEBUG("target->state: %s",
541 target_state_name(target
));
543 if (target
->state
!= TARGET_HALTED
) {
544 LOG_WARNING("target was not halted");
545 return ERROR_TARGET_NOT_HALTED
;
548 struct arm11_common
*arm11
= target_to_arm11(target
);
550 address
= arm11_nextpc(arm11
, current
, address
);
552 LOG_DEBUG("STEP PC %08" PRIx32
"%s", address
, !current
? "!" : "");
555 /** \todo TODO: Thumb not supported here */
557 uint32_t next_instruction
;
559 CHECK_RETVAL(arm11_read_memory_word(arm11
, address
, &next_instruction
));
562 if ((next_instruction
& 0xFFF00070) == 0xe1200070) {
563 address
= arm11_nextpc(arm11
, 0, address
+ 4);
564 LOG_DEBUG("Skipping BKPT %08" PRIx32
, address
);
566 /* skip over Wait for interrupt / Standby
567 * mcr 15, 0, r?, cr7, cr0, {4} */
568 else if ((next_instruction
& 0xFFFF0FFF) == 0xee070f90) {
569 address
= arm11_nextpc(arm11
, 0, address
+ 4);
570 LOG_DEBUG("Skipping WFI %08" PRIx32
, address
);
572 /* ignore B to self */
573 else if ((next_instruction
& 0xFEFFFFFF) == 0xeafffffe)
574 LOG_DEBUG("Not stepping jump to self");
576 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
579 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
580 * the VCR might be something worth looking into. */
583 /* Set up breakpoint for stepping */
585 struct arm11_sc7_action brp
[2];
588 brp
[0].address
= ARM11_SC7_BVR0
;
590 brp
[1].address
= ARM11_SC7_BCR0
;
592 if (arm11
->hardware_step
) {
593 /* Hardware single stepping ("instruction address
594 * mismatch") is used if enabled. It's not quite
595 * exactly "run one instruction"; "branch to here"
596 * loops won't break, neither will some other cases,
597 * but it's probably the best default.
599 * Hardware single stepping isn't supported on v6
600 * debug modules. ARM1176 and v7 can support it...
602 * FIXME Thumb stepping likely needs to use 0x03
603 * or 0xc0 byte masks, not 0x0f.
605 brp
[0].value
= address
;
606 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5)
607 | (0 << 14) | (0 << 16) | (0 << 20)
610 /* Sets a breakpoint on the next PC, as calculated
611 * by instruction set simulation.
613 * REVISIT stepping Thumb on ARM1156 requires Thumb2
614 * support from the simulator.
619 retval
= arm_simulate_step(target
, &next_pc
);
620 if (retval
!= ERROR_OK
)
623 brp
[0].value
= next_pc
;
624 brp
[1].value
= 0x1 | (3 << 1) | (0x0F << 5)
625 | (0 << 14) | (0 << 16) | (0 << 20)
629 CHECK_RETVAL(arm11_sc7_run(arm11
, brp
, ARRAY_SIZE(brp
)));
634 if (arm11
->step_irq_enable
)
635 /* this disable should be redundant ... */
636 arm11
->dscr
&= ~DSCR_INT_DIS
;
638 arm11
->dscr
|= DSCR_INT_DIS
;
641 CHECK_RETVAL(arm11_leave_debug_state(arm11
, handle_breakpoints
));
643 arm11_add_IR(arm11
, ARM11_RESTART
, TAP_IDLE
);
645 CHECK_RETVAL(jtag_execute_queue());
651 const uint32_t mask
= DSCR_CORE_RESTARTED
654 CHECK_RETVAL(arm11_read_DSCR(arm11
));
655 LOG_DEBUG("DSCR %08x e", (unsigned) arm11
->dscr
);
657 if ((arm11
->dscr
& mask
) == mask
)
664 if ((timeval_ms()-then
) > 1000) {
666 "Timeout (1000ms) waiting for instructions to complete");
673 /* clear breakpoint */
674 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11
));
677 CHECK_RETVAL(arm11_debug_entry(arm11
));
679 /* restore default state */
680 arm11
->dscr
&= ~DSCR_INT_DIS
;
684 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
686 CHECK_RETVAL(target_call_event_callbacks(target
, TARGET_EVENT_HALTED
));
691 static int arm11_assert_reset(struct target
*target
)
693 struct arm11_common
*arm11
= target_to_arm11(target
);
695 if (!(target_was_examined(target
))) {
696 if (jtag_get_reset_config() & RESET_HAS_SRST
)
697 jtag_add_reset(0, 1);
699 LOG_WARNING("Reset is not asserted because the target is not examined.");
700 LOG_WARNING("Use a reset button or power cycle the target.");
701 return ERROR_TARGET_NOT_EXAMINED
;
705 /* optionally catch reset vector */
706 if (target
->reset_halt
&& !(arm11
->vcr
& 1))
707 CHECK_RETVAL(arm11_sc7_set_vcr(arm11
, arm11
->vcr
| 1));
709 /* Issue some kind of warm reset. */
710 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
711 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
712 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
713 /* REVISIT handle "pulls" cases, if there's
714 * hardware that needs them to work.
716 jtag_add_reset(0, 1);
718 LOG_ERROR("%s: how to reset?", target_name(target
));
723 /* registers are now invalid */
724 register_cache_invalidate(arm11
->arm
.core_cache
);
726 target
->state
= TARGET_RESET
;
732 * - There is another bug in the arm11 core. (iMX31 specific again?)
733 * When you generate an access to external logic (for example DDR
734 * controller via AHB bus) and that block is not configured (perhaps
735 * it is still held in reset), that transaction will never complete.
736 * This will hang arm11 core but it will also hang JTAG controller.
737 * Nothing short of srst assertion will bring it out of this.
740 static int arm11_deassert_reset(struct target
*target
)
742 struct arm11_common
*arm11
= target_to_arm11(target
);
745 /* be certain SRST is off */
746 jtag_add_reset(0, 0);
748 /* WORKAROUND i.MX31 problems: SRST goofs the TAP, and resets
749 * at least DSCR. OMAP24xx doesn't show that problem, though
750 * SRST-only reset seems to be problematic for other reasons.
751 * (Secure boot sequences being one likelihood!)
755 CHECK_RETVAL(arm11_poll(target
));
757 if (target
->reset_halt
) {
758 if (target
->state
!= TARGET_HALTED
) {
759 LOG_WARNING("%s: ran after reset and before halt ...",
760 target_name(target
));
761 retval
= target_halt(target
);
762 if (retval
!= ERROR_OK
)
767 /* maybe restore vector catch config */
768 if (target
->reset_halt
&& !(arm11
->vcr
& 1))
769 CHECK_RETVAL(arm11_sc7_set_vcr(arm11
, arm11
->vcr
));
774 /* target memory access
775 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
776 * count: number of items of <size>
778 * arm11_config_memrw_no_increment - in the future we may want to be able
779 * to read/write a range of data to a "port". a "port" is an action on
780 * read memory address for some peripheral.
782 static int arm11_read_memory_inner(struct target
*target
,
783 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
,
784 bool arm11_config_memrw_no_increment
)
786 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment
790 if (target
->state
!= TARGET_HALTED
) {
791 LOG_WARNING("target was not halted");
792 return ERROR_TARGET_NOT_HALTED
;
795 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"",
800 struct arm11_common
*arm11
= target_to_arm11(target
);
802 retval
= arm11_run_instr_data_prepare(arm11
);
803 if (retval
!= ERROR_OK
)
806 /* MRC p14,0,r0,c0,c5,0 */
807 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
808 if (retval
!= ERROR_OK
)
813 arm11
->arm
.core_cache
->reg_list
[1].dirty
= true;
815 for (size_t i
= 0; i
< count
; i
++) {
816 /* ldrb r1, [r0], #1 */
818 CHECK_RETVAL(arm11_run_instr_no_data1(arm11
,
819 !arm11_config_memrw_no_increment
? 0xe4d01001 : 0xe5d01000));
822 /* MCR p14,0,R1,c0,c5,0 */
823 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1));
832 arm11
->arm
.core_cache
->reg_list
[1].dirty
= true;
834 for (size_t i
= 0; i
< count
; i
++) {
835 /* ldrh r1, [r0], #2 */
836 CHECK_RETVAL(arm11_run_instr_no_data1(arm11
,
837 !arm11_config_memrw_no_increment
? 0xe0d010b2 : 0xe1d010b0));
841 /* MCR p14,0,R1,c0,c5,0 */
842 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11
, 0xEE001E15, &res
, 1));
844 uint16_t svalue
= res
;
845 memcpy(buffer
+ i
* sizeof(uint16_t), &svalue
, sizeof(uint16_t));
853 uint32_t instr
= !arm11_config_memrw_no_increment
? 0xecb05e01 : 0xed905e00;
854 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
855 uint32_t *words
= (uint32_t *)(void *)buffer
;
857 /* LDC p14,c5,[R0],#4 */
858 /* LDC p14,c5,[R0] */
859 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11
, instr
, words
, count
));
864 return arm11_run_instr_data_finish(arm11
);
867 static int arm11_read_memory(struct target
*target
,
873 return arm11_read_memory_inner(target
, address
, size
, count
, buffer
, false);
877 * no_increment - in the future we may want to be able
878 * to read/write a range of data to a "port". a "port" is an action on
879 * read memory address for some peripheral.
881 static int arm11_write_memory_inner(struct target
*target
,
882 uint32_t address
, uint32_t size
,
883 uint32_t count
, const uint8_t *buffer
,
888 if (target
->state
!= TARGET_HALTED
) {
889 LOG_WARNING("target was not halted");
890 return ERROR_TARGET_NOT_HALTED
;
893 LOG_DEBUG("ADDR %08" PRIx32
" SIZE %08" PRIx32
" COUNT %08" PRIx32
"",
898 struct arm11_common
*arm11
= target_to_arm11(target
);
900 retval
= arm11_run_instr_data_prepare(arm11
);
901 if (retval
!= ERROR_OK
)
904 /* load r0 with buffer address
905 * MRC p14,0,r0,c0,c5,0 */
906 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee100e15, address
);
907 if (retval
!= ERROR_OK
)
910 /* burst writes are not used for single words as those may well be
911 * reset init script writes.
913 * The other advantage is that as burst writes are default, we'll
914 * now exercise both burst and non-burst code paths with the
915 * default settings, increasing code coverage.
917 bool burst
= arm11
->memwrite_burst
&& (count
> 1);
922 arm11
->arm
.core_cache
->reg_list
[1].dirty
= true;
924 for (size_t i
= 0; i
< count
; i
++) {
925 /* load r1 from DCC with byte data */
926 /* MRC p14,0,r1,c0,c5,0 */
927 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, *buffer
++);
928 if (retval
!= ERROR_OK
)
931 /* write r1 to memory */
932 /* strb r1, [r0], #1 */
934 retval
= arm11_run_instr_no_data1(arm11
,
935 !no_increment
? 0xe4c01001 : 0xe5c01000);
936 if (retval
!= ERROR_OK
)
945 arm11
->arm
.core_cache
->reg_list
[1].dirty
= true;
947 for (size_t i
= 0; i
< count
; i
++) {
949 memcpy(&value
, buffer
+ i
* sizeof(uint16_t), sizeof(uint16_t));
951 /* load r1 from DCC with halfword data */
952 /* MRC p14,0,r1,c0,c5,0 */
953 retval
= arm11_run_instr_data_to_core1(arm11
, 0xee101e15, value
);
954 if (retval
!= ERROR_OK
)
957 /* write r1 to memory */
958 /* strh r1, [r0], #2 */
960 retval
= arm11_run_instr_no_data1(arm11
,
961 !no_increment
? 0xe0c010b2 : 0xe1c010b0);
962 if (retval
!= ERROR_OK
)
970 /* stream word data through DCC directly to memory */
971 /* increment: STC p14,c5,[R0],#4 */
972 /* no increment: STC p14,c5,[R0]*/
973 uint32_t instr
= !no_increment
? 0xeca05e01 : 0xed805e00;
975 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
976 uint32_t *words
= (uint32_t *)(void *)buffer
;
978 /* "burst" here just means trusting each instruction executes
979 * fully before we run the next one: per-word roundtrips, to
980 * check the Ready flag, are not used.
983 retval
= arm11_run_instr_data_to_core(arm11
,
984 instr
, words
, count
);
986 retval
= arm11_run_instr_data_to_core_noack(arm11
,
987 instr
, words
, count
);
988 if (retval
!= ERROR_OK
)
995 /* r0 verification */
999 /* MCR p14,0,R0,c0,c5,0 */
1000 retval
= arm11_run_instr_data_from_core(arm11
, 0xEE000E15, &r0
, 1);
1001 if (retval
!= ERROR_OK
)
1004 if (address
+ size
* count
!= r0
) {
1005 LOG_ERROR("Data transfer failed. Expected end "
1006 "address 0x%08x, got 0x%08x",
1007 (unsigned) (address
+ size
* count
),
1012 "use 'arm11 memwrite burst disable' to disable fast burst mode");
1015 if (arm11
->memwrite_error_fatal
)
1020 return arm11_run_instr_data_finish(arm11
);
1023 static int arm11_write_memory(struct target
*target
,
1024 uint32_t address
, uint32_t size
,
1025 uint32_t count
, const uint8_t *buffer
)
1027 /* pointer increment matters only for multi-unit writes ...
1028 * not e.g. to a "reset the chip" controller.
1030 return arm11_write_memory_inner(target
, address
, size
,
1031 count
, buffer
, count
== 1);
1034 /* target break-/watchpoint control
1035 * rw: 0 = write, 1 = read, 2 = access
1037 static int arm11_add_breakpoint(struct target
*target
,
1038 struct breakpoint
*breakpoint
)
1040 struct arm11_common
*arm11
= target_to_arm11(target
);
1043 if (breakpoint
->type
== BKPT_SOFT
) {
1044 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1045 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1049 if (!arm11
->free_brps
) {
1050 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1051 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1054 if (breakpoint
->length
!= 4) {
1055 LOG_DEBUG("only breakpoints of four bytes length supported");
1056 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1064 static int arm11_remove_breakpoint(struct target
*target
,
1065 struct breakpoint
*breakpoint
)
1067 struct arm11_common
*arm11
= target_to_arm11(target
);
1074 static int arm11_target_create(struct target
*target
, Jim_Interp
*interp
)
1076 struct arm11_common
*arm11
;
1078 if (target
->tap
== NULL
)
1081 if (target
->tap
->ir_length
!= 5) {
1082 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1083 return ERROR_COMMAND_SYNTAX_ERROR
;
1086 arm11
= calloc(1, sizeof *arm11
);
1090 arm11
->arm
.core_type
= ARM_MODE_ANY
;
1091 arm_init_arch_info(target
, &arm11
->arm
);
1093 arm11
->jtag_info
.tap
= target
->tap
;
1094 arm11
->jtag_info
.scann_size
= 5;
1095 arm11
->jtag_info
.scann_instr
= ARM11_SCAN_N
;
1096 arm11
->jtag_info
.cur_scan_chain
= ~0; /* invalid/unknown */
1097 arm11
->jtag_info
.intest_instr
= ARM11_INTEST
;
1099 arm11
->memwrite_burst
= true;
1100 arm11
->memwrite_error_fatal
= true;
1105 static int arm11_init_target(struct command_context
*cmd_ctx
,
1106 struct target
*target
)
1108 /* Initialize anything we can set up without talking to the target */
1112 /* talk to the target and set things up */
1113 static int arm11_examine(struct target
*target
)
1117 struct arm11_common
*arm11
= target_to_arm11(target
);
1118 uint32_t didr
, device_id
;
1119 uint8_t implementor
;
1121 /* FIXME split into do-first-time and do-every-time logic ... */
1125 arm11_add_IR(arm11
, ARM11_IDCODE
, ARM11_TAP_DEFAULT
);
1127 struct scan_field idcode_field
;
1129 arm11_setup_field(arm11
, 32, NULL
, &device_id
, &idcode_field
);
1131 arm11_add_dr_scan_vc(arm11
->arm
.target
->tap
, 1, &idcode_field
, TAP_DRPAUSE
);
1135 arm11_add_debug_SCAN_N(arm11
, 0x00, ARM11_TAP_DEFAULT
);
1137 arm11_add_IR(arm11
, ARM11_INTEST
, ARM11_TAP_DEFAULT
);
1139 struct scan_field chain0_fields
[2];
1141 arm11_setup_field(arm11
, 32, NULL
, &didr
, chain0_fields
+ 0);
1142 arm11_setup_field(arm11
, 8, NULL
, &implementor
, chain0_fields
+ 1);
1144 arm11_add_dr_scan_vc(arm11
->arm
.target
->tap
, ARRAY_SIZE(
1145 chain0_fields
), chain0_fields
, TAP_IDLE
);
1147 CHECK_RETVAL(jtag_execute_queue());
1149 /* assume the manufacturer id is ok; check the part # */
1150 switch ((device_id
>> 12) & 0xFFFF) {
1155 type
= "ARM11 MPCore";
1161 arm11
->arm
.core_type
= ARM_MODE_MON
;
1162 /* NOTE: could default arm11->hardware_step to true */
1166 LOG_ERROR("unexpected ARM11 ID code");
1169 LOG_INFO("found %s", type
);
1171 /* unlikely this could ever fail, but ... */
1172 switch ((didr
>> 16) & 0x0F) {
1173 case ARM11_DEBUG_V6
:
1174 case ARM11_DEBUG_V61
: /* supports security extensions */
1177 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1181 arm11
->brp
= ((didr
>> 24) & 0x0F) + 1;
1183 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1184 arm11
->free_brps
= arm11
->brp
;
1186 LOG_DEBUG("IDCODE %08" PRIx32
" IMPLEMENTOR %02x DIDR %08" PRIx32
,
1187 device_id
, implementor
, didr
);
1189 /* Build register cache "late", after target_init(), since we
1190 * want to know if this core supports Secure Monitor mode.
1192 if (!target_was_examined(target
))
1193 CHECK_RETVAL(arm11_dpm_init(arm11
, didr
));
1195 /* as a side-effect this reads DSCR and thus
1196 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1197 * as suggested by the spec.
1200 retval
= arm11_check_init(arm11
);
1201 if (retval
!= ERROR_OK
)
1204 /* ETM on ARM11 still uses original scanchain 6 access mode */
1205 if (arm11
->arm
.etm
&& !target_was_examined(target
)) {
1206 *register_get_last_cache_p(&target
->reg_cache
) =
1207 etm_build_reg_cache(target
, &arm11
->jtag_info
,
1209 CHECK_RETVAL(etm_setup(target
));
1212 target_set_examined(target
);
1217 #define ARM11_BOOL_WRAPPER(name, print_name) \
1218 COMMAND_HANDLER(arm11_handle_bool_ ## name) \
1220 struct target *target = get_current_target(CMD_CTX); \
1221 struct arm11_common *arm11 = target_to_arm11(target); \
1223 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1224 &arm11->name, print_name); \
1227 ARM11_BOOL_WRAPPER(memwrite_burst
, "memory write burst mode")
1228 ARM11_BOOL_WRAPPER(memwrite_error_fatal
, "fatal error mode for memory writes")
1229 ARM11_BOOL_WRAPPER(step_irq_enable
, "IRQs while stepping")
1230 ARM11_BOOL_WRAPPER(hardware_step
, "hardware single step")
1232 /* REVISIT handle the VCR bits like other ARMs: use symbols for
1233 * input and output values.
1236 COMMAND_HANDLER(arm11_handle_vcr
)
1238 struct target
*target
= get_current_target(CMD_CTX
);
1239 struct arm11_common
*arm11
= target_to_arm11(target
);
1245 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], arm11
->vcr
);
1248 return ERROR_COMMAND_SYNTAX_ERROR
;
1251 LOG_INFO("VCR 0x%08" PRIx32
"", arm11
->vcr
);
1255 static const struct command_registration arm11_mw_command_handlers
[] = {
1258 .handler
= arm11_handle_bool_memwrite_burst
,
1259 .mode
= COMMAND_ANY
,
1260 .help
= "Display or modify flag controlling potentially "
1261 "risky fast burst mode (default: enabled)",
1262 .usage
= "['enable'|'disable']",
1265 .name
= "error_fatal",
1266 .handler
= arm11_handle_bool_memwrite_error_fatal
,
1267 .mode
= COMMAND_ANY
,
1268 .help
= "Display or modify flag controlling transfer "
1269 "termination on transfer errors"
1270 " (default: enabled)",
1271 .usage
= "['enable'|'disable']",
1273 COMMAND_REGISTRATION_DONE
1275 static const struct command_registration arm11_any_command_handlers
[] = {
1277 /* "hardware_step" is only here to check if the default
1278 * simulate + breakpoint implementation is broken.
1279 * TEMPORARY! NOT DOCUMENTED! */
1280 .name
= "hardware_step",
1281 .handler
= arm11_handle_bool_hardware_step
,
1282 .mode
= COMMAND_ANY
,
1283 .help
= "DEBUG ONLY - Hardware single stepping"
1284 " (default: disabled)",
1285 .usage
= "['enable'|'disable']",
1289 .mode
= COMMAND_ANY
,
1290 .help
= "memwrite command group",
1292 .chain
= arm11_mw_command_handlers
,
1295 .name
= "step_irq_enable",
1296 .handler
= arm11_handle_bool_step_irq_enable
,
1297 .mode
= COMMAND_ANY
,
1298 .help
= "Display or modify flag controlling interrupt "
1299 "enable while stepping (default: disabled)",
1300 .usage
= "['enable'|'disable']",
1304 .handler
= arm11_handle_vcr
,
1305 .mode
= COMMAND_ANY
,
1306 .help
= "Display or modify Vector Catch Register",
1309 COMMAND_REGISTRATION_DONE
1312 static const struct command_registration arm11_command_handlers
[] = {
1314 .chain
= arm_command_handlers
,
1317 .chain
= etm_command_handlers
,
1321 .mode
= COMMAND_ANY
,
1322 .help
= "ARM11 command group",
1324 .chain
= arm11_any_command_handlers
,
1326 COMMAND_REGISTRATION_DONE
1329 /** Holds methods for ARM11xx targets. */
1330 struct target_type arm11_target
= {
1334 .arch_state
= arm11_arch_state
,
1337 .resume
= arm11_resume
,
1340 .assert_reset
= arm11_assert_reset
,
1341 .deassert_reset
= arm11_deassert_reset
,
1343 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
1345 .read_memory
= arm11_read_memory
,
1346 .write_memory
= arm11_write_memory
,
1348 .checksum_memory
= arm_checksum_memory
,
1349 .blank_check_memory
= arm_blank_check_memory
,
1351 .add_breakpoint
= arm11_add_breakpoint
,
1352 .remove_breakpoint
= arm11_remove_breakpoint
,
1354 .run_algorithm
= armv4_5_run_algorithm
,
1356 .commands
= arm11_command_handlers
,
1357 .target_create
= arm11_target_create
,
1358 .init_target
= arm11_init_target
,
1359 .examine
= arm11_examine
,
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