target/arm11: Use 'bool' data type
[openocd.git] / src / target / arm11.c
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * Copyright (C) 2009 David Brownell *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "etm.h"
30 #include "breakpoints.h"
31 #include "arm11_dbgtap.h"
32 #include "arm_simulator.h"
33 #include <helper/time_support.h>
34 #include "target_type.h"
35 #include "algorithm.h"
36 #include "register.h"
37 #include "arm_opcodes.h"
38
39 #if 0
40 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #endif
42
43
44 static int arm11_step(struct target *target, int current,
45 target_addr_t address, int handle_breakpoints);
46
47
48 /** Check and if necessary take control of the system
49 *
50 * \param arm11 Target state variable.
51 */
52 static int arm11_check_init(struct arm11_common *arm11)
53 {
54 CHECK_RETVAL(arm11_read_DSCR(arm11));
55
56 if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) {
57 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
58 LOG_DEBUG("Bringing target into debug mode");
59
60 arm11->dscr |= DSCR_HALT_DBG_MODE;
61 CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
62
63 /* add further reset initialization here */
64
65 arm11->simulate_reset_on_next_halt = true;
66
67 if (arm11->dscr & DSCR_CORE_HALTED) {
68 /** \todo TODO: this needs further scrutiny because
69 * arm11_debug_entry() never gets called. (WHY NOT?)
70 * As a result we don't read the actual register states from
71 * the target.
72 */
73
74 arm11->arm.target->state = TARGET_HALTED;
75 arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
76 } else {
77 arm11->arm.target->state = TARGET_RUNNING;
78 arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
79 }
80
81 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
82 }
83
84 return ERROR_OK;
85 }
86
87 /**
88 * Save processor state. This is called after a HALT instruction
89 * succeeds, and on other occasions the processor enters debug mode
90 * (breakpoint, watchpoint, etc). Caller has updated arm11->dscr.
91 */
92 static int arm11_debug_entry(struct arm11_common *arm11)
93 {
94 int retval;
95
96 arm11->arm.target->state = TARGET_HALTED;
97 arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
98
99 /* REVISIT entire cache should already be invalid !!! */
100 register_cache_invalidate(arm11->arm.core_cache);
101
102 /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
103
104 /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
105 arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
106 if (arm11->is_wdtr_saved) {
107 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
108
109 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
110
111 struct scan_field chain5_fields[3];
112
113 arm11_setup_field(arm11, 32, NULL,
114 &arm11->saved_wdtr, chain5_fields + 0);
115 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
116 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
117
118 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
119 chain5_fields), chain5_fields, TAP_DRPAUSE);
120
121 }
122
123 /* DSCR: set the Execute ARM instruction enable bit.
124 *
125 * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
126 * but not to issue ITRs(?). The ARMv7 arch spec says it's required
127 * for executing instructions via ITR.
128 */
129 CHECK_RETVAL(arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr));
130
131
132 /* From the spec:
133 Before executing any instruction in debug state you have to drain the write buffer.
134 This ensures that no imprecise Data Aborts can return at a later point:*/
135
136 /** \todo TODO: Test drain write buffer. */
137
138 #if 0
139 while (1) {
140 /* MRC p14,0,R0,c5,c10,0 */
141 /* arm11_run_instr_no_data1(arm11, / *0xee150e1a* /0xe320f000); */
142
143 /* mcr 15, 0, r0, cr7, cr10, {4} */
144 arm11_run_instr_no_data1(arm11, 0xee070f9a);
145
146 uint32_t dscr = arm11_read_DSCR(arm11);
147
148 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
149
150 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) {
151 arm11_run_instr_no_data1(arm11, 0xe320f000);
152
153 dscr = arm11_read_DSCR(arm11);
154
155 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
156
157 break;
158 }
159 }
160 #endif
161
162 /* Save registers.
163 *
164 * NOTE: ARM1136 TRM suggests saving just R0 here now, then
165 * CPSR and PC after the rDTR stuff. We do it all at once.
166 */
167 retval = arm_dpm_read_current_registers(&arm11->dpm);
168 if (retval != ERROR_OK)
169 LOG_ERROR("DPM REG READ -- fail");
170
171 retval = arm11_run_instr_data_prepare(arm11);
172 if (retval != ERROR_OK)
173 return retval;
174
175 /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
176 arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
177 if (arm11->is_rdtr_saved) {
178 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
179 retval = arm11_run_instr_data_from_core_via_r0(arm11,
180 0xEE100E15, &arm11->saved_rdtr);
181 if (retval != ERROR_OK)
182 return retval;
183 }
184
185 /* REVISIT Now that we've saved core state, there's may also
186 * be MMU and cache state to care about ...
187 */
188
189 if (arm11->simulate_reset_on_next_halt) {
190 arm11->simulate_reset_on_next_halt = false;
191
192 LOG_DEBUG("Reset c1 Control Register");
193
194 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
195
196 /* MCR p15,0,R0,c1,c0,0 */
197 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
198 if (retval != ERROR_OK)
199 return retval;
200
201 }
202
203 if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
204 uint32_t wfar;
205
206 /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
207 retval = arm11_run_instr_data_from_core_via_r0(arm11,
208 ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
209 &wfar);
210 if (retval != ERROR_OK)
211 return retval;
212 arm_dpm_report_wfar(arm11->arm.dpm, wfar);
213 }
214
215
216 retval = arm11_run_instr_data_finish(arm11);
217 if (retval != ERROR_OK)
218 return retval;
219
220 return ERROR_OK;
221 }
222
223 /**
224 * Restore processor state. This is called in preparation for
225 * the RESTART function.
226 */
227 static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
228 {
229 int retval;
230
231 /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
232
233 /* NOTE: the ARM1136 TRM suggests restoring all registers
234 * except R0/PC/CPSR right now. Instead, we do them all
235 * at once, just a bit later on.
236 */
237
238 /* REVISIT once we start caring about MMU and cache state,
239 * address it here ...
240 */
241
242 /* spec says clear wDTR and rDTR; we assume they are clear as
243 otherwise our programming would be sloppy */
244 {
245 CHECK_RETVAL(arm11_read_DSCR(arm11));
246
247 if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) {
248 /*
249 The wDTR/rDTR two registers that are used to send/receive data to/from
250 the core in tandem with corresponding instruction codes that are
251 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
252 registers hold data that was written by one side (CPU or JTAG) and not
253 read out by the other side.
254 */
255 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
256 (unsigned) arm11->dscr);
257 return ERROR_FAIL;
258 }
259 }
260
261 /* maybe restore original wDTR */
262 if (arm11->is_wdtr_saved) {
263 retval = arm11_run_instr_data_prepare(arm11);
264 if (retval != ERROR_OK)
265 return retval;
266
267 /* MCR p14,0,R0,c0,c5,0 */
268 retval = arm11_run_instr_data_to_core_via_r0(arm11,
269 0xee000e15, arm11->saved_wdtr);
270 if (retval != ERROR_OK)
271 return retval;
272
273 retval = arm11_run_instr_data_finish(arm11);
274 if (retval != ERROR_OK)
275 return retval;
276 }
277
278 /* restore CPSR, PC, and R0 ... after flushing any modified
279 * registers.
280 */
281 CHECK_RETVAL(arm_dpm_write_dirty_registers(&arm11->dpm, bpwp));
282
283 CHECK_RETVAL(arm11_bpwp_flush(arm11));
284
285 register_cache_invalidate(arm11->arm.core_cache);
286
287 /* restore DSCR */
288 CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
289
290 /* maybe restore rDTR */
291 if (arm11->is_rdtr_saved) {
292 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
293
294 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
295
296 struct scan_field chain5_fields[3];
297
298 uint8_t Ready = 0; /* ignored */
299 uint8_t Valid = 0; /* ignored */
300
301 arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
302 NULL, chain5_fields + 0);
303 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
304 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
305
306 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
307 chain5_fields), chain5_fields, TAP_DRPAUSE);
308 }
309
310 /* now processor is ready to RESTART */
311
312 return ERROR_OK;
313 }
314
315 /* poll current target status */
316 static int arm11_poll(struct target *target)
317 {
318 int retval;
319 struct arm11_common *arm11 = target_to_arm11(target);
320
321 CHECK_RETVAL(arm11_check_init(arm11));
322
323 if (arm11->dscr & DSCR_CORE_HALTED) {
324 if (target->state != TARGET_HALTED) {
325 enum target_state old_state = target->state;
326
327 LOG_DEBUG("enter TARGET_HALTED");
328 retval = arm11_debug_entry(arm11);
329 if (retval != ERROR_OK)
330 return retval;
331
332 target_call_event_callbacks(target,
333 (old_state == TARGET_DEBUG_RUNNING)
334 ? TARGET_EVENT_DEBUG_HALTED
335 : TARGET_EVENT_HALTED);
336 }
337 } else {
338 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) {
339 LOG_DEBUG("enter TARGET_RUNNING");
340 target->state = TARGET_RUNNING;
341 target->debug_reason = DBG_REASON_NOTHALTED;
342 }
343 }
344
345 return ERROR_OK;
346 }
347 /* architecture specific status reply */
348 static int arm11_arch_state(struct target *target)
349 {
350 struct arm11_common *arm11 = target_to_arm11(target);
351 int retval;
352
353 retval = arm_arch_state(target);
354
355 /* REVISIT also display ARM11-specific MMU and cache status ... */
356
357 if (target->debug_reason == DBG_REASON_WATCHPOINT)
358 LOG_USER("Watchpoint triggered at PC %#08x",
359 (unsigned) arm11->dpm.wp_pc);
360
361 return retval;
362 }
363
364 /* target execution control */
365 static int arm11_halt(struct target *target)
366 {
367 struct arm11_common *arm11 = target_to_arm11(target);
368
369 LOG_DEBUG("target->state: %s",
370 target_state_name(target));
371
372 if (target->state == TARGET_UNKNOWN)
373 arm11->simulate_reset_on_next_halt = true;
374
375 if (target->state == TARGET_HALTED) {
376 LOG_DEBUG("target was already halted");
377 return ERROR_OK;
378 }
379
380 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
381
382 CHECK_RETVAL(jtag_execute_queue());
383
384 int i = 0;
385
386 while (1) {
387 CHECK_RETVAL(arm11_read_DSCR(arm11));
388
389 if (arm11->dscr & DSCR_CORE_HALTED)
390 break;
391
392
393 int64_t then = 0;
394 if (i == 1000)
395 then = timeval_ms();
396 if (i >= 1000) {
397 if ((timeval_ms()-then) > 1000) {
398 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
399 return ERROR_FAIL;
400 }
401 }
402 i++;
403 }
404
405 enum target_state old_state = target->state;
406
407 CHECK_RETVAL(arm11_debug_entry(arm11));
408
409 CHECK_RETVAL(
410 target_call_event_callbacks(target,
411 old_state ==
412 TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
413
414 return ERROR_OK;
415 }
416
417 static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
418 {
419 void *value = arm11->arm.pc->value;
420
421 /* use the current program counter */
422 if (current)
423 address = buf_get_u32(value, 0, 32);
424
425 /* Make sure that the gdb thumb fixup does not
426 * kill the return address
427 */
428 switch (arm11->arm.core_state) {
429 case ARM_STATE_ARM:
430 address &= 0xFFFFFFFC;
431 break;
432 case ARM_STATE_THUMB:
433 /* When the return address is loaded into PC
434 * bit 0 must be 1 to stay in Thumb state
435 */
436 address |= 0x1;
437 break;
438
439 /* catch-all for JAZELLE and THUMB_EE */
440 default:
441 break;
442 }
443
444 buf_set_u32(value, 0, 32, address);
445 arm11->arm.pc->dirty = true;
446 arm11->arm.pc->valid = true;
447
448 return address;
449 }
450
451 static int arm11_resume(struct target *target, int current,
452 target_addr_t address, int handle_breakpoints, int debug_execution)
453 {
454 /* LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", */
455 /* current, address, handle_breakpoints, debug_execution); */
456
457 struct arm11_common *arm11 = target_to_arm11(target);
458
459 LOG_DEBUG("target->state: %s",
460 target_state_name(target));
461
462
463 if (target->state != TARGET_HALTED) {
464 LOG_ERROR("Target not halted");
465 return ERROR_TARGET_NOT_HALTED;
466 }
467
468 address = arm11_nextpc(arm11, current, address);
469
470 LOG_DEBUG("RESUME PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
471
472 /* clear breakpoints/watchpoints and VCR*/
473 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
474
475 if (!debug_execution)
476 target_free_all_working_areas(target);
477
478 /* Should we skip over breakpoints matching the PC? */
479 if (handle_breakpoints) {
480 struct breakpoint *bp;
481
482 for (bp = target->breakpoints; bp; bp = bp->next) {
483 if (bp->address == address) {
484 LOG_DEBUG("must step over %08" TARGET_PRIxADDR "", bp->address);
485 arm11_step(target, 1, 0, 0);
486 break;
487 }
488 }
489 }
490
491 /* activate all breakpoints */
492 if (true) {
493 struct breakpoint *bp;
494 unsigned brp_num = 0;
495
496 for (bp = target->breakpoints; bp; bp = bp->next) {
497 struct arm11_sc7_action brp[2];
498
499 brp[0].write = 1;
500 brp[0].address = ARM11_SC7_BVR0 + brp_num;
501 brp[0].value = bp->address;
502 brp[1].write = 1;
503 brp[1].address = ARM11_SC7_BCR0 + brp_num;
504 brp[1].value = 0x1 |
505 (3 <<
506 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
507
508 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
509
510 LOG_DEBUG("Add BP %d at %08" TARGET_PRIxADDR, brp_num,
511 bp->address);
512
513 brp_num++;
514 }
515
516 if (arm11->vcr)
517 CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
518 }
519
520 /* activate all watchpoints and breakpoints */
521 CHECK_RETVAL(arm11_leave_debug_state(arm11, true));
522
523 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
524
525 CHECK_RETVAL(jtag_execute_queue());
526
527 int i = 0;
528 while (1) {
529 CHECK_RETVAL(arm11_read_DSCR(arm11));
530
531 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
532
533 if (arm11->dscr & DSCR_CORE_RESTARTED)
534 break;
535
536
537 int64_t then = 0;
538 if (i == 1000)
539 then = timeval_ms();
540 if (i >= 1000) {
541 if ((timeval_ms()-then) > 1000) {
542 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
543 return ERROR_FAIL;
544 }
545 }
546 i++;
547 }
548
549 target->debug_reason = DBG_REASON_NOTHALTED;
550 if (!debug_execution)
551 target->state = TARGET_RUNNING;
552 else
553 target->state = TARGET_DEBUG_RUNNING;
554 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
555
556 return ERROR_OK;
557 }
558
559 static int arm11_step(struct target *target, int current,
560 target_addr_t address, int handle_breakpoints)
561 {
562 LOG_DEBUG("target->state: %s",
563 target_state_name(target));
564
565 if (target->state != TARGET_HALTED) {
566 LOG_WARNING("target was not halted");
567 return ERROR_TARGET_NOT_HALTED;
568 }
569
570 struct arm11_common *arm11 = target_to_arm11(target);
571
572 address = arm11_nextpc(arm11, current, address);
573
574 LOG_DEBUG("STEP PC %08" TARGET_PRIxADDR "%s", address, !current ? "!" : "");
575
576
577 /** \todo TODO: Thumb not supported here */
578
579 uint32_t next_instruction;
580
581 CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
582
583 /* skip over BKPT */
584 if ((next_instruction & 0xFFF00070) == 0xe1200070) {
585 address = arm11_nextpc(arm11, 0, address + 4);
586 LOG_DEBUG("Skipping BKPT %08" TARGET_PRIxADDR, address);
587 }
588 /* skip over Wait for interrupt / Standby
589 * mcr 15, 0, r?, cr7, cr0, {4} */
590 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) {
591 address = arm11_nextpc(arm11, 0, address + 4);
592 LOG_DEBUG("Skipping WFI %08" TARGET_PRIxADDR, address);
593 }
594 /* ignore B to self */
595 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
596 LOG_DEBUG("Not stepping jump to self");
597 else {
598 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
599 * with this. */
600
601 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
602 * the VCR might be something worth looking into. */
603
604
605 /* Set up breakpoint for stepping */
606
607 struct arm11_sc7_action brp[2];
608
609 brp[0].write = 1;
610 brp[0].address = ARM11_SC7_BVR0;
611 brp[1].write = 1;
612 brp[1].address = ARM11_SC7_BCR0;
613
614 if (arm11->hardware_step) {
615 /* Hardware single stepping ("instruction address
616 * mismatch") is used if enabled. It's not quite
617 * exactly "run one instruction"; "branch to here"
618 * loops won't break, neither will some other cases,
619 * but it's probably the best default.
620 *
621 * Hardware single stepping isn't supported on v6
622 * debug modules. ARM1176 and v7 can support it...
623 *
624 * FIXME Thumb stepping likely needs to use 0x03
625 * or 0xc0 byte masks, not 0x0f.
626 */
627 brp[0].value = address;
628 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
629 | (0 << 14) | (0 << 16) | (0 << 20)
630 | (2 << 21);
631 } else {
632 /* Sets a breakpoint on the next PC, as calculated
633 * by instruction set simulation.
634 *
635 * REVISIT stepping Thumb on ARM1156 requires Thumb2
636 * support from the simulator.
637 */
638 uint32_t next_pc;
639 int retval;
640
641 retval = arm_simulate_step(target, &next_pc);
642 if (retval != ERROR_OK)
643 return retval;
644
645 brp[0].value = next_pc;
646 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
647 | (0 << 14) | (0 << 16) | (0 << 20)
648 | (0 << 21);
649 }
650
651 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
652
653 /* resume */
654
655
656 if (arm11->step_irq_enable)
657 /* this disable should be redundant ... */
658 arm11->dscr &= ~DSCR_INT_DIS;
659 else
660 arm11->dscr |= DSCR_INT_DIS;
661
662
663 CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
664
665 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
666
667 CHECK_RETVAL(jtag_execute_queue());
668
669 /* wait for halt */
670 int i = 0;
671
672 while (1) {
673 const uint32_t mask = DSCR_CORE_RESTARTED
674 | DSCR_CORE_HALTED;
675
676 CHECK_RETVAL(arm11_read_DSCR(arm11));
677 LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
678
679 if ((arm11->dscr & mask) == mask)
680 break;
681
682 long long then = 0;
683 if (i == 1000)
684 then = timeval_ms();
685 if (i >= 1000) {
686 if ((timeval_ms()-then) > 1000) {
687 LOG_WARNING(
688 "Timeout (1000ms) waiting for instructions to complete");
689 return ERROR_FAIL;
690 }
691 }
692 i++;
693 }
694
695 /* clear breakpoint */
696 CHECK_RETVAL(arm11_sc7_clear_vbw(arm11));
697
698 /* save state */
699 CHECK_RETVAL(arm11_debug_entry(arm11));
700
701 /* restore default state */
702 arm11->dscr &= ~DSCR_INT_DIS;
703
704 }
705
706 target->debug_reason = DBG_REASON_SINGLESTEP;
707
708 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
709
710 return ERROR_OK;
711 }
712
713 static int arm11_assert_reset(struct target *target)
714 {
715 struct arm11_common *arm11 = target_to_arm11(target);
716
717 if (!(target_was_examined(target))) {
718 if (jtag_get_reset_config() & RESET_HAS_SRST)
719 jtag_add_reset(0, 1);
720 else {
721 LOG_WARNING("Reset is not asserted because the target is not examined.");
722 LOG_WARNING("Use a reset button or power cycle the target.");
723 return ERROR_TARGET_NOT_EXAMINED;
724 }
725 } else {
726
727 /* optionally catch reset vector */
728 if (target->reset_halt && !(arm11->vcr & 1))
729 CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
730
731 /* Issue some kind of warm reset. */
732 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
733 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
734 else if (jtag_get_reset_config() & RESET_HAS_SRST) {
735 /* REVISIT handle "pulls" cases, if there's
736 * hardware that needs them to work.
737 */
738 jtag_add_reset(0, 1);
739 } else {
740 LOG_ERROR("%s: how to reset?", target_name(target));
741 return ERROR_FAIL;
742 }
743 }
744
745 /* registers are now invalid */
746 register_cache_invalidate(arm11->arm.core_cache);
747
748 target->state = TARGET_RESET;
749
750 return ERROR_OK;
751 }
752
753 /*
754 * - There is another bug in the arm11 core. (iMX31 specific again?)
755 * When you generate an access to external logic (for example DDR
756 * controller via AHB bus) and that block is not configured (perhaps
757 * it is still held in reset), that transaction will never complete.
758 * This will hang arm11 core but it will also hang JTAG controller.
759 * Nothing short of srst assertion will bring it out of this.
760 */
761
762 static int arm11_deassert_reset(struct target *target)
763 {
764 struct arm11_common *arm11 = target_to_arm11(target);
765 int retval;
766
767 /* be certain SRST is off */
768 jtag_add_reset(0, 0);
769
770 /* WORKAROUND i.MX31 problems: SRST goofs the TAP, and resets
771 * at least DSCR. OMAP24xx doesn't show that problem, though
772 * SRST-only reset seems to be problematic for other reasons.
773 * (Secure boot sequences being one likelihood!)
774 */
775 jtag_add_tlr();
776
777 CHECK_RETVAL(arm11_poll(target));
778
779 if (target->reset_halt) {
780 if (target->state != TARGET_HALTED) {
781 LOG_WARNING("%s: ran after reset and before halt ...",
782 target_name(target));
783 retval = target_halt(target);
784 if (retval != ERROR_OK)
785 return retval;
786 }
787 }
788
789 /* maybe restore vector catch config */
790 if (target->reset_halt && !(arm11->vcr & 1))
791 CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
792
793 return ERROR_OK;
794 }
795
796 /* target memory access
797 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
798 * count: number of items of <size>
799 *
800 * arm11_config_memrw_no_increment - in the future we may want to be able
801 * to read/write a range of data to a "port". a "port" is an action on
802 * read memory address for some peripheral.
803 */
804 static int arm11_read_memory_inner(struct target *target,
805 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
806 bool arm11_config_memrw_no_increment)
807 {
808 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment
809 *problems */
810 int retval;
811
812 if (target->state != TARGET_HALTED) {
813 LOG_WARNING("target was not halted");
814 return ERROR_TARGET_NOT_HALTED;
815 }
816
817 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
818 address,
819 size,
820 count);
821
822 struct arm11_common *arm11 = target_to_arm11(target);
823
824 retval = arm11_run_instr_data_prepare(arm11);
825 if (retval != ERROR_OK)
826 return retval;
827
828 /* MRC p14,0,r0,c0,c5,0 */
829 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
830 if (retval != ERROR_OK)
831 return retval;
832
833 switch (size) {
834 case 1:
835 arm11->arm.core_cache->reg_list[1].dirty = true;
836
837 for (size_t i = 0; i < count; i++) {
838 /* ldrb r1, [r0], #1 */
839 /* ldrb r1, [r0] */
840 CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
841 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
842
843 uint32_t res;
844 /* MCR p14,0,R1,c0,c5,0 */
845 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
846
847 *buffer++ = res;
848 }
849
850 break;
851
852 case 2:
853 {
854 arm11->arm.core_cache->reg_list[1].dirty = true;
855
856 for (size_t i = 0; i < count; i++) {
857 /* ldrh r1, [r0], #2 */
858 CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
859 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
860
861 uint32_t res;
862
863 /* MCR p14,0,R1,c0,c5,0 */
864 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
865
866 uint16_t svalue = res;
867 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
868 }
869
870 break;
871 }
872
873 case 4:
874 {
875 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
876 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
877 uint32_t *words = (uint32_t *)(void *)buffer;
878
879 /* LDC p14,c5,[R0],#4 */
880 /* LDC p14,c5,[R0] */
881 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
882 break;
883 }
884 }
885
886 return arm11_run_instr_data_finish(arm11);
887 }
888
889 static int arm11_read_memory(struct target *target,
890 target_addr_t address,
891 uint32_t size,
892 uint32_t count,
893 uint8_t *buffer)
894 {
895 return arm11_read_memory_inner(target, address, size, count, buffer, false);
896 }
897
898 /*
899 * no_increment - in the future we may want to be able
900 * to read/write a range of data to a "port". a "port" is an action on
901 * read memory address for some peripheral.
902 */
903 static int arm11_write_memory_inner(struct target *target,
904 uint32_t address, uint32_t size,
905 uint32_t count, const uint8_t *buffer,
906 bool no_increment)
907 {
908 int retval;
909
910 if (target->state != TARGET_HALTED) {
911 LOG_WARNING("target was not halted");
912 return ERROR_TARGET_NOT_HALTED;
913 }
914
915 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
916 address,
917 size,
918 count);
919
920 struct arm11_common *arm11 = target_to_arm11(target);
921
922 retval = arm11_run_instr_data_prepare(arm11);
923 if (retval != ERROR_OK)
924 return retval;
925
926 /* load r0 with buffer address
927 * MRC p14,0,r0,c0,c5,0 */
928 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
929 if (retval != ERROR_OK)
930 return retval;
931
932 /* burst writes are not used for single words as those may well be
933 * reset init script writes.
934 *
935 * The other advantage is that as burst writes are default, we'll
936 * now exercise both burst and non-burst code paths with the
937 * default settings, increasing code coverage.
938 */
939 bool burst = arm11->memwrite_burst && (count > 1);
940
941 switch (size) {
942 case 1:
943 {
944 arm11->arm.core_cache->reg_list[1].dirty = true;
945
946 for (size_t i = 0; i < count; i++) {
947 /* load r1 from DCC with byte data */
948 /* MRC p14,0,r1,c0,c5,0 */
949 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
950 if (retval != ERROR_OK)
951 return retval;
952
953 /* write r1 to memory */
954 /* strb r1, [r0], #1 */
955 /* strb r1, [r0] */
956 retval = arm11_run_instr_no_data1(arm11,
957 !no_increment ? 0xe4c01001 : 0xe5c01000);
958 if (retval != ERROR_OK)
959 return retval;
960 }
961
962 break;
963 }
964
965 case 2:
966 {
967 arm11->arm.core_cache->reg_list[1].dirty = true;
968
969 for (size_t i = 0; i < count; i++) {
970 uint16_t value;
971 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
972
973 /* load r1 from DCC with halfword data */
974 /* MRC p14,0,r1,c0,c5,0 */
975 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
976 if (retval != ERROR_OK)
977 return retval;
978
979 /* write r1 to memory */
980 /* strh r1, [r0], #2 */
981 /* strh r1, [r0] */
982 retval = arm11_run_instr_no_data1(arm11,
983 !no_increment ? 0xe0c010b2 : 0xe1c010b0);
984 if (retval != ERROR_OK)
985 return retval;
986 }
987
988 break;
989 }
990
991 case 4: {
992 /* stream word data through DCC directly to memory */
993 /* increment: STC p14,c5,[R0],#4 */
994 /* no increment: STC p14,c5,[R0]*/
995 uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
996
997 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
998 uint32_t *words = (uint32_t *)(void *)buffer;
999
1000 /* "burst" here just means trusting each instruction executes
1001 * fully before we run the next one: per-word roundtrips, to
1002 * check the Ready flag, are not used.
1003 */
1004 if (!burst)
1005 retval = arm11_run_instr_data_to_core(arm11,
1006 instr, words, count);
1007 else
1008 retval = arm11_run_instr_data_to_core_noack(arm11,
1009 instr, words, count);
1010 if (retval != ERROR_OK)
1011 return retval;
1012
1013 break;
1014 }
1015 }
1016
1017 /* r0 verification */
1018 if (!no_increment) {
1019 uint32_t r0;
1020
1021 /* MCR p14,0,R0,c0,c5,0 */
1022 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1023 if (retval != ERROR_OK)
1024 return retval;
1025
1026 if (address + size * count != r0) {
1027 LOG_ERROR("Data transfer failed. Expected end "
1028 "address 0x%08x, got 0x%08x",
1029 (unsigned) (address + size * count),
1030 (unsigned) r0);
1031
1032 if (burst)
1033 LOG_ERROR(
1034 "use 'arm11 memwrite burst disable' to disable fast burst mode");
1035
1036
1037 if (arm11->memwrite_error_fatal)
1038 return ERROR_FAIL;
1039 }
1040 }
1041
1042 return arm11_run_instr_data_finish(arm11);
1043 }
1044
1045 static int arm11_write_memory(struct target *target,
1046 target_addr_t address, uint32_t size,
1047 uint32_t count, const uint8_t *buffer)
1048 {
1049 /* pointer increment matters only for multi-unit writes ...
1050 * not e.g. to a "reset the chip" controller.
1051 */
1052 return arm11_write_memory_inner(target, address, size,
1053 count, buffer, count == 1);
1054 }
1055
1056 /* target break-/watchpoint control
1057 * rw: 0 = write, 1 = read, 2 = access
1058 */
1059 static int arm11_add_breakpoint(struct target *target,
1060 struct breakpoint *breakpoint)
1061 {
1062 struct arm11_common *arm11 = target_to_arm11(target);
1063
1064 #if 0
1065 if (breakpoint->type == BKPT_SOFT) {
1066 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1067 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1068 }
1069 #endif
1070
1071 if (!arm11->free_brps) {
1072 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1073 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1074 }
1075
1076 if (breakpoint->length != 4) {
1077 LOG_DEBUG("only breakpoints of four bytes length supported");
1078 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1079 }
1080
1081 arm11->free_brps--;
1082
1083 return ERROR_OK;
1084 }
1085
1086 static int arm11_remove_breakpoint(struct target *target,
1087 struct breakpoint *breakpoint)
1088 {
1089 struct arm11_common *arm11 = target_to_arm11(target);
1090
1091 arm11->free_brps++;
1092
1093 return ERROR_OK;
1094 }
1095
1096 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1097 {
1098 struct arm11_common *arm11;
1099
1100 if (target->tap == NULL)
1101 return ERROR_FAIL;
1102
1103 if (target->tap->ir_length != 5) {
1104 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1105 return ERROR_COMMAND_SYNTAX_ERROR;
1106 }
1107
1108 arm11 = calloc(1, sizeof *arm11);
1109 if (!arm11)
1110 return ERROR_FAIL;
1111
1112 arm11->arm.core_type = ARM_MODE_ANY;
1113 arm_init_arch_info(target, &arm11->arm);
1114
1115 arm11->jtag_info.tap = target->tap;
1116 arm11->jtag_info.scann_size = 5;
1117 arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1118 arm11->jtag_info.cur_scan_chain = ~0; /* invalid/unknown */
1119 arm11->jtag_info.intest_instr = ARM11_INTEST;
1120
1121 arm11->memwrite_burst = true;
1122 arm11->memwrite_error_fatal = true;
1123
1124 return ERROR_OK;
1125 }
1126
1127 static int arm11_init_target(struct command_context *cmd_ctx,
1128 struct target *target)
1129 {
1130 /* Initialize anything we can set up without talking to the target */
1131 return ERROR_OK;
1132 }
1133
1134 /* talk to the target and set things up */
1135 static int arm11_examine(struct target *target)
1136 {
1137 int retval;
1138 char *type;
1139 struct arm11_common *arm11 = target_to_arm11(target);
1140 uint32_t didr, device_id;
1141 uint8_t implementor;
1142
1143 /* FIXME split into do-first-time and do-every-time logic ... */
1144
1145 /* check IDCODE */
1146
1147 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1148
1149 struct scan_field idcode_field;
1150
1151 arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1152
1153 arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &idcode_field, TAP_DRPAUSE);
1154
1155 /* check DIDR */
1156
1157 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1158
1159 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1160
1161 struct scan_field chain0_fields[2];
1162
1163 arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1164 arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
1165
1166 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
1167 chain0_fields), chain0_fields, TAP_IDLE);
1168
1169 CHECK_RETVAL(jtag_execute_queue());
1170
1171 /* assume the manufacturer id is ok; check the part # */
1172 switch ((device_id >> 12) & 0xFFFF) {
1173 case 0x7B36:
1174 type = "ARM1136";
1175 break;
1176 case 0x7B37:
1177 type = "ARM11 MPCore";
1178 break;
1179 case 0x7B56:
1180 type = "ARM1156";
1181 break;
1182 case 0x7B76:
1183 arm11->arm.core_type = ARM_MODE_MON;
1184 /* NOTE: could default arm11->hardware_step to true */
1185 type = "ARM1176";
1186 break;
1187 default:
1188 LOG_ERROR("unexpected ARM11 ID code");
1189 return ERROR_FAIL;
1190 }
1191 LOG_INFO("found %s", type);
1192
1193 /* unlikely this could ever fail, but ... */
1194 switch ((didr >> 16) & 0x0F) {
1195 case ARM11_DEBUG_V6:
1196 case ARM11_DEBUG_V61: /* supports security extensions */
1197 break;
1198 default:
1199 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1200 return ERROR_FAIL;
1201 }
1202
1203 arm11->brp = ((didr >> 24) & 0x0F) + 1;
1204
1205 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1206 arm11->free_brps = arm11->brp;
1207
1208 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1209 device_id, implementor, didr);
1210
1211 /* Build register cache "late", after target_init(), since we
1212 * want to know if this core supports Secure Monitor mode.
1213 */
1214 if (!target_was_examined(target))
1215 CHECK_RETVAL(arm11_dpm_init(arm11, didr));
1216
1217 /* as a side-effect this reads DSCR and thus
1218 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1219 * as suggested by the spec.
1220 */
1221
1222 retval = arm11_check_init(arm11);
1223 if (retval != ERROR_OK)
1224 return retval;
1225
1226 /* ETM on ARM11 still uses original scanchain 6 access mode */
1227 if (arm11->arm.etm && !target_was_examined(target)) {
1228 *register_get_last_cache_p(&target->reg_cache) =
1229 etm_build_reg_cache(target, &arm11->jtag_info,
1230 arm11->arm.etm);
1231 CHECK_RETVAL(etm_setup(target));
1232 }
1233
1234 target_set_examined(target);
1235
1236 return ERROR_OK;
1237 }
1238
1239 #define ARM11_BOOL_WRAPPER(name, print_name) \
1240 COMMAND_HANDLER(arm11_handle_bool_ ## name) \
1241 { \
1242 struct target *target = get_current_target(CMD_CTX); \
1243 struct arm11_common *arm11 = target_to_arm11(target); \
1244 \
1245 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1246 &arm11->name, print_name); \
1247 }
1248
1249 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1250 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1251 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1252 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1253
1254 /* REVISIT handle the VCR bits like other ARMs: use symbols for
1255 * input and output values.
1256 */
1257
1258 COMMAND_HANDLER(arm11_handle_vcr)
1259 {
1260 struct target *target = get_current_target(CMD_CTX);
1261 struct arm11_common *arm11 = target_to_arm11(target);
1262
1263 switch (CMD_ARGC) {
1264 case 0:
1265 break;
1266 case 1:
1267 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr);
1268 break;
1269 default:
1270 return ERROR_COMMAND_SYNTAX_ERROR;
1271 }
1272
1273 LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr);
1274 return ERROR_OK;
1275 }
1276
1277 static const struct command_registration arm11_mw_command_handlers[] = {
1278 {
1279 .name = "burst",
1280 .handler = arm11_handle_bool_memwrite_burst,
1281 .mode = COMMAND_ANY,
1282 .help = "Display or modify flag controlling potentially "
1283 "risky fast burst mode (default: enabled)",
1284 .usage = "['enable'|'disable']",
1285 },
1286 {
1287 .name = "error_fatal",
1288 .handler = arm11_handle_bool_memwrite_error_fatal,
1289 .mode = COMMAND_ANY,
1290 .help = "Display or modify flag controlling transfer "
1291 "termination on transfer errors"
1292 " (default: enabled)",
1293 .usage = "['enable'|'disable']",
1294 },
1295 COMMAND_REGISTRATION_DONE
1296 };
1297 static const struct command_registration arm11_any_command_handlers[] = {
1298 {
1299 /* "hardware_step" is only here to check if the default
1300 * simulate + breakpoint implementation is broken.
1301 * TEMPORARY! NOT DOCUMENTED! */
1302 .name = "hardware_step",
1303 .handler = arm11_handle_bool_hardware_step,
1304 .mode = COMMAND_ANY,
1305 .help = "DEBUG ONLY - Hardware single stepping"
1306 " (default: disabled)",
1307 .usage = "['enable'|'disable']",
1308 },
1309 {
1310 .name = "memwrite",
1311 .mode = COMMAND_ANY,
1312 .help = "memwrite command group",
1313 .usage = "",
1314 .chain = arm11_mw_command_handlers,
1315 },
1316 {
1317 .name = "step_irq_enable",
1318 .handler = arm11_handle_bool_step_irq_enable,
1319 .mode = COMMAND_ANY,
1320 .help = "Display or modify flag controlling interrupt "
1321 "enable while stepping (default: disabled)",
1322 .usage = "['enable'|'disable']",
1323 },
1324 {
1325 .name = "vcr",
1326 .handler = arm11_handle_vcr,
1327 .mode = COMMAND_ANY,
1328 .help = "Display or modify Vector Catch Register",
1329 .usage = "[value]",
1330 },
1331 COMMAND_REGISTRATION_DONE
1332 };
1333
1334 static const struct command_registration arm11_command_handlers[] = {
1335 {
1336 .chain = arm_command_handlers,
1337 },
1338 {
1339 .chain = etm_command_handlers,
1340 },
1341 {
1342 .name = "arm11",
1343 .mode = COMMAND_ANY,
1344 .help = "ARM11 command group",
1345 .usage = "",
1346 .chain = arm11_any_command_handlers,
1347 },
1348 COMMAND_REGISTRATION_DONE
1349 };
1350
1351 /** Holds methods for ARM11xx targets. */
1352 struct target_type arm11_target = {
1353 .name = "arm11",
1354
1355 .poll = arm11_poll,
1356 .arch_state = arm11_arch_state,
1357
1358 .halt = arm11_halt,
1359 .resume = arm11_resume,
1360 .step = arm11_step,
1361
1362 .assert_reset = arm11_assert_reset,
1363 .deassert_reset = arm11_deassert_reset,
1364
1365 .get_gdb_arch = arm_get_gdb_arch,
1366 .get_gdb_reg_list = arm_get_gdb_reg_list,
1367
1368 .read_memory = arm11_read_memory,
1369 .write_memory = arm11_write_memory,
1370
1371 .checksum_memory = arm_checksum_memory,
1372 .blank_check_memory = arm_blank_check_memory,
1373
1374 .add_breakpoint = arm11_add_breakpoint,
1375 .remove_breakpoint = arm11_remove_breakpoint,
1376
1377 .run_algorithm = armv4_5_run_algorithm,
1378
1379 .commands = arm11_command_handlers,
1380 .target_create = arm11_target_create,
1381 .init_target = arm11_init_target,
1382 .examine = arm11_examine,
1383 };