f7a199c56c4735d0ddd4e5202c8df9bcff3365ad
[openocd.git] / src / target / adi_v5_swd.c
1 /***************************************************************************
2 *
3 * Copyright (C) 2010 by David Brownell
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the
17 * Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 ***************************************************************************/
20
21 /**
22 * @file
23 * Utilities to support ARM "Serial Wire Debug" (SWD), a low pin-count debug
24 * link protocol used in cases where JTAG is not wanted. This is coupled to
25 * recent versions of ARM's "CoreSight" debug framework. This specific code
26 * is a transport level interface, with "target/arm_adi_v5.[hc]" code
27 * understanding operation semantics, shared with the JTAG transport.
28 *
29 * Single-DAP support only.
30 *
31 * for details, see "ARM IHI 0031A"
32 * ARM Debug Interface v5 Architecture Specification
33 * especially section 5.3 for SWD protocol
34 *
35 * On many chips (most current Cortex-M3 parts) SWD is a run-time alternative
36 * to JTAG. Boards may support one or both. There are also SWD-only chips,
37 * (using SW-DP not SWJ-DP).
38 *
39 * Even boards that also support JTAG can benefit from SWD support, because
40 * usually there's no way to access the SWO trace view mechanism in JTAG mode.
41 * That is, trace access may require SWD support.
42 *
43 */
44
45 #ifdef HAVE_CONFIG_H
46 #include "config.h"
47 #endif
48
49 #include "arm.h"
50 #include "arm_adi_v5.h"
51 #include <helper/time_support.h>
52
53 #include <transport/transport.h>
54 #include <jtag/interface.h>
55
56 #include <jtag/swd.h>
57
58 /* YUK! - but this is currently a global.... */
59 extern struct jtag_interface *jtag_interface;
60 static bool do_sync;
61
62 static void swd_finish_read(struct adiv5_dap *dap)
63 {
64 const struct swd_driver *swd = jtag_interface->swd;
65 if (dap->last_read != NULL) {
66 swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read, 0);
67 dap->last_read = NULL;
68 }
69 }
70
71 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
72 uint32_t data);
73 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
74 uint32_t *data);
75
76 static void swd_clear_sticky_errors(struct adiv5_dap *dap)
77 {
78 const struct swd_driver *swd = jtag_interface->swd;
79 assert(swd);
80
81 swd->write_reg(swd_cmd(false, false, DP_ABORT),
82 STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
83 }
84
85 static int swd_run_inner(struct adiv5_dap *dap)
86 {
87 const struct swd_driver *swd = jtag_interface->swd;
88 int retval;
89
90 retval = swd->run();
91
92 if (retval != ERROR_OK) {
93 /* fault response */
94 dap->do_reconnect = true;
95 }
96
97 return retval;
98 }
99
100 static int swd_connect(struct adiv5_dap *dap)
101 {
102 uint32_t idcode;
103 int status;
104
105 /* FIXME validate transport config ... is the
106 * configured DAP present (check IDCODE)?
107 * Is *only* one DAP configured?
108 *
109 * MUST READ IDCODE
110 */
111
112 /* Note, debugport_init() does setup too */
113 jtag_interface->swd->switch_seq(JTAG_TO_SWD);
114
115 /* Make sure we don't try to perform any other accesses before the DPIDR read. */
116 dap->do_reconnect = false;
117 dap->select = 0;
118
119 swd_queue_dp_read(dap, DP_IDCODE, &idcode);
120
121 /* force clear all sticky faults */
122 swd_clear_sticky_errors(dap);
123
124 status = swd_run_inner(dap);
125
126 dap->select = DP_SELECT_INVALID;
127
128 if (status == ERROR_OK) {
129 LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
130 dap->do_reconnect = false;
131 } else
132 dap->do_reconnect = true;
133
134 return status;
135 }
136
137 static inline int check_sync(struct adiv5_dap *dap)
138 {
139 return do_sync ? swd_run_inner(dap) : ERROR_OK;
140 }
141
142 static int swd_check_reconnect(struct adiv5_dap *dap)
143 {
144 if (dap->do_reconnect)
145 return swd_connect(dap);
146
147 return ERROR_OK;
148 }
149
150 static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
151 {
152 const struct swd_driver *swd = jtag_interface->swd;
153 assert(swd);
154
155 swd->write_reg(swd_cmd(false, false, DP_ABORT),
156 DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
157 return check_sync(dap);
158 }
159
160 /** Select the DP register bank matching bits 7:4 of reg. */
161 static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
162 {
163 if (reg == DP_SELECT)
164 return;
165
166 uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
167 uint32_t sel = select_dp_bank
168 | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
169
170 if (sel == dap->select)
171 return;
172
173 dap->select = sel;
174
175 swd_queue_dp_write(dap, DP_SELECT, sel);
176 }
177
178 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
179 uint32_t *data)
180 {
181 const struct swd_driver *swd = jtag_interface->swd;
182 assert(swd);
183
184 int retval = swd_check_reconnect(dap);
185 if (retval != ERROR_OK)
186 return retval;
187
188 swd_queue_dp_bankselect(dap, reg);
189 swd->read_reg(swd_cmd(true, false, reg), data, 0);
190
191 return check_sync(dap);
192 }
193
194 static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
195 uint32_t data)
196 {
197 const struct swd_driver *swd = jtag_interface->swd;
198 assert(swd);
199
200 int retval = swd_check_reconnect(dap);
201 if (retval != ERROR_OK)
202 return retval;
203
204 swd_finish_read(dap);
205 swd_queue_dp_bankselect(dap, reg);
206 swd->write_reg(swd_cmd(false, false, reg), data, 0);
207
208 return check_sync(dap);
209 }
210
211 /** Select the AP register bank matching bits 7:4 of reg. */
212 static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
213 {
214 struct adiv5_dap *dap = ap->dap;
215 uint32_t sel = ((uint32_t)ap->ap_num << 24)
216 | (reg & 0x000000F0)
217 | (dap->select & DP_SELECT_DPBANK);
218
219 if (sel == dap->select)
220 return;
221
222 dap->select = sel;
223
224 swd_queue_dp_write(dap, DP_SELECT, sel);
225 }
226
227 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
228 uint32_t *data)
229 {
230 const struct swd_driver *swd = jtag_interface->swd;
231 assert(swd);
232
233 struct adiv5_dap *dap = ap->dap;
234
235 int retval = swd_check_reconnect(dap);
236 if (retval != ERROR_OK)
237 return retval;
238
239 swd_queue_ap_bankselect(ap, reg);
240 swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
241 dap->last_read = data;
242
243 return check_sync(dap);
244 }
245
246 static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
247 uint32_t data)
248 {
249 const struct swd_driver *swd = jtag_interface->swd;
250 assert(swd);
251
252 struct adiv5_dap *dap = ap->dap;
253
254 int retval = swd_check_reconnect(dap);
255 if (retval != ERROR_OK)
256 return retval;
257
258 swd_finish_read(dap);
259 swd_queue_ap_bankselect(ap, reg);
260 swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
261
262 return check_sync(dap);
263 }
264
265 /** Executes all queued DAP operations. */
266 static int swd_run(struct adiv5_dap *dap)
267 {
268 swd_finish_read(dap);
269 return swd_run_inner(dap);
270 }
271
272 const struct dap_ops swd_dap_ops = {
273 .queue_dp_read = swd_queue_dp_read,
274 .queue_dp_write = swd_queue_dp_write,
275 .queue_ap_read = swd_queue_ap_read,
276 .queue_ap_write = swd_queue_ap_write,
277 .queue_ap_abort = swd_queue_ap_abort,
278 .run = swd_run,
279 };
280
281 /*
282 * This represents the bits which must be sent out on TMS/SWDIO to
283 * switch a DAP implemented using an SWJ-DP module into SWD mode.
284 * These bits are stored (and transmitted) LSB-first.
285 *
286 * See the DAP-Lite specification, section 2.2.5 for information
287 * about making the debug link select SWD or JTAG. (Similar info
288 * is in a few other ARM documents.)
289 */
290 static const uint8_t jtag2swd_bitseq[] = {
291 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
292 * putting both JTAG and SWD logic into reset state.
293 */
294 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
295 /* Switching sequence enables SWD and disables JTAG
296 * NOTE: bits in the DP's IDCODE may expose the need for
297 * an old/obsolete/deprecated sequence (0xb6 0xed).
298 */
299 0x9e, 0xe7,
300 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
301 * putting both JTAG and SWD logic into reset state.
302 */
303 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
304 };
305
306 /**
307 * Put the debug link into SWD mode, if the target supports it.
308 * The link's initial mode may be either JTAG (for example,
309 * with SWJ-DP after reset) or SWD.
310 *
311 * @param target Enters SWD mode (if possible).
312 *
313 * Note that targets using the JTAG-DP do not support SWD, and that
314 * some targets which could otherwise support it may have have been
315 * configured to disable SWD signaling
316 *
317 * @return ERROR_OK or else a fault code.
318 */
319 int dap_to_swd(struct target *target)
320 {
321 struct arm *arm = target_to_arm(target);
322 int retval;
323
324 if (!arm->dap) {
325 LOG_ERROR("SWD mode is not available");
326 return ERROR_FAIL;
327 }
328
329 LOG_DEBUG("Enter SWD mode");
330
331 /* REVISIT it's ugly to need to make calls to a "jtag"
332 * subsystem if the link may not be in JTAG mode...
333 */
334
335 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
336 jtag2swd_bitseq, TAP_INVALID);
337 if (retval == ERROR_OK)
338 retval = jtag_execute_queue();
339
340 /* set up the DAP's ops vector for SWD mode. */
341 arm->dap->ops = &swd_dap_ops;
342
343 return retval;
344 }
345
346 COMMAND_HANDLER(handle_swd_wcr)
347 {
348 int retval;
349 struct target *target = get_current_target(CMD_CTX);
350 struct arm *arm = target_to_arm(target);
351 struct adiv5_dap *dap = arm->dap;
352 uint32_t wcr;
353 unsigned trn, scale = 0;
354
355 switch (CMD_ARGC) {
356 /* no-args: just dump state */
357 case 0:
358 /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
359 retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
360 if (retval == ERROR_OK)
361 dap->ops->run(dap);
362 if (retval != ERROR_OK) {
363 LOG_ERROR("can't read WCR?");
364 return retval;
365 }
366
367 command_print(CMD_CTX,
368 "turnaround=%" PRIu32 ", prescale=%" PRIu32,
369 WCR_TO_TRN(wcr),
370 WCR_TO_PRESCALE(wcr));
371 return ERROR_OK;
372
373 case 2: /* TRN and prescale */
374 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], scale);
375 if (scale > 7) {
376 LOG_ERROR("prescale %d is too big", scale);
377 return ERROR_FAIL;
378 }
379 /* FALL THROUGH */
380
381 case 1: /* TRN only */
382 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], trn);
383 if (trn < 1 || trn > 4) {
384 LOG_ERROR("turnaround %d is invalid", trn);
385 return ERROR_FAIL;
386 }
387
388 wcr = ((trn - 1) << 8) | scale;
389 /* FIXME
390 * write WCR ...
391 * then, re-init adapter with new TRN
392 */
393 LOG_ERROR("can't yet modify WCR");
394 return ERROR_FAIL;
395
396 default: /* too many arguments */
397 return ERROR_COMMAND_SYNTAX_ERROR;
398 }
399 }
400
401 static const struct command_registration swd_commands[] = {
402 {
403 /*
404 * Set up SWD and JTAG targets identically, unless/until
405 * infrastructure improves ... meanwhile, ignore all
406 * JTAG-specific stuff like IR length for SWD.
407 *
408 * REVISIT can we verify "just one SWD DAP" here/early?
409 */
410 .name = "newdap",
411 .jim_handler = jim_jtag_newtap,
412 .mode = COMMAND_CONFIG,
413 .help = "declare a new SWD DAP"
414 },
415 {
416 .name = "wcr",
417 .handler = handle_swd_wcr,
418 .mode = COMMAND_ANY,
419 .help = "display or update DAP's WCR register",
420 .usage = "turnaround (1..4), prescale (0..7)",
421 },
422
423 /* REVISIT -- add a command for SWV trace on/off */
424 COMMAND_REGISTRATION_DONE
425 };
426
427 static const struct command_registration swd_handlers[] = {
428 {
429 .name = "swd",
430 .mode = COMMAND_ANY,
431 .help = "SWD command group",
432 .chain = swd_commands,
433 },
434 COMMAND_REGISTRATION_DONE
435 };
436
437 static int swd_select(struct command_context *ctx)
438 {
439 int retval;
440
441 retval = register_commands(ctx, NULL, swd_handlers);
442
443 if (retval != ERROR_OK)
444 return retval;
445
446 const struct swd_driver *swd = jtag_interface->swd;
447
448 /* be sure driver is in SWD mode; start
449 * with hardware default TRN (1), it can be changed later
450 */
451 if (!swd || !swd->read_reg || !swd->write_reg || !swd->init) {
452 LOG_DEBUG("no SWD driver?");
453 return ERROR_FAIL;
454 }
455
456 retval = swd->init();
457 if (retval != ERROR_OK) {
458 LOG_DEBUG("can't init SWD driver");
459 return retval;
460 }
461
462 /* force DAP into SWD mode (not JTAG) */
463 /*retval = dap_to_swd(target);*/
464
465 if (ctx->current_target) {
466 /* force DAP into SWD mode (not JTAG) */
467 struct target *target = get_current_target(ctx);
468 retval = dap_to_swd(target);
469 }
470
471 return retval;
472 }
473
474 static int swd_init(struct command_context *ctx)
475 {
476 struct target *target = get_current_target(ctx);
477 struct arm *arm = target_to_arm(target);
478 struct adiv5_dap *dap = arm->dap;
479 /* Force the DAP's ops vector for SWD mode.
480 * messy - is there a better way? */
481 arm->dap->ops = &swd_dap_ops;
482
483 return swd_connect(dap);
484 }
485
486 static struct transport swd_transport = {
487 .name = "swd",
488 .select = swd_select,
489 .init = swd_init,
490 };
491
492 static void swd_constructor(void) __attribute__((constructor));
493 static void swd_constructor(void)
494 {
495 transport_register(&swd_transport);
496 }
497
498 /** Returns true if the current debug session
499 * is using SWD as its transport.
500 */
501 bool transport_is_swd(void)
502 {
503 return get_current_transport() == &swd_transport;
504 }