75461c3fa7e8bf95fd627e8914bf4136d56c6a92
[openocd.git] / src / target / adi_v5_jtag.c
1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin
3 * lundin@mlu.mine.nu
4 *
5 * Copyright (C) 2008 by Spencer Oliver
6 * spen@spen-soft.co.uk
7 *
8 * Copyright (C) 2009 by Oyvind Harboe
9 * oyvind.harboe@zylin.com
10 *
11 * Copyright (C) 2009-2010 by David Brownell
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the
25 * Free Software Foundation, Inc.,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 ***************************************************************************/
28
29 /**
30 * @file
31 * This file implements JTAG transport support for cores implementing
32 the ARM Debug Interface version 5 (ADIv5).
33 */
34
35 #ifdef HAVE_CONFIG_H
36 #include "config.h"
37 #endif
38
39 #include "arm.h"
40 #include "arm_adi_v5.h"
41 #include <helper/time_support.h>
42
43
44 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
45 #define JTAG_DP_ABORT 0x8
46 #define JTAG_DP_DPACC 0xA
47 #define JTAG_DP_APACC 0xB
48 #define JTAG_DP_IDCODE 0xE
49
50 /* three-bit ACK values for DPACC and APACC reads */
51 #define JTAG_ACK_OK_FAULT 0x2
52 #define JTAG_ACK_WAIT 0x1
53
54 /***************************************************************************
55 *
56 * DPACC and APACC scanchain access through JTAG-DP (or SWJ-DP)
57 *
58 ***************************************************************************/
59
60 /**
61 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
62 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
63 * discusses operations which access these registers.
64 *
65 * Note that only one scan is performed. If RnW is set, a separate scan
66 * will be needed to collect the data which was read; the "invalue" collects
67 * the posted result of a preceding operation, not the current one.
68 *
69 * @param dap the DAP
70 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
71 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
72 * SELECT register has more addressing bits.
73 * @param RnW false iff outvalue will be written to the DP or AP
74 * @param outvalue points to a 32-bit (little-endian) integer
75 * @param invalue NULL, or points to a 32-bit (little-endian) integer
76 * @param ack points to where the three bit JTAG_ACK_* code will be stored
77 */
78
79 /* FIXME don't export ... this is a temporary workaround for the
80 * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
81 */
82 int adi_jtag_dp_scan(struct adiv5_dap *dap,
83 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
84 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
85 {
86 struct arm_jtag *jtag_info = dap->jtag_info;
87 struct scan_field fields[2];
88 uint8_t out_addr_buf;
89 int retval;
90
91 retval = arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
92 if (retval != ERROR_OK)
93 return retval;
94
95 /* Scan out a read or write operation using some DP or AP register.
96 * For APACC access with any sticky error flag set, this is discarded.
97 */
98 fields[0].num_bits = 3;
99 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
100 fields[0].out_value = &out_addr_buf;
101 fields[0].in_value = ack;
102
103 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
104 * complete; data we write is discarded, data we read is unpredictable.
105 * When overrun detect is active, STICKYORUN is set.
106 */
107
108 fields[1].num_bits = 32;
109 fields[1].out_value = outvalue;
110 fields[1].in_value = invalue;
111
112 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
113
114 /* Add specified number of tck clocks after starting memory bus
115 * access, giving the hardware time to complete the access.
116 * They provide more time for the (MEM) AP to complete the read ...
117 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
118 */
119 if ((instr == JTAG_DP_APACC)
120 && ((reg_addr == AP_REG_DRW)
121 || ((reg_addr & 0xF0) == AP_REG_BD0))
122 && (dap->memaccess_tck != 0))
123 jtag_add_runtest(dap->memaccess_tck,
124 TAP_IDLE);
125
126 return ERROR_OK;
127 }
128
129 /**
130 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
131 * This is exactly like adi_jtag_dp_scan(), except that endianness
132 * conversions are performed (so the types of invalue and outvalue
133 * must be different).
134 */
135 static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
136 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
137 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
138 {
139 uint8_t out_value_buf[4];
140 int retval;
141
142 buf_set_u32(out_value_buf, 0, 32, outvalue);
143
144 retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
145 out_value_buf, (uint8_t *)invalue, ack);
146 if (retval != ERROR_OK)
147 return retval;
148
149 if (invalue)
150 jtag_add_callback(arm_le_to_h_u32,
151 (jtag_callback_data_t) invalue);
152
153 return retval;
154 }
155
156 /**
157 * Utility to write AP registers.
158 */
159 static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
160 uint8_t reg_addr, uint8_t *outvalue)
161 {
162 return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
163 outvalue, NULL, NULL);
164 }
165
166 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
167 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
168 uint32_t outvalue, uint32_t *invalue)
169 {
170 int retval;
171
172 /* Issue the read or write */
173 retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
174 RnW, outvalue, NULL, NULL);
175 if (retval != ERROR_OK)
176 return retval;
177
178 /* For reads, collect posted value; RDBUFF has no other effect.
179 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
180 */
181 if ((RnW == DPAP_READ) && (invalue != NULL))
182 retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
183 DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
184 return retval;
185 }
186
187 static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
188 {
189 int retval;
190 uint32_t ctrlstat;
191
192 /* too expensive to call keep_alive() here */
193
194 /* Here be dragons!
195 *
196 * It is easy to be in a JTAG clock range where the target
197 * is not operating in a stable fashion. This happens
198 * for a few reasons:
199 *
200 * - the user may construct a simple test case to try to see
201 * if a higher JTAG clock works to eke out more performance.
202 * This simple case may pass, but more complex situations can
203 * fail.
204 *
205 * - The mostly works JTAG clock rate and the complete failure
206 * JTAG clock rate may be as much as 2-4x apart. This seems
207 * to be especially true on RC oscillator driven parts.
208 *
209 * So: even if calling adi_jtag_scan_inout_check_u32() multiple
210 * times here seems to "make things better here", it is just
211 * hiding problems with too high a JTAG clock.
212 *
213 * Note that even if some parts have RCLK/RTCK, that doesn't
214 * mean that RCLK/RTCK is the *correct* rate to run the JTAG
215 * interface at, i.e. RCLK/RTCK rates can be "too high", especially
216 * before the RC oscillator phase is not yet complete.
217 */
218
219 /* Post CTRL/STAT read; discard any previous posted read value
220 * but collect its ACK status.
221 */
222 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
223 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
224 if (retval != ERROR_OK)
225 return retval;
226 if ((retval = jtag_execute_queue()) != ERROR_OK)
227 return retval;
228
229 dap->ack = dap->ack & 0x7;
230
231 /* common code path avoids calling timeval_ms() */
232 if (dap->ack != JTAG_ACK_OK_FAULT)
233 {
234 long long then = timeval_ms();
235
236 while (dap->ack != JTAG_ACK_OK_FAULT)
237 {
238 if (dap->ack == JTAG_ACK_WAIT)
239 {
240 if ((timeval_ms()-then) > 1000)
241 {
242 /* NOTE: this would be a good spot
243 * to use JTAG_DP_ABORT.
244 */
245 LOG_WARNING("Timeout (1000ms) waiting "
246 "for ACK=OK/FAULT "
247 "in JTAG-DP transaction");
248 return ERROR_JTAG_DEVICE_ERROR;
249 }
250 }
251 else
252 {
253 LOG_WARNING("Invalid ACK %#x "
254 "in JTAG-DP transaction",
255 dap->ack);
256 return ERROR_JTAG_DEVICE_ERROR;
257 }
258
259 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
260 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
261 if (retval != ERROR_OK)
262 return retval;
263 if ((retval = dap_run(dap)) != ERROR_OK)
264 return retval;
265 dap->ack = dap->ack & 0x7;
266 }
267 }
268
269 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
270
271 /* Check for STICKYERR and STICKYORUN */
272 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
273 {
274 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
275 /* Check power to debug regions */
276 if ((ctrlstat & 0xf0000000) != 0xf0000000)
277 {
278 retval = ahbap_debugport_init(dap);
279 if (retval != ERROR_OK)
280 return retval;
281 }
282 else
283 {
284 uint32_t mem_ap_csw, mem_ap_tar;
285
286 /* Maybe print information about last intended
287 * MEM-AP access; but not if autoincrementing.
288 * *Real* CSW and TAR values are always shown.
289 */
290 if (dap->ap_tar_value != (uint32_t) -1)
291 LOG_DEBUG("MEM-AP Cached values: "
292 "ap_bank 0x%" PRIx32
293 ", ap_csw 0x%" PRIx32
294 ", ap_tar 0x%" PRIx32,
295 dap->ap_bank_value,
296 dap->ap_csw_value,
297 dap->ap_tar_value);
298
299 if (ctrlstat & SSTICKYORUN)
300 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
301 "memaccess, or reduce jtag speed");
302
303 if (ctrlstat & SSTICKYERR)
304 LOG_ERROR("JTAG-DP STICKY ERROR");
305
306 /* Clear Sticky Error Bits */
307 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
308 DP_CTRL_STAT, DPAP_WRITE,
309 dap->dp_ctrl_stat | SSTICKYORUN
310 | SSTICKYERR, NULL);
311 if (retval != ERROR_OK)
312 return retval;
313 retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
314 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
315 if (retval != ERROR_OK)
316 return retval;
317 if ((retval = dap_run(dap)) != ERROR_OK)
318 return retval;
319
320 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
321
322 retval = dap_queue_ap_read(dap,
323 AP_REG_CSW, &mem_ap_csw);
324 if (retval != ERROR_OK)
325 return retval;
326
327 retval = dap_queue_ap_read(dap,
328 AP_REG_TAR, &mem_ap_tar);
329 if (retval != ERROR_OK)
330 return retval;
331
332 if ((retval = dap_run(dap)) != ERROR_OK)
333 return retval;
334 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
335 PRIx32, mem_ap_csw, mem_ap_tar);
336
337 }
338 if ((retval = dap_run(dap)) != ERROR_OK)
339 return retval;
340 return ERROR_JTAG_DEVICE_ERROR;
341 }
342
343 return ERROR_OK;
344 }
345
346 /*--------------------------------------------------------------------------*/
347
348 static int jtag_idcode_q_read(struct adiv5_dap *dap,
349 uint8_t *ack, uint32_t *data)
350 {
351 struct arm_jtag *jtag_info = dap->jtag_info;
352 int retval;
353 struct scan_field fields[1];
354
355 /* This is a standard JTAG operation -- no DAP tweakage */
356 retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
357 if (retval != ERROR_OK)
358 return retval;
359
360 fields[0].num_bits = 32;
361 fields[0].out_value = NULL;
362 fields[0].in_value = (void *) data;
363
364 jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
365
366 jtag_add_callback(arm_le_to_h_u32,
367 (jtag_callback_data_t) data);
368
369 return ERROR_OK;
370 }
371
372 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
373 uint32_t *data)
374 {
375 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
376 reg, DPAP_READ, 0, data);
377 }
378
379 static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
380 uint32_t data)
381 {
382 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
383 reg, DPAP_WRITE, data, NULL);
384 }
385
386 /** Select the AP register bank matching bits 7:4 of reg. */
387 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
388 {
389 uint32_t select_ap_bank = reg & 0x000000F0;
390
391 if (select_ap_bank == dap->ap_bank_value)
392 return ERROR_OK;
393 dap->ap_bank_value = select_ap_bank;
394
395 select_ap_bank |= dap->ap_current;
396
397 return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
398 }
399
400 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
401 uint32_t *data)
402 {
403 int retval = jtag_ap_q_bankselect(dap, reg);
404
405 if (retval != ERROR_OK)
406 return retval;
407
408 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
409 DPAP_READ, 0, data);
410 }
411
412 static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
413 uint32_t data)
414 {
415 uint8_t out_value_buf[4];
416
417 int retval = jtag_ap_q_bankselect(dap, reg);
418 if (retval != ERROR_OK)
419 return retval;
420
421 buf_set_u32(out_value_buf, 0, 32, data);
422
423 return adi_jtag_ap_write_check(dap, reg, out_value_buf);
424 }
425
426 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
427 {
428 /* for JTAG, this is the only valid ABORT register operation */
429 return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
430 0, DPAP_WRITE, 1, NULL, ack);
431 }
432
433 static int jtag_dp_run(struct adiv5_dap *dap)
434 {
435 return jtagdp_transaction_endcheck(dap);
436 }
437
438 /* FIXME don't export ... just initialize as
439 * part of DAP setup
440 */
441 const struct dap_ops jtag_dp_ops = {
442 .queue_idcode_read = jtag_idcode_q_read,
443 .queue_dp_read = jtag_dp_q_read,
444 .queue_dp_write = jtag_dp_q_write,
445 .queue_ap_read = jtag_ap_q_read,
446 .queue_ap_write = jtag_ap_q_write,
447 .queue_ap_abort = jtag_ap_q_abort,
448 .run = jtag_dp_run,
449 };
450
451
452 static const uint8_t swd2jtag_bitseq[] = {
453 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
454 * putting both JTAG and SWD logic into reset state.
455 */
456 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
457 /* Switching equence disables SWD and enables JTAG
458 * NOTE: bits in the DP's IDCODE can expose the need for
459 * the old/deprecated sequence (0xae 0xde).
460 */
461 0x3c, 0xe7,
462 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
463 * putting both JTAG and SWD logic into reset state.
464 * NOTE: some docs say "at least 5".
465 */
466 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
467 };
468
469 /** Put the debug link into JTAG mode, if the target supports it.
470 * The link's initial mode may be either SWD or JTAG.
471 *
472 * @param target Enters JTAG mode (if possible).
473 *
474 * Note that targets implemented with SW-DP do not support JTAG, and
475 * that some targets which could otherwise support it may have been
476 * configured to disable JTAG signaling
477 *
478 * @return ERROR_OK or else a fault code.
479 */
480 int dap_to_jtag(struct target *target)
481 {
482 int retval;
483
484 LOG_DEBUG("Enter JTAG mode");
485
486 /* REVISIT it's nasty to need to make calls to a "jtag"
487 * subsystem if the link isn't in JTAG mode...
488 */
489
490 retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
491 swd2jtag_bitseq, TAP_RESET);
492 if (retval == ERROR_OK)
493 retval = jtag_execute_queue();
494
495 /* REVISIT set up the DAP's ops vector for JTAG mode. */
496
497 return retval;
498 }