zy1000: removed JTAG master TCP/IP server
[openocd.git] / src / jtag / zy1000 / zy1000.c
1 /***************************************************************************
2 * Copyright (C) 2007-2010 by Øyvind Harboe *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 /* This file supports the zy1000 debugger: http://www.zylin.com/zy1000.html
21 *
22 * The zy1000 is a standalone debugger that has a web interface and
23 * requires no drivers on the developer host as all communication
24 * is via TCP/IP. The zy1000 gets it performance(~400-700kBytes/s
25 * DCC downloads @ 16MHz target) as it has an FPGA to hardware
26 * accelerate the JTAG commands, while offering *very* low latency
27 * between OpenOCD and the FPGA registers.
28 *
29 * The disadvantage of the zy1000 is that it has a feeble CPU compared to
30 * a PC(ca. 50-500 DMIPS depending on how one counts it), whereas a PC
31 * is on the order of 10000 DMIPS(i.e. at a factor of 20-200).
32 *
33 * The zy1000 revc hardware is using an Altera Nios CPU, whereas the
34 * revb is using ARM7 + Xilinx.
35 *
36 * See Zylin web pages or contact Zylin for more information.
37 *
38 * The reason this code is in OpenOCD rather than OpenOCD linked with the
39 * ZY1000 code is that OpenOCD is the long road towards getting
40 * libopenocd into place. libopenocd will support both low performance,
41 * low latency systems(embedded) and high performance high latency
42 * systems(PCs).
43 */
44 #ifdef HAVE_CONFIG_H
45 #include "config.h"
46 #endif
47
48 #include <pthread.h>
49
50 #include <target/embeddedice.h>
51 #include <jtag/minidriver.h>
52 #include <jtag/interface.h>
53 #include <time.h>
54 #include <helper/time_support.h>
55
56 #include <netinet/tcp.h>
57
58 #if BUILD_ECOSBOARD
59 #include "zy1000_version.h"
60
61 #include <cyg/hal/hal_io.h> // low level i/o
62 #include <cyg/hal/hal_diag.h>
63
64 #ifdef CYGPKG_HAL_NIOS2
65 #include <cyg/hal/io.h>
66 #include <cyg/firmwareutil/firmwareutil.h>
67 #define ZYLIN_KHZ 60000
68 #else
69 #define ZYLIN_KHZ 64000
70 #endif
71
72 #define ZYLIN_VERSION GIT_ZY1000_VERSION
73 #define ZYLIN_DATE __DATE__
74 #define ZYLIN_TIME __TIME__
75 #define ZYLIN_OPENOCD GIT_OPENOCD_VERSION
76 #define ZYLIN_OPENOCD_VERSION "ZY1000 " ZYLIN_VERSION " " ZYLIN_DATE
77
78 #else
79 /* Assume we're connecting to a revc w/60MHz clock. */
80 #define ZYLIN_KHZ 60000
81 #endif
82
83
84 /* The software needs to check if it's in RCLK mode or not */
85 static bool zy1000_rclk = false;
86
87 static int zy1000_khz(int khz, int *jtag_speed)
88 {
89 if (khz == 0)
90 {
91 *jtag_speed = 0;
92 }
93 else
94 {
95 int speed;
96 /* Round speed up to nearest divisor.
97 *
98 * E.g. 16000kHz
99 * (64000 + 15999) / 16000 = 4
100 * (4 + 1) / 2 = 2
101 * 2 * 2 = 4
102 *
103 * 64000 / 4 = 16000
104 *
105 * E.g. 15999
106 * (64000 + 15998) / 15999 = 5
107 * (5 + 1) / 2 = 3
108 * 3 * 2 = 6
109 *
110 * 64000 / 6 = 10666
111 *
112 */
113 speed = (ZYLIN_KHZ + (khz -1)) / khz;
114 speed = (speed + 1 ) / 2;
115 speed *= 2;
116 if (speed > 8190)
117 {
118 /* maximum dividend */
119 speed = 8190;
120 }
121 *jtag_speed = speed;
122 }
123 return ERROR_OK;
124 }
125
126 static int zy1000_speed_div(int speed, int *khz)
127 {
128 if (speed == 0)
129 {
130 *khz = 0;
131 }
132 else
133 {
134 *khz = ZYLIN_KHZ / speed;
135 }
136
137 return ERROR_OK;
138 }
139
140 static bool readPowerDropout(void)
141 {
142 uint32_t state;
143 // sample and clear power dropout
144 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x80);
145 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state);
146 bool powerDropout;
147 powerDropout = (state & 0x80) != 0;
148 return powerDropout;
149 }
150
151
152 static bool readSRST(void)
153 {
154 uint32_t state;
155 // sample and clear SRST sensing
156 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000040);
157 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state);
158 bool srstAsserted;
159 srstAsserted = (state & 0x40) != 0;
160 return srstAsserted;
161 }
162
163 static int zy1000_srst_asserted(int *srst_asserted)
164 {
165 *srst_asserted = readSRST();
166 return ERROR_OK;
167 }
168
169 static int zy1000_power_dropout(int *dropout)
170 {
171 *dropout = readPowerDropout();
172 return ERROR_OK;
173 }
174
175 /* Wait for SRST to assert or deassert */
176 static void waitSRST(bool asserted)
177 {
178 bool first = true;
179 long long start = 0;
180 long total = 0;
181 const char *mode = asserted ? "assert" : "deassert";
182
183 for (;;)
184 {
185 bool srstAsserted = readSRST();
186 if ( (asserted && srstAsserted) || (!asserted && !srstAsserted) )
187 {
188 if (total > 1)
189 {
190 LOG_USER("SRST took %dms to %s", (int)total, mode);
191 }
192 break;
193 }
194
195 if (first)
196 {
197 first = false;
198 start = timeval_ms();
199 }
200
201 total = timeval_ms() - start;
202
203 keep_alive();
204
205 if (total > 5000)
206 {
207 LOG_ERROR("SRST took too long to %s: %dms", mode, (int)total);
208 break;
209 }
210 }
211 }
212
213
214 void zy1000_reset(int trst, int srst)
215 {
216 LOG_DEBUG("zy1000 trst=%d, srst=%d", trst, srst);
217
218 /* flush the JTAG FIFO. Not flushing the queue before messing with
219 * reset has such interesting bugs as causing hard to reproduce
220 * RCLK bugs as RCLK will stop responding when TRST is asserted
221 */
222 waitIdle();
223
224 if (!srst)
225 {
226 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x00000001);
227 }
228 else
229 {
230 /* Danger!!! if clk != 0 when in
231 * idle in TAP_IDLE, reset halt on str912 will fail.
232 */
233 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000001);
234
235 waitSRST(true);
236 }
237
238 if (!trst)
239 {
240 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x00000002);
241 }
242 else
243 {
244 /* assert reset */
245 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000002);
246 }
247
248 if (trst||(srst && (jtag_get_reset_config() & RESET_SRST_PULLS_TRST)))
249 {
250 /* we're now in the RESET state until trst is deasserted */
251 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, TAP_RESET);
252 } else
253 {
254 /* We'll get RCLK failure when we assert TRST, so clear any false positives here */
255 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x400);
256 }
257
258 /* wait for srst to float back up */
259 if ((!srst && ((jtag_get_reset_config() & RESET_TRST_PULLS_SRST) == 0))||
260 (!srst && !trst && (jtag_get_reset_config() & RESET_TRST_PULLS_SRST)))
261 {
262 waitSRST(false);
263 }
264 }
265
266 int zy1000_speed(int speed)
267 {
268 /* flush JTAG master FIFO before setting speed */
269 waitIdle();
270
271 zy1000_rclk = false;
272
273 if (speed == 0)
274 {
275 /*0 means RCLK*/
276 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x100);
277 zy1000_rclk = true;
278 LOG_DEBUG("jtag_speed using RCLK");
279 }
280 else
281 {
282 if (speed > 8190 || speed < 2)
283 {
284 LOG_USER("valid ZY1000 jtag_speed=[8190,2]. With divisor is %dkHz / even values between 8190-2, i.e. min %dHz, max %dMHz",
285 ZYLIN_KHZ, (ZYLIN_KHZ * 1000) / 8190, ZYLIN_KHZ / (2 * 1000));
286 return ERROR_INVALID_ARGUMENTS;
287 }
288
289 int khz;
290 speed &= ~1;
291 zy1000_speed_div(speed, &khz);
292 LOG_USER("jtag_speed %d => JTAG clk=%d kHz", speed, khz);
293 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x100);
294 ZY1000_POKE(ZY1000_JTAG_BASE + 0x1c, speed);
295 }
296 return ERROR_OK;
297 }
298
299 static bool savePower;
300
301
302 static void setPower(bool power)
303 {
304 savePower = power;
305 if (power)
306 {
307 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x8);
308 } else
309 {
310 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x8);
311 }
312 }
313
314 COMMAND_HANDLER(handle_power_command)
315 {
316 switch (CMD_ARGC)
317 {
318 case 1: {
319 bool enable;
320 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
321 setPower(enable);
322 // fall through
323 }
324 case 0:
325 LOG_INFO("Target power %s", savePower ? "on" : "off");
326 break;
327 default:
328 return ERROR_INVALID_ARGUMENTS;
329 }
330
331 return ERROR_OK;
332 }
333
334 #if !BUILD_ZY1000_MASTER
335 static char *tcp_server = "notspecified";
336 static int jim_zy1000_server(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
337 {
338 if (argc != 2)
339 return JIM_ERR;
340
341 tcp_server = strdup(Jim_GetString(argv[1], NULL));
342
343 return JIM_OK;
344 }
345 #endif
346
347 #if BUILD_ECOSBOARD
348 /* Give TELNET a way to find out what version this is */
349 static int jim_zy1000_version(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
350 {
351 if ((argc < 1) || (argc > 3))
352 return JIM_ERR;
353 const char *version_str = NULL;
354
355 if (argc == 1)
356 {
357 version_str = ZYLIN_OPENOCD_VERSION;
358 } else
359 {
360 const char *str = Jim_GetString(argv[1], NULL);
361 const char *str2 = NULL;
362 if (argc > 2)
363 str2 = Jim_GetString(argv[2], NULL);
364 if (strcmp("openocd", str) == 0)
365 {
366 version_str = ZYLIN_OPENOCD;
367 }
368 else if (strcmp("zy1000", str) == 0)
369 {
370 version_str = ZYLIN_VERSION;
371 }
372 else if (strcmp("date", str) == 0)
373 {
374 version_str = ZYLIN_DATE;
375 }
376 else if (strcmp("time", str) == 0)
377 {
378 version_str = ZYLIN_TIME;
379 }
380 else if (strcmp("pcb", str) == 0)
381 {
382 #ifdef CYGPKG_HAL_NIOS2
383 version_str="c";
384 #else
385 version_str="b";
386 #endif
387 }
388 #ifdef CYGPKG_HAL_NIOS2
389 else if (strcmp("fpga", str) == 0)
390 {
391
392 /* return a list of 32 bit integers to describe the expected
393 * and actual FPGA
394 */
395 static char *fpga_id = "0x12345678 0x12345678 0x12345678 0x12345678";
396 uint32_t id, timestamp;
397 HAL_READ_UINT32(SYSID_BASE, id);
398 HAL_READ_UINT32(SYSID_BASE+4, timestamp);
399 sprintf(fpga_id, "0x%08x 0x%08x 0x%08x 0x%08x", id, timestamp, SYSID_ID, SYSID_TIMESTAMP);
400 version_str = fpga_id;
401 if ((argc>2) && (strcmp("time", str2) == 0))
402 {
403 time_t last_mod = timestamp;
404 char * t = ctime (&last_mod) ;
405 t[strlen(t)-1] = 0;
406 version_str = t;
407 }
408 }
409 #endif
410
411 else
412 {
413 return JIM_ERR;
414 }
415 }
416
417 Jim_SetResult(interp, Jim_NewStringObj(interp, version_str, -1));
418
419 return JIM_OK;
420 }
421 #endif
422
423 #ifdef CYGPKG_HAL_NIOS2
424
425
426 struct info_forward
427 {
428 void *data;
429 struct cyg_upgrade_info *upgraded_file;
430 };
431
432 static void report_info(void *data, const char * format, va_list args)
433 {
434 char *s = alloc_vprintf(format, args);
435 LOG_USER_N("%s", s);
436 free(s);
437 }
438
439 struct cyg_upgrade_info firmware_info =
440 {
441 (uint8_t *)0x84000000,
442 "/ram/firmware.phi",
443 "Firmware",
444 0x0300000,
445 0x1f00000 -
446 0x0300000,
447 "ZylinNiosFirmware\n",
448 report_info,
449 };
450
451 // File written to /ram/firmware.phi before arriving at this fn
452 static int jim_zy1000_writefirmware(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
453 {
454 if (argc != 1)
455 return JIM_ERR;
456
457 if (!cyg_firmware_upgrade(NULL, firmware_info))
458 return JIM_ERR;
459
460 return JIM_OK;
461 }
462 #endif
463
464 static int
465 zylinjtag_Jim_Command_powerstatus(Jim_Interp *interp,
466 int argc,
467 Jim_Obj * const *argv)
468 {
469 if (argc != 1)
470 {
471 Jim_WrongNumArgs(interp, 1, argv, "powerstatus");
472 return JIM_ERR;
473 }
474
475 bool dropout = readPowerDropout();
476
477 Jim_SetResult(interp, Jim_NewIntObj(interp, dropout));
478
479 return JIM_OK;
480 }
481
482
483
484 int zy1000_quit(void)
485 {
486
487 return ERROR_OK;
488 }
489
490
491
492 int interface_jtag_execute_queue(void)
493 {
494 uint32_t empty;
495
496 waitIdle();
497
498 /* We must make sure to write data read back to memory location before we return
499 * from this fn
500 */
501 zy1000_flush_readqueue();
502
503 /* and handle any callbacks... */
504 zy1000_flush_callbackqueue();
505
506 if (zy1000_rclk)
507 {
508 /* Only check for errors when using RCLK to speed up
509 * jtag over TCP/IP
510 */
511 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty);
512 /* clear JTAG error register */
513 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x400);
514
515 if ((empty&0x400) != 0)
516 {
517 LOG_WARNING("RCLK timeout");
518 /* the error is informative only as we don't want to break the firmware if there
519 * is a false positive.
520 */
521 // return ERROR_FAIL;
522 }
523 }
524 return ERROR_OK;
525 }
526
527
528
529
530 static void writeShiftValue(uint8_t *data, int bits);
531
532 // here we shuffle N bits out/in
533 static __inline void scanBits(const uint8_t *out_value, uint8_t *in_value, int num_bits, bool pause_now, tap_state_t shiftState, tap_state_t end_state)
534 {
535 tap_state_t pause_state = shiftState;
536 for (int j = 0; j < num_bits; j += 32)
537 {
538 int k = num_bits - j;
539 if (k > 32)
540 {
541 k = 32;
542 /* we have more to shift out */
543 } else if (pause_now)
544 {
545 /* this was the last to shift out this time */
546 pause_state = end_state;
547 }
548
549 // we have (num_bits + 7)/8 bytes of bits to toggle out.
550 // bits are pushed out LSB to MSB
551 uint32_t value;
552 value = 0;
553 if (out_value != NULL)
554 {
555 for (int l = 0; l < k; l += 8)
556 {
557 value|=out_value[(j + l)/8]<<l;
558 }
559 }
560 /* mask away unused bits for easier debugging */
561 if (k < 32)
562 {
563 value&=~(((uint32_t)0xffffffff) << k);
564 } else
565 {
566 /* Shifting by >= 32 is not defined by the C standard
567 * and will in fact shift by &0x1f bits on nios */
568 }
569
570 shiftValueInner(shiftState, pause_state, k, value);
571
572 if (in_value != NULL)
573 {
574 writeShiftValue(in_value + (j/8), k);
575 }
576 }
577 }
578
579 static __inline void scanFields(int num_fields, const struct scan_field *fields, tap_state_t shiftState, tap_state_t end_state)
580 {
581 for (int i = 0; i < num_fields; i++)
582 {
583 scanBits(fields[i].out_value,
584 fields[i].in_value,
585 fields[i].num_bits,
586 (i == num_fields-1),
587 shiftState,
588 end_state);
589 }
590 }
591
592 int interface_jtag_add_ir_scan(struct jtag_tap *active, const struct scan_field *fields, tap_state_t state)
593 {
594 int scan_size = 0;
595 struct jtag_tap *tap, *nextTap;
596 tap_state_t pause_state = TAP_IRSHIFT;
597
598 for (tap = jtag_tap_next_enabled(NULL); tap!= NULL; tap = nextTap)
599 {
600 nextTap = jtag_tap_next_enabled(tap);
601 if (nextTap==NULL)
602 {
603 pause_state = state;
604 }
605 scan_size = tap->ir_length;
606
607 /* search the list */
608 if (tap == active)
609 {
610 scanFields(1, fields, TAP_IRSHIFT, pause_state);
611 /* update device information */
612 buf_cpy(fields[0].out_value, tap->cur_instr, scan_size);
613
614 tap->bypass = 0;
615 } else
616 {
617 /* if a device isn't listed, set it to BYPASS */
618 assert(scan_size <= 32);
619 shiftValueInner(TAP_IRSHIFT, pause_state, scan_size, 0xffffffff);
620
621 tap->bypass = 1;
622 }
623 }
624
625 return ERROR_OK;
626 }
627
628
629
630
631
632 int interface_jtag_add_plain_ir_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state)
633 {
634 scanBits(out_bits, in_bits, num_bits, true, TAP_IRSHIFT, state);
635 return ERROR_OK;
636 }
637
638 int interface_jtag_add_dr_scan(struct jtag_tap *active, int num_fields, const struct scan_field *fields, tap_state_t state)
639 {
640 struct jtag_tap *tap, *nextTap;
641 tap_state_t pause_state = TAP_DRSHIFT;
642 for (tap = jtag_tap_next_enabled(NULL); tap!= NULL; tap = nextTap)
643 {
644 nextTap = jtag_tap_next_enabled(tap);
645 if (nextTap==NULL)
646 {
647 pause_state = state;
648 }
649
650 /* Find a range of fields to write to this tap */
651 if (tap == active)
652 {
653 assert(!tap->bypass);
654
655 scanFields(num_fields, fields, TAP_DRSHIFT, pause_state);
656 } else
657 {
658 /* Shift out a 0 for disabled tap's */
659 assert(tap->bypass);
660 shiftValueInner(TAP_DRSHIFT, pause_state, 1, 0);
661 }
662 }
663 return ERROR_OK;
664 }
665
666 int interface_jtag_add_plain_dr_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state)
667 {
668 scanBits(out_bits, in_bits, num_bits, true, TAP_DRSHIFT, state);
669 return ERROR_OK;
670 }
671
672 int interface_jtag_add_tlr()
673 {
674 setCurrentState(TAP_RESET);
675 return ERROR_OK;
676 }
677
678
679 int interface_jtag_add_reset(int req_trst, int req_srst)
680 {
681 zy1000_reset(req_trst, req_srst);
682 return ERROR_OK;
683 }
684
685 static int zy1000_jtag_add_clocks(int num_cycles, tap_state_t state, tap_state_t clockstate)
686 {
687 /* num_cycles can be 0 */
688 setCurrentState(clockstate);
689
690 /* execute num_cycles, 32 at the time. */
691 int i;
692 for (i = 0; i < num_cycles; i += 32)
693 {
694 int num;
695 num = 32;
696 if (num_cycles-i < num)
697 {
698 num = num_cycles-i;
699 }
700 shiftValueInner(clockstate, clockstate, num, 0);
701 }
702
703 #if !TEST_MANUAL()
704 /* finish in end_state */
705 setCurrentState(state);
706 #else
707 tap_state_t t = TAP_IDLE;
708 /* test manual drive code on any target */
709 int tms;
710 uint8_t tms_scan = tap_get_tms_path(t, state);
711 int tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
712
713 for (i = 0; i < tms_count; i++)
714 {
715 tms = (tms_scan >> i) & 1;
716 waitIdle();
717 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, tms);
718 }
719 waitIdle();
720 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, state);
721 #endif
722
723 return ERROR_OK;
724 }
725
726 int interface_jtag_add_runtest(int num_cycles, tap_state_t state)
727 {
728 return zy1000_jtag_add_clocks(num_cycles, state, TAP_IDLE);
729 }
730
731 int interface_jtag_add_clocks(int num_cycles)
732 {
733 return zy1000_jtag_add_clocks(num_cycles, cmd_queue_cur_state, cmd_queue_cur_state);
734 }
735
736 int interface_add_tms_seq(unsigned num_bits, const uint8_t *seq, enum tap_state state)
737 {
738 /*wait for the fifo to be empty*/
739 waitIdle();
740
741 for (unsigned i = 0; i < num_bits; i++)
742 {
743 int tms;
744
745 if (((seq[i/8] >> (i % 8)) & 1) == 0)
746 {
747 tms = 0;
748 }
749 else
750 {
751 tms = 1;
752 }
753
754 waitIdle();
755 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, tms);
756 }
757
758 waitIdle();
759 if (state != TAP_INVALID)
760 {
761 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, state);
762 } else
763 {
764 /* this would be normal if we are switching to SWD mode */
765 }
766 return ERROR_OK;
767 }
768
769 int interface_jtag_add_pathmove(int num_states, const tap_state_t *path)
770 {
771 int state_count;
772 int tms = 0;
773
774 state_count = 0;
775
776 tap_state_t cur_state = cmd_queue_cur_state;
777
778 uint8_t seq[16];
779 memset(seq, 0, sizeof(seq));
780 assert(num_states < (int)((sizeof(seq) * 8)));
781
782 while (num_states)
783 {
784 if (tap_state_transition(cur_state, false) == path[state_count])
785 {
786 tms = 0;
787 }
788 else if (tap_state_transition(cur_state, true) == path[state_count])
789 {
790 tms = 1;
791 }
792 else
793 {
794 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_name(cur_state), tap_state_name(path[state_count]));
795 exit(-1);
796 }
797
798 seq[state_count/8] = seq[state_count/8] | (tms << (state_count % 8));
799
800 cur_state = path[state_count];
801 state_count++;
802 num_states--;
803 }
804
805 return interface_add_tms_seq(state_count, seq, cur_state);
806 }
807
808 static void jtag_pre_post_bits(struct jtag_tap *tap, int *pre, int *post)
809 {
810 /* bypass bits before and after */
811 int pre_bits = 0;
812 int post_bits = 0;
813
814 bool found = false;
815 struct jtag_tap *cur_tap, *nextTap;
816 for (cur_tap = jtag_tap_next_enabled(NULL); cur_tap!= NULL; cur_tap = nextTap)
817 {
818 nextTap = jtag_tap_next_enabled(cur_tap);
819 if (cur_tap == tap)
820 {
821 found = true;
822 } else
823 {
824 if (found)
825 {
826 post_bits++;
827 } else
828 {
829 pre_bits++;
830 }
831 }
832 }
833 *pre = pre_bits;
834 *post = post_bits;
835 }
836
837 /*
838 static const int embeddedice_num_bits[] = {32, 6};
839 uint32_t values[2];
840
841 values[0] = value;
842 values[1] = (1 << 5) | reg_addr;
843
844 jtag_add_dr_out(tap,
845 2,
846 embeddedice_num_bits,
847 values,
848 TAP_IDLE);
849 */
850
851 void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer, int little, int count)
852 {
853 #if 0
854 int i;
855 for (i = 0; i < count; i++)
856 {
857 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
858 buffer += 4;
859 }
860 #else
861 int pre_bits;
862 int post_bits;
863 jtag_pre_post_bits(tap, &pre_bits, &post_bits);
864
865 if ((pre_bits > 32) || (post_bits + 6 > 32))
866 {
867 int i;
868 for (i = 0; i < count; i++)
869 {
870 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
871 buffer += 4;
872 }
873 } else
874 {
875 int i;
876 for (i = 0; i < count; i++)
877 {
878 /* Fewer pokes means we get to use the FIFO more efficiently */
879 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, pre_bits, 0);
880 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, little));
881 /* Danger! here we need to exit into the TAP_IDLE state to make
882 * DCC pick up this value.
883 */
884 shiftValueInner(TAP_DRSHIFT, TAP_IDLE, 6 + post_bits, (reg_addr | (1 << 5)));
885 buffer += 4;
886 }
887 }
888 #endif
889 }
890
891
892
893 int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count)
894 {
895 /* bypass bits before and after */
896 int pre_bits;
897 int post_bits;
898 jtag_pre_post_bits(tap, &pre_bits, &post_bits);
899 post_bits+=2;
900
901 if ((pre_bits > 32) || (post_bits > 32))
902 {
903 int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap *, uint32_t, uint32_t *, size_t);
904 return arm11_run_instr_data_to_core_noack_inner_default(tap, opcode, data, count);
905 } else
906 {
907 static const int bits[] = {32, 2};
908 uint32_t values[] = {0, 0};
909
910 /* FIX!!!!!! the target_write_memory() API started this nasty problem
911 * with unaligned uint32_t * pointers... */
912 const uint8_t *t = (const uint8_t *)data;
913
914 while (--count > 0)
915 {
916 #if 1
917 /* Danger! This code doesn't update cmd_queue_cur_state, so
918 * invoking jtag_add_pathmove() before jtag_add_dr_out() after
919 * this loop would fail!
920 */
921 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, pre_bits, 0);
922
923 uint32_t value;
924 value = *t++;
925 value |= (*t++<<8);
926 value |= (*t++<<16);
927 value |= (*t++<<24);
928
929 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, value);
930 /* minimum 2 bits */
931 shiftValueInner(TAP_DRSHIFT, TAP_DRPAUSE, post_bits, 0);
932
933 /* copy & paste from arm11_dbgtap.c */
934 //TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
935 /* KLUDGE! we have to flush the fifo or the Nios CPU locks up.
936 * This is probably a bug in the Avalon bus(cross clocking bridge?)
937 * or in the jtag registers module.
938 */
939 waitIdle();
940 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
941 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
942 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
943 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
944 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
945 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
946 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
947 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
948 /* we don't have to wait for the queue to empty here */
949 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, TAP_DRSHIFT);
950 waitIdle();
951 #else
952 static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
953 {
954 TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
955 };
956
957 values[0] = *t++;
958 values[0] |= (*t++<<8);
959 values[0] |= (*t++<<16);
960 values[0] |= (*t++<<24);
961
962 jtag_add_dr_out(tap,
963 2,
964 bits,
965 values,
966 TAP_IDLE);
967
968 jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
969 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
970 #endif
971 }
972
973 values[0] = *t++;
974 values[0] |= (*t++<<8);
975 values[0] |= (*t++<<16);
976 values[0] |= (*t++<<24);
977
978 /* This will happen on the last iteration updating cmd_queue_cur_state
979 * so we don't have to track it during the common code path
980 */
981 jtag_add_dr_out(tap,
982 2,
983 bits,
984 values,
985 TAP_IDLE);
986
987 return jtag_execute_queue();
988 }
989 }
990
991
992 static const struct command_registration zy1000_commands[] = {
993 {
994 .name = "power",
995 .handler = handle_power_command,
996 .mode = COMMAND_ANY,
997 .help = "Turn power switch to target on/off. "
998 "With no arguments, prints status.",
999 .usage = "('on'|'off)",
1000 },
1001 #if BUILD_ZY1000_MASTER
1002 #if BUILD_ECOSBOARD
1003 {
1004 .name = "zy1000_version",
1005 .mode = COMMAND_ANY,
1006 .jim_handler = jim_zy1000_version,
1007 .help = "Print version info for zy1000.",
1008 .usage = "['openocd'|'zy1000'|'date'|'time'|'pcb'|'fpga']",
1009 },
1010 #endif
1011 #else
1012 {
1013 .name = "zy1000_server",
1014 .mode = COMMAND_ANY,
1015 .jim_handler = jim_zy1000_server,
1016 .help = "Tcpip address for ZY1000 server.",
1017 .usage = "address",
1018 },
1019 #endif
1020 {
1021 .name = "powerstatus",
1022 .mode = COMMAND_ANY,
1023 .jim_handler = zylinjtag_Jim_Command_powerstatus,
1024 .help = "Returns power status of target",
1025 },
1026 #ifdef CYGPKG_HAL_NIOS2
1027 {
1028 .name = "updatezy1000firmware",
1029 .mode = COMMAND_ANY,
1030 .jim_handler = jim_zy1000_writefirmware,
1031 .help = "writes firmware to flash",
1032 /* .usage = "some_string", */
1033 },
1034 #endif
1035 COMMAND_REGISTRATION_DONE
1036 };
1037
1038
1039 #if !BUILD_ZY1000_MASTER
1040
1041 static int tcp_ip = -1;
1042
1043 /* Write large packets if we can */
1044 static size_t out_pos;
1045 static uint8_t out_buffer[16384];
1046 static size_t in_pos;
1047 static size_t in_write;
1048 static uint8_t in_buffer[16384];
1049
1050 static bool flush_writes(void)
1051 {
1052 bool ok = (write(tcp_ip, out_buffer, out_pos) == (int)out_pos);
1053 out_pos = 0;
1054 return ok;
1055 }
1056
1057 static bool writeLong(uint32_t l)
1058 {
1059 int i;
1060 for (i = 0; i < 4; i++)
1061 {
1062 uint8_t c = (l >> (i*8))&0xff;
1063 out_buffer[out_pos++] = c;
1064 if (out_pos >= sizeof(out_buffer))
1065 {
1066 if (!flush_writes())
1067 {
1068 return false;
1069 }
1070 }
1071 }
1072 return true;
1073 }
1074
1075 static bool readLong(uint32_t *out_data)
1076 {
1077 uint32_t data = 0;
1078 int i;
1079 for (i = 0; i < 4; i++)
1080 {
1081 uint8_t c;
1082 if (in_pos == in_write)
1083 {
1084 /* If we have some data that we can send, send them before
1085 * we wait for more data
1086 */
1087 if (out_pos > 0)
1088 {
1089 if (!flush_writes())
1090 {
1091 return false;
1092 }
1093 }
1094
1095 /* read more */
1096 int t;
1097 t = read(tcp_ip, in_buffer, sizeof(in_buffer));
1098 if (t < 1)
1099 {
1100 return false;
1101 }
1102 in_write = (size_t) t;
1103 in_pos = 0;
1104 }
1105 c = in_buffer[in_pos++];
1106
1107 data |= (c << (i*8));
1108 }
1109 *out_data = data;
1110 return true;
1111 }
1112
1113 enum ZY1000_CMD
1114 {
1115 ZY1000_CMD_POKE = 0x0,
1116 ZY1000_CMD_PEEK = 0x8,
1117 ZY1000_CMD_SLEEP = 0x1,
1118 ZY1000_CMD_WAITIDLE = 2
1119 };
1120
1121 #include <sys/socket.h> /* for socket(), connect(), send(), and recv() */
1122 #include <arpa/inet.h> /* for sockaddr_in and inet_addr() */
1123
1124 /* We initialize this late since we need to know the server address
1125 * first.
1126 */
1127 static void tcpip_open(void)
1128 {
1129 if (tcp_ip >= 0)
1130 return;
1131
1132 struct sockaddr_in echoServAddr; /* Echo server address */
1133
1134 /* Create a reliable, stream socket using TCP */
1135 if ((tcp_ip = socket(PF_INET, SOCK_STREAM, IPPROTO_TCP)) < 0)
1136 {
1137 fprintf(stderr, "Failed to connect to zy1000 server\n");
1138 exit(-1);
1139 }
1140
1141 /* Construct the server address structure */
1142 memset(&echoServAddr, 0, sizeof(echoServAddr)); /* Zero out structure */
1143 echoServAddr.sin_family = AF_INET; /* Internet address family */
1144 echoServAddr.sin_addr.s_addr = inet_addr(tcp_server); /* Server IP address */
1145 echoServAddr.sin_port = htons(7777); /* Server port */
1146
1147 /* Establish the connection to the echo server */
1148 if (connect(tcp_ip, (struct sockaddr *) &echoServAddr, sizeof(echoServAddr)) < 0)
1149 {
1150 fprintf(stderr, "Failed to connect to zy1000 server\n");
1151 exit(-1);
1152 }
1153
1154 int flag = 1;
1155 setsockopt(tcp_ip, /* socket affected */
1156 IPPROTO_TCP, /* set option at TCP level */
1157 TCP_NODELAY, /* name of option */
1158 (char *)&flag, /* the cast is historical cruft */
1159 sizeof(int)); /* length of option value */
1160
1161 }
1162
1163
1164 /* send a poke */
1165 void zy1000_tcpout(uint32_t address, uint32_t data)
1166 {
1167 tcpip_open();
1168 if (!writeLong((ZY1000_CMD_POKE << 24) | address)||
1169 !writeLong(data))
1170 {
1171 fprintf(stderr, "Could not write to zy1000 server\n");
1172 exit(-1);
1173 }
1174 }
1175
1176 /* By sending the wait to the server, we avoid a readback
1177 * of status. Radically improves performance for this operation
1178 * with long ping times.
1179 */
1180 void waitIdle(void)
1181 {
1182 tcpip_open();
1183 if (!writeLong((ZY1000_CMD_WAITIDLE << 24)))
1184 {
1185 fprintf(stderr, "Could not write to zy1000 server\n");
1186 exit(-1);
1187 }
1188 }
1189
1190 uint32_t zy1000_tcpin(uint32_t address)
1191 {
1192 tcpip_open();
1193
1194 zy1000_flush_readqueue();
1195
1196 uint32_t data;
1197 if (!writeLong((ZY1000_CMD_PEEK << 24) | address)||
1198 !readLong(&data))
1199 {
1200 fprintf(stderr, "Could not read from zy1000 server\n");
1201 exit(-1);
1202 }
1203 return data;
1204 }
1205
1206 int interface_jtag_add_sleep(uint32_t us)
1207 {
1208 tcpip_open();
1209 if (!writeLong((ZY1000_CMD_SLEEP << 24))||
1210 !writeLong(us))
1211 {
1212 fprintf(stderr, "Could not read from zy1000 server\n");
1213 exit(-1);
1214 }
1215 return ERROR_OK;
1216 }
1217
1218 /* queue a readback */
1219 #define readqueue_size 16384
1220 static struct
1221 {
1222 uint8_t *dest;
1223 int bits;
1224 } readqueue[readqueue_size];
1225
1226 static int readqueue_pos = 0;
1227
1228 /* flush the readqueue, this means reading any data that
1229 * we're expecting and store them into the final position
1230 */
1231 void zy1000_flush_readqueue(void)
1232 {
1233 if (readqueue_pos == 0)
1234 {
1235 /* simply debugging by allowing easy breakpoints when there
1236 * is something to do. */
1237 return;
1238 }
1239 int i;
1240 tcpip_open();
1241 for (i = 0; i < readqueue_pos; i++)
1242 {
1243 uint32_t value;
1244 if (!readLong(&value))
1245 {
1246 fprintf(stderr, "Could not read from zy1000 server\n");
1247 exit(-1);
1248 }
1249
1250 uint8_t *in_value = readqueue[i].dest;
1251 int k = readqueue[i].bits;
1252
1253 // we're shifting in data to MSB, shift data to be aligned for returning the value
1254 value >>= 32-k;
1255
1256 for (int l = 0; l < k; l += 8)
1257 {
1258 in_value[l/8]=(value >> l)&0xff;
1259 }
1260 }
1261 readqueue_pos = 0;
1262 }
1263
1264 /* By queuing the callback's we avoid flushing the
1265 read queue until jtag_execute_queue(). This can
1266 reduce latency dramatically for cases where
1267 callbacks are used extensively.
1268 */
1269 #define callbackqueue_size 128
1270 static struct callbackentry
1271 {
1272 jtag_callback_t callback;
1273 jtag_callback_data_t data0;
1274 jtag_callback_data_t data1;
1275 jtag_callback_data_t data2;
1276 jtag_callback_data_t data3;
1277 } callbackqueue[callbackqueue_size];
1278
1279 static int callbackqueue_pos = 0;
1280
1281 void zy1000_jtag_add_callback4(jtag_callback_t callback, jtag_callback_data_t data0, jtag_callback_data_t data1, jtag_callback_data_t data2, jtag_callback_data_t data3)
1282 {
1283 if (callbackqueue_pos >= callbackqueue_size)
1284 {
1285 zy1000_flush_callbackqueue();
1286 }
1287
1288 callbackqueue[callbackqueue_pos].callback = callback;
1289 callbackqueue[callbackqueue_pos].data0 = data0;
1290 callbackqueue[callbackqueue_pos].data1 = data1;
1291 callbackqueue[callbackqueue_pos].data2 = data2;
1292 callbackqueue[callbackqueue_pos].data3 = data3;
1293 callbackqueue_pos++;
1294 }
1295
1296 static int zy1000_jtag_convert_to_callback4(jtag_callback_data_t data0, jtag_callback_data_t data1, jtag_callback_data_t data2, jtag_callback_data_t data3)
1297 {
1298 ((jtag_callback1_t)data1)(data0);
1299 return ERROR_OK;
1300 }
1301
1302 void zy1000_jtag_add_callback(jtag_callback1_t callback, jtag_callback_data_t data0)
1303 {
1304 zy1000_jtag_add_callback4(zy1000_jtag_convert_to_callback4, data0, (jtag_callback_data_t)callback, 0, 0);
1305 }
1306
1307 void zy1000_flush_callbackqueue(void)
1308 {
1309 /* we have to flush the read queue so we have access to
1310 the data the callbacks will use
1311 */
1312 zy1000_flush_readqueue();
1313 int i;
1314 for (i = 0; i < callbackqueue_pos; i++)
1315 {
1316 struct callbackentry *entry = &callbackqueue[i];
1317 jtag_set_error(entry->callback(entry->data0, entry->data1, entry->data2, entry->data3));
1318 }
1319 callbackqueue_pos = 0;
1320 }
1321
1322 static void writeShiftValue(uint8_t *data, int bits)
1323 {
1324 waitIdle();
1325
1326 if (!writeLong((ZY1000_CMD_PEEK << 24) | (ZY1000_JTAG_BASE + 0xc)))
1327 {
1328 fprintf(stderr, "Could not read from zy1000 server\n");
1329 exit(-1);
1330 }
1331
1332 if (readqueue_pos >= readqueue_size)
1333 {
1334 zy1000_flush_readqueue();
1335 }
1336
1337 readqueue[readqueue_pos].dest = data;
1338 readqueue[readqueue_pos].bits = bits;
1339 readqueue_pos++;
1340 }
1341
1342 #else
1343
1344 static void writeShiftValue(uint8_t *data, int bits)
1345 {
1346 uint32_t value;
1347 waitIdle();
1348 ZY1000_PEEK(ZY1000_JTAG_BASE + 0xc, value);
1349 VERBOSE(LOG_INFO("getShiftValue %08x", value));
1350
1351 // data in, LSB to MSB
1352 // we're shifting in data to MSB, shift data to be aligned for returning the value
1353 value >>= 32 - bits;
1354
1355 for (int l = 0; l < bits; l += 8)
1356 {
1357 data[l/8]=(value >> l)&0xff;
1358 }
1359 }
1360
1361 #endif
1362
1363 #if BUILD_ZY1000_MASTER
1364
1365 #if BUILD_ECOSBOARD
1366 static char watchdog_stack[2048];
1367 static cyg_thread watchdog_thread_object;
1368 static cyg_handle_t watchdog_thread_handle;
1369 #endif
1370
1371 #ifdef WATCHDOG_BASE
1372 /* If we connect to port 8888 we must send a char every 10s or the board resets itself */
1373 static void watchdog_server(cyg_addrword_t data)
1374 {
1375 int so_reuseaddr_option = 1;
1376
1377 int fd;
1378 if ((fd = socket(AF_INET, SOCK_STREAM, 0)) == -1)
1379 {
1380 LOG_ERROR("error creating socket: %s", strerror(errno));
1381 exit(-1);
1382 }
1383
1384 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (void*) &so_reuseaddr_option,
1385 sizeof(int));
1386
1387 struct sockaddr_in sin;
1388 unsigned int address_size;
1389 address_size = sizeof(sin);
1390 memset(&sin, 0, sizeof(sin));
1391 sin.sin_family = AF_INET;
1392 sin.sin_addr.s_addr = INADDR_ANY;
1393 sin.sin_port = htons(8888);
1394
1395 if (bind(fd, (struct sockaddr *) &sin, sizeof(sin)) == -1)
1396 {
1397 LOG_ERROR("couldn't bind to socket: %s", strerror(errno));
1398 exit(-1);
1399 }
1400
1401 if (listen(fd, 1) == -1)
1402 {
1403 LOG_ERROR("couldn't listen on socket: %s", strerror(errno));
1404 exit(-1);
1405 }
1406
1407
1408 for (;;)
1409 {
1410 int watchdog_ip = accept(fd, (struct sockaddr *) &sin, &address_size);
1411
1412 /* Start watchdog, must be reset every 10 seconds. */
1413 HAL_WRITE_UINT32(WATCHDOG_BASE + 4, 4);
1414
1415 if (watchdog_ip < 0)
1416 {
1417 LOG_ERROR("couldn't open watchdog socket: %s", strerror(errno));
1418 exit(-1);
1419 }
1420
1421 int flag = 1;
1422 setsockopt(watchdog_ip, /* socket affected */
1423 IPPROTO_TCP, /* set option at TCP level */
1424 TCP_NODELAY, /* name of option */
1425 (char *)&flag, /* the cast is historical cruft */
1426 sizeof(int)); /* length of option value */
1427
1428
1429 char buf;
1430 for (;;)
1431 {
1432 if (read(watchdog_ip, &buf, 1) == 1)
1433 {
1434 /* Reset timer */
1435 HAL_WRITE_UINT32(WATCHDOG_BASE + 8, 0x1234);
1436 /* Echo so we can telnet in and see that resetting works */
1437 write(watchdog_ip, &buf, 1);
1438 } else
1439 {
1440 /* Stop tickling the watchdog, the CPU will reset in < 10 seconds
1441 * now.
1442 */
1443 return;
1444 }
1445
1446 }
1447
1448 /* Never reached */
1449 }
1450 }
1451 #endif
1452
1453 #endif
1454
1455 #if BUILD_ZY1000_MASTER
1456 int interface_jtag_add_sleep(uint32_t us)
1457 {
1458 jtag_sleep(us);
1459 return ERROR_OK;
1460 }
1461 #endif
1462
1463 #if BUILD_ZY1000_MASTER && !BUILD_ECOSBOARD
1464 volatile void *zy1000_jtag_master;
1465 #include <sys/mman.h>
1466 #endif
1467
1468 int zy1000_init(void)
1469 {
1470 #if BUILD_ECOSBOARD
1471 LOG_USER("%s", ZYLIN_OPENOCD_VERSION);
1472 #elif BUILD_ZY1000_MASTER
1473 int fd;
1474 if((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1)
1475 {
1476 LOG_ERROR("No access to /dev/mem");
1477 return ERROR_FAIL;
1478 }
1479 #ifndef REGISTERS_BASE
1480 #define REGISTERS_BASE 0x9002000
1481 #define REGISTERS_SPAN 128
1482 #endif
1483
1484 zy1000_jtag_master = mmap(0, REGISTERS_SPAN, PROT_READ | PROT_WRITE, MAP_SHARED, fd, REGISTERS_BASE);
1485
1486 if(zy1000_jtag_master == (void *) -1)
1487 {
1488 close(fd);
1489 LOG_ERROR("No access to /dev/mem");
1490 return ERROR_FAIL;
1491 }
1492 #endif
1493
1494
1495
1496 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x30); // Turn on LED1 & LED2
1497
1498 setPower(true); // on by default
1499
1500
1501 /* deassert resets. Important to avoid infinite loop waiting for SRST to deassert */
1502 zy1000_reset(0, 0);
1503 int jtag_speed_var;
1504 int retval = jtag_get_speed(&jtag_speed_var);
1505 if (retval != ERROR_OK)
1506 return retval;
1507 zy1000_speed(jtag_speed_var);
1508
1509 #if BUILD_ZY1000_MASTER
1510 #if BUILD_ECOSBOARD
1511 #ifdef WATCHDOG_BASE
1512 cyg_thread_create(1, watchdog_server, (cyg_addrword_t) 0, "watchdog tcip/ip server",
1513 (void *) watchdog_stack, sizeof(watchdog_stack),
1514 &watchdog_thread_handle, &watchdog_thread_object);
1515 cyg_thread_resume(watchdog_thread_handle);
1516 #endif
1517 #endif
1518 #endif
1519
1520 return ERROR_OK;
1521 }
1522
1523
1524
1525 struct jtag_interface zy1000_interface =
1526 {
1527 .name = "ZY1000",
1528 .supported = DEBUG_CAP_TMS_SEQ,
1529 .execute_queue = NULL,
1530 .speed = zy1000_speed,
1531 .commands = zy1000_commands,
1532 .init = zy1000_init,
1533 .quit = zy1000_quit,
1534 .khz = zy1000_khz,
1535 .speed_div = zy1000_speed_div,
1536 .power_dropout = zy1000_power_dropout,
1537 .srst_asserted = zy1000_srst_asserted,
1538 };

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