907b96578616885f560acb9f2e510f62c798040e
[openocd.git] / src / jtag / zy1000 / zy1000.c
1 /***************************************************************************
2 * Copyright (C) 2007-2010 by Øyvind Harboe *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 /* This file supports the zy1000 debugger: http://www.zylin.com/zy1000.html
21 *
22 * The zy1000 is a standalone debugger that has a web interface and
23 * requires no drivers on the developer host as all communication
24 * is via TCP/IP. The zy1000 gets it performance(~400-700kBytes/s
25 * DCC downloads @ 16MHz target) as it has an FPGA to hardware
26 * accelerate the JTAG commands, while offering *very* low latency
27 * between OpenOCD and the FPGA registers.
28 *
29 * The disadvantage of the zy1000 is that it has a feeble CPU compared to
30 * a PC(ca. 50-500 DMIPS depending on how one counts it), whereas a PC
31 * is on the order of 10000 DMIPS(i.e. at a factor of 20-200).
32 *
33 * The zy1000 revc hardware is using an Altera Nios CPU, whereas the
34 * revb is using ARM7 + Xilinx.
35 *
36 * See Zylin web pages or contact Zylin for more information.
37 *
38 * The reason this code is in OpenOCD rather than OpenOCD linked with the
39 * ZY1000 code is that OpenOCD is the long road towards getting
40 * libopenocd into place. libopenocd will support both low performance,
41 * low latency systems(embedded) and high performance high latency
42 * systems(PCs).
43 */
44 #ifdef HAVE_CONFIG_H
45 #include "config.h"
46 #endif
47
48 #include <target/embeddedice.h>
49 #include <jtag/minidriver.h>
50 #include <jtag/interface.h>
51 #include <time.h>
52
53
54 #if BUILD_ECOSBOARD
55 #include "zy1000_version.h"
56
57 #include <cyg/hal/hal_io.h> // low level i/o
58 #include <cyg/hal/hal_diag.h>
59
60 #ifdef CYGPKG_HAL_NIOS2
61 #include <cyg/hal/io.h>
62 #include <cyg/firmwareutil/firmwareutil.h>
63 #endif
64
65 #define ZYLIN_VERSION GIT_ZY1000_VERSION
66 #define ZYLIN_DATE __DATE__
67 #define ZYLIN_TIME __TIME__
68 #define ZYLIN_OPENOCD GIT_OPENOCD_VERSION
69 #define ZYLIN_OPENOCD_VERSION "ZY1000 " ZYLIN_VERSION " " ZYLIN_DATE
70
71 #endif
72
73 static int zy1000_khz(int khz, int *jtag_speed)
74 {
75 if (khz == 0)
76 {
77 *jtag_speed = 0;
78 }
79 else
80 {
81 *jtag_speed = 64000/khz;
82 }
83 return ERROR_OK;
84 }
85
86 static int zy1000_speed_div(int speed, int *khz)
87 {
88 if (speed == 0)
89 {
90 *khz = 0;
91 }
92 else
93 {
94 *khz = 64000/speed;
95 }
96
97 return ERROR_OK;
98 }
99
100 static bool readPowerDropout(void)
101 {
102 uint32_t state;
103 // sample and clear power dropout
104 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x80);
105 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state);
106 bool powerDropout;
107 powerDropout = (state & 0x80) != 0;
108 return powerDropout;
109 }
110
111
112 static bool readSRST(void)
113 {
114 uint32_t state;
115 // sample and clear SRST sensing
116 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000040);
117 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state);
118 bool srstAsserted;
119 srstAsserted = (state & 0x40) != 0;
120 return srstAsserted;
121 }
122
123 static int zy1000_srst_asserted(int *srst_asserted)
124 {
125 *srst_asserted = readSRST();
126 return ERROR_OK;
127 }
128
129 static int zy1000_power_dropout(int *dropout)
130 {
131 *dropout = readPowerDropout();
132 return ERROR_OK;
133 }
134
135 void zy1000_reset(int trst, int srst)
136 {
137 LOG_DEBUG("zy1000 trst=%d, srst=%d", trst, srst);
138
139 /* flush the JTAG FIFO. Not flushing the queue before messing with
140 * reset has such interesting bugs as causing hard to reproduce
141 * RCLK bugs as RCLK will stop responding when TRST is asserted
142 */
143 waitIdle();
144
145 if (!srst)
146 {
147 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x00000001);
148 }
149 else
150 {
151 /* Danger!!! if clk != 0 when in
152 * idle in TAP_IDLE, reset halt on str912 will fail.
153 */
154 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000001);
155 }
156
157 if (!trst)
158 {
159 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x00000002);
160 }
161 else
162 {
163 /* assert reset */
164 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000002);
165 }
166
167 if (trst||(srst && (jtag_get_reset_config() & RESET_SRST_PULLS_TRST)))
168 {
169 /* we're now in the RESET state until trst is deasserted */
170 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, TAP_RESET);
171 } else
172 {
173 /* We'll get RCLK failure when we assert TRST, so clear any false positives here */
174 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x400);
175 }
176
177 /* wait for srst to float back up */
178 if (!srst)
179 {
180 int i;
181 for (i = 0; i < 1000; i++)
182 {
183 // We don't want to sense our own reset, so we clear here.
184 // There is of course a timing hole where we could loose
185 // a "real" reset.
186 if (!readSRST())
187 break;
188
189 /* wait 1ms */
190 alive_sleep(1);
191 }
192
193 if (i == 1000)
194 {
195 LOG_USER("SRST didn't deassert after %dms", i);
196 } else if (i > 1)
197 {
198 LOG_USER("SRST took %dms to deassert", i);
199 }
200 }
201 }
202
203 int zy1000_speed(int speed)
204 {
205 /* flush JTAG master FIFO before setting speed */
206 waitIdle();
207
208 if (speed == 0)
209 {
210 /*0 means RCLK*/
211 speed = 0;
212 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x100);
213 LOG_DEBUG("jtag_speed using RCLK");
214 }
215 else
216 {
217 if (speed > 8190 || speed < 2)
218 {
219 LOG_USER("valid ZY1000 jtag_speed=[8190,2]. Divisor is 64MHz / even values between 8190-2, i.e. min 7814Hz, max 32MHz");
220 return ERROR_INVALID_ARGUMENTS;
221 }
222
223 LOG_USER("jtag_speed %d => JTAG clk=%f", speed, 64.0/(float)speed);
224 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x100);
225 ZY1000_POKE(ZY1000_JTAG_BASE + 0x1c, speed&~1);
226 }
227 return ERROR_OK;
228 }
229
230 static bool savePower;
231
232
233 static void setPower(bool power)
234 {
235 savePower = power;
236 if (power)
237 {
238 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x8);
239 } else
240 {
241 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x8);
242 }
243 }
244
245 COMMAND_HANDLER(handle_power_command)
246 {
247 switch (CMD_ARGC)
248 {
249 case 1: {
250 bool enable;
251 COMMAND_PARSE_ON_OFF(CMD_ARGV[0], enable);
252 setPower(enable);
253 // fall through
254 }
255 case 0:
256 LOG_INFO("Target power %s", savePower ? "on" : "off");
257 break;
258 default:
259 return ERROR_INVALID_ARGUMENTS;
260 }
261
262 return ERROR_OK;
263 }
264
265
266 #if BUILD_ECOSBOARD
267 /* Give TELNET a way to find out what version this is */
268 static int jim_zy1000_version(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
269 {
270 if ((argc < 1) || (argc > 3))
271 return JIM_ERR;
272 const char *version_str = NULL;
273
274 if (argc == 1)
275 {
276 version_str = ZYLIN_OPENOCD_VERSION;
277 } else
278 {
279 const char *str = Jim_GetString(argv[1], NULL);
280 const char *str2 = NULL;
281 if (argc > 2)
282 str2 = Jim_GetString(argv[2], NULL);
283 if (strcmp("openocd", str) == 0)
284 {
285 version_str = ZYLIN_OPENOCD;
286 }
287 else if (strcmp("zy1000", str) == 0)
288 {
289 version_str = ZYLIN_VERSION;
290 }
291 else if (strcmp("date", str) == 0)
292 {
293 version_str = ZYLIN_DATE;
294 }
295 else if (strcmp("time", str) == 0)
296 {
297 version_str = ZYLIN_TIME;
298 }
299 else if (strcmp("pcb", str) == 0)
300 {
301 #ifdef CYGPKG_HAL_NIOS2
302 version_str="c";
303 #else
304 version_str="b";
305 #endif
306 }
307 #ifdef CYGPKG_HAL_NIOS2
308 else if (strcmp("fpga", str) == 0)
309 {
310
311 /* return a list of 32 bit integers to describe the expected
312 * and actual FPGA
313 */
314 static char *fpga_id = "0x12345678 0x12345678 0x12345678 0x12345678";
315 uint32_t id, timestamp;
316 HAL_READ_UINT32(SYSID_BASE, id);
317 HAL_READ_UINT32(SYSID_BASE+4, timestamp);
318 sprintf(fpga_id, "0x%08x 0x%08x 0x%08x 0x%08x", id, timestamp, SYSID_ID, SYSID_TIMESTAMP);
319 version_str = fpga_id;
320 if ((argc>2) && (strcmp("time", str2) == 0))
321 {
322 time_t last_mod = timestamp;
323 char * t = ctime (&last_mod) ;
324 t[strlen(t)-1] = 0;
325 version_str = t;
326 }
327 }
328 #endif
329
330 else
331 {
332 return JIM_ERR;
333 }
334 }
335
336 Jim_SetResult(interp, Jim_NewStringObj(interp, version_str, -1));
337
338 return JIM_OK;
339 }
340 #endif
341
342 #ifdef CYGPKG_HAL_NIOS2
343
344
345 struct info_forward
346 {
347 void *data;
348 struct cyg_upgrade_info *upgraded_file;
349 };
350
351 static void report_info(void *data, const char * format, va_list args)
352 {
353 char *s = alloc_vprintf(format, args);
354 LOG_USER_N("%s", s);
355 free(s);
356 }
357
358 struct cyg_upgrade_info firmware_info =
359 {
360 (uint8_t *)0x84000000,
361 "/ram/firmware.phi",
362 "Firmware",
363 0x0300000,
364 0x1f00000 -
365 0x0300000,
366 "ZylinNiosFirmware\n",
367 report_info,
368 };
369
370 static int jim_zy1000_writefirmware(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
371 {
372 if (argc != 2)
373 return JIM_ERR;
374
375 int length;
376 const char *str = Jim_GetString(argv[1], &length);
377
378 /* */
379 int tmpFile;
380 if ((tmpFile = open(firmware_info.file, O_RDWR | O_CREAT | O_TRUNC)) <= 0)
381 {
382 return JIM_ERR;
383 }
384 bool success;
385 success = write(tmpFile, str, length) == length;
386 close(tmpFile);
387 if (!success)
388 return JIM_ERR;
389
390 if (!cyg_firmware_upgrade(NULL, firmware_info))
391 return JIM_ERR;
392
393 return JIM_OK;
394 }
395 #endif
396
397 static int
398 zylinjtag_Jim_Command_powerstatus(Jim_Interp *interp,
399 int argc,
400 Jim_Obj * const *argv)
401 {
402 if (argc != 1)
403 {
404 Jim_WrongNumArgs(interp, 1, argv, "powerstatus");
405 return JIM_ERR;
406 }
407
408 uint32_t status;
409 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, status);
410
411 Jim_SetResult(interp, Jim_NewIntObj(interp, (status&0x80) != 0));
412
413 return JIM_OK;
414 }
415
416
417
418
419 int zy1000_init(void)
420 {
421 #if BUILD_ECOSBOARD
422 LOG_USER("%s", ZYLIN_OPENOCD_VERSION);
423 #endif
424
425 ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x30); // Turn on LED1 & LED2
426
427 setPower(true); // on by default
428
429
430 /* deassert resets. Important to avoid infinite loop waiting for SRST to deassert */
431 zy1000_reset(0, 0);
432 zy1000_speed(jtag_get_speed());
433
434 return ERROR_OK;
435 }
436
437 int zy1000_quit(void)
438 {
439
440 return ERROR_OK;
441 }
442
443
444
445 int interface_jtag_execute_queue(void)
446 {
447 uint32_t empty;
448
449 waitIdle();
450 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty);
451 /* clear JTAG error register */
452 ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x400);
453
454 if ((empty&0x400) != 0)
455 {
456 LOG_WARNING("RCLK timeout");
457 /* the error is informative only as we don't want to break the firmware if there
458 * is a false positive.
459 */
460 // return ERROR_FAIL;
461 }
462 return ERROR_OK;
463 }
464
465
466
467
468
469 static uint32_t getShiftValue(void)
470 {
471 uint32_t value;
472 waitIdle();
473 ZY1000_PEEK(ZY1000_JTAG_BASE + 0xc, value);
474 VERBOSE(LOG_INFO("getShiftValue %08x", value));
475 return value;
476 }
477 #if 0
478 static uint32_t getShiftValueFlip(void)
479 {
480 uint32_t value;
481 waitIdle();
482 ZY1000_PEEK(ZY1000_JTAG_BASE + 0x18, value);
483 VERBOSE(LOG_INFO("getShiftValue %08x (flipped)", value));
484 return value;
485 }
486 #endif
487
488 #if 0
489 static void shiftValueInnerFlip(const tap_state_t state, const tap_state_t endState, int repeat, uint32_t value)
490 {
491 VERBOSE(LOG_INFO("shiftValueInner %s %s %d %08x (flipped)", tap_state_name(state), tap_state_name(endState), repeat, value));
492 uint32_t a,b;
493 a = state;
494 b = endState;
495 ZY1000_POKE(ZY1000_JTAG_BASE + 0xc, value);
496 ZY1000_POKE(ZY1000_JTAG_BASE + 0x8, (1 << 15) | (repeat << 8) | (a << 4) | b);
497 VERBOSE(getShiftValueFlip());
498 }
499 #endif
500
501 // here we shuffle N bits out/in
502 static __inline void scanBits(const uint8_t *out_value, uint8_t *in_value, int num_bits, bool pause, tap_state_t shiftState, tap_state_t end_state)
503 {
504 tap_state_t pause_state = shiftState;
505 for (int j = 0; j < num_bits; j += 32)
506 {
507 int k = num_bits - j;
508 if (k > 32)
509 {
510 k = 32;
511 /* we have more to shift out */
512 } else if (pause)
513 {
514 /* this was the last to shift out this time */
515 pause_state = end_state;
516 }
517
518 // we have (num_bits + 7)/8 bytes of bits to toggle out.
519 // bits are pushed out LSB to MSB
520 uint32_t value;
521 value = 0;
522 if (out_value != NULL)
523 {
524 for (int l = 0; l < k; l += 8)
525 {
526 value|=out_value[(j + l)/8]<<l;
527 }
528 }
529 /* mask away unused bits for easier debugging */
530 if (k < 32)
531 {
532 value&=~(((uint32_t)0xffffffff) << k);
533 } else
534 {
535 /* Shifting by >= 32 is not defined by the C standard
536 * and will in fact shift by &0x1f bits on nios */
537 }
538
539 shiftValueInner(shiftState, pause_state, k, value);
540
541 if (in_value != NULL)
542 {
543 // data in, LSB to MSB
544 value = getShiftValue();
545 // we're shifting in data to MSB, shift data to be aligned for returning the value
546 value >>= 32-k;
547
548 for (int l = 0; l < k; l += 8)
549 {
550 in_value[(j + l)/8]=(value >> l)&0xff;
551 }
552 }
553 }
554 }
555
556 static __inline void scanFields(int num_fields, const struct scan_field *fields, tap_state_t shiftState, tap_state_t end_state)
557 {
558 for (int i = 0; i < num_fields; i++)
559 {
560 scanBits(fields[i].out_value,
561 fields[i].in_value,
562 fields[i].num_bits,
563 (i == num_fields-1),
564 shiftState,
565 end_state);
566 }
567 }
568
569 int interface_jtag_add_ir_scan(struct jtag_tap *active, const struct scan_field *fields, tap_state_t state)
570 {
571 int scan_size = 0;
572 struct jtag_tap *tap, *nextTap;
573 tap_state_t pause_state = TAP_IRSHIFT;
574
575 for (tap = jtag_tap_next_enabled(NULL); tap!= NULL; tap = nextTap)
576 {
577 nextTap = jtag_tap_next_enabled(tap);
578 if (nextTap==NULL)
579 {
580 pause_state = state;
581 }
582 scan_size = tap->ir_length;
583
584 /* search the list */
585 if (tap == active)
586 {
587 scanFields(1, fields, TAP_IRSHIFT, pause_state);
588 /* update device information */
589 buf_cpy(fields[0].out_value, tap->cur_instr, scan_size);
590
591 tap->bypass = 0;
592 } else
593 {
594 /* if a device isn't listed, set it to BYPASS */
595 assert(scan_size <= 32);
596 shiftValueInner(TAP_IRSHIFT, pause_state, scan_size, 0xffffffff);
597
598 tap->bypass = 1;
599 }
600 }
601
602 return ERROR_OK;
603 }
604
605
606
607
608
609 int interface_jtag_add_plain_ir_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state)
610 {
611 scanBits(out_bits, in_bits, num_bits, true, TAP_IRSHIFT, state);
612 return ERROR_OK;
613 }
614
615 int interface_jtag_add_dr_scan(struct jtag_tap *active, int num_fields, const struct scan_field *fields, tap_state_t state)
616 {
617 struct jtag_tap *tap, *nextTap;
618 tap_state_t pause_state = TAP_DRSHIFT;
619 for (tap = jtag_tap_next_enabled(NULL); tap!= NULL; tap = nextTap)
620 {
621 nextTap = jtag_tap_next_enabled(tap);
622 if (nextTap==NULL)
623 {
624 pause_state = state;
625 }
626
627 /* Find a range of fields to write to this tap */
628 if (tap == active)
629 {
630 assert(!tap->bypass);
631
632 scanFields(num_fields, fields, TAP_DRSHIFT, pause_state);
633 } else
634 {
635 /* Shift out a 0 for disabled tap's */
636 assert(tap->bypass);
637 shiftValueInner(TAP_DRSHIFT, pause_state, 1, 0);
638 }
639 }
640 return ERROR_OK;
641 }
642
643 int interface_jtag_add_plain_dr_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state)
644 {
645 scanBits(out_bits, in_bits, num_bits, true, TAP_DRSHIFT, state);
646 return ERROR_OK;
647 }
648
649 int interface_jtag_add_tlr()
650 {
651 setCurrentState(TAP_RESET);
652 return ERROR_OK;
653 }
654
655
656 int interface_jtag_add_reset(int req_trst, int req_srst)
657 {
658 zy1000_reset(req_trst, req_srst);
659 return ERROR_OK;
660 }
661
662 static int zy1000_jtag_add_clocks(int num_cycles, tap_state_t state, tap_state_t clockstate)
663 {
664 /* num_cycles can be 0 */
665 setCurrentState(clockstate);
666
667 /* execute num_cycles, 32 at the time. */
668 int i;
669 for (i = 0; i < num_cycles; i += 32)
670 {
671 int num;
672 num = 32;
673 if (num_cycles-i < num)
674 {
675 num = num_cycles-i;
676 }
677 shiftValueInner(clockstate, clockstate, num, 0);
678 }
679
680 #if !TEST_MANUAL()
681 /* finish in end_state */
682 setCurrentState(state);
683 #else
684 tap_state_t t = TAP_IDLE;
685 /* test manual drive code on any target */
686 int tms;
687 uint8_t tms_scan = tap_get_tms_path(t, state);
688 int tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
689
690 for (i = 0; i < tms_count; i++)
691 {
692 tms = (tms_scan >> i) & 1;
693 waitIdle();
694 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, tms);
695 }
696 waitIdle();
697 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, state);
698 #endif
699
700 return ERROR_OK;
701 }
702
703 int interface_jtag_add_runtest(int num_cycles, tap_state_t state)
704 {
705 return zy1000_jtag_add_clocks(num_cycles, state, TAP_IDLE);
706 }
707
708 int interface_jtag_add_clocks(int num_cycles)
709 {
710 return zy1000_jtag_add_clocks(num_cycles, cmd_queue_cur_state, cmd_queue_cur_state);
711 }
712
713 int interface_jtag_add_sleep(uint32_t us)
714 {
715 jtag_sleep(us);
716 return ERROR_OK;
717 }
718
719 int interface_add_tms_seq(unsigned num_bits, const uint8_t *seq, enum tap_state state)
720 {
721 /*wait for the fifo to be empty*/
722 waitIdle();
723
724 for (unsigned i = 0; i < num_bits; i++)
725 {
726 int tms;
727
728 if (((seq[i/8] >> (i % 8)) & 1) == 0)
729 {
730 tms = 0;
731 }
732 else
733 {
734 tms = 1;
735 }
736
737 waitIdle();
738 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, tms);
739 }
740
741 waitIdle();
742 if (state != TAP_INVALID)
743 {
744 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, state);
745 } else
746 {
747 /* this would be normal if we are switching to SWD mode */
748 }
749 return ERROR_OK;
750 }
751
752 int interface_jtag_add_pathmove(int num_states, const tap_state_t *path)
753 {
754 int state_count;
755 int tms = 0;
756
757 state_count = 0;
758
759 tap_state_t cur_state = cmd_queue_cur_state;
760
761 uint8_t seq[16];
762 memset(seq, 0, sizeof(seq));
763 assert(num_states < (int)((sizeof(seq) * 8)));
764
765 while (num_states)
766 {
767 if (tap_state_transition(cur_state, false) == path[state_count])
768 {
769 tms = 0;
770 }
771 else if (tap_state_transition(cur_state, true) == path[state_count])
772 {
773 tms = 1;
774 }
775 else
776 {
777 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_name(cur_state), tap_state_name(path[state_count]));
778 exit(-1);
779 }
780
781 seq[state_count/8] = seq[state_count/8] | (tms << (state_count % 8));
782
783 cur_state = path[state_count];
784 state_count++;
785 num_states--;
786 }
787
788 return interface_add_tms_seq(state_count, seq, cur_state);
789 }
790
791 static void jtag_pre_post_bits(struct jtag_tap *tap, int *pre, int *post)
792 {
793 /* bypass bits before and after */
794 int pre_bits = 0;
795 int post_bits = 0;
796
797 bool found = false;
798 struct jtag_tap *cur_tap, *nextTap;
799 for (cur_tap = jtag_tap_next_enabled(NULL); cur_tap!= NULL; cur_tap = nextTap)
800 {
801 nextTap = jtag_tap_next_enabled(cur_tap);
802 if (cur_tap == tap)
803 {
804 found = true;
805 } else
806 {
807 if (found)
808 {
809 post_bits++;
810 } else
811 {
812 pre_bits++;
813 }
814 }
815 }
816 *pre = pre_bits;
817 *post = post_bits;
818 }
819
820 void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer, int little, int count)
821 {
822
823 int pre_bits;
824 int post_bits;
825 jtag_pre_post_bits(tap, &pre_bits, &post_bits);
826
827 if (pre_bits + post_bits + 6 > 32)
828 {
829 int i;
830 for (i = 0; i < count; i++)
831 {
832 embeddedice_write_reg_inner(tap, reg_addr, fast_target_buffer_get_u32(buffer, little));
833 buffer += 4;
834 }
835 } else
836 {
837 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, pre_bits, 0);
838 int i;
839 for (i = 0; i < count - 1; i++)
840 {
841 /* Fewer pokes means we get to use the FIFO more efficiently */
842 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, little));
843 shiftValueInner(TAP_DRSHIFT, TAP_IDLE, 6 + post_bits + pre_bits, (reg_addr | (1 << 5)));
844 buffer += 4;
845 }
846 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, little));
847 shiftValueInner(TAP_DRSHIFT, TAP_IDLE, 6 + post_bits, (reg_addr | (1 << 5)));
848 }
849 }
850
851
852
853 int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count)
854 {
855 #if 0
856 int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count);
857 return arm11_run_instr_data_to_core_noack_inner_default(tap, opcode, data, count);
858 #else
859 static const int bits[] = {32, 2};
860 uint32_t values[] = {0, 0};
861
862 /* FIX!!!!!! the target_write_memory() API started this nasty problem
863 * with unaligned uint32_t * pointers... */
864 const uint8_t *t = (const uint8_t *)data;
865
866
867 /* bypass bits before and after */
868 int pre_bits;
869 int post_bits;
870 jtag_pre_post_bits(tap, &pre_bits, &post_bits);
871
872 bool found = false;
873 struct jtag_tap *cur_tap, *nextTap;
874 for (cur_tap = jtag_tap_next_enabled(NULL); cur_tap!= NULL; cur_tap = nextTap)
875 {
876 nextTap = jtag_tap_next_enabled(cur_tap);
877 if (cur_tap == tap)
878 {
879 found = true;
880 } else
881 {
882 if (found)
883 {
884 post_bits++;
885 } else
886 {
887 pre_bits++;
888 }
889 }
890 }
891
892 post_bits+=2;
893
894
895 while (--count > 0)
896 {
897 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, pre_bits, 0);
898
899 uint32_t value;
900 value = *t++;
901 value |= (*t++<<8);
902 value |= (*t++<<16);
903 value |= (*t++<<24);
904
905 shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, value);
906 /* minimum 2 bits */
907 shiftValueInner(TAP_DRSHIFT, TAP_DRPAUSE, post_bits, 0);
908
909 #if 1
910 /* copy & paste from arm11_dbgtap.c */
911 //TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
912
913 waitIdle();
914 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
915 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
916 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
917 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
918 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
919 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 1);
920 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
921 ZY1000_POKE(ZY1000_JTAG_BASE + 0x28, 0);
922 /* we don't have to wait for the queue to empty here. waitIdle(); */
923 ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, TAP_DRSHIFT);
924 #else
925 static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
926 {
927 TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
928 };
929
930 jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
931 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
932 #endif
933 }
934
935 values[0] = *t++;
936 values[0] |= (*t++<<8);
937 values[0] |= (*t++<<16);
938 values[0] |= (*t++<<24);
939
940 /* This will happen on the last iteration updating the current tap state
941 * so we don't have to track it during the common code path */
942 jtag_add_dr_out(tap,
943 2,
944 bits,
945 values,
946 TAP_IDLE);
947
948 return jtag_execute_queue();
949 #endif
950 }
951
952
953 static const struct command_registration zy1000_commands[] = {
954 {
955 .name = "power",
956 .handler = handle_power_command,
957 .mode = COMMAND_ANY,
958 .help = "Turn power switch to target on/off. "
959 "With no arguments, prints status.",
960 .usage = "('on'|'off)",
961 },
962 #if BUILD_ECOSBOARD
963 {
964 .name = "zy1000_version",
965 .mode = COMMAND_ANY,
966 .jim_handler = jim_zy1000_version,
967 .help = "Print version info for zy1000.",
968 .usage = "['openocd'|'zy1000'|'date'|'time'|'pcb'|'fpga']",
969 },
970 #endif
971 {
972 .name = "powerstatus",
973 .mode = COMMAND_ANY,
974 .jim_handler = zylinjtag_Jim_Command_powerstatus,
975 .help = "Returns power status of target",
976 },
977 #ifdef CYGPKG_HAL_NIOS2
978 {
979 .name = "updatezy1000firmware",
980 .mode = COMMAND_ANY,
981 .jim_handler = jim_zy1000_writefirmware,
982 .help = "writes firmware to flash",
983 /* .usage = "some_string", */
984 },
985 #endif
986 COMMAND_REGISTRATION_DONE
987 };
988
989
990
991 struct jtag_interface zy1000_interface =
992 {
993 .name = "ZY1000",
994 .supported = DEBUG_CAP_TMS_SEQ,
995 .execute_queue = NULL,
996 .speed = zy1000_speed,
997 .commands = zy1000_commands,
998 .init = zy1000_init,
999 .quit = zy1000_quit,
1000 .khz = zy1000_khz,
1001 .speed_div = zy1000_speed_div,
1002 .power_dropout = zy1000_power_dropout,
1003 .srst_asserted = zy1000_srst_asserted,
1004 };
1005

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