1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
45 static u8 output_value
= 0x0;
46 static int dev_mem_fd
;
47 static void *gpio_controller
;
48 static volatile u8
*gpio_data_register
;
49 static volatile u8
*gpio_data_direction_register
;
51 /* low level command set
53 int ep93xx_read(void);
54 void ep93xx_write(int tck
, int tms
, int tdi
);
55 void ep93xx_reset(int trst
, int srst
);
57 int ep93xx_speed(int speed
);
58 int ep93xx_register_commands(struct command_context_s
*cmd_ctx
);
59 int ep93xx_init(void);
60 int ep93xx_quit(void);
62 struct timespec ep93xx_zzzz
;
64 jtag_interface_t ep93xx_interface
=
68 .execute_queue
= bitbang_execute_queue
,
70 .speed
= ep93xx_speed
,
71 .register_commands
= ep93xx_register_commands
,
76 bitbang_interface_t ep93xx_bitbang
=
79 .write
= ep93xx_write
,
80 .reset
= ep93xx_reset
,
86 return !!(*gpio_data_register
& TDO_BIT
);
89 void ep93xx_write(int tck
, int tms
, int tdi
)
92 output_value
|= TCK_BIT
;
94 output_value
&= ~TCK_BIT
;
97 output_value
|= TMS_BIT
;
99 output_value
&= ~TMS_BIT
;
102 output_value
|= TDI_BIT
;
104 output_value
&= ~TDI_BIT
;
106 *gpio_data_register
= output_value
;
107 nanosleep(&ep93xx_zzzz
, NULL
);
110 /* (1) assert or (0) deassert reset lines */
111 void ep93xx_reset(int trst
, int srst
)
114 output_value
|= TRST_BIT
;
116 output_value
&= ~TRST_BIT
;
119 output_value
|= SRST_BIT
;
121 output_value
&= ~SRST_BIT
;
123 *gpio_data_register
= output_value
;
124 nanosleep(&ep93xx_zzzz
, NULL
);
127 int ep93xx_speed(int speed
)
133 int ep93xx_register_commands(struct command_context_s
*cmd_ctx
)
139 static int set_gonk_mode(void)
144 syscon
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
145 MAP_SHARED
, dev_mem_fd
, 0x80930000);
146 if (syscon
== MAP_FAILED
) {
148 return ERROR_JTAG_INIT_FAILED
;
151 devicecfg
= *((volatile int *)(syscon
+ 0x80));
152 *((volatile int *)(syscon
+ 0xc0)) = 0xaa;
153 *((volatile int *)(syscon
+ 0x80)) = devicecfg
| 0x08000000;
155 munmap(syscon
, 4096);
160 int ep93xx_init(void)
164 bitbang_interface
= &ep93xx_bitbang
;
166 ep93xx_zzzz
.tv_sec
= 0;
167 ep93xx_zzzz
.tv_nsec
= 10000000;
169 dev_mem_fd
= open("/dev/mem", O_RDWR
| O_SYNC
);
170 if (dev_mem_fd
< 0) {
172 return ERROR_JTAG_INIT_FAILED
;
175 gpio_controller
= mmap(NULL
, 4096, PROT_READ
| PROT_WRITE
,
176 MAP_SHARED
, dev_mem_fd
, 0x80840000);
177 if (gpio_controller
== MAP_FAILED
) {
180 return ERROR_JTAG_INIT_FAILED
;
183 ret
= set_gonk_mode();
184 if (ret
!= ERROR_OK
) {
185 munmap(gpio_controller
, 4096);
191 /* Use GPIO port A. */
192 gpio_data_register
= gpio_controller
+ 0x00;
193 gpio_data_direction_register
= gpio_controller
+ 0x10;
196 /* Use GPIO port B. */
197 gpio_data_register
= gpio_controller
+ 0x04;
198 gpio_data_direction_register
= gpio_controller
+ 0x14;
200 /* Use GPIO port C. */
201 gpio_data_register
= gpio_controller
+ 0x08;
202 gpio_data_direction_register
= gpio_controller
+ 0x18;
204 /* Use GPIO port D. */
205 gpio_data_register
= gpio_controller
+ 0x0c;
206 gpio_data_direction_register
= gpio_controller
+ 0x1c;
209 /* Use GPIO port C. */
210 gpio_data_register
= gpio_controller
+ 0x08;
211 gpio_data_direction_register
= gpio_controller
+ 0x18;
213 LOG_INFO("gpio_data_register = %p\n", gpio_data_register
);
214 LOG_INFO("gpio_data_direction_reg = %p\n", gpio_data_direction_register
);
216 * Configure bit 0 (TDO) as an input, and bits 1-5 (TDI, TCK
217 * TMS, TRST, SRST) as outputs. Drive TDI and TCK low, and
218 * TMS/TRST/SRST high.
220 output_value
= TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
221 *gpio_data_register
= output_value
;
222 nanosleep(&ep93xx_zzzz
, NULL
);
225 * Configure the direction register. 1 = output, 0 = input.
227 *gpio_data_direction_register
=
228 TDI_BIT
| TCK_BIT
| TMS_BIT
| TRST_BIT
| SRST_BIT
| VCC_BIT
;
230 nanosleep(&ep93xx_zzzz
, NULL
);
234 int ep93xx_quit(void)
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