src/jtag/drivers/OpenULINK/include/reg_ezusb.h

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Martin Schmoelzer                               *
   3  *   <martin.schmoelzer@student.tuwien.ac.at>                              *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef REG_EZUSB_H
  20 #define REG_EZUSB_H
  21
  22 /**
  23  * @file
  24  * All information in this file was taken from the EZ-USB Technical
  25  * Reference Manual, Cypress Semiconductor, 3901 North First Street
  26  * San Jose, CA 95134 (www.cypress.com).
  27  *
  28  * The EZ-USB Technical Reference Manual is called "EZ-USB TRM" hereafter.
  29  *
  30  * The following bit name  definitions differ from those in the EZ-USB TRM:
  31  * - All lowercase characters in the EZ-USB TRM bit names have been converted
  32  *   to capitals (e. g. "WakeSRC" converted to "WAKESRC").
  33  * - CPUCS:  8051RES is named "RES8051".
  34  * - ISOCTL: Two MBZ ("Must Be Zero") bits are named "MBZ0" and "MBZ1".
  35  * - I2CS: STOP and START bits are preceded by "I2C_"
  36  * - INxCS, OUTxCS: the busy and stall bits are named "EPBSY" and "EPSTALL".
  37  * - TOGCTL: EZ-USB TRM bit names are preceded by "TOG_".
  38  */
  39
  40 /* Compiler-specific definitions of SBIT, SFR, SFRX, ... macros */
  41 #include <mcs51/compiler.h>
  42
  43 /* Bit vectors */
  44 #define bmBit0      0x01
  45 #define bmBit1      0x02
  46 #define bmBit2      0x04
  47 #define bmBit3      0x08
  48 #define bmBit4      0x10
  49 #define bmBit5      0x20
  50 #define bmBit6      0x40
  51 #define bmBit7      0x80
  52
  53 /**************************************************************************
  54  ************************ Special Function Registers **********************
  55  ***************************************************************************/
  56
  57 /* See EZ-USB TRM, pp. A-9 - A-10 */
  58
  59 SFR(SP,             0x81);
  60 SFR(DPL0,           0x82);
  61 SFR(DPH0,           0x83);
  62 SFR(DPL1,           0x84);
  63 SFR(DPL2,           0x85);
  64
  65 SFR(DPS,            0x86);
  66 #define SEL         bmBit0
  67 /* Bit 1 read-only, always reads '0' */
  68 /* Bit 2 read-only, always reads '0' */
  69 /* Bit 3 read-only, always reads '0' */
  70 /* Bit 4 read-only, always reads '0' */
  71 /* Bit 5 read-only, always reads '0' */
  72 /* Bit 6 read-only, always reads '0' */
  73 /* Bit 7 read-only, always reads '0' */
  74
  75 SFR(PCON,           0x87);
  76 #define IDLE        bmBit0
  77 #define STOP        bmBit1
  78 #define GF0         bmBit2
  79 #define GF1         bmBit3
  80 /* Bit 4 read-only, always reads '1' */
  81 /* Bit 5 read-only, always reads '1' */
  82 /* Bit 6 unused */
  83 #define SMOD0     bmBit7
  84
  85 SFR(TCON,           0x88);
  86 SBIT(IT0,           0x88, 0);
  87 SBIT(IE0,           0x88, 1);
  88 SBIT(IT1,           0x88, 2);
  89 SBIT(IE1,           0x88, 3);
  90 SBIT(TR0,           0x88, 4);
  91 SBIT(TF0,           0x88, 5);
  92 SBIT(TR1,           0x88, 6);
  93 SBIT(TF1,           0x88, 7);
  94
  95 SFR(TMOD,           0x89);
  96 /* Some bits in this register share the same name in the EZ-USB TRM. Therefore,
  97  * we add a '0'/'1' to distinguish them */
  98 #define M00         bmBit0
  99 #define M01         bmBit1
 100 #define CT0         bmBit2
 101 #define GATE0       bmBit3
 102 #define M10         bmBit4
 103 #define M11         bmBit5
 104 #define CT1         bmBit6
 105 #define GATE1       bmBit7
 106
 107 SFR(TL0,            0x8A);
 108 SFR(TL1,            0x8B);
 109 SFR(TH0,            0x8C);
 110 SFR(TH1,            0x8D);
 111
 112 SFR(CKCON,          0x8E);
 113 #define MD0         bmBit0
 114 #define MD1         bmBit1
 115 #define MD2         bmBit2
 116 #define T0M         bmBit3
 117 #define T1M         bmBit4
 118 #define T2M         bmBit5
 119 /* Bit 6 unused */
 120 /* Bit 7 unused */
 121
 122 SFR(SPC_FNC,        0x8D);
 123 #define bmWRS       bmBit0
 124 /* Bit 1 read-only, always reads '0' */
 125 /* Bit 2 read-only, always reads '0' */
 126 /* Bit 3 read-only, always reads '0' */
 127 /* Bit 4 read-only, always reads '0' */
 128 /* Bit 5 read-only, always reads '0' */
 129 /* Bit 6 read-only, always reads '0' */
 130 /* Bit 7 read-only, always reads '0' */
 131
 132 SFR(EXIF,           0x91);
 133 /* Bit 0 read-only, always reads '0' */
 134 /* Bit 1 read-only, always reads '0' */
 135 /* Bit 2 read-only, always reads '0' */
 136 /* Bit 3 read-only, always reads '1' */
 137 #define USBINT      bmBit4
 138 #define I2CINT      bmBit5
 139 #define IE4         bmBit6
 140 #define IE5         bmBit7
 141
 142 /* Definition of the _XPAGE register, according to SDCC Compiler User Guide,
 143  * Version 3.0.1, Chapter 4, p. 61. Also see EZ-USB TRM, p. 2-4. */
 144 SFR(MPAGE,          0x92);
 145 SFR(_XPAGE,         0x92);
 146
 147 SFR(SCON0,          0x98);
 148 SBIT(RI_0,          0x98, 0);
 149 SBIT(TI_0,          0x98, 1);
 150 SBIT(RB8_0,         0x98, 2);
 151 SBIT(TB8_0,         0x98, 3);
 152 SBIT(REN_0,         0x98, 4);
 153 SBIT(SM2_0,         0x98, 5);
 154 SBIT(SM1_0,         0x98, 6);
 155 SBIT(SM0_0,         0x98, 7);
 156
 157 SFR(SBUF0,          0x99);
 158
 159 SFR(IE,             0xA8);
 160 SBIT(EX0,           0xA8, 0);
 161 SBIT(ET0,           0xA8, 1);
 162 SBIT(EX1,           0xA8, 2);
 163 SBIT(ET1,           0xA8, 3);
 164 SBIT(ES0,           0xA8, 4);
 165 SBIT(ET2,           0xA8, 5);
 166 SBIT(ES1,           0xA8, 6);
 167 SBIT(EA,            0xA8, 7);
 168
 169 SFR(IP,             0xB8);
 170 SBIT(PX0,           0xB8, 0);
 171 SBIT(PT0,           0xB8, 1);
 172 SBIT(PX1,           0xB8, 2);
 173 SBIT(PT1,           0xB8, 3);
 174 SBIT(PS0,           0xB8, 4);
 175 SBIT(PT2,           0xB8, 5);
 176 SBIT(PS1,           0xB8, 6);
 177 /* Bit 7 read-only, always reads '1' */
 178
 179 SFR(SCON1,          0xC0);
 180 SBIT(RI_1,          0xC0, 0);
 181 SBIT(TI_1,          0xC0, 1);
 182 SBIT(RB8_1,         0xC0, 2);
 183 SBIT(TB8_1,         0xC0, 3);
 184 SBIT(REN_1,         0xC0, 4);
 185 SBIT(SM2_1,         0xC0, 5);
 186 SBIT(SM1_1,         0xC0, 6);
 187 SBIT(SM0_1,         0xC0, 7);
 188
 189 SFR(SBUF1,          0xC1);
 190
 191 SFR(T2CON,          0xC8);
 192 SBIT(CPRL2,         0xC8, 0);
 193 SBIT(CT2,           0xC8, 1);
 194 SBIT(TR2,           0xC8, 2);
 195 SBIT(EXEN2,         0xC8, 3);
 196 SBIT(TCLK,          0xC8, 4);
 197 SBIT(RCLK,          0xC8, 5);
 198 SBIT(EXF2,          0xC8, 6);
 199 SBIT(TF2,           0xC8, 7);
 200
 201 SFR(RCAP2L,         0xCA);
 202 SFR(RCAP2H,         0xCB);
 203 SFR(TL2,            0xCC);
 204 SFR(TH2,            0xCD);
 205
 206 SFR(PSW,            0xD0);
 207 SBIT(P,             0xD0, 0);
 208 SBIT(F1,            0xD0, 1);
 209 SBIT(OV,            0xD0, 2);
 210 SBIT(RS0,           0xD0, 3);
 211 SBIT(RS1,           0xD0, 4);
 212 SBIT(F0,            0xD0, 5);
 213 SBIT(AC,            0xD0, 6);
 214 SBIT(CY,            0xD0, 7);
 215
 216 SFR(EICON,          0xD8);
 217 /* Bit 0 read-only, always reads '0' */
 218 /* Bit 1 read-only, always reads '0' */
 219 /* Bit 2 read-only, always reads '0' */
 220 SBIT(INT6,          0xD8, 3);
 221 SBIT(RESI,          0xD8, 4);
 222 SBIT(ERESI,         0xD8, 5);
 223 /* Bit 6 read-only, always reads '1' */
 224 SBIT(SMOD1,         0xD8, 7);
 225
 226 SFR(ACC,            0xE0);
 227
 228 SFR(EIE,            0xE8);
 229 SBIT(EUSB,          0xE8, 0);
 230 SBIT(EI2C,          0xE8, 1);
 231 SBIT(EX4,           0xE8, 2);
 232 SBIT(EX5,           0xE8, 3);
 233 SBIT(EWDI,          0xE8, 4);
 234 /* Bit 5 read-only, always reads '1' */
 235 /* Bit 6 read-only, always reads '1' */
 236 /* Bit 7 read-only, always reads '1' */
 237
 238 SFR(B,              0xF0);
 239
 240 SFR(EIP,            0xF8);
 241 SBIT(PUSB,          0xF8, 0);
 242 SBIT(PI2C,          0xF8, 1);
 243 SBIT(PX4,           0xF8, 2);
 244 SBIT(PX5,           0xF8, 3);
 245 SBIT(PX6,           0xF8, 4);
 246 /* Bit 5 read-only, always reads '1' */
 247 /* Bit 6 read-only, always reads '1' */
 248 /* Bit 7 read-only, always reads '1' */
 249
 250 /**************************************************************************
 251  ***************************** XDATA Registers ****************************
 252  ***************************************************************************/
 253
 254 /************************ Endpoint 0-7 Data Buffers ************************/
 255 SFRX(OUT7BUF[64],   0x7B40);
 256 SFRX(IN7BUF[64],    0x7B80);
 257 SFRX(OUT6BUF[64],   0x7BC0);
 258 SFRX(IN6BUF[64],    0x7C00);
 259 SFRX(OUT5BUF[64],   0x7C40);
 260 SFRX(IN5BUF[64],    0x7C80);
 261 SFRX(OUT4BUF[64],   0x7CC0);
 262 SFRX(IN4BUF[64],    0x7D00);
 263 SFRX(OUT3BUF[64],   0x7D40);
 264 SFRX(IN3BUF[64],    0x7D80);
 265 SFRX(OUT2BUF[64],   0x7DC0);
 266 SFRX(IN2BUF[64],    0x7E00);
 267 SFRX(OUT1BUF[64],   0x7E40);
 268 SFRX(IN1BUF[64],    0x7E80);
 269 SFRX(OUT0BUF[64],   0x7EC0);
 270 SFRX(IN0BUF[64],    0x7F00);
 271 /* 0x7F40 - 0x7F5F reserved */
 272
 273 /**************************** Isochronous Data *****************************/
 274 SFRX(OUT8DATA,      0x7F60);
 275 SFRX(OUT9DATA,      0x7F61);
 276 SFRX(OUT10DATA,     0x7F62);
 277 SFRX(OUT11DATA,     0x7F63);
 278 SFRX(OUT12DATA,     0x7F64);
 279 SFRX(OUT13DATA,     0x7F65);
 280 SFRX(OUT14DATA,     0x7F66);
 281 SFRX(OUT15DATA,     0x7F67);
 282
 283 SFRX(IN8DATA,       0x7F68);
 284 SFRX(IN9DATA,       0x7F69);
 285 SFRX(IN10DATA,      0x7F6A);
 286 SFRX(IN11DATA,      0x7F6B);
 287 SFRX(IN12DATA,      0x7F6C);
 288 SFRX(IN13DATA,      0x7F6D);
 289 SFRX(IN14DATA,      0x7F6E);
 290 SFRX(IN15DATA,      0x7F6F);
 291
 292 /************************* Isochronous Byte Counts *************************/
 293 SFRX(OUT8BCH,       0x7F70);
 294 SFRX(OUT8BCL,       0x7F71);
 295 SFRX(OUT9BCH,       0x7F72);
 296 SFRX(OUT9BCL,       0x7F73);
 297 SFRX(OUT10BCH,      0x7F74);
 298 SFRX(OUT10BCL,      0x7F75);
 299 SFRX(OUT11BCH,      0x7F76);
 300 SFRX(OUT11BCL,      0x7F77);
 301 SFRX(OUT12BCH,      0x7F78);
 302 SFRX(OUT12BCL,      0x7F79);
 303 SFRX(OUT13BCH,      0x7F7A);
 304 SFRX(OUT13BCL,      0x7F7B);
 305 SFRX(OUT14BCH,      0x7F7C);
 306 SFRX(OUT14BCL,      0x7F7D);
 307 SFRX(OUT15BCH,      0x7F7E);
 308 SFRX(OUT16BCL,      0x7F7F);
 309
 310 /****************************** CPU Registers ******************************/
 311 SFRX(CPUCS,         0x7F92);
 312 #define RES8051     bmBit0
 313 #define CLK24OE     bmBit1
 314 /* Bit 2 read-only, always reads '0' */
 315 /* Bit 3 read-only, always reads '0' */
 316 /* Bits 4...7: Chip Revision */
 317
 318 SFRX(PORTACFG,      0x7F93);
 319 #define T0OUT       bmBit0
 320 #define T1OUT       bmBit1
 321 #define OE          bmBit2
 322 #define CS          bmBit3
 323 #define FWR         bmBit4
 324 #define FRD         bmBit5
 325 #define RXD0OUT     bmBit6
 326 #define RXD1OUT     bmBit7
 327
 328 SFRX(PORTBCFG,      0x7F94);
 329 #define T2          bmBit0
 330 #define T2EX        bmBit1
 331 #define RXD1        bmBit2
 332 #define TXD1        bmBit3
 333 #define INT4        bmBit4
 334 #define INT5        bmBit5
 335 #define INT6        bmBit6
 336 #define T2OUT       bmBit7
 337
 338 SFRX(PORTCCFG,      0x7F95);
 339 #define RXD0        bmBit0
 340 #define TXD0        bmBit1
 341 #define INT0        bmBit2
 342 #define INT1        bmBit3
 343 #define T0          bmBit4
 344 #define T1          bmBit5
 345 #define WR          bmBit6
 346 #define RD          bmBit7
 347
 348 /*********************** Input-Output Port Registers ***********************/
 349 SFRX(OUTA,          0x7F96);
 350 #define OUTA0       bmBit0
 351 #define OUTA1       bmBit1
 352 #define OUTA2       bmBit2
 353 #define OUTA3       bmBit3
 354 #define OUTA4       bmBit4
 355 #define OUTA5       bmBit5
 356 #define OUTA6       bmBit6
 357 #define OUTA7       bmBit7
 358
 359 SFRX(OUTB,          0x7F97);
 360 #define OUTB0       bmBit0
 361 #define OUTB1       bmBit1
 362 #define OUTB2       bmBit2
 363 #define OUTB3       bmBit3
 364 #define OUTB4       bmBit4
 365 #define OUTB5       bmBit5
 366 #define OUTB6       bmBit6
 367 #define OUTB7       bmBit7
 368
 369 SFRX(OUTC,          0x7F98);
 370 #define OUTC0       bmBit0
 371 #define OUTC1       bmBit1
 372 #define OUTC2       bmBit2
 373 #define OUTC3       bmBit3
 374 #define OUTC4       bmBit4
 375 #define OUTC5       bmBit5
 376 #define OUTC6       bmBit6
 377 #define OUTC7       bmBit7
 378
 379 SFRX(PINSA,         0x7F99);
 380 #define PINA0       bmBit0
 381 #define PINA1       bmBit1
 382 #define PINA2       bmBit2
 383 #define PINA3       bmBit3
 384 #define PINA4       bmBit4
 385 #define PINA5       bmBit5
 386 #define PINA6       bmBit6
 387 #define PINA7       bmBit7
 388
 389 SFRX(PINSB,         0x7F9A);
 390 #define PINB0       bmBit0
 391 #define PINB1       bmBit1
 392 #define PINB2       bmBit2
 393 #define PINB3       bmBit3
 394 #define PINB4       bmBit4
 395 #define PINB5       bmBit5
 396 #define PINB6       bmBit6
 397 #define PINB7       bmBit7
 398
 399 SFRX(PINSC,         0x7F9B);
 400 #define PINC0       bmBit0
 401 #define PINC1       bmBit1
 402 #define PINC2       bmBit2
 403 #define PINC3       bmBit3
 404 #define PINC4       bmBit4
 405 #define PINC5       bmBit5
 406 #define PINC6      bmBit6
 407 #define PINC7       bmBit7
 408
 409 SFRX(OEA,           0x7F9C);
 410 #define OEA0        bmBit0
 411 #define OEA1        bmBit1
 412 #define OEA2        bmBit2
 413 #define OEA3        bmBit3
 414 #define OEA4        bmBit4
 415 #define OEA5        bmBit5
 416 #define OEA6        bmBit6
 417 #define OEA7        bmBit7
 418
 419 SFRX(OEB,           0x7F9D);
 420 #define OEB0        bmBit0
 421 #define OEB1        bmBit1
 422 #define OEB2        bmBit2
 423 #define OEB3        bmBit3
 424 #define OEB4        bmBit4
 425 #define OEB5        bmBit5
 426 #define OEB6        bmBit6
 427 #define OEB7        bmBit7
 428
 429 SFRX(OEC,           0x7F9E);
 430 #define OEC0        bmBit0
 431 #define OEC1        bmBit1
 432 #define OEC2        bmBit2
 433 #define OEC3        bmBit3
 434 #define OEC4        bmBit4
 435 #define OEC5        bmBit5
 436 #define OEC6        bmBit6
 437 #define OEC7        bmBit7
 438
 439 /* 0x7F9F reserved */
 440
 441 /****************** Isochronous Control/Status Registers *******************/
 442 SFRX(ISOERR,        0x7FA0);
 443 #define ISO8ERR     bmBit0
 444 #define ISO9ERR     bmBit1
 445 #define ISO10ERR    bmBit2
 446 #define ISO11ERR    bmBit3
 447 #define ISO12ERR    bmBit4
 448 #define ISO13ERR    bmBit5
 449 #define ISO14ERR    bmBit6
 450 #define ISO15ERR    bmBit7
 451
 452 SFRX(ISOCTL,        0x7FA1);
 453 #define ISODISAB    bmBit0
 454 #define MBZ0        bmBit1
 455 #define MBZ1        bmBit2
 456 #define PPSTAT      bmBit3
 457 /* Bit 4 unused */
 458 /* Bit 5 unused */
 459 /* Bit 6 unused */
 460 /* Bit 7 unused */
 461
 462 SFRX(ZBCOUT,        0x7FA2);
 463 #define EP8         bmBit0
 464 #define EP9         bmBit1
 465 #define EP10        bmBit2
 466 #define EP11        bmBit3
 467 #define EP12        bmBit4
 468 #define EP13        bmBit5
 469 #define EP14        bmBit6
 470 #define EP15        bmBit7
 471
 472 /* 0x7FA3 reserved */
 473 /* 0x7FA4 reserved */
 474
 475 /****************************** I2C Registers ******************************/
 476 SFRX(I2CS,          0x7FA5);
 477 #define DONE        bmBit0
 478 #define ACK         bmBit1
 479 #define BERR        bmBit2
 480 #define ID0         bmBit3
 481 #define ID1         bmBit4
 482 #define LASTRD      bmBit5
 483 #define I2C_STOP    bmBit6
 484 #define I2C_START   bmBit7
 485
 486 SFRX(I2DAT,         0x7FA6);
 487 /* 0x7FA7 reserved */
 488
 489 /******************************* Interrupts ********************************/
 490 SFRX(IVEC,          0x7FA8);
 491 /* Bit 0 read-only, always reads '0' */
 492 /* Bit 1 read-only, always reads '0' */
 493 #define IV0         bmBit2
 494 #define IV1         bmBit3
 495 #define IV2         bmBit4
 496 #define IV3         bmBit5
 497 #define IV4         bmBit6
 498 /* Bit 7 read-only, always reads '0' */
 499
 500 SFRX(IN07IRQ,       0x7FA9);
 501 #define IN0IR       bmBit0
 502 #define IN1IR       bmBit1
 503 #define IN2IR       bmBit2
 504 #define IN3IR       bmBit3
 505 #define IN4IR       bmBit4
 506 #define IN5IR       bmBit5
 507 #define IN6IR       bmBit6
 508 #define IN7IR       bmBit7
 509
 510 SFRX(OUT07IRQ,      0x7FAA);
 511 #define OUT0IR      bmBit0
 512 #define OUT1IR      bmBit1
 513 #define OUT2IR      bmBit2
 514 #define OUT3IR      bmBit3
 515 #define OUT4IR      bmBit4
 516 #define OUT5IR      bmBit5
 517 #define OUT6IR      bmBit6
 518 #define OUT7IR      bmBit7
 519
 520 SFRX(USBIRQ,        0x7FAB);
 521 #define SUDAVIR     bmBit0
 522 #define SOFIR       bmBit1
 523 #define SUTOKIR     bmBit2
 524 #define SUSPIR      bmBit3
 525 #define URESIR      bmBit4
 526 /* Bit 5 unused */
 527 /* Bit 6 unused */
 528 /* Bit 7 unused */
 529
 530 SFRX(IN07IEN,       0x7FAC);
 531 #define IN0IEN      bmBit0
 532 #define IN1IEN      bmBit1
 533 #define IN2IEN      bmBit2
 534 #define IN3IEN      bmBit3
 535 #define IN4IEN      bmBit4
 536 #define IN5IEN      bmBit5
 537 #define IN6IEN      bmBit6
 538 #define IN7IEN      bmBit7
 539
 540 SFRX(OUT07IEN,      0x7FAD);
 541 #define OUT0IEN     bmBit0
 542 #define OUT1IEN     bmBit1
 543 #define OUT2IEN     bmBit2
 544 #define OUT3IEN     bmBit3
 545 #define OUT4IEN     bmBit4
 546 #define OUT5IEN     bmBit5
 547 #define OUT6IEN     bmBit6
 548 #define OUT7IEN     bmBit7
 549
 550 SFRX(USBIEN,        0x7FAE);
 551 #define SUDAVIE     bmBit0
 552 #define SOFIE       bmBit1
 553 #define SUTOKIE     bmBit2
 554 #define SUSPIE      bmBit3
 555 #define URESIE      bmBit4
 556 /* Bit 5 unused */
 557 /* Bit 6 unused */
 558 /* Bit 7 unused */
 559
 560 SFRX(USBBAV,        0x7FAF);
 561 #define AVEN        bmBit0
 562 #define BPEN        bmBit1
 563 #define BPPULSE     bmBit2
 564 #define BREAK       bmBit3
 565 /* Bit 4 unused */
 566 /* Bit 5 unused */
 567 /* Bit 6 unused */
 568 /* Bit 7 unused */
 569
 570 /* 0x7FB0 reserved */
 571 /* 0x7FB1 reserved */
 572 SFRX(BPADDRH,       0x7FB2);
 573 SFRX(BPADDRL,       0x7FB3);
 574
 575 /****************************** Endpoints 0-7 ******************************/
 576 SFRX(EP0CS,         0x7FB4);
 577 #define EP0STALL    bmBit0
 578 #define HSNAK       bmBit1
 579 #define IN0BSY      bmBit2
 580 #define OUT0BSY     bmBit3
 581 /* Bit 4 unused */
 582 /* Bit 5 unused */
 583 /* Bit 6 unused */
 584 /* Bit 7 unused */
 585
 586 SFRX(IN0BC,         0x7FB5);
 587 SFRX(IN1CS,         0x7FB6);
 588 SFRX(IN1BC,         0x7FB7);
 589 SFRX(IN2CS,         0x7FB8);
 590 SFRX(IN2BC,         0x7FB9);
 591 SFRX(IN3CS,         0x7FBA);
 592 SFRX(IN3BC,         0x7FBB);
 593 SFRX(IN4CS,         0x7FBC);
 594 SFRX(IN4BC,         0x7FBD);
 595 SFRX(IN5CS,         0x7FBE);
 596 SFRX(IN5BC,         0x7FBF);
 597 SFRX(IN6CS,         0x7FC0);
 598 SFRX(IN6BC,         0x7FC1);
 599 SFRX(IN7CS,         0x7FC2);
 600 SFRX(IN7BC,         0x7FC3);
 601 /* 0x7FC4 reserved */
 602 SFRX(OUT0BC,        0x7FC5);
 603 SFRX(OUT1CS,        0x7FC6);
 604 SFRX(OUT1BC,        0x7FC7);
 605 SFRX(OUT2CS,        0x7FC8);
 606 SFRX(OUT2BC,        0x7FC9);
 607 SFRX(OUT3CS,        0x7FCA);
 608 SFRX(OUT3BC,        0x7FCB);
 609 SFRX(OUT4CS,        0x7FCC);
 610 SFRX(OUT4BC,        0x7FCD);
 611 SFRX(OUT5CS,        0x7FCE);
 612 SFRX(OUT5BC,        0x7FCF);
 613 SFRX(OUT6CS,        0x7FD0);
 614 SFRX(OUT6BC,        0x7FD1);
 615 SFRX(OUT7CS,        0x7FD2);
 616 SFRX(OUT7BC,        0x7FD3);
 617
 618 /* The INxSTALL, OUTxSTALL, INxBSY and OUTxBSY bits are the same for all
 619  * INxCS/OUTxCS registers. For better readability, we define them only once */
 620 #define EPSTALL     bmBit0
 621 #define EPBSY       bmBit1
 622
 623 /************************** Global USB Registers ***************************/
 624 SFRX(SUDPTRH,       0x7FD4);
 625 SFRX(SUDPTRL,       0x7FD5);
 626
 627 SFRX(USBCS,         0x7FD6);
 628 #define SIGRSUME    bmBit0
 629 #define RENUM       bmBit1
 630 #define DISCOE      bmBit2
 631 #define DISCON      bmBit3
 632 /* Bit 4 unused */
 633 /* Bit 5 unused */
 634 /* Bit 6 unused */
 635 #define WAKESRC     bmBit7
 636
 637 SFRX(TOGCTL,        0x7FD7);
 638 #define TOG_EP0     bmBit0
 639 #define TOG_EP1     bmBit1
 640 #define TOG_EP2     bmBit2
 641 /* Bit 3 is read-only, always reads '0' */
 642 #define TOG_IO      bmBit4
 643 #define TOG_R       bmBit5
 644 #define TOG_S       bmBit6
 645 #define TOG_Q       bmBit7
 646
 647 SFRX(USBFRAMEL,     0x7FD8);
 648 SFRX(USBFRAMEH,     0x7FD9);
 649 /* 0x7FDA reserved */
 650 SFRX(FNADDR,        0x7FDB);
 651 /* 0x7FDC reserved */
 652
 653 SFRX(USBPAIR,       0x7FDD);
 654 #define PR2IN       bmBit0
 655 #define PR4IN       bmBit1
 656 #define PR6IN       bmBit2
 657 #define PR2OUT      bmBit3
 658 #define PR4OUT      bmBit4
 659 #define PR6OUT      bmBit5
 660 /* Bit 6 unused */
 661 #define ISOSEND0    bmBit7
 662
 663 SFRX(IN07VAL,       0x7FDE);
 664 /* Bit 0 is read-only, always reads '1' */
 665 #define IN1VAL      bmBit1
 666 #define IN2VAL      bmBit2
 667 #define IN3VAL      bmBit3
 668 #define IN4VAL      bmBit4
 669 #define IN5VAL      bmBit5
 670 #define IN6VAL      bmBit6
 671 #define IN7VAL      bmBit7
 672
 673 SFRX(OUT07VAL,      0x7FDF);
 674 /* Bit 0 is read-only, always reads '1' */
 675 #define OUT1VAL     bmBit1
 676 #define OUT2VAL     bmBit2
 677 #define OUT3VAL     bmBit3
 678 #define OUT4VAL     bmBit4
 679 #define OUT5VAL     bmBit5
 680 #define OUT6VAL     bmBit6
 681 #define OUT7VAL     bmBit7
 682
 683 SFRX(INISOVAL,      0x7FE0);
 684 #define IN8VAL      bmBit0
 685 #define IN9VAL      bmBit1
 686 #define IN10VAL     bmBit2
 687 #define IN11VAL     bmBit3
 688 #define IN12VAL     bmBit4
 689 #define IN13VAL     bmBit5
 690 #define IN14VAL     bmBit6
 691 #define IN15VAL     bmBit7
 692
 693 SFRX(OUTISOVAL,     0x7FE1);
 694 #define OUT8VAL     bmBit0
 695 #define OUT9VAL     bmBit1
 696 #define OUT10VAL    bmBit2
 697 #define OUT11VAL    bmBit3
 698 #define OUT12VAL    bmBit4
 699 #define OUT13VAL    bmBit5
 700 #define OUT14VAL    bmBit6
 701 #define OUT15VAL    bmBit7
 702
 703 SFRX(FASTXFR,       0x7FE2);
 704 #define WMOD0       bmBit0
 705 #define WMOD1       bmBit1
 706 #define WPOL        bmBit2
 707 #define RMOD0       bmBit3
 708 #define RMOD1       bmBit4
 709 #define RPOL        bmBit5
 710 #define FBLK        bmBit6
 711 #define FISO        bmBit7
 712
 713 SFRX(AUTOPTRH,      0x7FE3);
 714 SFRX(AUTOPTRL,      0x7FE4);
 715 SFRX(AUTODATA,      0x7FE5);
 716 /* 0x7FE6 reserved */
 717 /* 0x7FE7 reserved */
 718
 719 /******************************* Setup Data ********************************/
 720 SFRX(SETUPDAT[8],   0x7FE8);
 721
 722 /************************* Isochronous FIFO sizes **************************/
 723 SFRX(OUT8ADDR,      0x7FF0);
 724 SFRX(OUT9ADDR,      0x7FF1);
 725 SFRX(OUT10ADDR,     0x7FF2);
 726 SFRX(OUT11ADDR,     0x7FF3);
 727 SFRX(OUT12ADDR,     0x7FF4);
 728 SFRX(OUT13ADDR,     0x7FF5);
 729 SFRX(OUT14ADDR,     0x7FF6);
 730 SFRX(OUT15ADDR,     0x7FF7);
 731
 732 SFRX(IN8ADDR,       0x7FF8);
 733 SFRX(IN9ADDR,       0x7FF9);
 734 SFRX(IN10ADDR,      0x7FFA);
 735 SFRX(IN11ADDR,      0x7FFB);
 736 SFRX(IN12ADDR,      0x7FFC);
 737 SFRX(IN13ADDR,      0x7FFD);
 738 SFRX(IN14ADDR,      0x7FFE);
 739 SFRX(IN15ADDR,      0x7FFF);
 740
 741 #endif