found out why str912 reset halt failed.
[openocd.git] / src / jtag / bitbang.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "bitbang.h"
25
26 /* project specific includes */
27 #include "log.h"
28 #include "types.h"
29 #include "jtag.h"
30 #include "configuration.h"
31
32 /* system includes */
33 #include <string.h>
34 #include <stdlib.h>
35 #include <unistd.h>
36
37 bitbang_interface_t *bitbang_interface;
38
39
40 /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
41 *
42 * Set this to 1 and str912 reset halt will fail.
43 *
44 * If someone can submit a patch with an explanation it will be greatly
45 * appreciated, but as far as I can tell (ØH) DCLK is generated upon
46 * clk=0 in TAP_RTI. Good luck deducing that from the ARM documentation!
47 * The ARM documentation uses the term "DCLK is asserted while in the TAP_RTI
48 * state". With hardware there is no such thing as *while* in a state. There
49 * are only edges. So clk => 0 is in fact a very subtle state transition that
50 * happens *while* in the TAP_RTI state. "#&¤"#¤&"#&"#&
51 *
52 * For "reset halt" the last thing that happens before srst is asserted
53 * is that the breakpoint is set up. If DCLK is not wiggled one last
54 * time before the reset, then the breakpoint is not set up and
55 * "reset halt" will fail to halt.
56 *
57 */
58 #define CLOCK_IDLE() 0
59
60 int bitbang_execute_queue(void);
61
62 /* The bitbang driver leaves the TCK 0 when in idle */
63
64 void bitbang_end_state(enum tap_state state)
65 {
66 if (tap_move_map[state] != -1)
67 end_state = state;
68 else
69 {
70 LOG_ERROR("BUG: %i is not a valid end state", state);
71 exit(-1);
72 }
73 }
74
75 void bitbang_state_move(void) {
76
77 int i=0, tms=0;
78 u8 tms_scan = TAP_MOVE(cur_state, end_state);
79
80 for (i = 0; i < 7; i++)
81 {
82 tms = (tms_scan >> i) & 1;
83 bitbang_interface->write(0, tms, 0);
84 bitbang_interface->write(1, tms, 0);
85 }
86 bitbang_interface->write(CLOCK_IDLE(), tms, 0);
87
88 cur_state = end_state;
89 }
90
91 void bitbang_path_move(pathmove_command_t *cmd)
92 {
93 int num_states = cmd->num_states;
94 int state_count;
95 int tms = 0;
96
97 state_count = 0;
98 while (num_states)
99 {
100 if (tap_transitions[cur_state].low == cmd->path[state_count])
101 {
102 tms = 0;
103 }
104 else if (tap_transitions[cur_state].high == cmd->path[state_count])
105 {
106 tms = 1;
107 }
108 else
109 {
110 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition", tap_state_strings[cur_state], tap_state_strings[cmd->path[state_count]]);
111 exit(-1);
112 }
113
114 bitbang_interface->write(0, tms, 0);
115 bitbang_interface->write(1, tms, 0);
116
117 cur_state = cmd->path[state_count];
118 state_count++;
119 num_states--;
120 }
121
122 bitbang_interface->write(CLOCK_IDLE(), tms, 0);
123
124 end_state = cur_state;
125 }
126
127 void bitbang_runtest(int num_cycles)
128 {
129 int i;
130
131 enum tap_state saved_end_state = end_state;
132
133 /* only do a state_move when we're not already in RTI */
134 if (cur_state != TAP_RTI)
135 {
136 bitbang_end_state(TAP_RTI);
137 bitbang_state_move();
138 }
139
140 /* execute num_cycles */
141 for (i = 0; i < num_cycles; i++)
142 {
143 bitbang_interface->write(0, 0, 0);
144 bitbang_interface->write(1, 0, 0);
145 }
146 bitbang_interface->write(CLOCK_IDLE(), 0, 0);
147
148 /* finish in end_state */
149 bitbang_end_state(saved_end_state);
150 if (cur_state != end_state)
151 bitbang_state_move();
152 }
153
154 void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
155 {
156 enum tap_state saved_end_state = end_state;
157 int bit_cnt;
158
159 if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI))))
160 {
161 if (ir_scan)
162 bitbang_end_state(TAP_SI);
163 else
164 bitbang_end_state(TAP_SD);
165
166 bitbang_state_move();
167 bitbang_end_state(saved_end_state);
168 }
169
170 for (bit_cnt = 0; bit_cnt < scan_size; bit_cnt++)
171 {
172 /* if we're just reading the scan, but don't care about the output
173 * default to outputting 'low', this also makes valgrind traces more readable,
174 * as it removes the dependency on an uninitialised value
175 */
176 if ((type != SCAN_IN) && ((buffer[bit_cnt/8] >> (bit_cnt % 8)) & 0x1))
177 {
178 bitbang_interface->write(0, (bit_cnt==scan_size-1) ? 1 : 0, 1);
179 bitbang_interface->write(1, (bit_cnt==scan_size-1) ? 1 : 0, 1);
180 } else {
181 bitbang_interface->write(0, (bit_cnt==scan_size-1) ? 1 : 0, 0);
182 bitbang_interface->write(1, (bit_cnt==scan_size-1) ? 1 : 0, 0);
183 }
184
185 if (type != SCAN_OUT)
186 {
187 /*
188 TDO should be sampled on the rising edge, and will change
189 on the falling edge.
190
191 Because there is no way to read the signal exactly at the rising edge,
192 read after the rising edge.
193
194 This is plain IEEE 1149 JTAG - nothing specific to the OpenOCD or its JTAG
195 API.
196 */
197 if (bitbang_interface->read())
198 buffer[(bit_cnt)/8] |= 1 << ((bit_cnt) % 8);
199 else
200 buffer[(bit_cnt)/8] &= ~(1 << ((bit_cnt) % 8));
201 }
202 }
203
204 /* TAP_SD & TAP_SI are illegal end states, so we always transition to the pause
205 * state which is a legal stable state from which statemove will work.
206 *
207 * Exit1 -> Pause
208 */
209 bitbang_interface->write(0, 0, 0);
210 bitbang_interface->write(1, 0, 0);
211 bitbang_interface->write(CLOCK_IDLE(), 0, 0);
212
213 if (ir_scan)
214 cur_state = TAP_PI;
215 else
216 cur_state = TAP_PD;
217
218 if (cur_state != end_state)
219 bitbang_state_move();
220 }
221
222 int bitbang_execute_queue(void)
223 {
224 jtag_command_t *cmd = jtag_command_queue; /* currently processed command */
225 int scan_size;
226 enum scan_type type;
227 u8 *buffer;
228 int retval;
229
230 if (!bitbang_interface)
231 {
232 LOG_ERROR("BUG: Bitbang interface called, but not yet initialized");
233 exit(-1);
234 }
235
236 /* return ERROR_OK, unless a jtag_read_buffer returns a failed check
237 * that wasn't handled by a caller-provided error handler
238 */
239 retval = ERROR_OK;
240
241 if(bitbang_interface->blink)
242 bitbang_interface->blink(1);
243
244 while (cmd)
245 {
246 switch (cmd->type)
247 {
248 case JTAG_END_STATE:
249 #ifdef _DEBUG_JTAG_IO_
250 LOG_DEBUG("end_state: %i", cmd->cmd.end_state->end_state);
251 #endif
252 if (cmd->cmd.end_state->end_state != -1)
253 bitbang_end_state(cmd->cmd.end_state->end_state);
254 break;
255 case JTAG_RESET:
256 #ifdef _DEBUG_JTAG_IO_
257 LOG_DEBUG("reset trst: %i srst %i", cmd->cmd.reset->trst, cmd->cmd.reset->srst);
258 #endif
259 if ((cmd->cmd.reset->trst == 1) || (cmd->cmd.reset->srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
260 {
261 cur_state = TAP_TLR;
262 }
263 bitbang_interface->reset(cmd->cmd.reset->trst, cmd->cmd.reset->srst);
264 break;
265 case JTAG_RUNTEST:
266 #ifdef _DEBUG_JTAG_IO_
267 LOG_DEBUG("runtest %i cycles, end in %i", cmd->cmd.runtest->num_cycles, cmd->cmd.runtest->end_state);
268 #endif
269 if (cmd->cmd.runtest->end_state != -1)
270 bitbang_end_state(cmd->cmd.runtest->end_state);
271 bitbang_runtest(cmd->cmd.runtest->num_cycles);
272 break;
273 case JTAG_STATEMOVE:
274 #ifdef _DEBUG_JTAG_IO_
275 LOG_DEBUG("statemove end in %i", cmd->cmd.statemove->end_state);
276 #endif
277 if (cmd->cmd.statemove->end_state != -1)
278 bitbang_end_state(cmd->cmd.statemove->end_state);
279 bitbang_state_move();
280 break;
281 case JTAG_PATHMOVE:
282 #ifdef _DEBUG_JTAG_IO_
283 LOG_DEBUG("pathmove: %i states, end in %i", cmd->cmd.pathmove->num_states, cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]);
284 #endif
285 bitbang_path_move(cmd->cmd.pathmove);
286 break;
287 case JTAG_SCAN:
288 #ifdef _DEBUG_JTAG_IO_
289 LOG_DEBUG("%s scan end in %i", (cmd->cmd.scan->ir_scan) ? "IR" : "DR", cmd->cmd.scan->end_state);
290 #endif
291 if (cmd->cmd.scan->end_state != -1)
292 bitbang_end_state(cmd->cmd.scan->end_state);
293 scan_size = jtag_build_buffer(cmd->cmd.scan, &buffer);
294 type = jtag_scan_type(cmd->cmd.scan);
295 bitbang_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
296 if (jtag_read_buffer(buffer, cmd->cmd.scan) != ERROR_OK)
297 retval = ERROR_JTAG_QUEUE_FAILED;
298 if (buffer)
299 free(buffer);
300 break;
301 case JTAG_SLEEP:
302 #ifdef _DEBUG_JTAG_IO_
303 LOG_DEBUG("sleep %i", cmd->cmd.sleep->us);
304 #endif
305 jtag_sleep(cmd->cmd.sleep->us);
306 break;
307 default:
308 LOG_ERROR("BUG: unknown JTAG command type encountered");
309 exit(-1);
310 }
311 cmd = cmd->next;
312 }
313 if(bitbang_interface->blink)
314 bitbang_interface->blink(0);
315
316 return retval;
317 }
318

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)