1 /***************************************************************************
2 * Copyright (C) 2013 by Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
22 #include <helper/system.h>
23 #include <jtag/drivers/libusb_helper.h>
24 #include <helper/log.h>
25 #include <helper/time_support.h>
26 #include <target/target.h>
27 #include <jtag/jtag.h>
28 #include <target/nds32_insn.h>
29 #include <target/nds32_reg.h>
33 /* Global USB buffers */
34 static uint8_t usb_in_buffer
[AICE_IN_BUFFER_SIZE
];
35 static uint8_t usb_out_buffer
[AICE_OUT_BUFFER_SIZE
];
36 static uint32_t jtag_clock
;
37 static struct aice_usb_handler_s aice_handler
;
38 /* AICE max retry times. If AICE command timeout, retry it. */
39 static int aice_max_retry_times
= 50;
40 /* Default endian is little endian. */
41 static enum aice_target_endian data_endian
;
43 /* Constants for AICE command format length */
44 #define AICE_FORMAT_HTDA (3)
45 #define AICE_FORMAT_HTDC (7)
46 #define AICE_FORMAT_HTDMA (4)
47 #define AICE_FORMAT_HTDMB (8)
48 #define AICE_FORMAT_HTDMC (8)
49 #define AICE_FORMAT_HTDMD (12)
50 #define AICE_FORMAT_DTHA (6)
51 #define AICE_FORMAT_DTHB (2)
52 #define AICE_FORMAT_DTHMA (8)
53 #define AICE_FORMAT_DTHMB (4)
55 /* Constants for AICE command */
56 #define AICE_CMD_SCAN_CHAIN 0x00
57 #define AICE_CMD_T_READ_MISC 0x20
58 #define AICE_CMD_T_READ_EDMSR 0x21
59 #define AICE_CMD_T_READ_DTR 0x22
60 #define AICE_CMD_T_READ_MEM_B 0x24
61 #define AICE_CMD_T_READ_MEM_H 0x25
62 #define AICE_CMD_T_READ_MEM 0x26
63 #define AICE_CMD_T_FASTREAD_MEM 0x27
64 #define AICE_CMD_T_WRITE_MISC 0x28
65 #define AICE_CMD_T_WRITE_EDMSR 0x29
66 #define AICE_CMD_T_WRITE_DTR 0x2A
67 #define AICE_CMD_T_WRITE_DIM 0x2B
68 #define AICE_CMD_T_WRITE_MEM_B 0x2C
69 #define AICE_CMD_T_WRITE_MEM_H 0x2D
70 #define AICE_CMD_T_WRITE_MEM 0x2E
71 #define AICE_CMD_T_FASTWRITE_MEM 0x2F
72 #define AICE_CMD_T_EXECUTE 0x3E
73 #define AICE_CMD_READ_CTRL 0x50
74 #define AICE_CMD_WRITE_CTRL 0x51
75 #define AICE_CMD_BATCH_BUFFER_READ 0x60
76 #define AICE_CMD_READ_DTR_TO_BUFFER 0x61
77 #define AICE_CMD_BATCH_BUFFER_WRITE 0x68
78 #define AICE_CMD_WRITE_DTR_FROM_BUFFER 0x69
80 /***************************************************************************/
81 /* AICE commands' pack/unpack functions */
82 static void aice_pack_htda(uint8_t cmd_code
, uint8_t extra_word_length
,
85 usb_out_buffer
[0] = cmd_code
;
86 usb_out_buffer
[1] = extra_word_length
;
87 usb_out_buffer
[2] = (uint8_t)(address
& 0xFF);
90 static void aice_pack_htdc(uint8_t cmd_code
, uint8_t extra_word_length
,
91 uint32_t address
, uint32_t word
, enum aice_target_endian access_endian
)
93 usb_out_buffer
[0] = cmd_code
;
94 usb_out_buffer
[1] = extra_word_length
;
95 usb_out_buffer
[2] = (uint8_t)(address
& 0xFF);
96 if (access_endian
== AICE_BIG_ENDIAN
) {
97 usb_out_buffer
[6] = (uint8_t)((word
>> 24) & 0xFF);
98 usb_out_buffer
[5] = (uint8_t)((word
>> 16) & 0xFF);
99 usb_out_buffer
[4] = (uint8_t)((word
>> 8) & 0xFF);
100 usb_out_buffer
[3] = (uint8_t)(word
& 0xFF);
102 usb_out_buffer
[3] = (uint8_t)((word
>> 24) & 0xFF);
103 usb_out_buffer
[4] = (uint8_t)((word
>> 16) & 0xFF);
104 usb_out_buffer
[5] = (uint8_t)((word
>> 8) & 0xFF);
105 usb_out_buffer
[6] = (uint8_t)(word
& 0xFF);
109 static void aice_pack_htdma(uint8_t cmd_code
, uint8_t target_id
,
110 uint8_t extra_word_length
, uint32_t address
)
112 usb_out_buffer
[0] = cmd_code
;
113 usb_out_buffer
[1] = target_id
;
114 usb_out_buffer
[2] = extra_word_length
;
115 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
118 static void aice_pack_htdmb(uint8_t cmd_code
, uint8_t target_id
,
119 uint8_t extra_word_length
, uint32_t address
)
121 usb_out_buffer
[0] = cmd_code
;
122 usb_out_buffer
[1] = target_id
;
123 usb_out_buffer
[2] = extra_word_length
;
124 usb_out_buffer
[3] = 0;
125 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
126 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
127 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
128 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
131 static void aice_pack_htdmc(uint8_t cmd_code
, uint8_t target_id
,
132 uint8_t extra_word_length
, uint32_t address
, uint32_t word
,
133 enum aice_target_endian access_endian
)
135 usb_out_buffer
[0] = cmd_code
;
136 usb_out_buffer
[1] = target_id
;
137 usb_out_buffer
[2] = extra_word_length
;
138 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
139 if (access_endian
== AICE_BIG_ENDIAN
) {
140 usb_out_buffer
[7] = (uint8_t)((word
>> 24) & 0xFF);
141 usb_out_buffer
[6] = (uint8_t)((word
>> 16) & 0xFF);
142 usb_out_buffer
[5] = (uint8_t)((word
>> 8) & 0xFF);
143 usb_out_buffer
[4] = (uint8_t)(word
& 0xFF);
145 usb_out_buffer
[4] = (uint8_t)((word
>> 24) & 0xFF);
146 usb_out_buffer
[5] = (uint8_t)((word
>> 16) & 0xFF);
147 usb_out_buffer
[6] = (uint8_t)((word
>> 8) & 0xFF);
148 usb_out_buffer
[7] = (uint8_t)(word
& 0xFF);
152 static void aice_pack_htdmc_multiple_data(uint8_t cmd_code
, uint8_t target_id
,
153 uint8_t extra_word_length
, uint32_t address
, uint32_t *word
,
154 uint8_t num_of_words
, enum aice_target_endian access_endian
)
156 usb_out_buffer
[0] = cmd_code
;
157 usb_out_buffer
[1] = target_id
;
158 usb_out_buffer
[2] = extra_word_length
;
159 usb_out_buffer
[3] = (uint8_t)(address
& 0xFF);
162 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
163 if (access_endian
== AICE_BIG_ENDIAN
) {
164 usb_out_buffer
[7 + i
* 4] = (uint8_t)((*word
>> 24) & 0xFF);
165 usb_out_buffer
[6 + i
* 4] = (uint8_t)((*word
>> 16) & 0xFF);
166 usb_out_buffer
[5 + i
* 4] = (uint8_t)((*word
>> 8) & 0xFF);
167 usb_out_buffer
[4 + i
* 4] = (uint8_t)(*word
& 0xFF);
169 usb_out_buffer
[4 + i
* 4] = (uint8_t)((*word
>> 24) & 0xFF);
170 usb_out_buffer
[5 + i
* 4] = (uint8_t)((*word
>> 16) & 0xFF);
171 usb_out_buffer
[6 + i
* 4] = (uint8_t)((*word
>> 8) & 0xFF);
172 usb_out_buffer
[7 + i
* 4] = (uint8_t)(*word
& 0xFF);
177 static void aice_pack_htdmd(uint8_t cmd_code
, uint8_t target_id
,
178 uint8_t extra_word_length
, uint32_t address
, uint32_t word
,
179 enum aice_target_endian access_endian
)
181 usb_out_buffer
[0] = cmd_code
;
182 usb_out_buffer
[1] = target_id
;
183 usb_out_buffer
[2] = extra_word_length
;
184 usb_out_buffer
[3] = 0;
185 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
186 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
187 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
188 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
189 if (access_endian
== AICE_BIG_ENDIAN
) {
190 usb_out_buffer
[11] = (uint8_t)((word
>> 24) & 0xFF);
191 usb_out_buffer
[10] = (uint8_t)((word
>> 16) & 0xFF);
192 usb_out_buffer
[9] = (uint8_t)((word
>> 8) & 0xFF);
193 usb_out_buffer
[8] = (uint8_t)(word
& 0xFF);
195 usb_out_buffer
[8] = (uint8_t)((word
>> 24) & 0xFF);
196 usb_out_buffer
[9] = (uint8_t)((word
>> 16) & 0xFF);
197 usb_out_buffer
[10] = (uint8_t)((word
>> 8) & 0xFF);
198 usb_out_buffer
[11] = (uint8_t)(word
& 0xFF);
202 static void aice_pack_htdmd_multiple_data(uint8_t cmd_code
, uint8_t target_id
,
203 uint8_t extra_word_length
, uint32_t address
, const uint8_t *word
,
204 enum aice_target_endian access_endian
)
206 usb_out_buffer
[0] = cmd_code
;
207 usb_out_buffer
[1] = target_id
;
208 usb_out_buffer
[2] = extra_word_length
;
209 usb_out_buffer
[3] = 0;
210 usb_out_buffer
[4] = (uint8_t)((address
>> 24) & 0xFF);
211 usb_out_buffer
[5] = (uint8_t)((address
>> 16) & 0xFF);
212 usb_out_buffer
[6] = (uint8_t)((address
>> 8) & 0xFF);
213 usb_out_buffer
[7] = (uint8_t)(address
& 0xFF);
216 /* num_of_words may be over 0xFF, so use uint32_t */
217 uint32_t num_of_words
= extra_word_length
+ 1;
219 for (i
= 0 ; i
< num_of_words
; i
++, word
+= 4) {
220 if (access_endian
== AICE_BIG_ENDIAN
) {
221 usb_out_buffer
[11 + i
* 4] = word
[3];
222 usb_out_buffer
[10 + i
* 4] = word
[2];
223 usb_out_buffer
[9 + i
* 4] = word
[1];
224 usb_out_buffer
[8 + i
* 4] = word
[0];
226 usb_out_buffer
[8 + i
* 4] = word
[3];
227 usb_out_buffer
[9 + i
* 4] = word
[2];
228 usb_out_buffer
[10 + i
* 4] = word
[1];
229 usb_out_buffer
[11 + i
* 4] = word
[0];
234 static void aice_unpack_dtha(uint8_t *cmd_ack_code
, uint8_t *extra_word_length
,
235 uint32_t *word
, enum aice_target_endian access_endian
)
237 *cmd_ack_code
= usb_in_buffer
[0];
238 *extra_word_length
= usb_in_buffer
[1];
240 if (access_endian
== AICE_BIG_ENDIAN
) {
241 *word
= (usb_in_buffer
[5] << 24) |
242 (usb_in_buffer
[4] << 16) |
243 (usb_in_buffer
[3] << 8) |
246 *word
= (usb_in_buffer
[2] << 24) |
247 (usb_in_buffer
[3] << 16) |
248 (usb_in_buffer
[4] << 8) |
253 static void aice_unpack_dtha_multiple_data(uint8_t *cmd_ack_code
,
254 uint8_t *extra_word_length
, uint32_t *word
, uint8_t num_of_words
,
255 enum aice_target_endian access_endian
)
257 *cmd_ack_code
= usb_in_buffer
[0];
258 *extra_word_length
= usb_in_buffer
[1];
261 for (i
= 0 ; i
< num_of_words
; i
++, word
++) {
262 if (access_endian
== AICE_BIG_ENDIAN
) {
263 *word
= (usb_in_buffer
[5 + i
* 4] << 24) |
264 (usb_in_buffer
[4 + i
* 4] << 16) |
265 (usb_in_buffer
[3 + i
* 4] << 8) |
266 (usb_in_buffer
[2 + i
* 4]);
268 *word
= (usb_in_buffer
[2 + i
* 4] << 24) |
269 (usb_in_buffer
[3 + i
* 4] << 16) |
270 (usb_in_buffer
[4 + i
* 4] << 8) |
271 (usb_in_buffer
[5 + i
* 4]);
276 static void aice_unpack_dthb(uint8_t *cmd_ack_code
, uint8_t *extra_word_length
)
278 *cmd_ack_code
= usb_in_buffer
[0];
279 *extra_word_length
= usb_in_buffer
[1];
282 static void aice_unpack_dthma(uint8_t *cmd_ack_code
, uint8_t *target_id
,
283 uint8_t *extra_word_length
, uint32_t *word
,
284 enum aice_target_endian access_endian
)
286 *cmd_ack_code
= usb_in_buffer
[0];
287 *target_id
= usb_in_buffer
[1];
288 *extra_word_length
= usb_in_buffer
[2];
289 if (access_endian
== AICE_BIG_ENDIAN
) {
290 *word
= (usb_in_buffer
[7] << 24) |
291 (usb_in_buffer
[6] << 16) |
292 (usb_in_buffer
[5] << 8) |
295 *word
= (usb_in_buffer
[4] << 24) |
296 (usb_in_buffer
[5] << 16) |
297 (usb_in_buffer
[6] << 8) |
302 static void aice_unpack_dthma_multiple_data(uint8_t *cmd_ack_code
,
303 uint8_t *target_id
, uint8_t *extra_word_length
, uint8_t *word
,
304 enum aice_target_endian access_endian
)
306 *cmd_ack_code
= usb_in_buffer
[0];
307 *target_id
= usb_in_buffer
[1];
308 *extra_word_length
= usb_in_buffer
[2];
309 if (access_endian
== AICE_BIG_ENDIAN
) {
310 word
[0] = usb_in_buffer
[4];
311 word
[1] = usb_in_buffer
[5];
312 word
[2] = usb_in_buffer
[6];
313 word
[3] = usb_in_buffer
[7];
315 word
[0] = usb_in_buffer
[7];
316 word
[1] = usb_in_buffer
[6];
317 word
[2] = usb_in_buffer
[5];
318 word
[3] = usb_in_buffer
[4];
323 for (i
= 0; i
< *extra_word_length
; i
++) {
324 if (access_endian
== AICE_BIG_ENDIAN
) {
325 word
[0] = usb_in_buffer
[8 + i
* 4];
326 word
[1] = usb_in_buffer
[9 + i
* 4];
327 word
[2] = usb_in_buffer
[10 + i
* 4];
328 word
[3] = usb_in_buffer
[11 + i
* 4];
330 word
[0] = usb_in_buffer
[11 + i
* 4];
331 word
[1] = usb_in_buffer
[10 + i
* 4];
332 word
[2] = usb_in_buffer
[9 + i
* 4];
333 word
[3] = usb_in_buffer
[8 + i
* 4];
339 static void aice_unpack_dthmb(uint8_t *cmd_ack_code
, uint8_t *target_id
,
340 uint8_t *extra_word_length
)
342 *cmd_ack_code
= usb_in_buffer
[0];
343 *target_id
= usb_in_buffer
[1];
344 *extra_word_length
= usb_in_buffer
[2];
347 /***************************************************************************/
348 /* End of AICE commands' pack/unpack functions */
350 /* calls the given usb_bulk_* function, allowing for the data to
351 * trickle in with some timeouts */
352 static int usb_bulk_with_retries(
353 int (*f
)(struct libusb_device_handle
*, int, char *, int, int, int *),
354 struct libusb_device_handle
*dev
, int ep
,
355 char *bytes
, int size
, int timeout
, int *transferred
)
357 int tries
= 3, count
= 0;
359 while (tries
&& (count
< size
)) {
362 ret
= f(dev
, ep
, bytes
+ count
, size
- count
, timeout
, &result
);
365 else if ((ret
!= ERROR_TIMEOUT_REACHED
) || !--tries
)
369 *transferred
= count
;
373 static int wrap_usb_bulk_write(struct libusb_device_handle
*dev
, int ep
,
374 char *buff
, int size
, int timeout
, int *transferred
)
377 /* usb_bulk_write() takes const char *buff */
378 jtag_libusb_bulk_write(dev
, ep
, buff
, size
, timeout
, transferred
);
383 static inline int usb_bulk_write_ex(struct libusb_device_handle
*dev
, int ep
,
384 char *bytes
, int size
, int timeout
)
388 usb_bulk_with_retries(&wrap_usb_bulk_write
,
389 dev
, ep
, bytes
, size
, timeout
, &tr
);
393 static inline int usb_bulk_read_ex(struct libusb_device_handle
*dev
, int ep
,
394 char *bytes
, int size
, int timeout
)
397 usb_bulk_with_retries(&jtag_libusb_bulk_read
,
398 dev
, ep
, bytes
, size
, timeout
, &tr
);
402 /* Write data from out_buffer to USB. */
403 static int aice_usb_write(uint8_t *out_buffer
, int out_length
)
407 if (out_length
> AICE_OUT_BUFFER_SIZE
) {
408 LOG_ERROR("aice_write illegal out_length=%i (max=%i)",
409 out_length
, AICE_OUT_BUFFER_SIZE
);
413 result
= usb_bulk_write_ex(aice_handler
.usb_handle
, aice_handler
.usb_write_ep
,
414 (char *)out_buffer
, out_length
, AICE_USB_TIMEOUT
);
416 LOG_DEBUG_IO("aice_usb_write, out_length = %i, result = %i",
422 /* Read data from USB into in_buffer. */
423 static int aice_usb_read(uint8_t *in_buffer
, int expected_size
)
425 int result
= usb_bulk_read_ex(aice_handler
.usb_handle
, aice_handler
.usb_read_ep
,
426 (char *)in_buffer
, expected_size
, AICE_USB_TIMEOUT
);
428 LOG_DEBUG_IO("aice_usb_read, result = %d", result
);
433 static uint8_t usb_out_packets_buffer
[AICE_OUT_PACKETS_BUFFER_SIZE
];
434 static uint8_t usb_in_packets_buffer
[AICE_IN_PACKETS_BUFFER_SIZE
];
435 static uint32_t usb_out_packets_buffer_length
;
436 static uint32_t usb_in_packets_buffer_length
;
437 static enum aice_command_mode aice_command_mode
;
439 static int aice_batch_buffer_write(uint8_t buf_index
, const uint8_t *word
,
440 uint32_t num_of_words
);
442 static int aice_usb_packet_flush(void)
444 if (usb_out_packets_buffer_length
== 0)
447 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
448 LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_PACK)");
450 if (aice_usb_write(usb_out_packets_buffer
,
451 usb_out_packets_buffer_length
) < 0)
454 if (aice_usb_read(usb_in_packets_buffer
,
455 usb_in_packets_buffer_length
) < 0)
458 usb_out_packets_buffer_length
= 0;
459 usb_in_packets_buffer_length
= 0;
461 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
462 LOG_DEBUG("Flush usb packets (AICE_COMMAND_MODE_BATCH)");
464 /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
465 if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0
,
466 usb_out_packets_buffer
,
467 (usb_out_packets_buffer_length
+ 3) / 4) != ERROR_OK
)
470 usb_out_packets_buffer_length
= 0;
471 usb_in_packets_buffer_length
= 0;
473 /* enable BATCH command */
474 aice_command_mode
= AICE_COMMAND_MODE_NORMAL
;
475 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL
, 0x80000000) != ERROR_OK
)
477 aice_command_mode
= AICE_COMMAND_MODE_BATCH
;
479 /* wait 1 second (AICE bug, workaround) */
484 uint32_t batch_status
;
488 int retval
= aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS
, &batch_status
);
489 if (retval
!= ERROR_OK
)
492 if (batch_status
& 0x1)
494 else if (batch_status
& 0xE)
507 static int aice_usb_packet_append(uint8_t *out_buffer
, int out_length
, int in_length
)
509 uint32_t max_packet_size
= AICE_OUT_PACKETS_BUFFER_SIZE
;
511 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
512 max_packet_size
= AICE_OUT_PACK_COMMAND_SIZE
;
513 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
514 max_packet_size
= AICE_OUT_BATCH_COMMAND_SIZE
;
516 /* AICE_COMMAND_MODE_NORMAL */
517 if (aice_usb_packet_flush() != ERROR_OK
)
521 if (usb_out_packets_buffer_length
+ out_length
> max_packet_size
)
522 if (aice_usb_packet_flush() != ERROR_OK
) {
523 LOG_DEBUG("Flush usb packets failed");
527 LOG_DEBUG("Append usb packets 0x%02x", out_buffer
[0]);
529 memcpy(usb_out_packets_buffer
+ usb_out_packets_buffer_length
, out_buffer
, out_length
);
530 usb_out_packets_buffer_length
+= out_length
;
531 usb_in_packets_buffer_length
+= in_length
;
536 /***************************************************************************/
538 static int aice_reset_box(void)
540 if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS
, 0x1) != ERROR_OK
)
543 /* turn off FASTMODE */
545 if (aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS
, &pin_status
)
549 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
& (~0x2))
556 static int aice_scan_chain(uint32_t *id_codes
, uint8_t *num_of_ids
)
560 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
561 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
))
562 aice_usb_packet_flush();
565 aice_pack_htda(AICE_CMD_SCAN_CHAIN
, 0x0F, 0x0);
567 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDA
);
569 LOG_DEBUG("SCAN_CHAIN, length: 0x0F");
571 /** TODO: modify receive length */
572 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHA
);
573 if (result
!= AICE_FORMAT_DTHA
) {
574 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
575 AICE_FORMAT_DTHA
, result
);
579 uint8_t cmd_ack_code
;
580 aice_unpack_dtha_multiple_data(&cmd_ack_code
, num_of_ids
, id_codes
,
581 0x10, AICE_LITTLE_ENDIAN
);
583 if (cmd_ack_code
!= AICE_CMD_SCAN_CHAIN
) {
585 if (retry_times
> aice_max_retry_times
) {
586 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
587 AICE_CMD_SCAN_CHAIN
, cmd_ack_code
);
591 /* clear timeout and retry */
592 if (aice_reset_box() != ERROR_OK
)
599 LOG_DEBUG("SCAN_CHAIN response, # of IDs: %" PRIu8
, *num_of_ids
);
601 if (*num_of_ids
== 0xFF) {
602 LOG_ERROR("No target connected");
604 } else if (*num_of_ids
== AICE_MAX_NUM_CORE
) {
605 LOG_INFO("The ice chain over 16 targets");
615 int aice_read_ctrl(uint32_t address
, uint32_t *data
)
617 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
618 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
))
619 aice_usb_packet_flush();
621 aice_pack_htda(AICE_CMD_READ_CTRL
, 0, address
);
623 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDA
);
625 LOG_DEBUG("READ_CTRL, address: 0x%" PRIx32
, address
);
627 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHA
);
628 if (result
!= AICE_FORMAT_DTHA
) {
629 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
630 AICE_FORMAT_DTHA
, result
);
634 uint8_t cmd_ack_code
;
635 uint8_t extra_length
;
636 aice_unpack_dtha(&cmd_ack_code
, &extra_length
, data
, AICE_LITTLE_ENDIAN
);
638 LOG_DEBUG("READ_CTRL response, data: 0x%" PRIx32
, *data
);
640 if (cmd_ack_code
!= AICE_CMD_READ_CTRL
) {
641 LOG_ERROR("aice command error (command=0x%" PRIx32
", response=0x%" PRIx8
")",
642 (uint32_t)AICE_CMD_READ_CTRL
, cmd_ack_code
);
649 int aice_write_ctrl(uint32_t address
, uint32_t data
)
651 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
652 aice_usb_packet_flush();
653 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
654 aice_pack_htdc(AICE_CMD_WRITE_CTRL
, 0, address
, data
, AICE_LITTLE_ENDIAN
);
655 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDC
,
659 aice_pack_htdc(AICE_CMD_WRITE_CTRL
, 0, address
, data
, AICE_LITTLE_ENDIAN
);
661 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDC
);
663 LOG_DEBUG("WRITE_CTRL, address: 0x%" PRIx32
", data: 0x%" PRIx32
, address
, data
);
665 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHB
);
666 if (result
!= AICE_FORMAT_DTHB
) {
667 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
668 AICE_FORMAT_DTHB
, result
);
672 uint8_t cmd_ack_code
;
673 uint8_t extra_length
;
674 aice_unpack_dthb(&cmd_ack_code
, &extra_length
);
676 LOG_DEBUG("WRITE_CTRL response");
678 if (cmd_ack_code
!= AICE_CMD_WRITE_CTRL
) {
679 LOG_ERROR("aice command error (command=0x%" PRIx8
", response=0x%" PRIx8
")",
680 AICE_CMD_WRITE_CTRL
, cmd_ack_code
);
687 static int aice_read_dtr(uint8_t target_id
, uint32_t *data
)
691 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
692 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
))
693 aice_usb_packet_flush();
696 aice_pack_htdma(AICE_CMD_T_READ_DTR
, target_id
, 0, 0);
698 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
700 LOG_DEBUG("READ_DTR, COREID: %" PRIu8
, target_id
);
702 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
703 if (result
!= AICE_FORMAT_DTHMA
) {
704 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
705 AICE_FORMAT_DTHMA
, result
);
709 uint8_t cmd_ack_code
;
710 uint8_t extra_length
;
711 uint8_t res_target_id
;
712 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
713 data
, AICE_LITTLE_ENDIAN
);
715 if (cmd_ack_code
== AICE_CMD_T_READ_DTR
) {
716 LOG_DEBUG("READ_DTR response, data: 0x%" PRIx32
, *data
);
720 if (retry_times
> aice_max_retry_times
) {
721 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
722 AICE_CMD_T_READ_DTR
, cmd_ack_code
);
726 /* clear timeout and retry */
727 if (aice_reset_box() != ERROR_OK
)
737 static int aice_read_dtr_to_buffer(uint8_t target_id
, uint32_t buffer_idx
)
741 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
742 aice_usb_packet_flush();
743 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
744 aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER
, target_id
, 0, buffer_idx
);
745 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMA
,
750 aice_pack_htdma(AICE_CMD_READ_DTR_TO_BUFFER
, target_id
, 0, buffer_idx
);
752 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
754 LOG_DEBUG("READ_DTR_TO_BUFFER, COREID: %" PRIu8
, target_id
);
756 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
757 if (result
!= AICE_FORMAT_DTHMB
) {
758 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB
, result
);
762 uint8_t cmd_ack_code
;
763 uint8_t extra_length
;
764 uint8_t res_target_id
;
765 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
767 if (cmd_ack_code
== AICE_CMD_READ_DTR_TO_BUFFER
) {
770 if (retry_times
> aice_max_retry_times
) {
771 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
772 AICE_CMD_READ_DTR_TO_BUFFER
, cmd_ack_code
);
777 /* clear timeout and retry */
778 if (aice_reset_box() != ERROR_OK
)
788 static int aice_write_dtr(uint8_t target_id
, uint32_t data
)
792 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
793 aice_usb_packet_flush();
794 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
795 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR
, target_id
, 0, 0, data
, AICE_LITTLE_ENDIAN
);
796 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMC
,
801 aice_pack_htdmc(AICE_CMD_T_WRITE_DTR
, target_id
, 0, 0, data
, AICE_LITTLE_ENDIAN
);
803 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
805 LOG_DEBUG("WRITE_DTR, COREID: %" PRIu8
", data: 0x%" PRIx32
, target_id
, data
);
807 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
808 if (result
!= AICE_FORMAT_DTHMB
) {
809 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB
, result
);
813 uint8_t cmd_ack_code
;
814 uint8_t extra_length
;
815 uint8_t res_target_id
;
816 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
818 if (cmd_ack_code
== AICE_CMD_T_WRITE_DTR
) {
819 LOG_DEBUG("WRITE_DTR response");
822 if (retry_times
> aice_max_retry_times
) {
823 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
824 AICE_CMD_T_WRITE_DTR
, cmd_ack_code
);
829 /* clear timeout and retry */
830 if (aice_reset_box() != ERROR_OK
)
840 static int aice_write_dtr_from_buffer(uint8_t target_id
, uint32_t buffer_idx
)
844 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
845 aice_usb_packet_flush();
846 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
847 aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER
, target_id
, 0, buffer_idx
);
848 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMA
,
853 aice_pack_htdma(AICE_CMD_WRITE_DTR_FROM_BUFFER
, target_id
, 0, buffer_idx
);
855 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
857 LOG_DEBUG("WRITE_DTR_FROM_BUFFER, COREID: %" PRIu8
"", target_id
);
859 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
860 if (result
!= AICE_FORMAT_DTHMB
) {
861 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB
, result
);
865 uint8_t cmd_ack_code
;
866 uint8_t extra_length
;
867 uint8_t res_target_id
;
868 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
870 if (cmd_ack_code
== AICE_CMD_WRITE_DTR_FROM_BUFFER
) {
873 if (retry_times
> aice_max_retry_times
) {
874 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
875 AICE_CMD_WRITE_DTR_FROM_BUFFER
, cmd_ack_code
);
880 /* clear timeout and retry */
881 if (aice_reset_box() != ERROR_OK
)
891 static int aice_read_misc(uint8_t target_id
, uint32_t address
, uint32_t *data
)
895 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
896 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
))
897 aice_usb_packet_flush();
900 aice_pack_htdma(AICE_CMD_T_READ_MISC
, target_id
, 0, address
);
902 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
904 LOG_DEBUG("READ_MISC, COREID: %" PRIu8
", address: 0x%" PRIx32
, target_id
, address
);
906 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
907 if (result
!= AICE_FORMAT_DTHMA
) {
908 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
909 AICE_FORMAT_DTHMA
, result
);
910 return ERROR_AICE_DISCONNECT
;
913 uint8_t cmd_ack_code
;
914 uint8_t extra_length
;
915 uint8_t res_target_id
;
916 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
917 data
, AICE_LITTLE_ENDIAN
);
919 if (cmd_ack_code
== AICE_CMD_T_READ_MISC
) {
920 LOG_DEBUG("READ_MISC response, data: 0x%" PRIx32
, *data
);
923 if (retry_times
> aice_max_retry_times
) {
924 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
925 AICE_CMD_T_READ_MISC
, cmd_ack_code
);
929 /* clear timeout and retry */
930 if (aice_reset_box() != ERROR_OK
)
940 static int aice_write_misc(uint8_t target_id
, uint32_t address
, uint32_t data
)
944 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
945 aice_usb_packet_flush();
946 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
947 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC
, target_id
, 0, address
, data
,
949 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMC
,
954 aice_pack_htdmc(AICE_CMD_T_WRITE_MISC
, target_id
, 0, address
,
955 data
, AICE_LITTLE_ENDIAN
);
957 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
959 LOG_DEBUG("WRITE_MISC, COREID: %" PRIu8
", address: 0x%" PRIx32
", data: 0x%" PRIx32
,
960 target_id
, address
, data
);
962 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
963 if (result
!= AICE_FORMAT_DTHMB
) {
964 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
965 AICE_FORMAT_DTHMB
, result
);
969 uint8_t cmd_ack_code
;
970 uint8_t extra_length
;
971 uint8_t res_target_id
;
972 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
974 if (cmd_ack_code
== AICE_CMD_T_WRITE_MISC
) {
975 LOG_DEBUG("WRITE_MISC response");
978 if (retry_times
> aice_max_retry_times
) {
979 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
980 AICE_CMD_T_WRITE_MISC
, cmd_ack_code
);
985 /* clear timeout and retry */
986 if (aice_reset_box() != ERROR_OK
)
996 static int aice_read_edmsr(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1000 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
1001 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
))
1002 aice_usb_packet_flush();
1005 aice_pack_htdma(AICE_CMD_T_READ_EDMSR
, target_id
, 0, address
);
1007 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
1009 LOG_DEBUG("READ_EDMSR, COREID: %" PRIu8
", address: 0x%" PRIx32
, target_id
, address
);
1011 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1012 if (result
!= AICE_FORMAT_DTHMA
) {
1013 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1014 AICE_FORMAT_DTHMA
, result
);
1018 uint8_t cmd_ack_code
;
1019 uint8_t extra_length
;
1020 uint8_t res_target_id
;
1021 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1022 data
, AICE_LITTLE_ENDIAN
);
1024 if (cmd_ack_code
== AICE_CMD_T_READ_EDMSR
) {
1025 LOG_DEBUG("READ_EDMSR response, data: 0x%" PRIx32
, *data
);
1028 if (retry_times
> aice_max_retry_times
) {
1029 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1030 AICE_CMD_T_READ_EDMSR
, cmd_ack_code
);
1035 /* clear timeout and retry */
1036 if (aice_reset_box() != ERROR_OK
)
1046 static int aice_write_edmsr(uint8_t target_id
, uint32_t address
, uint32_t data
)
1048 int retry_times
= 0;
1050 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
1051 aice_usb_packet_flush();
1052 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
1053 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR
, target_id
, 0, address
, data
,
1054 AICE_LITTLE_ENDIAN
);
1055 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMC
,
1060 aice_pack_htdmc(AICE_CMD_T_WRITE_EDMSR
, target_id
, 0, address
,
1061 data
, AICE_LITTLE_ENDIAN
);
1063 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
1065 LOG_DEBUG("WRITE_EDMSR, COREID: %" PRIu8
", address: 0x%" PRIx32
", data: 0x%" PRIx32
,
1066 target_id
, address
, data
);
1068 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1069 if (result
!= AICE_FORMAT_DTHMB
) {
1070 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1071 AICE_FORMAT_DTHMB
, result
);
1075 uint8_t cmd_ack_code
;
1076 uint8_t extra_length
;
1077 uint8_t res_target_id
;
1078 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1080 if (cmd_ack_code
== AICE_CMD_T_WRITE_EDMSR
) {
1081 LOG_DEBUG("WRITE_EDMSR response");
1084 if (retry_times
> aice_max_retry_times
) {
1085 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1086 AICE_CMD_T_WRITE_EDMSR
, cmd_ack_code
);
1091 /* clear timeout and retry */
1092 if (aice_reset_box() != ERROR_OK
)
1102 static int aice_switch_to_big_endian(uint32_t *word
, uint8_t num_of_words
)
1106 for (uint8_t i
= 0 ; i
< num_of_words
; i
++) {
1107 tmp
= ((word
[i
] >> 24) & 0x000000FF) |
1108 ((word
[i
] >> 8) & 0x0000FF00) |
1109 ((word
[i
] << 8) & 0x00FF0000) |
1110 ((word
[i
] << 24) & 0xFF000000);
1117 static int aice_write_dim(uint8_t target_id
, uint32_t *word
, uint8_t num_of_words
)
1119 uint32_t big_endian_word
[4];
1120 int retry_times
= 0;
1122 /** instruction is big-endian */
1123 memcpy(big_endian_word
, word
, sizeof(big_endian_word
));
1124 aice_switch_to_big_endian(big_endian_word
, num_of_words
);
1126 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
1127 aice_usb_packet_flush();
1128 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
1129 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM
, target_id
,
1130 num_of_words
- 1, 0, big_endian_word
, num_of_words
,
1131 AICE_LITTLE_ENDIAN
);
1132 return aice_usb_packet_append(usb_out_buffer
,
1133 AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4,
1138 aice_pack_htdmc_multiple_data(AICE_CMD_T_WRITE_DIM
, target_id
, num_of_words
- 1, 0,
1139 big_endian_word
, num_of_words
, AICE_LITTLE_ENDIAN
);
1141 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4);
1143 LOG_DEBUG("WRITE_DIM, COREID: %" PRIu8
1144 ", data: 0x%08" PRIx32
", 0x%08" PRIx32
", 0x%08" PRIx32
", 0x%08" PRIx32
,
1149 big_endian_word
[3]);
1151 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1152 if (result
!= AICE_FORMAT_DTHMB
) {
1153 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB
, result
);
1157 uint8_t cmd_ack_code
;
1158 uint8_t extra_length
;
1159 uint8_t res_target_id
;
1160 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1163 if (cmd_ack_code
== AICE_CMD_T_WRITE_DIM
) {
1164 LOG_DEBUG("WRITE_DIM response");
1167 if (retry_times
> aice_max_retry_times
) {
1168 LOG_ERROR("aice command timeout (command=0x%" PRIx8
1169 ", response=0x%" PRIx8
")",
1170 AICE_CMD_T_WRITE_DIM
, cmd_ack_code
);
1175 /* clear timeout and retry */
1176 if (aice_reset_box() != ERROR_OK
)
1186 static int aice_do_execute(uint8_t target_id
)
1188 int retry_times
= 0;
1190 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
1191 aice_usb_packet_flush();
1192 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
1193 aice_pack_htdmc(AICE_CMD_T_EXECUTE
, target_id
, 0, 0, 0, AICE_LITTLE_ENDIAN
);
1194 return aice_usb_packet_append(usb_out_buffer
,
1200 aice_pack_htdmc(AICE_CMD_T_EXECUTE
, target_id
, 0, 0, 0, AICE_LITTLE_ENDIAN
);
1202 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
);
1204 LOG_DEBUG("EXECUTE, COREID: %" PRIu8
"", target_id
);
1206 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1207 if (result
!= AICE_FORMAT_DTHMB
) {
1208 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1209 AICE_FORMAT_DTHMB
, result
);
1213 uint8_t cmd_ack_code
;
1214 uint8_t extra_length
;
1215 uint8_t res_target_id
;
1216 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1218 if (cmd_ack_code
== AICE_CMD_T_EXECUTE
) {
1219 LOG_DEBUG("EXECUTE response");
1222 if (retry_times
> aice_max_retry_times
) {
1223 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1224 AICE_CMD_T_EXECUTE
, cmd_ack_code
);
1229 /* clear timeout and retry */
1230 if (aice_reset_box() != ERROR_OK
)
1240 static int aice_write_mem_b(uint8_t target_id
, uint32_t address
, uint32_t data
)
1242 int retry_times
= 0;
1244 LOG_DEBUG("WRITE_MEM_B, COREID: %" PRIu8
", ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1249 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
1250 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
)) {
1251 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B
, target_id
, 0, address
,
1252 data
& 0x000000FF, data_endian
);
1253 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
,
1257 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_B
, target_id
, 0,
1258 address
, data
& 0x000000FF, data_endian
);
1259 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1261 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1262 if (result
!= AICE_FORMAT_DTHMB
) {
1263 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)", AICE_FORMAT_DTHMB
, result
);
1267 uint8_t cmd_ack_code
;
1268 uint8_t extra_length
;
1269 uint8_t res_target_id
;
1270 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1272 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM_B
) {
1275 if (retry_times
> aice_max_retry_times
) {
1276 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1277 AICE_CMD_T_WRITE_MEM_B
, cmd_ack_code
);
1282 /* clear timeout and retry */
1283 if (aice_reset_box() != ERROR_OK
)
1294 static int aice_write_mem_h(uint8_t target_id
, uint32_t address
, uint32_t data
)
1296 int retry_times
= 0;
1298 LOG_DEBUG("WRITE_MEM_H, COREID: %" PRIu8
", ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1303 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
1304 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
)) {
1305 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H
, target_id
, 0,
1306 (address
>> 1) & 0x7FFFFFFF, data
& 0x0000FFFF, data_endian
);
1307 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
,
1311 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM_H
, target_id
, 0,
1312 (address
>> 1) & 0x7FFFFFFF, data
& 0x0000FFFF, data_endian
);
1313 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1315 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1316 if (result
!= AICE_FORMAT_DTHMB
) {
1317 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1318 AICE_FORMAT_DTHMB
, result
);
1322 uint8_t cmd_ack_code
;
1323 uint8_t extra_length
;
1324 uint8_t res_target_id
;
1325 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1327 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM_H
) {
1330 if (retry_times
> aice_max_retry_times
) {
1331 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1332 AICE_CMD_T_WRITE_MEM_H
, cmd_ack_code
);
1337 /* clear timeout and retry */
1338 if (aice_reset_box() != ERROR_OK
)
1349 static int aice_write_mem(uint8_t target_id
, uint32_t address
, uint32_t data
)
1351 int retry_times
= 0;
1353 LOG_DEBUG("WRITE_MEM, COREID: %" PRIu8
", ADDRESS %08" PRIx32
" VALUE %08" PRIx32
,
1358 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
1359 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
)) {
1360 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM
, target_id
, 0,
1361 (address
>> 2) & 0x3FFFFFFF, data
, data_endian
);
1362 return aice_usb_packet_append(usb_out_buffer
, AICE_FORMAT_HTDMD
,
1366 aice_pack_htdmd(AICE_CMD_T_WRITE_MEM
, target_id
, 0,
1367 (address
>> 2) & 0x3FFFFFFF, data
, data_endian
);
1368 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
);
1370 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1371 if (result
!= AICE_FORMAT_DTHMB
) {
1372 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1373 AICE_FORMAT_DTHMB
, result
);
1377 uint8_t cmd_ack_code
;
1378 uint8_t extra_length
;
1379 uint8_t res_target_id
;
1380 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1382 if (cmd_ack_code
== AICE_CMD_T_WRITE_MEM
) {
1385 if (retry_times
> aice_max_retry_times
) {
1386 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1387 AICE_CMD_T_WRITE_MEM
, cmd_ack_code
);
1392 /* clear timeout and retry */
1393 if (aice_reset_box() != ERROR_OK
)
1404 static int aice_fastread_mem(uint8_t target_id
, uint8_t *word
, uint32_t num_of_words
)
1406 int retry_times
= 0;
1408 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
1409 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
))
1410 aice_usb_packet_flush();
1413 aice_pack_htdmb(AICE_CMD_T_FASTREAD_MEM
, target_id
, num_of_words
- 1, 0);
1415 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1417 LOG_DEBUG("FASTREAD_MEM, COREID: %" PRIu8
", # of DATA %08" PRIx32
,
1418 target_id
, num_of_words
);
1420 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4);
1422 LOG_ERROR("aice_usb_read failed (requested=%" PRIu32
", result=%d)",
1423 AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4, result
);
1427 uint8_t cmd_ack_code
;
1428 uint8_t extra_length
;
1429 uint8_t res_target_id
;
1430 aice_unpack_dthma_multiple_data(&cmd_ack_code
, &res_target_id
,
1431 &extra_length
, word
, data_endian
);
1433 if (cmd_ack_code
== AICE_CMD_T_FASTREAD_MEM
) {
1436 if (retry_times
> aice_max_retry_times
) {
1437 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1438 AICE_CMD_T_FASTREAD_MEM
, cmd_ack_code
);
1443 /* clear timeout and retry */
1444 if (aice_reset_box() != ERROR_OK
)
1454 static int aice_fastwrite_mem(uint8_t target_id
, const uint8_t *word
, uint32_t num_of_words
)
1456 int retry_times
= 0;
1458 if (aice_command_mode
== AICE_COMMAND_MODE_PACK
) {
1459 aice_usb_packet_flush();
1460 } else if (aice_command_mode
== AICE_COMMAND_MODE_BATCH
) {
1461 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM
, target_id
,
1462 num_of_words
- 1, 0, word
, data_endian
);
1463 return aice_usb_packet_append(usb_out_buffer
,
1464 AICE_FORMAT_HTDMD
+ (num_of_words
- 1) * 4,
1469 aice_pack_htdmd_multiple_data(AICE_CMD_T_FASTWRITE_MEM
, target_id
,
1470 num_of_words
- 1, 0, word
, data_endian
);
1472 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMD
+ (num_of_words
- 1) * 4);
1474 LOG_DEBUG("FASTWRITE_MEM, COREID: %" PRIu8
", # of DATA %08" PRIx32
,
1475 target_id
, num_of_words
);
1477 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1478 if (result
!= AICE_FORMAT_DTHMB
) {
1479 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1480 AICE_FORMAT_DTHMB
, result
);
1484 uint8_t cmd_ack_code
;
1485 uint8_t extra_length
;
1486 uint8_t res_target_id
;
1487 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1489 if (cmd_ack_code
== AICE_CMD_T_FASTWRITE_MEM
) {
1492 if (retry_times
> aice_max_retry_times
) {
1493 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1494 AICE_CMD_T_FASTWRITE_MEM
, cmd_ack_code
);
1499 /* clear timeout and retry */
1500 if (aice_reset_box() != ERROR_OK
)
1510 static int aice_read_mem_b(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1512 int retry_times
= 0;
1514 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
1515 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
))
1516 aice_usb_packet_flush();
1519 aice_pack_htdmb(AICE_CMD_T_READ_MEM_B
, target_id
, 0, address
);
1521 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1523 LOG_DEBUG("READ_MEM_B, COREID: %" PRIu8
"", target_id
);
1525 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1526 if (result
!= AICE_FORMAT_DTHMA
) {
1527 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1528 AICE_FORMAT_DTHMA
, result
);
1532 uint8_t cmd_ack_code
;
1533 uint8_t extra_length
;
1534 uint8_t res_target_id
;
1535 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1538 if (cmd_ack_code
== AICE_CMD_T_READ_MEM_B
) {
1539 LOG_DEBUG("READ_MEM_B response, data: 0x%02" PRIx32
, *data
);
1542 if (retry_times
> aice_max_retry_times
) {
1543 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1544 AICE_CMD_T_READ_MEM_B
, cmd_ack_code
);
1549 /* clear timeout and retry */
1550 if (aice_reset_box() != ERROR_OK
)
1560 static int aice_read_mem_h(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1562 int retry_times
= 0;
1564 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
1565 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
))
1566 aice_usb_packet_flush();
1569 aice_pack_htdmb(AICE_CMD_T_READ_MEM_H
, target_id
, 0, (address
>> 1) & 0x7FFFFFFF);
1571 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1573 LOG_DEBUG("READ_MEM_H, CORE_ID: %" PRIu8
"", target_id
);
1575 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1576 if (result
!= AICE_FORMAT_DTHMA
) {
1577 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1578 AICE_FORMAT_DTHMA
, result
);
1582 uint8_t cmd_ack_code
;
1583 uint8_t extra_length
;
1584 uint8_t res_target_id
;
1585 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1588 if (cmd_ack_code
== AICE_CMD_T_READ_MEM_H
) {
1589 LOG_DEBUG("READ_MEM_H response, data: 0x%" PRIx32
, *data
);
1592 if (retry_times
> aice_max_retry_times
) {
1593 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1594 AICE_CMD_T_READ_MEM_H
, cmd_ack_code
);
1599 /* clear timeout and retry */
1600 if (aice_reset_box() != ERROR_OK
)
1610 static int aice_read_mem(uint8_t target_id
, uint32_t address
, uint32_t *data
)
1612 int retry_times
= 0;
1614 if ((aice_command_mode
== AICE_COMMAND_MODE_PACK
) ||
1615 (aice_command_mode
== AICE_COMMAND_MODE_BATCH
))
1616 aice_usb_packet_flush();
1619 aice_pack_htdmb(AICE_CMD_T_READ_MEM
, target_id
, 0,
1620 (address
>> 2) & 0x3FFFFFFF);
1622 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMB
);
1624 LOG_DEBUG("READ_MEM, COREID: %" PRIu8
"", target_id
);
1626 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
);
1627 if (result
!= AICE_FORMAT_DTHMA
) {
1628 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1629 AICE_FORMAT_DTHMA
, result
);
1633 uint8_t cmd_ack_code
;
1634 uint8_t extra_length
;
1635 uint8_t res_target_id
;
1636 aice_unpack_dthma(&cmd_ack_code
, &res_target_id
, &extra_length
,
1639 if (cmd_ack_code
== AICE_CMD_T_READ_MEM
) {
1640 LOG_DEBUG("READ_MEM response, data: 0x%" PRIx32
, *data
);
1643 if (retry_times
> aice_max_retry_times
) {
1644 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1645 AICE_CMD_T_READ_MEM
, cmd_ack_code
);
1650 /* clear timeout and retry */
1651 if (aice_reset_box() != ERROR_OK
)
1661 static int aice_batch_buffer_read(uint8_t buf_index
, uint32_t *word
, uint32_t num_of_words
)
1663 int retry_times
= 0;
1666 aice_pack_htdma(AICE_CMD_BATCH_BUFFER_READ
, 0, num_of_words
- 1, buf_index
);
1668 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMA
);
1670 LOG_DEBUG("BATCH_BUFFER_READ, # of DATA %08" PRIx32
, num_of_words
);
1672 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4);
1674 LOG_ERROR("aice_usb_read failed (requested=%" PRIu32
", result=%d)",
1675 AICE_FORMAT_DTHMA
+ (num_of_words
- 1) * 4, result
);
1679 uint8_t cmd_ack_code
;
1680 uint8_t extra_length
;
1681 uint8_t res_target_id
;
1682 aice_unpack_dthma_multiple_data(&cmd_ack_code
, &res_target_id
,
1683 &extra_length
, (uint8_t *)word
, data_endian
);
1685 if (cmd_ack_code
== AICE_CMD_BATCH_BUFFER_READ
) {
1688 if (retry_times
> aice_max_retry_times
) {
1689 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1690 AICE_CMD_BATCH_BUFFER_READ
, cmd_ack_code
);
1695 /* clear timeout and retry */
1696 if (aice_reset_box() != ERROR_OK
)
1706 int aice_batch_buffer_write(uint8_t buf_index
, const uint8_t *word
, uint32_t num_of_words
)
1708 int retry_times
= 0;
1710 if (num_of_words
== 0)
1714 /* only pack AICE_CMD_BATCH_BUFFER_WRITE command header */
1715 aice_pack_htdmc(AICE_CMD_BATCH_BUFFER_WRITE
, 0, num_of_words
- 1, buf_index
,
1718 /* use append instead of pack */
1719 memcpy(usb_out_buffer
+ 4, word
, num_of_words
* 4);
1721 aice_usb_write(usb_out_buffer
, AICE_FORMAT_HTDMC
+ (num_of_words
- 1) * 4);
1723 LOG_DEBUG("BATCH_BUFFER_WRITE, # of DATA %08" PRIx32
, num_of_words
);
1725 int result
= aice_usb_read(usb_in_buffer
, AICE_FORMAT_DTHMB
);
1726 if (result
!= AICE_FORMAT_DTHMB
) {
1727 LOG_ERROR("aice_usb_read failed (requested=%d, result=%d)",
1728 AICE_FORMAT_DTHMB
, result
);
1732 uint8_t cmd_ack_code
;
1733 uint8_t extra_length
;
1734 uint8_t res_target_id
;
1735 aice_unpack_dthmb(&cmd_ack_code
, &res_target_id
, &extra_length
);
1737 if (cmd_ack_code
== AICE_CMD_BATCH_BUFFER_WRITE
) {
1740 if (retry_times
> aice_max_retry_times
) {
1741 LOG_ERROR("aice command timeout (command=0x%" PRIx8
", response=0x%" PRIx8
")",
1742 AICE_CMD_BATCH_BUFFER_WRITE
, cmd_ack_code
);
1747 /* clear timeout and retry */
1748 if (aice_reset_box() != ERROR_OK
)
1758 /***************************************************************************/
1759 /* End of AICE commands */
1761 typedef int (*read_mem_func_t
)(uint32_t coreid
, uint32_t address
, uint32_t *data
);
1762 typedef int (*write_mem_func_t
)(uint32_t coreid
, uint32_t address
, uint32_t data
);
1764 static struct aice_nds32_info core_info
[AICE_MAX_NUM_CORE
];
1765 static uint8_t total_num_of_core
;
1767 static char *custom_srst_script
;
1768 static char *custom_trst_script
;
1769 static char *custom_restart_script
;
1770 static uint32_t aice_count_to_check_dbger
= 30;
1772 static int aice_read_reg(uint32_t coreid
, uint32_t num
, uint32_t *val
);
1773 static int aice_write_reg(uint32_t coreid
, uint32_t num
, uint32_t val
);
1775 static int check_suppressed_exception(uint32_t coreid
, uint32_t dbger_value
)
1777 uint32_t ir4_value
= 0;
1778 uint32_t ir6_value
= 0;
1779 /* the default value of handling_suppressed_exception is false */
1780 static bool handling_suppressed_exception
;
1782 if (handling_suppressed_exception
)
1785 if ((dbger_value
& NDS_DBGER_ALL_SUPRS_EX
) == NDS_DBGER_ALL_SUPRS_EX
) {
1786 LOG_ERROR("<-- TARGET WARNING! Exception is detected and suppressed. -->");
1787 handling_suppressed_exception
= true;
1789 aice_read_reg(coreid
, IR4
, &ir4_value
);
1790 /* Clear IR6.SUPRS_EXC, IR6.IMP_EXC */
1791 aice_read_reg(coreid
, IR6
, &ir6_value
);
1793 * For MCU version(MSC_CFG.MCU == 1) like V3m
1794 * | SWID[30:16] | Reserved[15:10] | SUPRS_EXC[9] | IMP_EXC[8]
1795 * |VECTOR[7:5] | INST[4] | Exc Type[3:0] |
1797 * For non-MCU version(MSC_CFG.MCU == 0) like V3
1798 * | SWID[30:16] | Reserved[15:14] | SUPRS_EXC[13] | IMP_EXC[12]
1799 * | VECTOR[11:5] | INST[4] | Exc Type[3:0] |
1801 LOG_INFO("EVA: 0x%08" PRIx32
, ir4_value
);
1802 LOG_INFO("ITYPE: 0x%08" PRIx32
, ir6_value
);
1804 ir6_value
= ir6_value
& (~0x300); /* for MCU */
1805 ir6_value
= ir6_value
& (~0x3000); /* for non-MCU */
1806 aice_write_reg(coreid
, IR6
, ir6_value
);
1808 handling_suppressed_exception
= false;
1814 static int check_privilege(uint32_t coreid
, uint32_t dbger_value
)
1816 if ((dbger_value
& NDS_DBGER_ILL_SEC_ACC
) == NDS_DBGER_ILL_SEC_ACC
) {
1817 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege "
1818 "to execute the debug operations. -->");
1820 /* Clear DBGER.ILL_SEC_ACC */
1821 if (aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
1822 NDS_DBGER_ILL_SEC_ACC
) != ERROR_OK
)
1829 static int aice_check_dbger(uint32_t coreid
, uint32_t expect_status
)
1832 uint32_t value_dbger
= 0;
1835 aice_read_misc(coreid
, NDS_EDM_MISC_DBGER
, &value_dbger
);
1837 if ((value_dbger
& expect_status
) == expect_status
) {
1838 if (ERROR_OK
!= check_suppressed_exception(coreid
, value_dbger
))
1840 if (ERROR_OK
!= check_privilege(coreid
, value_dbger
))
1849 if (i
== aice_count_to_check_dbger
)
1850 then
= timeval_ms();
1851 if (i
>= aice_count_to_check_dbger
) {
1852 if ((timeval_ms() - then
) > 1000) {
1853 LOG_ERROR("Timeout (1000ms) waiting for $DBGER status "
1854 "being 0x%08" PRIx32
, expect_status
);
1864 static int aice_execute_dim(uint32_t coreid
, uint32_t *insts
, uint8_t n_inst
)
1867 if (aice_write_dim(coreid
, insts
, n_inst
) != ERROR_OK
)
1870 /** clear DBGER.DPED */
1871 if (aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_DPED
) != ERROR_OK
)
1875 if (aice_do_execute(coreid
) != ERROR_OK
)
1878 /** read DBGER.DPED */
1879 if (aice_check_dbger(coreid
, NDS_DBGER_DPED
) != ERROR_OK
) {
1880 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly: "
1881 "0x%08" PRIx32
"0x%08" PRIx32
"0x%08" PRIx32
"0x%08" PRIx32
". -->",
1892 static int aice_read_reg(uint32_t coreid
, uint32_t num
, uint32_t *val
)
1894 LOG_DEBUG("aice_read_reg, reg_no: 0x%08" PRIx32
, num
);
1896 uint32_t instructions
[4]; /** execute instructions in DIM */
1898 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(num
)) { /* general registers */
1899 instructions
[0] = MTSR_DTR(num
);
1900 instructions
[1] = DSB
;
1901 instructions
[2] = NOP
;
1902 instructions
[3] = BEQ_MINUS_12
;
1903 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(num
)) { /* user special registers */
1904 instructions
[0] = MFUSR_G0(0, nds32_reg_sr_index(num
));
1905 instructions
[1] = MTSR_DTR(0);
1906 instructions
[2] = DSB
;
1907 instructions
[3] = BEQ_MINUS_12
;
1908 } else if (NDS32_REG_TYPE_AUMR
== nds32_reg_type(num
)) { /* audio registers */
1909 if ((CB_CTL
<= num
) && (num
<= CBE3
)) {
1910 instructions
[0] = AMFAR2(0, nds32_reg_sr_index(num
));
1911 instructions
[1] = MTSR_DTR(0);
1912 instructions
[2] = DSB
;
1913 instructions
[3] = BEQ_MINUS_12
;
1915 instructions
[0] = AMFAR(0, nds32_reg_sr_index(num
));
1916 instructions
[1] = MTSR_DTR(0);
1917 instructions
[2] = DSB
;
1918 instructions
[3] = BEQ_MINUS_12
;
1920 } else if (NDS32_REG_TYPE_FPU
== nds32_reg_type(num
)) { /* fpu registers */
1922 instructions
[0] = FMFCSR
;
1923 instructions
[1] = MTSR_DTR(0);
1924 instructions
[2] = DSB
;
1925 instructions
[3] = BEQ_MINUS_12
;
1926 } else if (num
== FPCFG
) {
1927 instructions
[0] = FMFCFG
;
1928 instructions
[1] = MTSR_DTR(0);
1929 instructions
[2] = DSB
;
1930 instructions
[3] = BEQ_MINUS_12
;
1932 if (num
>= FS0
&& num
<= FS31
) { /* single precision */
1933 instructions
[0] = FMFSR(0, nds32_reg_sr_index(num
));
1934 instructions
[1] = MTSR_DTR(0);
1935 instructions
[2] = DSB
;
1936 instructions
[3] = BEQ_MINUS_12
;
1937 } else if (num
>= FD0
&& num
<= FD31
) { /* double precision */
1938 instructions
[0] = FMFDR(0, nds32_reg_sr_index(num
));
1939 instructions
[1] = MTSR_DTR(0);
1940 instructions
[2] = DSB
;
1941 instructions
[3] = BEQ_MINUS_12
;
1944 } else { /* system registers */
1945 instructions
[0] = MFSR(0, nds32_reg_sr_index(num
));
1946 instructions
[1] = MTSR_DTR(0);
1947 instructions
[2] = DSB
;
1948 instructions
[3] = BEQ_MINUS_12
;
1951 aice_execute_dim(coreid
, instructions
, 4);
1953 uint32_t value_edmsw
= 0;
1954 aice_read_edmsr(coreid
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
1955 if (value_edmsw
& NDS_EDMSW_WDV
)
1956 aice_read_dtr(coreid
, val
);
1958 LOG_ERROR("<-- TARGET ERROR! The debug target failed to update "
1959 "the DTR register. -->");
1966 static int aice_usb_read_reg(uint32_t coreid
, uint32_t num
, uint32_t *val
)
1968 LOG_DEBUG("aice_usb_read_reg");
1971 *val
= core_info
[coreid
].r0_backup
;
1972 } else if (num
== R1
) {
1973 *val
= core_info
[coreid
].r1_backup
;
1974 } else if (num
== DR41
) {
1975 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
1976 * As user wants to read these registers, OpenOCD should return
1977 * the backup values, instead of reading the real values.
1978 * As user wants to write these registers, OpenOCD should write
1979 * to the backup values, instead of writing to real registers. */
1980 *val
= core_info
[coreid
].edmsw_backup
;
1981 } else if (num
== DR42
) {
1982 *val
= core_info
[coreid
].edm_ctl_backup
;
1983 } else if ((core_info
[coreid
].target_dtr_valid
== true) && (num
== DR43
)) {
1984 *val
= core_info
[coreid
].target_dtr_backup
;
1986 if (ERROR_OK
!= aice_read_reg(coreid
, num
, val
))
1993 static int aice_write_reg(uint32_t coreid
, uint32_t num
, uint32_t val
)
1995 LOG_DEBUG("aice_write_reg, reg_no: 0x%08" PRIx32
", value: 0x%08" PRIx32
, num
, val
);
1997 uint32_t instructions
[4]; /** execute instructions in DIM */
1998 uint32_t value_edmsw
= 0;
2000 aice_write_dtr(coreid
, val
);
2001 aice_read_edmsr(coreid
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
2002 if (0 == (value_edmsw
& NDS_EDMSW_RDV
)) {
2003 LOG_ERROR("<-- TARGET ERROR! AICE failed to write to the DTR register. -->");
2007 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(num
)) { /* general registers */
2008 instructions
[0] = MFSR_DTR(num
);
2009 instructions
[1] = DSB
;
2010 instructions
[2] = NOP
;
2011 instructions
[3] = BEQ_MINUS_12
;
2012 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(num
)) { /* user special registers */
2013 instructions
[0] = MFSR_DTR(0);
2014 instructions
[1] = MTUSR_G0(0, nds32_reg_sr_index(num
));
2015 instructions
[2] = DSB
;
2016 instructions
[3] = BEQ_MINUS_12
;
2017 } else if (NDS32_REG_TYPE_AUMR
== nds32_reg_type(num
)) { /* audio registers */
2018 if ((CB_CTL
<= num
) && (num
<= CBE3
)) {
2019 instructions
[0] = MFSR_DTR(0);
2020 instructions
[1] = AMTAR2(0, nds32_reg_sr_index(num
));
2021 instructions
[2] = DSB
;
2022 instructions
[3] = BEQ_MINUS_12
;
2024 instructions
[0] = MFSR_DTR(0);
2025 instructions
[1] = AMTAR(0, nds32_reg_sr_index(num
));
2026 instructions
[2] = DSB
;
2027 instructions
[3] = BEQ_MINUS_12
;
2029 } else if (NDS32_REG_TYPE_FPU
== nds32_reg_type(num
)) { /* fpu registers */
2031 instructions
[0] = MFSR_DTR(0);
2032 instructions
[1] = FMTCSR
;
2033 instructions
[2] = DSB
;
2034 instructions
[3] = BEQ_MINUS_12
;
2035 } else if (num
== FPCFG
) {
2036 /* FPCFG is readonly */
2038 if (num
>= FS0
&& num
<= FS31
) { /* single precision */
2039 instructions
[0] = MFSR_DTR(0);
2040 instructions
[1] = FMTSR(0, nds32_reg_sr_index(num
));
2041 instructions
[2] = DSB
;
2042 instructions
[3] = BEQ_MINUS_12
;
2043 } else if (num
>= FD0
&& num
<= FD31
) { /* double precision */
2044 instructions
[0] = MFSR_DTR(0);
2045 instructions
[1] = FMTDR(0, nds32_reg_sr_index(num
));
2046 instructions
[2] = DSB
;
2047 instructions
[3] = BEQ_MINUS_12
;
2051 instructions
[0] = MFSR_DTR(0);
2052 instructions
[1] = MTSR(0, nds32_reg_sr_index(num
));
2053 instructions
[2] = DSB
;
2054 instructions
[3] = BEQ_MINUS_12
;
2057 return aice_execute_dim(coreid
, instructions
, 4);
2060 static int aice_usb_write_reg(uint32_t coreid
, uint32_t num
, uint32_t val
)
2062 LOG_DEBUG("aice_usb_write_reg");
2065 core_info
[coreid
].r0_backup
= val
;
2067 core_info
[coreid
].r1_backup
= val
;
2068 else if (num
== DR42
)
2069 /* As target is halted, OpenOCD will backup DR41/DR42/DR43.
2070 * As user wants to read these registers, OpenOCD should return
2071 * the backup values, instead of reading the real values.
2072 * As user wants to write these registers, OpenOCD should write
2073 * to the backup values, instead of writing to real registers. */
2074 core_info
[coreid
].edm_ctl_backup
= val
;
2075 else if ((core_info
[coreid
].target_dtr_valid
== true) && (num
== DR43
))
2076 core_info
[coreid
].target_dtr_backup
= val
;
2078 return aice_write_reg(coreid
, num
, val
);
2083 static int aice_usb_open(struct aice_port_param_s
*param
)
2085 const uint16_t vids
[] = { param
->vid
, 0 };
2086 const uint16_t pids
[] = { param
->pid
, 0 };
2087 struct libusb_device_handle
*devh
;
2089 if (jtag_libusb_open(vids
, pids
, NULL
, &devh
, NULL
) != ERROR_OK
)
2092 /* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS
2093 * AREA!!!!!!!!!!! The behavior of libusb is not completely
2094 * consistent across Windows, Linux, and Mac OS X platforms.
2095 * The actions taken in the following compiler conditionals may
2096 * not agree with published documentation for libusb, but were
2097 * found to be necessary through trials and tribulations. Even
2098 * little tweaks can break one or more platforms, so if you do
2099 * make changes test them carefully on all platforms before
2105 libusb_reset_device(devh
);
2110 /* reopen jlink after usb_reset
2111 * on win32 this may take a second or two to re-enumerate */
2113 while ((retval
= jtag_libusb_open(vids
, pids
, NULL
, &devh
, NULL
)) != ERROR_OK
) {
2119 if (retval
!= ERROR_OK
)
2125 /* usb_set_configuration required under win32 */
2126 libusb_set_configuration(devh
, 0);
2127 libusb_claim_interface(devh
, 0);
2129 unsigned int aice_read_ep
;
2130 unsigned int aice_write_ep
;
2132 jtag_libusb_choose_interface(devh
, &aice_read_ep
, &aice_write_ep
, -1, -1, -1, LIBUSB_TRANSFER_TYPE_BULK
);
2133 LOG_DEBUG("aice_read_ep=0x%x, aice_write_ep=0x%x", aice_read_ep
, aice_write_ep
);
2135 aice_handler
.usb_read_ep
= aice_read_ep
;
2136 aice_handler
.usb_write_ep
= aice_write_ep
;
2137 aice_handler
.usb_handle
= devh
;
2142 static int aice_usb_read_reg_64(uint32_t coreid
, uint32_t num
, uint64_t *val
)
2144 LOG_DEBUG("aice_usb_read_reg_64, %s", nds32_reg_simple_name(num
));
2147 uint32_t high_value
;
2149 if (ERROR_OK
!= aice_read_reg(coreid
, num
, &value
))
2152 aice_read_reg(coreid
, R1
, &high_value
);
2154 LOG_DEBUG("low: 0x%08" PRIx32
", high: 0x%08" PRIx32
"\n", value
, high_value
);
2156 if (data_endian
== AICE_BIG_ENDIAN
)
2157 *val
= (((uint64_t)high_value
) << 32) | value
;
2159 *val
= (((uint64_t)value
) << 32) | high_value
;
2164 static int aice_usb_write_reg_64(uint32_t coreid
, uint32_t num
, uint64_t val
)
2167 uint32_t high_value
;
2169 if (data_endian
== AICE_BIG_ENDIAN
) {
2170 value
= val
& 0xFFFFFFFF;
2171 high_value
= (val
>> 32) & 0xFFFFFFFF;
2173 high_value
= val
& 0xFFFFFFFF;
2174 value
= (val
>> 32) & 0xFFFFFFFF;
2177 LOG_DEBUG("aice_usb_write_reg_64, %s, low: 0x%08" PRIx32
", high: 0x%08" PRIx32
"\n",
2178 nds32_reg_simple_name(num
), value
, high_value
);
2180 aice_write_reg(coreid
, R1
, high_value
);
2181 return aice_write_reg(coreid
, num
, value
);
2184 static int aice_get_version_info(void)
2186 uint32_t hardware_version
;
2187 uint32_t firmware_version
;
2188 uint32_t fpga_version
;
2190 if (aice_read_ctrl(AICE_READ_CTRL_GET_HARDWARE_VERSION
, &hardware_version
) != ERROR_OK
)
2193 if (aice_read_ctrl(AICE_READ_CTRL_GET_FIRMWARE_VERSION
, &firmware_version
) != ERROR_OK
)
2196 if (aice_read_ctrl(AICE_READ_CTRL_GET_FPGA_VERSION
, &fpga_version
) != ERROR_OK
)
2199 LOG_INFO("AICE version: hw_ver = 0x%" PRIx32
", fw_ver = 0x%" PRIx32
", fpga_ver = 0x%" PRIx32
,
2200 hardware_version
, firmware_version
, fpga_version
);
2205 #define LINE_BUFFER_SIZE 1024
2207 static int aice_execute_custom_script(const char *script
)
2210 char line_buffer
[LINE_BUFFER_SIZE
];
2214 uint32_t write_ctrl_value
;
2217 script_fd
= fopen(script
, "r");
2218 if (script_fd
== NULL
) {
2221 while (fgets(line_buffer
, LINE_BUFFER_SIZE
, script_fd
) != NULL
) {
2222 /* execute operations */
2224 op_str
= strstr(line_buffer
, "set");
2225 if (op_str
!= NULL
) {
2227 goto get_reset_type
;
2230 op_str
= strstr(line_buffer
, "clear");
2234 reset_str
= strstr(op_str
, "srst");
2235 if (reset_str
!= NULL
) {
2237 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_SRST
;
2239 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_SRST
;
2242 reset_str
= strstr(op_str
, "dbgi");
2243 if (reset_str
!= NULL
) {
2245 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_DBGI
;
2247 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_DBGI
;
2250 reset_str
= strstr(op_str
, "trst");
2251 if (reset_str
!= NULL
) {
2253 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_TRST
;
2255 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_TRST
;
2261 delay
= strtoul(reset_str
+ 4, NULL
, 0);
2262 write_ctrl_value
|= (delay
<< 16);
2264 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
2265 write_ctrl_value
) != ERROR_OK
) {
2276 static int aice_usb_set_clock(int set_clock
)
2278 if (set_clock
& AICE_TCK_CONTROL_TCK_SCAN
) {
2279 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL
,
2280 AICE_TCK_CONTROL_TCK_SCAN
) != ERROR_OK
)
2283 /* Read out TCK_SCAN clock value */
2284 uint32_t scan_clock
;
2285 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &scan_clock
) != ERROR_OK
)
2290 uint32_t scan_base_freq
;
2291 if (scan_clock
& 0x8)
2292 scan_base_freq
= 48000; /* 48 MHz */
2294 scan_base_freq
= 30000; /* 30 MHz */
2296 uint32_t set_base_freq
;
2297 if (set_clock
& 0x8)
2298 set_base_freq
= 48000;
2300 set_base_freq
= 30000;
2304 set_freq
= set_base_freq
>> (set_clock
& 0x7);
2305 scan_freq
= scan_base_freq
>> (scan_clock
& 0x7);
2307 if (scan_freq
< set_freq
) {
2308 LOG_ERROR("User specifies higher jtag clock than TCK_SCAN clock");
2313 if (aice_write_ctrl(AICE_WRITE_CTRL_TCK_CONTROL
, set_clock
) != ERROR_OK
)
2316 uint32_t check_speed
;
2317 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &check_speed
) != ERROR_OK
)
2320 if (((int)check_speed
& 0x0F) != set_clock
) {
2321 LOG_ERROR("Set jtag clock failed");
2328 static int aice_edm_init(uint32_t coreid
)
2330 aice_write_edmsr(coreid
, NDS_EDM_SR_DIMBR
, 0xFFFF0000);
2331 aice_write_misc(coreid
, NDS_EDM_MISC_DIMIR
, 0);
2333 /* unconditionally try to turn on V3_EDM_MODE */
2334 uint32_t edm_ctl_value
;
2335 aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_value
);
2336 aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
| 0x00000040);
2339 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
2340 NDS_DBGER_DPED
| NDS_DBGER_CRST
| NDS_DBGER_AT_MAX
);
2342 /* get EDM version */
2343 uint32_t value_edmcfg
;
2344 aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CFG
, &value_edmcfg
);
2345 core_info
[coreid
].edm_version
= (value_edmcfg
>> 16) & 0xFFFF;
2350 static bool is_v2_edm(uint32_t coreid
)
2352 if ((core_info
[coreid
].edm_version
& 0x1000) == 0)
2358 static int aice_init_edm_registers(uint32_t coreid
, bool clear_dex_use_psw
)
2360 /* enable DEH_SEL & MAX_STOP & V3_EDM_MODE & DBGI_MASK */
2361 uint32_t host_edm_ctl
= core_info
[coreid
].edm_ctl_backup
| 0xA000004F;
2362 if (clear_dex_use_psw
)
2363 /* After entering debug mode, OpenOCD may set
2364 * DEX_USE_PSW accidentally through backup value
2365 * of target EDM_CTL.
2366 * So, clear DEX_USE_PSW by force. */
2367 host_edm_ctl
&= ~(0x40000000);
2369 LOG_DEBUG("aice_init_edm_registers - EDM_CTL: 0x%08" PRIx32
, host_edm_ctl
);
2371 int result
= aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, host_edm_ctl
);
2377 * EDM_CTL will be modified by OpenOCD as debugging. OpenOCD has the
2378 * responsibility to keep EDM_CTL untouched after debugging.
2380 * There are two scenarios to consider:
2381 * 1. single step/running as debugging (running under debug session)
2382 * 2. detached from gdb (exit debug session)
2384 * So, we need to bakcup EDM_CTL before halted and restore it after
2385 * running. The difference of these two scenarios is EDM_CTL.DEH_SEL
2386 * is on for scenario 1, and off for scenario 2.
2388 static int aice_backup_edm_registers(uint32_t coreid
)
2390 int result
= aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
,
2391 &core_info
[coreid
].edm_ctl_backup
);
2393 /* To call aice_backup_edm_registers() after DEX on, DEX_USE_PSW
2394 * may be not correct. (For example, hit breakpoint, then backup
2395 * EDM_CTL. EDM_CTL.DEX_USE_PSW will be cleared.) Because debug
2396 * interrupt will clear DEX_USE_PSW, DEX_USE_PSW is always off after
2397 * DEX is on. It only backups correct value before OpenOCD issues DBGI.
2398 * (Backup EDM_CTL, then issue DBGI actively (refer aice_usb_halt())) */
2399 if (core_info
[coreid
].edm_ctl_backup
& 0x40000000)
2400 core_info
[coreid
].dex_use_psw_on
= true;
2402 core_info
[coreid
].dex_use_psw_on
= false;
2404 LOG_DEBUG("aice_backup_edm_registers - EDM_CTL: 0x%08" PRIx32
", DEX_USE_PSW: %s",
2405 core_info
[coreid
].edm_ctl_backup
,
2406 core_info
[coreid
].dex_use_psw_on
? "on" : "off");
2411 static int aice_restore_edm_registers(uint32_t coreid
)
2413 LOG_DEBUG("aice_restore_edm_registers -");
2415 /* set DEH_SEL, because target still under EDM control */
2416 int result
= aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
,
2417 core_info
[coreid
].edm_ctl_backup
| 0x80000000);
2422 static int aice_backup_tmp_registers(uint32_t coreid
)
2424 LOG_DEBUG("backup_tmp_registers -");
2426 /* backup target DTR first(if the target DTR is valid) */
2427 uint32_t value_edmsw
= 0;
2428 aice_read_edmsr(coreid
, NDS_EDM_SR_EDMSW
, &value_edmsw
);
2429 core_info
[coreid
].edmsw_backup
= value_edmsw
;
2430 if (value_edmsw
& 0x1) { /* EDMSW.WDV == 1 */
2431 aice_read_dtr(coreid
, &core_info
[coreid
].target_dtr_backup
);
2432 core_info
[coreid
].target_dtr_valid
= true;
2434 LOG_DEBUG("Backup target DTR: 0x%08" PRIx32
, core_info
[coreid
].target_dtr_backup
);
2436 core_info
[coreid
].target_dtr_valid
= false;
2439 /* Target DTR has been backup, then backup $R0 and $R1 */
2440 aice_read_reg(coreid
, R0
, &core_info
[coreid
].r0_backup
);
2441 aice_read_reg(coreid
, R1
, &core_info
[coreid
].r1_backup
);
2443 /* backup host DTR(if the host DTR is valid) */
2444 if (value_edmsw
& 0x2) { /* EDMSW.RDV == 1*/
2445 /* read out host DTR and write into target DTR, then use aice_read_edmsr to
2447 uint32_t instructions
[4] = {
2448 MFSR_DTR(R0
), /* R0 has already been backup */
2453 aice_execute_dim(coreid
, instructions
, 4);
2455 aice_read_dtr(coreid
, &core_info
[coreid
].host_dtr_backup
);
2456 core_info
[coreid
].host_dtr_valid
= true;
2458 LOG_DEBUG("Backup host DTR: 0x%08" PRIx32
, core_info
[coreid
].host_dtr_backup
);
2460 core_info
[coreid
].host_dtr_valid
= false;
2463 LOG_DEBUG("r0: 0x%08" PRIx32
", r1: 0x%08" PRIx32
,
2464 core_info
[coreid
].r0_backup
, core_info
[coreid
].r1_backup
);
2469 static int aice_restore_tmp_registers(uint32_t coreid
)
2471 LOG_DEBUG("restore_tmp_registers - r0: 0x%08" PRIx32
", r1: 0x%08" PRIx32
,
2472 core_info
[coreid
].r0_backup
, core_info
[coreid
].r1_backup
);
2474 if (core_info
[coreid
].target_dtr_valid
) {
2475 uint32_t instructions
[4] = {
2476 SETHI(R0
, core_info
[coreid
].target_dtr_backup
>> 12),
2477 ORI(R0
, R0
, core_info
[coreid
].target_dtr_backup
& 0x00000FFF),
2481 aice_execute_dim(coreid
, instructions
, 4);
2483 instructions
[0] = MTSR_DTR(R0
);
2484 instructions
[1] = DSB
;
2485 instructions
[2] = NOP
;
2486 instructions
[3] = BEQ_MINUS_12
;
2487 aice_execute_dim(coreid
, instructions
, 4);
2489 LOG_DEBUG("Restore target DTR: 0x%08" PRIx32
, core_info
[coreid
].target_dtr_backup
);
2492 aice_write_reg(coreid
, R0
, core_info
[coreid
].r0_backup
);
2493 aice_write_reg(coreid
, R1
, core_info
[coreid
].r1_backup
);
2495 if (core_info
[coreid
].host_dtr_valid
) {
2496 aice_write_dtr(coreid
, core_info
[coreid
].host_dtr_backup
);
2498 LOG_DEBUG("Restore host DTR: 0x%08" PRIx32
, core_info
[coreid
].host_dtr_backup
);
2504 static int aice_open_device(struct aice_port_param_s
*param
)
2506 if (ERROR_OK
!= aice_usb_open(param
))
2509 if (ERROR_FAIL
== aice_get_version_info()) {
2510 LOG_ERROR("Cannot get AICE version!");
2514 LOG_INFO("AICE initialization started");
2516 /* attempt to reset Andes EDM */
2517 if (ERROR_FAIL
== aice_reset_box()) {
2518 LOG_ERROR("Cannot initial AICE box!");
2525 static int aice_usb_set_jtag_clock(uint32_t a_clock
)
2527 jtag_clock
= a_clock
;
2529 if (ERROR_OK
!= aice_usb_set_clock(a_clock
)) {
2530 LOG_ERROR("Cannot set AICE JTAG clock!");
2537 static int aice_usb_close(void)
2539 jtag_libusb_close(aice_handler
.usb_handle
);
2541 free(custom_srst_script
);
2542 free(custom_trst_script
);
2543 free(custom_restart_script
);
2547 static int aice_core_init(uint32_t coreid
)
2549 core_info
[coreid
].access_channel
= NDS_MEMORY_ACC_CPU
;
2550 core_info
[coreid
].memory_select
= NDS_MEMORY_SELECT_AUTO
;
2551 core_info
[coreid
].core_state
= AICE_TARGET_UNKNOWN
;
2556 static int aice_usb_idcode(uint32_t *idcode
, uint8_t *num_of_idcode
)
2560 retval
= aice_scan_chain(idcode
, num_of_idcode
);
2561 if (retval
== ERROR_OK
) {
2562 for (int i
= 0; i
< *num_of_idcode
; i
++) {
2566 total_num_of_core
= *num_of_idcode
;
2572 static int aice_usb_halt(uint32_t coreid
)
2574 if (core_info
[coreid
].core_state
== AICE_TARGET_HALTED
) {
2575 LOG_DEBUG("aice_usb_halt check halted");
2579 LOG_DEBUG("aice_usb_halt");
2581 /** backup EDM registers */
2582 aice_backup_edm_registers(coreid
);
2583 /** init EDM for host debugging */
2584 /** no need to clear dex_use_psw, because dbgi will clear it */
2585 aice_init_edm_registers(coreid
, false);
2587 /** Clear EDM_CTL.DBGIM & EDM_CTL.DBGACKM */
2588 uint32_t edm_ctl_value
= 0;
2589 aice_read_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, &edm_ctl_value
);
2590 if (edm_ctl_value
& 0x3)
2591 aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
& ~(0x3));
2594 uint32_t acc_ctl_value
= 0;
2596 core_info
[coreid
].debug_under_dex_on
= false;
2597 aice_read_misc(coreid
, NDS_EDM_MISC_DBGER
, &dbger
);
2599 if (dbger
& NDS_DBGER_AT_MAX
)
2600 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level. -->");
2602 if (dbger
& NDS_DBGER_DEX
) {
2603 if (is_v2_edm(coreid
) == false) {
2604 /** debug 'debug mode'. use force_debug to issue dbgi */
2605 aice_read_misc(coreid
, NDS_EDM_MISC_ACC_CTL
, &acc_ctl_value
);
2606 acc_ctl_value
|= 0x8;
2607 aice_write_misc(coreid
, NDS_EDM_MISC_ACC_CTL
, acc_ctl_value
);
2608 core_info
[coreid
].debug_under_dex_on
= true;
2610 aice_write_misc(coreid
, NDS_EDM_MISC_EDM_CMDR
, 0);
2611 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2612 if (dbger
& NDS_DBGER_AT_MAX
)
2613 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_AT_MAX
);
2616 /** Issue DBGI normally */
2617 aice_write_misc(coreid
, NDS_EDM_MISC_EDM_CMDR
, 0);
2618 /* If CPU stalled due to AT_MAX, clear AT_MAX status. */
2619 if (dbger
& NDS_DBGER_AT_MAX
)
2620 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_AT_MAX
);
2623 if (aice_check_dbger(coreid
, NDS_DBGER_DEX
) != ERROR_OK
) {
2624 LOG_ERROR("<-- TARGET ERROR! Unable to stop the debug target through DBGI. -->");
2628 if (core_info
[coreid
].debug_under_dex_on
) {
2629 if (core_info
[coreid
].dex_use_psw_on
== false) {
2630 /* under debug 'debug mode', force $psw to 'debug mode' behavior */
2631 /* !!!NOTICE!!! this is workaround for debug 'debug mode'.
2632 * it is only for debugging 'debug exception handler' purpose.
2633 * after openocd detaches from target, target behavior is
2635 uint32_t ir0_value
= 0;
2636 uint32_t debug_mode_ir0_value
;
2637 aice_read_reg(coreid
, IR0
, &ir0_value
);
2638 debug_mode_ir0_value
= ir0_value
| 0x408; /* turn on DEX, set POM = 1 */
2639 debug_mode_ir0_value
&= ~(0x000000C1); /* turn off DT/IT/GIE */
2640 aice_write_reg(coreid
, IR0
, debug_mode_ir0_value
);
2644 /** set EDM_CTL.DBGIM & EDM_CTL.DBGACKM after halt */
2645 if (edm_ctl_value
& 0x3)
2646 aice_write_edmsr(coreid
, NDS_EDM_SR_EDM_CTL
, edm_ctl_value
);
2648 /* backup r0 & r1 */
2649 aice_backup_tmp_registers(coreid
);
2650 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2655 static int aice_usb_state(uint32_t coreid
, enum aice_target_state_s
*state
)
2657 uint32_t dbger_value
;
2660 int result
= aice_read_misc(coreid
, NDS_EDM_MISC_DBGER
, &dbger_value
);
2662 if (result
== ERROR_AICE_TIMEOUT
) {
2663 if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE
, &ice_state
) != ERROR_OK
) {
2664 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2668 if ((ice_state
& 0x20) == 0) {
2669 LOG_ERROR("<-- TARGET ERROR! Target is disconnected with AICE. -->");
2674 } else if (result
== ERROR_AICE_DISCONNECT
) {
2675 LOG_ERROR("<-- AICE ERROR! AICE is unplugged. -->");
2679 if ((dbger_value
& NDS_DBGER_ILL_SEC_ACC
) == NDS_DBGER_ILL_SEC_ACC
) {
2680 LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege. -->");
2682 /* Clear ILL_SEC_ACC */
2683 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_ILL_SEC_ACC
);
2685 *state
= AICE_TARGET_RUNNING
;
2686 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2687 } else if ((dbger_value
& NDS_DBGER_AT_MAX
) == NDS_DBGER_AT_MAX
) {
2688 /* Issue DBGI to exit cpu stall */
2689 aice_usb_halt(coreid
);
2691 /* Read OIPC to find out the trigger point */
2692 uint32_t ir11_value
;
2693 aice_read_reg(coreid
, IR11
, &ir11_value
);
2695 LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level; "
2696 "CPU is stalled at 0x%08" PRIx32
" for debugging. -->", ir11_value
);
2698 *state
= AICE_TARGET_HALTED
;
2699 } else if ((dbger_value
& NDS_DBGER_CRST
) == NDS_DBGER_CRST
) {
2700 LOG_DEBUG("DBGER.CRST is on.");
2702 *state
= AICE_TARGET_RESET
;
2703 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2706 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
, NDS_DBGER_CRST
);
2707 } else if ((dbger_value
& NDS_DBGER_DEX
) == NDS_DBGER_DEX
) {
2708 if (AICE_TARGET_RUNNING
== core_info
[coreid
].core_state
) {
2709 /* enter debug mode, init EDM registers */
2710 /* backup EDM registers */
2711 aice_backup_edm_registers(coreid
);
2712 /* init EDM for host debugging */
2713 aice_init_edm_registers(coreid
, true);
2714 aice_backup_tmp_registers(coreid
);
2715 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2716 } else if (AICE_TARGET_UNKNOWN
== core_info
[coreid
].core_state
) {
2717 /* debug 'debug mode', use force debug to halt core */
2718 aice_usb_halt(coreid
);
2720 *state
= AICE_TARGET_HALTED
;
2722 *state
= AICE_TARGET_RUNNING
;
2723 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2729 static int aice_usb_reset(void)
2731 if (aice_reset_box() != ERROR_OK
)
2735 if (custom_trst_script
== NULL
) {
2736 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2737 AICE_JTAG_PIN_CONTROL_TRST
) != ERROR_OK
)
2740 /* custom trst operations */
2741 if (aice_execute_custom_script(custom_trst_script
) != ERROR_OK
)
2745 if (aice_usb_set_clock(jtag_clock
) != ERROR_OK
)
2751 static int aice_issue_srst(uint32_t coreid
)
2753 LOG_DEBUG("aice_issue_srst");
2755 /* After issuing srst, target will be running. So we need to restore EDM_CTL. */
2756 aice_restore_edm_registers(coreid
);
2758 if (custom_srst_script
== NULL
) {
2759 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2760 AICE_JTAG_PIN_CONTROL_SRST
) != ERROR_OK
)
2763 /* custom srst operations */
2764 if (aice_execute_custom_script(custom_srst_script
) != ERROR_OK
)
2768 /* wait CRST infinitely */
2769 uint32_t dbger_value
;
2772 if (aice_read_misc(coreid
,
2773 NDS_EDM_MISC_DBGER
, &dbger_value
) != ERROR_OK
)
2776 if (dbger_value
& NDS_DBGER_CRST
)
2784 core_info
[coreid
].host_dtr_valid
= false;
2785 core_info
[coreid
].target_dtr_valid
= false;
2787 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2791 static int aice_issue_reset_hold(uint32_t coreid
)
2793 LOG_DEBUG("aice_issue_reset_hold");
2795 /* set no_dbgi_pin to 0 */
2796 uint32_t pin_status
;
2797 aice_read_ctrl(AICE_READ_CTRL_GET_JTAG_PIN_STATUS
, &pin_status
);
2798 if (pin_status
& 0x4)
2799 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
& (~0x4));
2802 if (custom_restart_script
== NULL
) {
2803 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2804 AICE_JTAG_PIN_CONTROL_RESTART
) != ERROR_OK
)
2807 /* custom restart operations */
2808 if (aice_execute_custom_script(custom_restart_script
) != ERROR_OK
)
2812 if (aice_check_dbger(coreid
, NDS_DBGER_CRST
| NDS_DBGER_DEX
) == ERROR_OK
) {
2813 aice_backup_tmp_registers(coreid
);
2814 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2818 /* set no_dbgi_pin to 1 */
2819 aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_STATUS
, pin_status
| 0x4);
2821 /* issue restart again */
2822 if (custom_restart_script
== NULL
) {
2823 if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL
,
2824 AICE_JTAG_PIN_CONTROL_RESTART
) != ERROR_OK
)
2827 /* custom restart operations */
2828 if (aice_execute_custom_script(custom_restart_script
) != ERROR_OK
)
2832 if (aice_check_dbger(coreid
, NDS_DBGER_CRST
| NDS_DBGER_DEX
) == ERROR_OK
) {
2833 aice_backup_tmp_registers(coreid
);
2834 core_info
[coreid
].core_state
= AICE_TARGET_HALTED
;
2839 /* do software reset-and-hold */
2840 aice_issue_srst(coreid
);
2841 aice_usb_halt(coreid
);
2844 aice_read_reg(coreid
, IR3
, &value_ir3
);
2845 aice_write_reg(coreid
, PC
, value_ir3
& 0xFFFF0000);
2851 static int aice_issue_reset_hold_multi(void)
2853 uint32_t write_ctrl_value
= 0;
2856 write_ctrl_value
= AICE_CUSTOM_DELAY_SET_SRST
;
2857 write_ctrl_value
|= (0x200 << 16);
2858 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
2859 write_ctrl_value
) != ERROR_OK
)
2862 for (uint8_t i
= 0 ; i
< total_num_of_core
; i
++)
2863 aice_write_misc(i
, NDS_EDM_MISC_EDM_CMDR
, 0);
2866 write_ctrl_value
= AICE_CUSTOM_DELAY_CLEAN_SRST
;
2867 write_ctrl_value
|= (0x200 << 16);
2868 if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY
,
2869 write_ctrl_value
) != ERROR_OK
)
2872 for (uint8_t i
= 0; i
< total_num_of_core
; i
++)
2878 static int aice_usb_assert_srst(uint32_t coreid
, enum aice_srst_type_s srst
)
2880 if ((srst
!= AICE_SRST
) && (srst
!= AICE_RESET_HOLD
))
2884 if (aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
2885 NDS_DBGER_CLEAR_ALL
) != ERROR_OK
)
2888 int result
= ERROR_OK
;
2889 if (srst
== AICE_SRST
)
2890 result
= aice_issue_srst(coreid
);
2892 if (1 == total_num_of_core
)
2893 result
= aice_issue_reset_hold(coreid
);
2895 result
= aice_issue_reset_hold_multi();
2898 /* Clear DBGER.CRST after reset to avoid 'core-reset checking' errors.
2899 * assert_srst is user-intentional reset behavior, so we could
2900 * clear DBGER.CRST safely.
2902 if (aice_write_misc(coreid
,
2903 NDS_EDM_MISC_DBGER
, NDS_DBGER_CRST
) != ERROR_OK
)
2909 static int aice_usb_run(uint32_t coreid
)
2911 LOG_DEBUG("aice_usb_run");
2913 uint32_t dbger_value
;
2914 if (aice_read_misc(coreid
,
2915 NDS_EDM_MISC_DBGER
, &dbger_value
) != ERROR_OK
)
2918 if ((dbger_value
& NDS_DBGER_DEX
) != NDS_DBGER_DEX
) {
2919 LOG_WARNING("<-- TARGET WARNING! The debug target exited "
2920 "the debug mode unexpectedly. -->");
2924 /* restore r0 & r1 before free run */
2925 aice_restore_tmp_registers(coreid
);
2926 core_info
[coreid
].core_state
= AICE_TARGET_RUNNING
;
2929 aice_write_misc(coreid
, NDS_EDM_MISC_DBGER
,
2930 NDS_DBGER_CLEAR_ALL
);
2932 /** restore EDM registers */
2933 /** OpenOCD should restore EDM_CTL **before** to exit debug state.
2934 * Otherwise, following instruction will read wrong EDM_CTL value.
2936 * pc -> mfsr $p0, EDM_CTL (single step)
2940 aice_restore_edm_registers(coreid
);
2942 /** execute instructions in DIM */
2943 uint32_t instructions
[4] = {
2949 int result
= aice_execute_dim(coreid
, instructions
, 4);
2954 static int aice_usb_step(uint32_t coreid
)
2956 LOG_DEBUG("aice_usb_step");
2959 uint32_t ir0_reg_num
;
2961 if (is_v2_edm(coreid
) == true)
2962 /* V2 EDM will push interrupt stack as debug exception */
2968 aice_read_reg(coreid
, ir0_reg_num
, &ir0_value
);
2969 if ((ir0_value
& 0x800) == 0) {
2971 ir0_value
|= (0x01 << 11);
2972 aice_write_reg(coreid
, ir0_reg_num
, ir0_value
);
2975 if (ERROR_FAIL
== aice_usb_run(coreid
))
2979 enum aice_target_state_s state
;
2982 if (aice_usb_state(coreid
, &state
) != ERROR_OK
)
2985 if (state
== AICE_TARGET_HALTED
)
2990 then
= timeval_ms();
2993 if ((timeval_ms() - then
) > 1000)
2994 LOG_WARNING("Timeout (1000ms) waiting for halt to complete");
3002 aice_read_reg(coreid
, ir0_reg_num
, &ir0_value
);
3003 ir0_value
&= ~(0x01 << 11);
3004 aice_write_reg(coreid
, ir0_reg_num
, ir0_value
);
3009 static int aice_usb_read_mem_b_bus(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3011 return aice_read_mem_b(coreid
, address
, data
);
3014 static int aice_usb_read_mem_h_bus(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3016 return aice_read_mem_h(coreid
, address
, data
);
3019 static int aice_usb_read_mem_w_bus(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3021 return aice_read_mem(coreid
, address
, data
);
3024 static int aice_usb_read_mem_b_dim(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3027 uint32_t instructions
[4] = {
3034 aice_execute_dim(coreid
, instructions
, 4);
3036 aice_read_dtr(coreid
, &value
);
3037 *data
= value
& 0xFF;
3042 static int aice_usb_read_mem_h_dim(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3045 uint32_t instructions
[4] = {
3052 aice_execute_dim(coreid
, instructions
, 4);
3054 aice_read_dtr(coreid
, &value
);
3055 *data
= value
& 0xFFFF;
3060 static int aice_usb_read_mem_w_dim(uint32_t coreid
, uint32_t address
, uint32_t *data
)
3062 uint32_t instructions
[4] = {
3069 aice_execute_dim(coreid
, instructions
, 4);
3071 aice_read_dtr(coreid
, data
);
3076 static int aice_usb_set_address_dim(uint32_t coreid
, uint32_t address
)
3078 uint32_t instructions
[4] = {
3079 SETHI(R0
, address
>> 12),
3080 ORI(R0
, R0
, address
& 0x00000FFF),
3085 return aice_execute_dim(coreid
, instructions
, 4);
3088 static int aice_usb_read_memory_unit(uint32_t coreid
, uint32_t addr
, uint32_t size
,
3089 uint32_t count
, uint8_t *buffer
)
3091 LOG_DEBUG("aice_usb_read_memory_unit, addr: 0x%08" PRIx32
3092 ", size: %" PRIu32
", count: %" PRIu32
"",
3095 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3096 aice_usb_set_address_dim(coreid
, addr
);
3100 read_mem_func_t read_mem_func
;
3104 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3105 read_mem_func
= aice_usb_read_mem_b_bus
;
3107 read_mem_func
= aice_usb_read_mem_b_dim
;
3109 for (i
= 0; i
< count
; i
++) {
3110 read_mem_func(coreid
, addr
, &value
);
3111 *buffer
++ = (uint8_t)value
;
3116 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3117 read_mem_func
= aice_usb_read_mem_h_bus
;
3119 read_mem_func
= aice_usb_read_mem_h_dim
;
3121 for (i
= 0; i
< count
; i
++) {
3122 read_mem_func(coreid
, addr
, &value
);
3123 uint16_t svalue
= value
;
3124 memcpy(buffer
, &svalue
, sizeof(uint16_t));
3130 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3131 read_mem_func
= aice_usb_read_mem_w_bus
;
3133 read_mem_func
= aice_usb_read_mem_w_dim
;
3135 for (i
= 0; i
< count
; i
++) {
3136 read_mem_func(coreid
, addr
, &value
);
3137 memcpy(buffer
, &value
, sizeof(uint32_t));
3147 static int aice_usb_write_mem_b_bus(uint32_t coreid
, uint32_t address
, uint32_t data
)
3149 return aice_write_mem_b(coreid
, address
, data
);
3152 static int aice_usb_write_mem_h_bus(uint32_t coreid
, uint32_t address
, uint32_t data
)
3154 return aice_write_mem_h(coreid
, address
, data
);
3157 static int aice_usb_write_mem_w_bus(uint32_t coreid
, uint32_t address
, uint32_t data
)
3159 return aice_write_mem(coreid
, address
, data
);
3162 static int aice_usb_write_mem_b_dim(uint32_t coreid
, uint32_t address
, uint32_t data
)
3164 uint32_t instructions
[4] = {
3171 aice_write_dtr(coreid
, data
& 0xFF);
3172 aice_execute_dim(coreid
, instructions
, 4);
3177 static int aice_usb_write_mem_h_dim(uint32_t coreid
, uint32_t address
, uint32_t data
)
3179 uint32_t instructions
[4] = {
3186 aice_write_dtr(coreid
, data
& 0xFFFF);
3187 aice_execute_dim(coreid
, instructions
, 4);
3192 static int aice_usb_write_mem_w_dim(uint32_t coreid
, uint32_t address
, uint32_t data
)
3194 uint32_t instructions
[4] = {
3201 aice_write_dtr(coreid
, data
);
3202 aice_execute_dim(coreid
, instructions
, 4);
3207 static int aice_usb_write_memory_unit(uint32_t coreid
, uint32_t addr
, uint32_t size
,
3208 uint32_t count
, const uint8_t *buffer
)
3210 LOG_DEBUG("aice_usb_write_memory_unit, addr: 0x%08" PRIx32
3211 ", size: %" PRIu32
", count: %" PRIu32
"",
3214 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3215 aice_usb_set_address_dim(coreid
, addr
);
3218 write_mem_func_t write_mem_func
;
3222 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3223 write_mem_func
= aice_usb_write_mem_b_bus
;
3225 write_mem_func
= aice_usb_write_mem_b_dim
;
3227 for (i
= 0; i
< count
; i
++) {
3228 write_mem_func(coreid
, addr
, *buffer
);
3234 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3235 write_mem_func
= aice_usb_write_mem_h_bus
;
3237 write_mem_func
= aice_usb_write_mem_h_dim
;
3239 for (i
= 0; i
< count
; i
++) {
3241 memcpy(&value
, buffer
, sizeof(uint16_t));
3243 write_mem_func(coreid
, addr
, value
);
3249 if (NDS_MEMORY_ACC_BUS
== core_info
[coreid
].access_channel
)
3250 write_mem_func
= aice_usb_write_mem_w_bus
;
3252 write_mem_func
= aice_usb_write_mem_w_dim
;
3254 for (i
= 0; i
< count
; i
++) {
3256 memcpy(&value
, buffer
, sizeof(uint32_t));
3258 write_mem_func(coreid
, addr
, value
);
3268 static int aice_bulk_read_mem(uint32_t coreid
, uint32_t addr
, uint32_t count
,
3271 uint32_t packet_size
;
3274 packet_size
= (count
>= 0x100) ? 0x100 : count
;
3278 if (aice_write_misc(coreid
, NDS_EDM_MISC_SBAR
, addr
) != ERROR_OK
)
3281 if (aice_fastread_mem(coreid
, buffer
,
3282 packet_size
) != ERROR_OK
)
3285 buffer
+= (packet_size
* 4);
3286 addr
+= (packet_size
* 4);
3287 count
-= packet_size
;
3293 static int aice_bulk_write_mem(uint32_t coreid
, uint32_t addr
, uint32_t count
,
3294 const uint8_t *buffer
)
3296 uint32_t packet_size
;
3299 packet_size
= (count
>= 0x100) ? 0x100 : count
;
3303 if (aice_write_misc(coreid
, NDS_EDM_MISC_SBAR
, addr
| 1) != ERROR_OK
)
3306 if (aice_fastwrite_mem(coreid
, buffer
,
3307 packet_size
) != ERROR_OK
)
3310 buffer
+= (packet_size
* 4);
3311 addr
+= (packet_size
* 4);
3312 count
-= packet_size
;
3318 static int aice_usb_bulk_read_mem(uint32_t coreid
, uint32_t addr
,
3319 uint32_t length
, uint8_t *buffer
)
3321 LOG_DEBUG("aice_usb_bulk_read_mem, addr: 0x%08" PRIx32
", length: 0x%08" PRIx32
, addr
, length
);
3325 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3326 aice_usb_set_address_dim(coreid
, addr
);
3328 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3329 retval
= aice_usb_read_memory_unit(coreid
, addr
, 4, length
/ 4, buffer
);
3331 retval
= aice_bulk_read_mem(coreid
, addr
, length
/ 4, buffer
);
3336 static int aice_usb_bulk_write_mem(uint32_t coreid
, uint32_t addr
,
3337 uint32_t length
, const uint8_t *buffer
)
3339 LOG_DEBUG("aice_usb_bulk_write_mem, addr: 0x%08" PRIx32
", length: 0x%08" PRIx32
, addr
, length
);
3343 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3344 aice_usb_set_address_dim(coreid
, addr
);
3346 if (NDS_MEMORY_ACC_CPU
== core_info
[coreid
].access_channel
)
3347 retval
= aice_usb_write_memory_unit(coreid
, addr
, 4, length
/ 4, buffer
);
3349 retval
= aice_bulk_write_mem(coreid
, addr
, length
/ 4, buffer
);
3354 static int aice_usb_read_debug_reg(uint32_t coreid
, uint32_t addr
, uint32_t *val
)
3356 if (AICE_TARGET_HALTED
== core_info
[coreid
].core_state
) {
3357 if (addr
== NDS_EDM_SR_EDMSW
) {
3358 *val
= core_info
[coreid
].edmsw_backup
;
3359 } else if (addr
== NDS_EDM_SR_EDM_DTR
) {
3360 if (core_info
[coreid
].target_dtr_valid
) {
3361 /* if EDM_DTR has read out, clear it. */
3362 *val
= core_info
[coreid
].target_dtr_backup
;
3363 core_info
[coreid
].edmsw_backup
&= (~0x1);
3364 core_info
[coreid
].target_dtr_valid
= false;
3371 return aice_read_edmsr(coreid
, addr
, val
);
3374 static int aice_usb_write_debug_reg(uint32_t coreid
, uint32_t addr
, const uint32_t val
)
3376 if (AICE_TARGET_HALTED
== core_info
[coreid
].core_state
) {
3377 if (addr
== NDS_EDM_SR_EDM_DTR
) {
3378 core_info
[coreid
].host_dtr_backup
= val
;
3379 core_info
[coreid
].edmsw_backup
|= 0x2;
3380 core_info
[coreid
].host_dtr_valid
= true;
3384 return aice_write_edmsr(coreid
, addr
, val
);
3387 static int aice_usb_memory_access(uint32_t coreid
, enum nds_memory_access channel
)
3389 LOG_DEBUG("aice_usb_memory_access, access channel: %u", channel
);
3391 core_info
[coreid
].access_channel
= channel
;
3396 static int aice_usb_memory_mode(uint32_t coreid
, enum nds_memory_select mem_select
)
3398 if (core_info
[coreid
].memory_select
== mem_select
)
3401 LOG_DEBUG("aice_usb_memory_mode, memory select: %u", mem_select
);
3403 core_info
[coreid
].memory_select
= mem_select
;
3405 if (NDS_MEMORY_SELECT_AUTO
!= core_info
[coreid
].memory_select
)
3406 aice_write_misc(coreid
, NDS_EDM_MISC_ACC_CTL
,
3407 core_info
[coreid
].memory_select
- 1);
3409 aice_write_misc(coreid
, NDS_EDM_MISC_ACC_CTL
,
3410 NDS_MEMORY_SELECT_MEM
- 1);
3415 static int aice_usb_read_tlb(uint32_t coreid
, target_addr_t virtual_address
,
3416 target_addr_t
*physical_address
)
3418 LOG_DEBUG("aice_usb_read_tlb, virtual address: 0x%08" TARGET_PRIxADDR
, virtual_address
);
3420 uint32_t instructions
[4];
3421 uint32_t probe_result
;
3424 uint32_t access_page_size
;
3425 uint32_t virtual_offset
;
3426 uint32_t physical_page_number
;
3428 aice_write_dtr(coreid
, virtual_address
);
3430 /* probe TLB first */
3431 instructions
[0] = MFSR_DTR(R0
);
3432 instructions
[1] = TLBOP_TARGET_PROBE(R1
, R0
);
3433 instructions
[2] = DSB
;
3434 instructions
[3] = BEQ_MINUS_12
;
3435 aice_execute_dim(coreid
, instructions
, 4);
3437 aice_read_reg(coreid
, R1
, &probe_result
);
3439 if (probe_result
& 0x80000000)
3442 /* read TLB entry */
3443 aice_write_dtr(coreid
, probe_result
& 0x7FF);
3445 /* probe TLB first */
3446 instructions
[0] = MFSR_DTR(R0
);
3447 instructions
[1] = TLBOP_TARGET_READ(R0
);
3448 instructions
[2] = DSB
;
3449 instructions
[3] = BEQ_MINUS_12
;
3450 aice_execute_dim(coreid
, instructions
, 4);
3452 /* TODO: it should backup mr3, mr4 */
3453 aice_read_reg(coreid
, MR3
, &value_mr3
);
3454 aice_read_reg(coreid
, MR4
, &value_mr4
);
3456 access_page_size
= value_mr4
& 0xF;
3457 if (0 == access_page_size
) { /* 4K page */
3458 virtual_offset
= virtual_address
& 0x00000FFF;
3459 physical_page_number
= value_mr3
& 0xFFFFF000;
3460 } else if (1 == access_page_size
) { /* 8K page */
3461 virtual_offset
= virtual_address
& 0x00001FFF;
3462 physical_page_number
= value_mr3
& 0xFFFFE000;
3463 } else if (5 == access_page_size
) { /* 1M page */
3464 virtual_offset
= virtual_address
& 0x000FFFFF;
3465 physical_page_number
= value_mr3
& 0xFFF00000;
3470 *physical_address
= physical_page_number
| virtual_offset
;
3475 static int aice_usb_init_cache(uint32_t coreid
)
3477 LOG_DEBUG("aice_usb_init_cache");
3482 aice_read_reg(coreid
, CR1
, &value_cr1
);
3483 aice_read_reg(coreid
, CR2
, &value_cr2
);
3485 struct cache_info
*icache
= &core_info
[coreid
].icache
;
3487 icache
->set
= value_cr1
& 0x7;
3488 icache
->log2_set
= icache
->set
+ 6;
3489 icache
->set
= 64 << icache
->set
;
3490 icache
->way
= ((value_cr1
>> 3) & 0x7) + 1;
3491 icache
->line_size
= (value_cr1
>> 6) & 0x7;
3492 if (icache
->line_size
!= 0) {
3493 icache
->log2_line_size
= icache
->line_size
+ 2;
3494 icache
->line_size
= 8 << (icache
->line_size
- 1);
3496 icache
->log2_line_size
= 0;
3499 LOG_DEBUG("\ticache set: %" PRIu32
", way: %" PRIu32
", line size: %" PRIu32
", "
3500 "log2(set): %" PRIu32
", log2(line_size): %" PRIu32
"",
3501 icache
->set
, icache
->way
, icache
->line_size
,
3502 icache
->log2_set
, icache
->log2_line_size
);
3504 struct cache_info
*dcache
= &core_info
[coreid
].dcache
;
3506 dcache
->set
= value_cr2
& 0x7;
3507 dcache
->log2_set
= dcache
->set
+ 6;
3508 dcache
->set
= 64 << dcache
->set
;
3509 dcache
->way
= ((value_cr2
>> 3) & 0x7) + 1;
3510 dcache
->line_size
= (value_cr2
>> 6) & 0x7;
3511 if (dcache
->line_size
!= 0) {
3512 dcache
->log2_line_size
= dcache
->line_size
+ 2;
3513 dcache
->line_size
= 8 << (dcache
->line_size
- 1);
3515 dcache
->log2_line_size
= 0;
3518 LOG_DEBUG("\tdcache set: %" PRIu32
", way: %" PRIu32
", line size: %" PRIu32
", "
3519 "log2(set): %" PRIu32
", log2(line_size): %" PRIu32
"",
3520 dcache
->set
, dcache
->way
, dcache
->line_size
,
3521 dcache
->log2_set
, dcache
->log2_line_size
);
3523 core_info
[coreid
].cache_init
= true;
3528 static int aice_usb_dcache_inval_all(uint32_t coreid
)
3530 LOG_DEBUG("aice_usb_dcache_inval_all");
3534 uint32_t cache_index
;
3535 uint32_t instructions
[4];
3537 instructions
[0] = MFSR_DTR(R0
);
3538 instructions
[1] = L1D_IX_INVAL(R0
);
3539 instructions
[2] = DSB
;
3540 instructions
[3] = BEQ_MINUS_12
;
3542 struct cache_info
*dcache
= &core_info
[coreid
].dcache
;
3544 for (set_index
= 0; set_index
< dcache
->set
; set_index
++) {
3545 for (way_index
= 0; way_index
< dcache
->way
; way_index
++) {
3546 cache_index
= (way_index
<< (dcache
->log2_set
+ dcache
->log2_line_size
)) |
3547 (set_index
<< dcache
->log2_line_size
);
3549 if (ERROR_OK
!= aice_write_dtr(coreid
, cache_index
))
3552 if (ERROR_OK
!= aice_execute_dim(coreid
, instructions
, 4))
3560 static int aice_usb_dcache_va_inval(uint32_t coreid
, uint32_t address
)
3562 LOG_DEBUG("aice_usb_dcache_va_inval");
3564 uint32_t instructions
[4];
3566 aice_write_dtr(coreid
, address
);
3568 instructions
[0] = MFSR_DTR(R0
);
3569 instructions
[1] = L1D_VA_INVAL(R0
);
3570 instructions
[2] = DSB
;
3571 instructions
[3] = BEQ_MINUS_12
;
3573 return aice_execute_dim(coreid
, instructions
, 4);
3576 static int aice_usb_dcache_wb_all(uint32_t coreid
)
3578 LOG_DEBUG("aice_usb_dcache_wb_all");
3582 uint32_t cache_index
;
3583 uint32_t instructions
[4];
3585 instructions
[0] = MFSR_DTR(R0
);
3586 instructions
[1] = L1D_IX_WB(R0
);
3587 instructions
[2] = DSB
;
3588 instructions
[3] = BEQ_MINUS_12
;
3590 struct cache_info
*dcache
= &core_info
[coreid
].dcache
;
3592 for (set_index
= 0; set_index
< dcache
->set
; set_index
++) {
3593 for (way_index
= 0; way_index
< dcache
->way
; way_index
++) {
3594 cache_index
= (way_index
<< (dcache
->log2_set
+ dcache
->log2_line_size
)) |
3595 (set_index
<< dcache
->log2_line_size
);
3597 if (ERROR_OK
!= aice_write_dtr(coreid
, cache_index
))
3600 if (ERROR_OK
!= aice_execute_dim(coreid
, instructions
, 4))
3608 static int aice_usb_dcache_va_wb(uint32_t coreid
, uint32_t address
)
3610 LOG_DEBUG("aice_usb_dcache_va_wb");
3612 uint32_t instructions
[4];
3614 aice_write_dtr(coreid
, address
);
3616 instructions
[0] = MFSR_DTR(R0
);
3617 instructions
[1] = L1D_VA_WB(R0
);
3618 instructions
[2] = DSB
;
3619 instructions
[3] = BEQ_MINUS_12
;
3621 return aice_execute_dim(coreid
, instructions
, 4);
3624 static int aice_usb_icache_inval_all(uint32_t coreid
)
3626 LOG_DEBUG("aice_usb_icache_inval_all");
3630 uint32_t cache_index
;
3631 uint32_t instructions
[4];
3633 instructions
[0] = MFSR_DTR(R0
);
3634 instructions
[1] = L1I_IX_INVAL(R0
);
3635 instructions
[2] = ISB
;
3636 instructions
[3] = BEQ_MINUS_12
;
3638 struct cache_info
*icache
= &core_info
[coreid
].icache
;
3640 for (set_index
= 0; set_index
< icache
->set
; set_index
++) {
3641 for (way_index
= 0; way_index
< icache
->way
; way_index
++) {
3642 cache_index
= (way_index
<< (icache
->log2_set
+ icache
->log2_line_size
)) |
3643 (set_index
<< icache
->log2_line_size
);
3645 if (ERROR_OK
!= aice_write_dtr(coreid
, cache_index
))
3648 if (ERROR_OK
!= aice_execute_dim(coreid
, instructions
, 4))
3656 static int aice_usb_icache_va_inval(uint32_t coreid
, uint32_t address
)
3658 LOG_DEBUG("aice_usb_icache_va_inval");
3660 uint32_t instructions
[4];
3662 aice_write_dtr(coreid
, address
);
3664 instructions
[0] = MFSR_DTR(R0
);
3665 instructions
[1] = L1I_VA_INVAL(R0
);
3666 instructions
[2] = ISB
;
3667 instructions
[3] = BEQ_MINUS_12
;
3669 return aice_execute_dim(coreid
, instructions
, 4);
3672 static int aice_usb_cache_ctl(uint32_t coreid
, uint32_t subtype
, uint32_t address
)
3674 LOG_DEBUG("aice_usb_cache_ctl");
3678 if (core_info
[coreid
].cache_init
== false)
3679 aice_usb_init_cache(coreid
);
3682 case AICE_CACHE_CTL_L1D_INVALALL
:
3683 result
= aice_usb_dcache_inval_all(coreid
);
3685 case AICE_CACHE_CTL_L1D_VA_INVAL
:
3686 result
= aice_usb_dcache_va_inval(coreid
, address
);
3688 case AICE_CACHE_CTL_L1D_WBALL
:
3689 result
= aice_usb_dcache_wb_all(coreid
);
3691 case AICE_CACHE_CTL_L1D_VA_WB
:
3692 result
= aice_usb_dcache_va_wb(coreid
, address
);
3694 case AICE_CACHE_CTL_L1I_INVALALL
:
3695 result
= aice_usb_icache_inval_all(coreid
);
3697 case AICE_CACHE_CTL_L1I_VA_INVAL
:
3698 result
= aice_usb_icache_va_inval(coreid
, address
);
3701 result
= ERROR_FAIL
;
3708 static int aice_usb_set_retry_times(uint32_t a_retry_times
)
3710 aice_max_retry_times
= a_retry_times
;
3714 static int aice_usb_program_edm(uint32_t coreid
, char *command_sequence
)
3719 uint32_t data_value
;
3723 command_str
= strtok(command_sequence
, ";");
3724 if (command_str
== NULL
)
3729 /* process one command */
3730 while (command_str
[i
] == ' ' ||
3731 command_str
[i
] == '\n' ||
3732 command_str
[i
] == '\r' ||
3733 command_str
[i
] == '\t')
3736 /* skip ' ', '\r', '\n', '\t' */
3737 command_str
= command_str
+ i
;
3739 if (strncmp(command_str
, "write_misc", 10) == 0) {
3740 reg_name_0
= strstr(command_str
, "gen_port0");
3741 reg_name_1
= strstr(command_str
, "gen_port1");
3743 if (reg_name_0
!= NULL
) {
3744 data_value
= strtoul(reg_name_0
+ 9, NULL
, 0);
3746 if (aice_write_misc(coreid
,
3747 NDS_EDM_MISC_GEN_PORT0
, data_value
) != ERROR_OK
)
3750 } else if (reg_name_1
!= NULL
) {
3751 data_value
= strtoul(reg_name_1
+ 9, NULL
, 0);
3753 if (aice_write_misc(coreid
,
3754 NDS_EDM_MISC_GEN_PORT1
, data_value
) != ERROR_OK
)
3757 LOG_ERROR("program EDM, unsupported misc register: %s", command_str
);
3760 LOG_ERROR("program EDM, unsupported command: %s", command_str
);
3763 /* update command_str */
3764 command_str
= strtok(NULL
, ";");
3766 } while (command_str
!= NULL
);
3771 static int aice_usb_set_command_mode(enum aice_command_mode command_mode
)
3773 int retval
= ERROR_OK
;
3775 /* flush usb_packets_buffer as users change mode */
3776 retval
= aice_usb_packet_flush();
3778 if (command_mode
== AICE_COMMAND_MODE_BATCH
) {
3779 /* reset batch buffer */
3780 aice_command_mode
= AICE_COMMAND_MODE_NORMAL
;
3781 retval
= aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL
, 0x40000);
3784 aice_command_mode
= command_mode
;
3789 static int aice_usb_execute(uint32_t coreid
, uint32_t *instructions
,
3790 uint32_t instruction_num
)
3793 uint8_t current_instruction_num
;
3794 uint32_t dim_instructions
[4] = {NOP
, NOP
, NOP
, BEQ_MINUS_12
};
3796 /* To execute 4 instructions as a special case */
3797 if (instruction_num
== 4)
3798 return aice_execute_dim(coreid
, instructions
, 4);
3800 for (i
= 0 ; i
< instruction_num
; i
+= 3) {
3801 if (instruction_num
- i
< 3) {
3802 current_instruction_num
= instruction_num
- i
;
3803 for (j
= current_instruction_num
; j
< 3 ; j
++)
3804 dim_instructions
[j
] = NOP
;
3806 current_instruction_num
= 3;
3809 memcpy(dim_instructions
, instructions
+ i
,
3810 current_instruction_num
* sizeof(uint32_t));
3813 if (aice_write_dim(coreid
,
3818 /** clear DBGER.DPED */
3819 if (aice_write_misc(coreid
,
3820 NDS_EDM_MISC_DBGER
, NDS_DBGER_DPED
) != ERROR_OK
)
3824 if (aice_do_execute(coreid
) != ERROR_OK
)
3827 /** check DBGER.DPED */
3828 if (aice_check_dbger(coreid
, NDS_DBGER_DPED
) != ERROR_OK
) {
3830 LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly:"
3831 "0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
". -->",
3832 dim_instructions
[0],
3833 dim_instructions
[1],
3834 dim_instructions
[2],
3835 dim_instructions
[3]);
3843 static int aice_usb_set_custom_srst_script(const char *script
)
3845 custom_srst_script
= strdup(script
);
3850 static int aice_usb_set_custom_trst_script(const char *script
)
3852 custom_trst_script
= strdup(script
);
3857 static int aice_usb_set_custom_restart_script(const char *script
)
3859 custom_restart_script
= strdup(script
);
3864 static int aice_usb_set_count_to_check_dbger(uint32_t count_to_check
)
3866 aice_count_to_check_dbger
= count_to_check
;
3871 static int aice_usb_set_data_endian(uint32_t coreid
,
3872 enum aice_target_endian target_data_endian
)
3874 data_endian
= target_data_endian
;
3879 static int fill_profiling_batch_commands(uint32_t coreid
, uint32_t reg_no
)
3881 uint32_t dim_instructions
[4];
3883 aice_usb_set_command_mode(AICE_COMMAND_MODE_BATCH
);
3886 if (aice_write_misc(coreid
, NDS_EDM_MISC_EDM_CMDR
, 0) != ERROR_OK
)
3890 dim_instructions
[0] = MTSR_DTR(0);
3891 dim_instructions
[1] = DSB
;
3892 dim_instructions
[2] = NOP
;
3893 dim_instructions
[3] = BEQ_MINUS_12
;
3894 if (aice_write_dim(coreid
, dim_instructions
, 4) != ERROR_OK
)
3896 aice_read_dtr_to_buffer(coreid
, AICE_BATCH_DATA_BUFFER_0
);
3899 if (NDS32_REG_TYPE_GPR
== nds32_reg_type(reg_no
)) {
3900 /* general registers */
3901 dim_instructions
[0] = MTSR_DTR(reg_no
);
3902 dim_instructions
[1] = DSB
;
3903 dim_instructions
[2] = NOP
;
3904 dim_instructions
[3] = BEQ_MINUS_12
;
3905 } else if (NDS32_REG_TYPE_SPR
== nds32_reg_type(reg_no
)) {
3906 /* user special registers */
3907 dim_instructions
[0] = MFUSR_G0(0, nds32_reg_sr_index(reg_no
));
3908 dim_instructions
[1] = MTSR_DTR(0);
3909 dim_instructions
[2] = DSB
;
3910 dim_instructions
[3] = BEQ_MINUS_12
;
3911 } else { /* system registers */
3912 dim_instructions
[0] = MFSR(0, nds32_reg_sr_index(reg_no
));
3913 dim_instructions
[1] = MTSR_DTR(0);
3914 dim_instructions
[2] = DSB
;
3915 dim_instructions
[3] = BEQ_MINUS_12
;
3917 if (aice_write_dim(coreid
, dim_instructions
, 4) != ERROR_OK
)
3919 aice_read_dtr_to_buffer(coreid
, AICE_BATCH_DATA_BUFFER_1
);
3922 aice_write_dtr_from_buffer(coreid
, AICE_BATCH_DATA_BUFFER_0
);
3923 dim_instructions
[0] = MFSR_DTR(0);
3924 dim_instructions
[1] = DSB
;
3925 dim_instructions
[2] = NOP
;
3926 dim_instructions
[3] = IRET
; /* free run */
3927 if (aice_write_dim(coreid
, dim_instructions
, 4) != ERROR_OK
)
3930 aice_command_mode
= AICE_COMMAND_MODE_NORMAL
;
3932 /* use BATCH_BUFFER_WRITE to fill command-batch-buffer */
3933 if (aice_batch_buffer_write(AICE_BATCH_COMMAND_BUFFER_0
,
3934 usb_out_packets_buffer
,
3935 (usb_out_packets_buffer_length
+ 3) / 4) != ERROR_OK
)
3938 usb_out_packets_buffer_length
= 0;
3939 usb_in_packets_buffer_length
= 0;
3944 static int aice_usb_profiling(uint32_t coreid
, uint32_t interval
, uint32_t iteration
,
3945 uint32_t reg_no
, uint32_t *samples
, uint32_t *num_samples
)
3947 uint32_t iteration_count
;
3948 uint32_t this_iteration
;
3949 int retval
= ERROR_OK
;
3950 const uint32_t MAX_ITERATION
= 250;
3955 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DIM_SIZE
, 4) != ERROR_OK
)
3958 /* Use AICE_BATCH_DATA_BUFFER_0 to read/write $DTR.
3959 * Set it to circular buffer */
3960 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL
, 0xC0000) != ERROR_OK
)
3963 fill_profiling_batch_commands(coreid
, reg_no
);
3965 iteration_count
= 0;
3966 while (iteration_count
< iteration
) {
3967 if (iteration
- iteration_count
< MAX_ITERATION
)
3968 this_iteration
= iteration
- iteration_count
;
3970 this_iteration
= MAX_ITERATION
;
3972 /* set number of iterations */
3973 uint32_t val_iteration
;
3974 val_iteration
= interval
<< 16 | this_iteration
;
3975 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_ITERATION
,
3976 val_iteration
) != ERROR_OK
) {
3977 retval
= ERROR_FAIL
;
3981 /* init AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL to store $PC */
3982 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL
,
3983 0x40000) != ERROR_OK
) {
3984 retval
= ERROR_FAIL
;
3988 aice_usb_run(coreid
);
3990 /* enable BATCH command */
3991 if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL
,
3992 0x80000000) != ERROR_OK
) {
3993 aice_usb_halt(coreid
);
3994 retval
= ERROR_FAIL
;
3998 /* wait a while (AICE bug, workaround) */
3999 alive_sleep(this_iteration
);
4003 uint32_t batch_status
= 0;
4007 aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS
, &batch_status
);
4009 if (batch_status
& 0x1) {
4011 } else if (batch_status
& 0xE) {
4012 aice_usb_halt(coreid
);
4013 retval
= ERROR_FAIL
;
4023 aice_usb_halt(coreid
);
4025 /* get samples from batch data buffer */
4026 if (aice_batch_buffer_read(AICE_BATCH_DATA_BUFFER_1
,
4027 samples
+ iteration_count
, this_iteration
) != ERROR_OK
) {
4028 retval
= ERROR_FAIL
;
4032 iteration_count
+= this_iteration
;
4036 *num_samples
= iteration_count
;
4042 struct aice_port_api_s aice_usb_api
= {
4044 .open
= aice_open_device
,
4046 .close
= aice_usb_close
,
4048 .idcode
= aice_usb_idcode
,
4050 .state
= aice_usb_state
,
4052 .reset
= aice_usb_reset
,
4054 .assert_srst
= aice_usb_assert_srst
,
4056 .run
= aice_usb_run
,
4058 .halt
= aice_usb_halt
,
4060 .step
= aice_usb_step
,
4062 .read_reg
= aice_usb_read_reg
,
4064 .write_reg
= aice_usb_write_reg
,
4066 .read_reg_64
= aice_usb_read_reg_64
,
4068 .write_reg_64
= aice_usb_write_reg_64
,
4070 .read_mem_unit
= aice_usb_read_memory_unit
,
4072 .write_mem_unit
= aice_usb_write_memory_unit
,
4074 .read_mem_bulk
= aice_usb_bulk_read_mem
,
4076 .write_mem_bulk
= aice_usb_bulk_write_mem
,
4078 .read_debug_reg
= aice_usb_read_debug_reg
,
4080 .write_debug_reg
= aice_usb_write_debug_reg
,
4082 .set_jtag_clock
= aice_usb_set_jtag_clock
,
4084 .memory_access
= aice_usb_memory_access
,
4086 .memory_mode
= aice_usb_memory_mode
,
4088 .read_tlb
= aice_usb_read_tlb
,
4090 .cache_ctl
= aice_usb_cache_ctl
,
4092 .set_retry_times
= aice_usb_set_retry_times
,
4094 .program_edm
= aice_usb_program_edm
,
4096 .set_command_mode
= aice_usb_set_command_mode
,
4098 .execute
= aice_usb_execute
,
4100 .set_custom_srst_script
= aice_usb_set_custom_srst_script
,
4102 .set_custom_trst_script
= aice_usb_set_custom_trst_script
,
4104 .set_custom_restart_script
= aice_usb_set_custom_restart_script
,
4106 .set_count_to_check_dbger
= aice_usb_set_count_to_check_dbger
,
4108 .set_data_endian
= aice_usb_set_data_endian
,
4110 .profiling
= aice_usb_profiling
,