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[openocd.git] / src / flash / tms470.c
1 /***************************************************************************
2 * (c) Copyright 2007, 2008 by Christopher Kilgour *
3 * techie |_at_| whiterocker |_dot_| com *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "log.h"
26 #include "tms470.h"
27 #include <string.h>
28 #include <unistd.h>
29
30 int tms470_register_commands(struct command_context_s *cmd_ctx);
31 int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
32 int tms470_erase(struct flash_bank_s *bank, int first, int last);
33 int tms470_protect(struct flash_bank_s *bank, int set, int first, int last);
34 int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count);
35 int tms470_probe(struct flash_bank_s *bank);
36 int tms470_auto_probe(struct flash_bank_s *bank);
37 int tms470_erase_check(struct flash_bank_s *bank);
38 int tms470_protect_check(struct flash_bank_s *bank);
39 int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size);
40
41 flash_driver_t tms470_flash = {
42 .name = "tms470",
43 .register_commands = tms470_register_commands,
44 .flash_bank_command = tms470_flash_bank_command,
45 .erase = tms470_erase,
46 .protect = tms470_protect,
47 .write = tms470_write,
48 .probe = tms470_probe,
49 .auto_probe = tms470_auto_probe,
50 .erase_check = tms470_erase_check,
51 .protect_check = tms470_protect_check,
52 .info = tms470_info
53 };
54
55 /* ----------------------------------------------------------------------
56 Internal Support, Helpers
57 ---------------------------------------------------------------------- */
58
59 const flash_sector_t TMS470R1A256_SECTORS[] = {
60 {0x00000000, 0x00002000, -1, -1},
61 {0x00002000, 0x00002000, -1, -1},
62 {0x00004000, 0x00002000, -1, -1},
63 {0x00006000, 0x00002000, -1, -1},
64 {0x00008000, 0x00008000, -1, -1},
65 {0x00010000, 0x00008000, -1, -1},
66 {0x00018000, 0x00008000, -1, -1},
67 {0x00020000, 0x00008000, -1, -1},
68 {0x00028000, 0x00008000, -1, -1},
69 {0x00030000, 0x00008000, -1, -1},
70 {0x00038000, 0x00002000, -1, -1},
71 {0x0003A000, 0x00002000, -1, -1},
72 {0x0003C000, 0x00002000, -1, -1},
73 {0x0003E000, 0x00002000, -1, -1},
74 };
75
76 #define TMS470R1A256_NUM_SECTORS \
77 (sizeof(TMS470R1A256_SECTORS)/sizeof(TMS470R1A256_SECTORS[0]))
78
79 const flash_sector_t TMS470R1A288_BANK0_SECTORS[] = {
80 {0x00000000, 0x00002000, -1, -1},
81 {0x00002000, 0x00002000, -1, -1},
82 {0x00004000, 0x00002000, -1, -1},
83 {0x00006000, 0x00002000, -1, -1},
84 };
85
86 #define TMS470R1A288_BANK0_NUM_SECTORS \
87 (sizeof(TMS470R1A288_BANK0_SECTORS)/sizeof(TMS470R1A288_BANK0_SECTORS[0]))
88
89 const flash_sector_t TMS470R1A288_BANK1_SECTORS[] = {
90 {0x00040000, 0x00010000, -1, -1},
91 {0x00050000, 0x00010000, -1, -1},
92 {0x00060000, 0x00010000, -1, -1},
93 {0x00070000, 0x00010000, -1, -1},
94 };
95
96 #define TMS470R1A288_BANK1_NUM_SECTORS \
97 (sizeof(TMS470R1A288_BANK1_SECTORS)/sizeof(TMS470R1A288_BANK1_SECTORS[0]))
98
99 /* ---------------------------------------------------------------------- */
100
101 int tms470_read_part_info(struct flash_bank_s *bank)
102 {
103 tms470_flash_bank_t *tms470_info = bank->driver_priv;
104 target_t *target = bank->target;
105 u32 device_ident_reg;
106 u32 silicon_version;
107 u32 technology_family;
108 u32 rom_flash;
109 u32 part_number;
110 char *part_name;
111
112 if (target->state != TARGET_HALTED)
113 {
114 WARNING("Cannot communicate... target not halted.");
115 return ERROR_TARGET_NOT_HALTED;
116 }
117
118 /* read and parse the device identification register */
119 target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
120
121 INFO("device_ident_reg=0x%08x", device_ident_reg);
122
123 if ((device_ident_reg & 7) == 0)
124 {
125 WARNING("Cannot identify target as a TMS470 family.");
126 return ERROR_FLASH_OPERATION_FAILED;
127 }
128
129 silicon_version = (device_ident_reg >> 12) & 0xF;
130 technology_family = (device_ident_reg >> 11) & 1;
131 rom_flash = (device_ident_reg >> 10) & 1;
132 part_number = (device_ident_reg >> 3) & 0x7f;
133
134 /*
135 * If the part number is known, determine if the flash bank is valid
136 * based on the base address being within the known flash bank
137 * ranges. Then fixup/complete the remaining fields of the flash
138 * bank structure.
139 */
140 switch (part_number)
141 {
142 case 0x0a:
143 part_name = "TMS470R1A256";
144
145 if (bank->base >= 0x00040000)
146 {
147 ERROR("No %s flash bank contains base address 0x%08x.", part_name, bank->base);
148 return ERROR_FLASH_OPERATION_FAILED;
149 }
150 tms470_info->ordinal = 0;
151 bank->base = 0x00000000;
152 bank->size = 256 * 1024;
153 bank->num_sectors = TMS470R1A256_NUM_SECTORS;
154 bank->sectors = malloc(sizeof(TMS470R1A256_SECTORS));
155 if (!bank->sectors)
156 {
157 return ERROR_FLASH_OPERATION_FAILED;
158 }
159 (void)memcpy(bank->sectors, TMS470R1A256_SECTORS, sizeof(TMS470R1A256_SECTORS));
160 break;
161
162 case 0x2b:
163 part_name = "TMS470R1A288";
164
165 if ((bank->base >= 0x00000000) && (bank->base < 0x00008000))
166 {
167 tms470_info->ordinal = 0;
168 bank->base = 0x00000000;
169 bank->size = 32 * 1024;
170 bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
171 bank->sectors = malloc(sizeof(TMS470R1A288_BANK0_SECTORS));
172 if (!bank->sectors)
173 {
174 return ERROR_FLASH_OPERATION_FAILED;
175 }
176 (void)memcpy(bank->sectors, TMS470R1A288_BANK0_SECTORS, sizeof(TMS470R1A288_BANK0_SECTORS));
177 }
178 else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000))
179 {
180 tms470_info->ordinal = 1;
181 bank->base = 0x00040000;
182 bank->size = 256 * 1024;
183 bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
184 bank->sectors = malloc(sizeof(TMS470R1A288_BANK1_SECTORS));
185 if (!bank->sectors)
186 {
187 return ERROR_FLASH_OPERATION_FAILED;
188 }
189 (void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS, sizeof(TMS470R1A288_BANK1_SECTORS));
190 }
191 else
192 {
193 ERROR("No %s flash bank contains base address 0x%08x.", part_name, bank->base);
194 return ERROR_FLASH_OPERATION_FAILED;
195 }
196 break;
197
198 default:
199 WARNING("Could not identify part 0x%02x as a member of the TMS470 family.", part_number);
200 return ERROR_FLASH_OPERATION_FAILED;
201 }
202
203 /* turn off memory selects */
204 target_write_u32(target, 0xFFFFFFE4, 0x00000000);
205 target_write_u32(target, 0xFFFFFFE0, 0x00000000);
206
207 bank->chip_width = 32;
208 bank->bus_width = 32;
209
210 INFO("Identified %s, ver=%d, core=%s, nvmem=%s.", part_name, silicon_version, (technology_family ? "1.8v" : "3.3v"), (rom_flash ? "rom" : "flash"));
211
212 tms470_info->device_ident_reg = device_ident_reg;
213 tms470_info->silicon_version = silicon_version;
214 tms470_info->technology_family = technology_family;
215 tms470_info->rom_flash = rom_flash;
216 tms470_info->part_number = part_number;
217 tms470_info->part_name = part_name;
218
219 /*
220 * Disable reset on address access violation.
221 */
222 target_write_u32(target, 0xFFFFFFE0, 0x00004007);
223
224 return ERROR_OK;
225 }
226
227 /* ---------------------------------------------------------------------- */
228
229 u32 keysSet = 0;
230 u32 flashKeys[4];
231
232 int tms470_handle_flash_keyset_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
233 {
234 if (argc > 4)
235 {
236 command_print(cmd_ctx, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
237 return ERROR_INVALID_ARGUMENTS;
238 }
239 else if (argc == 4)
240 {
241 int i;
242
243 for (i = 0; i < 4; i++)
244 {
245 int start = (0 == strncmp(args[i], "0x", 2)) ? 2 : 0;
246
247 if (1 != sscanf(&args[i][start], "%x", &flashKeys[i]))
248 {
249 command_print(cmd_ctx, "could not process flash key %s", args[i]);
250 ERROR("could not process flash key %s", args[i]);
251 return ERROR_INVALID_ARGUMENTS;
252 }
253 }
254
255 keysSet = 1;
256 }
257 else if (argc != 0)
258 {
259 command_print(cmd_ctx, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
260 return ERROR_INVALID_ARGUMENTS;
261 }
262
263 if (keysSet)
264 {
265 command_print(cmd_ctx, "using flash keys 0x%08x, 0x%08x, 0x%08x, 0x%08x", flashKeys[0], flashKeys[1], flashKeys[2], flashKeys[3]);
266 }
267 else
268 {
269 command_print(cmd_ctx, "flash keys not set");
270 }
271
272 return ERROR_OK;
273 }
274
275 const u32 FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
276 0xFFFFFFFF, 0xFFFFFFFF,
277 };
278
279 const u32 FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
280 0x00000000, 0x00000000,
281 };
282
283 const u32 FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
284 0xf0fff0ff, 0xf0fff0ff
285 };
286
287 const u32 FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
288 0x0000ffff, 0x0000ffff
289 };
290
291 /* ---------------------------------------------------------------------- */
292
293 int oscMHz = 12;
294
295 int tms470_handle_osc_megahertz_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
296 {
297 if (argc > 1)
298 {
299 command_print(cmd_ctx, "tms470 osc_megahertz <MHz>");
300 return ERROR_INVALID_ARGUMENTS;
301 }
302 else if (argc == 1)
303 {
304 sscanf(args[0], "%d", &oscMHz);
305 }
306
307 if (oscMHz <= 0)
308 {
309 ERROR("osc_megahertz must be positive and non-zero!");
310 command_print(cmd_ctx, "osc_megahertz must be positive and non-zero!");
311 oscMHz = 12;
312 return ERROR_INVALID_ARGUMENTS;
313 }
314
315 command_print(cmd_ctx, "osc_megahertz=%d", oscMHz);
316
317 return ERROR_OK;
318 }
319
320 /* ---------------------------------------------------------------------- */
321
322 int plldis = 0;
323
324 int tms470_handle_plldis_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
325 {
326 if (argc > 1)
327 {
328 command_print(cmd_ctx, "tms470 plldis <0|1>");
329 return ERROR_INVALID_ARGUMENTS;
330 }
331 else if (argc == 1)
332 {
333 sscanf(args[0], "%d", &plldis);
334 plldis = plldis ? 1 : 0;
335 }
336
337 command_print(cmd_ctx, "plldis=%d", plldis);
338
339 return ERROR_OK;
340 }
341
342 /* ---------------------------------------------------------------------- */
343
344 int tms470_check_flash_unlocked(target_t * target)
345 {
346 u32 fmbbusy;
347
348 target_read_u32(target, 0xFFE89C08, &fmbbusy);
349 INFO("tms470 fmbbusy=0x%08x -> %s", fmbbusy, fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
350 return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
351 }
352
353 /* ---------------------------------------------------------------------- */
354
355 int tms470_try_flash_keys(target_t * target, const u32 * key_set)
356 {
357 u32 glbctrl, fmmstat;
358 int retval = ERROR_FLASH_OPERATION_FAILED;
359
360 /* set GLBCTRL.4 */
361 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
362 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
363
364 /* only perform the key match when 3VSTAT is clear */
365 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
366 if (!(fmmstat & 0x08))
367 {
368 unsigned i;
369 u32 fmbptr, fmbac2, orig_fmregopt;
370
371 target_write_u32(target, 0xFFE8BC04, fmmstat & ~0x07);
372
373 /* wait for pump ready */
374 do
375 {
376 target_read_u32(target, 0xFFE8A814, &fmbptr);
377 usleep(1000);
378 }
379 while (!(fmbptr & 0x0200));
380
381 /* force max wait states */
382 target_read_u32(target, 0xFFE88004, &fmbac2);
383 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
384
385 /* save current access mode, force normal read mode */
386 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
387 target_write_u32(target, 0xFFE89C00, 0x00);
388
389 for (i = 0; i < 4; i++)
390 {
391 u32 tmp;
392
393 /* There is no point displaying the value of tmp, it is
394 * filtered by the chip. The purpose of this read is to
395 * prime the unlocking logic rather than read out the value.
396 */
397 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
398
399 INFO("tms470 writing fmpkey=0x%08x", key_set[i]);
400 target_write_u32(target, 0xFFE89C0C, key_set[i]);
401 }
402
403 if (ERROR_OK == tms470_check_flash_unlocked(target))
404 {
405 /*
406 * There seems to be a side-effect of reading the FMPKEY
407 * register in that it re-enables the protection. So we
408 * re-enable it.
409 */
410 for (i = 0; i < 4; i++)
411 {
412 u32 tmp;
413
414 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
415 target_write_u32(target, 0xFFE89C0C, key_set[i]);
416 }
417 retval = ERROR_OK;
418 }
419
420 /* restore settings */
421 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
422 target_write_u32(target, 0xFFE88004, fmbac2);
423 }
424
425 /* clear config bit */
426 target_write_u32(target, 0xFFFFFFDC, glbctrl);
427
428 return retval;
429 }
430
431 /* ---------------------------------------------------------------------- */
432
433 int tms470_unlock_flash(struct flash_bank_s *bank)
434 {
435 target_t *target = bank->target;
436 const u32 *p_key_sets[5];
437 unsigned i, key_set_count;
438
439 if (keysSet)
440 {
441 p_key_sets[0] = flashKeys;
442 p_key_sets[1] = FLASH_KEYS_ALL_ONES;
443 p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
444 p_key_sets[3] = FLASH_KEYS_MIX1;
445 p_key_sets[4] = FLASH_KEYS_MIX2;
446 }
447 else
448 {
449 key_set_count = 4;
450 p_key_sets[0] = FLASH_KEYS_ALL_ONES;
451 p_key_sets[1] = FLASH_KEYS_ALL_ZEROS;
452 p_key_sets[2] = FLASH_KEYS_MIX1;
453 p_key_sets[3] = FLASH_KEYS_MIX2;
454 }
455
456 for (i = 0; i < key_set_count; i++)
457 {
458 if (tms470_try_flash_keys(target, p_key_sets[i]) == ERROR_OK)
459 {
460 INFO("tms470 flash is unlocked");
461 return ERROR_OK;
462 }
463 }
464
465 WARNING("tms470 could not unlock flash memory protection level 2");
466 return ERROR_FLASH_OPERATION_FAILED;
467 }
468
469 /* ---------------------------------------------------------------------- */
470
471 int tms470_flash_initialize_internal_state_machine(struct flash_bank_s *bank)
472 {
473 u32 fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
474 target_t *target = bank->target;
475 tms470_flash_bank_t *tms470_info = bank->driver_priv;
476 int result = ERROR_OK;
477
478 /*
479 * Select the desired bank to be programmed by writing BANK[2:0] of
480 * FMMAC2.
481 */
482 target_read_u32(target, 0xFFE8BC04, &fmmac2);
483 fmmac2 &= ~0x0007;
484 fmmac2 |= (tms470_info->ordinal & 7);
485 target_write_u32(target, 0xFFE8BC04, fmmac2);
486 DEBUG("set fmmac2=0x%04x", fmmac2);
487
488 /*
489 * Disable level 1 sector protection by setting bit 15 of FMMAC1.
490 */
491 target_read_u32(target, 0xFFE8BC00, &fmmac1);
492 fmmac1 |= 0x8000;
493 target_write_u32(target, 0xFFE8BC00, fmmac1);
494 DEBUG("set fmmac1=0x%04x", fmmac1);
495
496 /*
497 * FMTCREG=0x2fc0;
498 */
499 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
500 DEBUG("set fmtcreg=0x2fc0");
501
502 /*
503 * MAXPP=50
504 */
505 target_write_u32(target, 0xFFE8A07C, 50);
506 DEBUG("set fmmaxpp=50");
507
508 /*
509 * MAXCP=0xf000+2000
510 */
511 target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
512 DEBUG("set fmmaxcp=0x%04x", 0xf000 + 2000);
513
514 /*
515 * configure VHV
516 */
517 target_read_u32(target, 0xFFE8A080, &fmmaxep);
518 if (fmmaxep == 0xf000)
519 {
520 fmmaxep = 0xf000 + 4095;
521 target_write_u32(target, 0xFFE8A80C, 0x9964);
522 DEBUG("set fmptr3=0x9964");
523 }
524 else
525 {
526 fmmaxep = 0xa000 + 4095;
527 target_write_u32(target, 0xFFE8A80C, 0x9b64);
528 DEBUG("set fmptr3=0x9b64");
529 }
530 target_write_u32(target, 0xFFE8A080, fmmaxep);
531 DEBUG("set fmmaxep=0x%04x", fmmaxep);
532
533 /*
534 * FMPTR4=0xa000
535 */
536 target_write_u32(target, 0xFFE8A810, 0xa000);
537 DEBUG("set fmptr4=0xa000");
538
539 /*
540 * FMPESETUP, delay parameter selected based on clock frequency.
541 *
542 * According to the TI App Note SPNU257 and flashing code, delay is
543 * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
544 * clock is usually derived from the ZPLL module, and selected by
545 * the plldis global.
546 */
547 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
548 sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7));
549 delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
550 target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
551 DEBUG("set fmpsetup=0x%04x", (delay << 4) | (delay << 8));
552
553 /*
554 * FMPVEVACCESS, based on delay.
555 */
556 k = delay | (delay << 8);
557 target_write_u32(target, 0xFFE8A05C, k);
558 DEBUG("set fmpvevaccess=0x%04x", k);
559
560 /*
561 * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
562 */
563 k <<= 1;
564 target_write_u32(target, 0xFFE8A034, k);
565 DEBUG("set fmpchold=0x%04x", k);
566 target_write_u32(target, 0xFFE8A040, k);
567 DEBUG("set fmpvevhold=0x%04x", k);
568 target_write_u32(target, 0xFFE8A024, k);
569 DEBUG("set fmpvevsetup=0x%04x", k);
570
571 /*
572 * FMCVACCESS, based on delay.
573 */
574 k = delay * 16;
575 target_write_u32(target, 0xFFE8A060, k);
576 DEBUG("set fmcvaccess=0x%04x", k);
577
578 /*
579 * FMCSETUP, based on delay.
580 */
581 k = 0x3000 | delay * 20;
582 target_write_u32(target, 0xFFE8A020, k);
583 DEBUG("set fmcsetup=0x%04x", k);
584
585 /*
586 * FMEHOLD, based on delay.
587 */
588 k = (delay * 20) << 2;
589 target_write_u32(target, 0xFFE8A038, k);
590 DEBUG("set fmehold=0x%04x", k);
591
592 /*
593 * PWIDTH, CWIDTH, EWIDTH, based on delay.
594 */
595 target_write_u32(target, 0xFFE8A050, delay * 8);
596 DEBUG("set fmpwidth=0x%04x", delay * 8);
597 target_write_u32(target, 0xFFE8A058, delay * 1000);
598 DEBUG("set fmcwidth=0x%04x", delay * 1000);
599 target_write_u32(target, 0xFFE8A054, delay * 5400);
600 DEBUG("set fmewidth=0x%04x", delay * 5400);
601
602 return result;
603 }
604
605 /* ---------------------------------------------------------------------- */
606
607 int tms470_flash_status(struct flash_bank_s *bank)
608 {
609 target_t *target = bank->target;
610 int result = ERROR_OK;
611 u32 fmmstat;
612
613 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
614 DEBUG("set fmmstat=0x%04x", fmmstat);
615
616 if (fmmstat & 0x0080)
617 {
618 WARNING("tms470 flash command: erase still active after busy clear.");
619 result = ERROR_FLASH_OPERATION_FAILED;
620 }
621
622 if (fmmstat & 0x0040)
623 {
624 WARNING("tms470 flash command: program still active after busy clear.");
625 result = ERROR_FLASH_OPERATION_FAILED;
626 }
627
628 if (fmmstat & 0x0020)
629 {
630 WARNING("tms470 flash command: invalid data command.");
631 result = ERROR_FLASH_OPERATION_FAILED;
632 }
633
634 if (fmmstat & 0x0010)
635 {
636 WARNING("tms470 flash command: program, erase or validate sector failed.");
637 result = ERROR_FLASH_OPERATION_FAILED;
638 }
639
640 if (fmmstat & 0x0008)
641 {
642 WARNING("tms470 flash command: voltage instability detected.");
643 result = ERROR_FLASH_OPERATION_FAILED;
644 }
645
646 if (fmmstat & 0x0006)
647 {
648 WARNING("tms470 flash command: command suspend detected.");
649 result = ERROR_FLASH_OPERATION_FAILED;
650 }
651
652 if (fmmstat & 0x0001)
653 {
654 WARNING("tms470 flash command: sector was locked.");
655 result = ERROR_FLASH_OPERATION_FAILED;
656 }
657
658 return result;
659 }
660
661 /* ---------------------------------------------------------------------- */
662
663 int tms470_erase_sector(struct flash_bank_s *bank, int sector)
664 {
665 u32 glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
666 target_t *target = bank->target;
667 u32 flashAddr = bank->base + bank->sectors[sector].offset;
668 int result = ERROR_OK;
669
670 /*
671 * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
672 * module) to enable writing to the flash registers }.
673 */
674 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
675 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
676 DEBUG("set glbctrl=0x%08x", glbctrl | 0x10);
677
678 /* Force normal read mode. */
679 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
680 target_write_u32(target, 0xFFE89C00, 0);
681 DEBUG("set fmregopt=0x%08x", 0);
682
683 (void)tms470_flash_initialize_internal_state_machine(bank);
684
685 /*
686 * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
687 * protection for the particular sector to be erased/written.
688 */
689 if (sector < 16)
690 {
691 target_read_u32(target, 0xFFE88008, &fmbsea);
692 target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
693 DEBUG("set fmbsea=0x%04x", fmbsea | (1 << sector));
694 }
695 else
696 {
697 target_read_u32(target, 0xFFE8800C, &fmbseb);
698 target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
699 DEBUG("set fmbseb=0x%04x", fmbseb | (1 << (sector - 16)));
700 }
701 bank->sectors[sector].is_protected = 0;
702
703 /*
704 * clear status regiser, sent erase command, kickoff erase
705 */
706 target_write_u16(target, flashAddr, 0x0040);
707 DEBUG("write *(u16 *)0x%08x=0x0040", flashAddr);
708 target_write_u16(target, flashAddr, 0x0020);
709 DEBUG("write *(u16 *)0x%08x=0x0020", flashAddr);
710 target_write_u16(target, flashAddr, 0xffff);
711 DEBUG("write *(u16 *)0x%08x=0xffff", flashAddr);
712
713 /*
714 * Monitor FMMSTAT, busy until clear, then check and other flags for
715 * ultimate result of the operation.
716 */
717 do
718 {
719 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
720 if (fmmstat & 0x0100)
721 {
722 usleep(1000);
723 }
724 }
725 while (fmmstat & 0x0100);
726
727 result = tms470_flash_status(bank);
728
729 if (sector < 16)
730 {
731 target_write_u32(target, 0xFFE88008, fmbsea);
732 DEBUG("set fmbsea=0x%04x", fmbsea);
733 bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
734 }
735 else
736 {
737 target_write_u32(target, 0xFFE8800C, fmbseb);
738 DEBUG("set fmbseb=0x%04x", fmbseb);
739 bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
740 }
741 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
742 DEBUG("set fmregopt=0x%08x", orig_fmregopt);
743 target_write_u32(target, 0xFFFFFFDC, glbctrl);
744 DEBUG("set glbctrl=0x%08x", glbctrl);
745
746 if (result == ERROR_OK)
747 {
748 bank->sectors[sector].is_erased = 1;
749 }
750
751 return result;
752 }
753
754 /* ----------------------------------------------------------------------
755 Implementation of Flash Driver Interfaces
756 ---------------------------------------------------------------------- */
757
758 int tms470_register_commands(struct command_context_s *cmd_ctx)
759 {
760 command_t *tms470_cmd = register_command(cmd_ctx, NULL, "tms470", NULL, COMMAND_ANY, "applies to TI tms470 family");
761
762 register_command(cmd_ctx, tms470_cmd, "flash_keyset", tms470_handle_flash_keyset_command, COMMAND_ANY, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
763 register_command(cmd_ctx, tms470_cmd, "osc_megahertz", tms470_handle_osc_megahertz_command, COMMAND_ANY, "tms470 osc_megahertz <MHz>");
764 register_command(cmd_ctx, tms470_cmd, "plldis", tms470_handle_plldis_command, COMMAND_ANY, "tms470 plldis <0/1>");
765
766 return ERROR_OK;
767 }
768
769 /* ---------------------------------------------------------------------- */
770
771 int tms470_erase(struct flash_bank_s *bank, int first, int last)
772 {
773 tms470_flash_bank_t *tms470_info = bank->driver_priv;
774 int sector, result = ERROR_OK;
775
776 if (!tms470_info->device_ident_reg)
777 {
778 tms470_read_part_info(bank);
779 }
780
781 if ((first < 0) || (first >= bank->num_sectors) || (last < 0) || (last >= bank->num_sectors) || (first > last))
782 {
783 ERROR("Sector range %d to %d invalid.", first, last);
784 return ERROR_FLASH_SECTOR_INVALID;
785 }
786
787 result = tms470_unlock_flash(bank);
788 if (result != ERROR_OK)
789 {
790 return result;
791 }
792
793 for (sector = first; sector <= last; sector++)
794 {
795 INFO("Erasing tms470 bank %d sector %d...", tms470_info->ordinal, sector);
796
797 result = tms470_erase_sector(bank, sector);
798
799 if (result != ERROR_OK)
800 {
801 ERROR("tms470 could not erase flash sector.");
802 break;
803 }
804 else
805 {
806 INFO("sector erased successfully.");
807 }
808 }
809
810 return result;
811 }
812
813 /* ---------------------------------------------------------------------- */
814
815 int tms470_protect(struct flash_bank_s *bank, int set, int first, int last)
816 {
817 tms470_flash_bank_t *tms470_info = bank->driver_priv;
818 target_t *target = bank->target;
819 u32 fmmac2, fmbsea, fmbseb;
820 int sector;
821
822 if (!tms470_info->device_ident_reg)
823 {
824 tms470_read_part_info(bank);
825 }
826
827 if ((first < 0) || (first >= bank->num_sectors) || (last < 0) || (last >= bank->num_sectors) || (first > last))
828 {
829 ERROR("Sector range %d to %d invalid.", first, last);
830 return ERROR_FLASH_SECTOR_INVALID;
831 }
832
833 /* enable the appropriate bank */
834 target_read_u32(target, 0xFFE8BC04, &fmmac2);
835 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
836
837 /* get the original sector proection flags for this bank */
838 target_read_u32(target, 0xFFE88008, &fmbsea);
839 target_read_u32(target, 0xFFE8800C, &fmbseb);
840
841 for (sector = 0; sector < bank->num_sectors; sector++)
842 {
843 if (sector < 16)
844 {
845 fmbsea = set ? fmbsea & ~(1 << sector) : fmbsea | (1 << sector);
846 bank->sectors[sector].is_protected = set ? 1 : 0;
847 }
848 else
849 {
850 fmbseb = set ? fmbseb & ~(1 << (sector - 16)) : fmbseb | (1 << (sector - 16));
851 bank->sectors[sector].is_protected = set ? 1 : 0;
852 }
853 }
854
855 /* update the protection bits */
856 target_write_u32(target, 0xFFE88008, fmbsea);
857 target_write_u32(target, 0xFFE8800C, fmbseb);
858
859 return ERROR_OK;
860 }
861
862 /* ---------------------------------------------------------------------- */
863
864 int tms470_write(struct flash_bank_s *bank, u8 * buffer, u32 offset, u32 count)
865 {
866 target_t *target = bank->target;
867 tms470_flash_bank_t *tms470_info = bank->driver_priv;
868 u32 glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
869 int i, result = ERROR_OK;
870
871 if (!tms470_info->device_ident_reg)
872 {
873 tms470_read_part_info(bank);
874 }
875
876 INFO("Writing %d bytes starting at 0x%08x", count, bank->base + offset);
877
878 /* set GLBCTRL.4 */
879 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
880 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
881
882 (void)tms470_flash_initialize_internal_state_machine(bank);
883
884 /* force max wait states */
885 target_read_u32(target, 0xFFE88004, &fmbac2);
886 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
887
888 /* save current access mode, force normal read mode */
889 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
890 target_write_u32(target, 0xFFE89C00, 0x00);
891
892 /*
893 * Disable Level 1 protection for all sectors to be erased/written.
894 */
895 target_read_u32(target, 0xFFE88008, &fmbsea);
896 target_write_u32(target, 0xFFE88008, 0xffff);
897 target_read_u32(target, 0xFFE8800C, &fmbseb);
898 target_write_u32(target, 0xFFE8800C, 0xffff);
899
900 /* read MAXPP */
901 target_read_u32(target, 0xFFE8A07C, &fmmaxpp);
902
903 for (i = 0; i < count; i += 2)
904 {
905 u32 addr = bank->base + offset + i;
906 u16 word = (((u16) buffer[i]) << 8) | (u16) buffer[i + 1];
907
908 if (word != 0xffff)
909 {
910 INFO("writing 0x%04x at 0x%08x", word, addr);
911
912 /* clear status register */
913 target_write_u16(target, addr, 0x0040);
914 /* program flash command */
915 target_write_u16(target, addr, 0x0010);
916 /* burn the 16-bit word (big-endian) */
917 target_write_u16(target, addr, word);
918
919 /*
920 * Monitor FMMSTAT, busy until clear, then check and other flags
921 * for ultimate result of the operation.
922 */
923 do
924 {
925 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
926 if (fmmstat & 0x0100)
927 {
928 usleep(1000);
929 }
930 }
931 while (fmmstat & 0x0100);
932
933 if (fmmstat & 0x3ff)
934 {
935 ERROR("fmstat=0x%04x", fmmstat);
936 ERROR("Could not program word 0x%04x at address 0x%08x.", word, addr);
937 result = ERROR_FLASH_OPERATION_FAILED;
938 break;
939 }
940 }
941 else
942 {
943 INFO("skipping 0xffff at 0x%08x", addr);
944 }
945 }
946
947 /* restore */
948 target_write_u32(target, 0xFFE88008, fmbsea);
949 target_write_u32(target, 0xFFE8800C, fmbseb);
950 target_write_u32(target, 0xFFE88004, fmbac2);
951 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
952 target_write_u32(target, 0xFFFFFFDC, glbctrl);
953
954 return result;
955 }
956
957 /* ---------------------------------------------------------------------- */
958
959 int tms470_probe(struct flash_bank_s *bank)
960 {
961 tms470_flash_bank_t *tms470_info = bank->driver_priv;
962
963 tms470_info->probed = 0;
964
965 if (!tms470_info->device_ident_reg)
966 {
967 tms470_read_part_info(bank);
968 }
969
970 tms470_info->probed = 1;
971
972 return ERROR_OK;
973 }
974
975 int tms470_auto_probe(struct flash_bank_s *bank)
976 {
977 tms470_flash_bank_t *tms470_info = bank->driver_priv;
978
979 if (tms470_info->probed)
980 return ERROR_OK;
981 return tms470_probe(bank);
982 }
983
984 /* ---------------------------------------------------------------------- */
985
986 int tms470_erase_check(struct flash_bank_s *bank)
987 {
988 target_t *target = bank->target;
989 tms470_flash_bank_t *tms470_info = bank->driver_priv;
990 int sector, result = ERROR_OK;
991 u32 fmmac2, fmbac2, glbctrl, orig_fmregopt;
992 static u8 buffer[64 * 1024];
993
994 if (!tms470_info->device_ident_reg)
995 {
996 tms470_read_part_info(bank);
997 }
998
999 /* set GLBCTRL.4 */
1000 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
1001 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
1002
1003 /* save current access mode, force normal read mode */
1004 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
1005 target_write_u32(target, 0xFFE89C00, 0x00);
1006
1007 /* enable the appropriate bank */
1008 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1009 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1010
1011 /* TCR=0 */
1012 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
1013
1014 /* clear TEZ in fmbrdy */
1015 target_write_u32(target, 0xFFE88010, 0x0b);
1016
1017 /* save current wait states, force max */
1018 target_read_u32(target, 0xFFE88004, &fmbac2);
1019 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
1020
1021 /*
1022 * The TI primitives inspect the flash memory by reading one 32-bit
1023 * word at a time. Here we read an entire sector and inspect it in
1024 * an attempt to reduce the JTAG overhead.
1025 */
1026 for (sector = 0; sector < bank->num_sectors; sector++)
1027 {
1028 if (bank->sectors[sector].is_erased != 1)
1029 {
1030 u32 i, addr = bank->base + bank->sectors[sector].offset;
1031
1032 INFO("checking flash bank %d sector %d", tms470_info->ordinal, sector);
1033
1034 target_read_buffer(target, addr, bank->sectors[sector].size, buffer);
1035
1036 bank->sectors[sector].is_erased = 1;
1037 for (i = 0; i < bank->sectors[sector].size; i++)
1038 {
1039 if (buffer[i] != 0xff)
1040 {
1041 WARNING("tms470 bank %d, sector %d, not erased.", tms470_info->ordinal, sector);
1042 WARNING("at location 0x%08x: flash data is 0x%02x.", addr + i, buffer[i]);
1043
1044 bank->sectors[sector].is_erased = 0;
1045 break;
1046 }
1047 }
1048 }
1049 if (bank->sectors[sector].is_erased != 1)
1050 {
1051 result = ERROR_FLASH_SECTOR_NOT_ERASED;
1052 break;
1053 }
1054 else
1055 {
1056 INFO("sector erased");
1057 }
1058 }
1059
1060 /* reset TEZ, wait states, read mode, GLBCTRL.4 */
1061 target_write_u32(target, 0xFFE88010, 0x0f);
1062 target_write_u32(target, 0xFFE88004, fmbac2);
1063 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
1064 target_write_u32(target, 0xFFFFFFDC, glbctrl);
1065
1066 return result;
1067 }
1068
1069 /* ---------------------------------------------------------------------- */
1070
1071 int tms470_protect_check(struct flash_bank_s *bank)
1072 {
1073 target_t *target = bank->target;
1074 tms470_flash_bank_t *tms470_info = bank->driver_priv;
1075 int sector, result = ERROR_OK;
1076 u32 fmmac2, fmbsea, fmbseb;
1077
1078 if (!tms470_info->device_ident_reg)
1079 {
1080 tms470_read_part_info(bank);
1081 }
1082
1083 /* enable the appropriate bank */
1084 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1085 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1086
1087 target_read_u32(target, 0xFFE88008, &fmbsea);
1088 target_read_u32(target, 0xFFE8800C, &fmbseb);
1089
1090 for (sector = 0; sector < bank->num_sectors; sector++)
1091 {
1092 int protected;
1093
1094 if (sector < 16)
1095 {
1096 protected = fmbsea & (1 << sector) ? 0 : 1;
1097 bank->sectors[sector].is_protected = protected;
1098 }
1099 else
1100 {
1101 protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
1102 bank->sectors[sector].is_protected = protected;
1103 }
1104
1105 DEBUG("bank %d sector %d is %s", tms470_info->ordinal, sector, protected ? "protected" : "not protected");
1106 }
1107
1108 return result;
1109 }
1110
1111 /* ---------------------------------------------------------------------- */
1112
1113 int tms470_info(struct flash_bank_s *bank, char *buf, int buf_size)
1114 {
1115 int used = 0;
1116 tms470_flash_bank_t *tms470_info = bank->driver_priv;
1117
1118 if (!tms470_info->device_ident_reg)
1119 {
1120 tms470_read_part_info(bank);
1121 }
1122
1123 if (!tms470_info->device_ident_reg)
1124 {
1125 (void)snprintf(buf, buf_size, "Cannot identify target as a TMS470\n");
1126 return ERROR_FLASH_OPERATION_FAILED;
1127 }
1128
1129 used += snprintf(buf, buf_size, "\ntms470 information: Chip is %s\n", tms470_info->part_name);
1130 buf += used;
1131 buf_size -= used;
1132
1133 used += snprintf(buf, buf_size, "Flash protection level 2 is %s\n", tms470_check_flash_unlocked(bank->target) == ERROR_OK ? "disabled" : "enabled");
1134 buf += used;
1135 buf_size -= used;
1136
1137 return ERROR_OK;
1138 }
1139
1140 /* ---------------------------------------------------------------------- */
1141
1142 /*
1143 * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
1144 * [options...]
1145 */
1146
1147 int tms470_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
1148 {
1149 bank->driver_priv = malloc(sizeof(tms470_flash_bank_t));
1150
1151 if (!bank->driver_priv)
1152 {
1153 return ERROR_FLASH_OPERATION_FAILED;
1154 }
1155
1156 (void)memset(bank->driver_priv, 0, sizeof(tms470_flash_bank_t));
1157
1158 return ERROR_OK;
1159 }
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