1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
32 #include "algorithm.h"
33 #include "binarybuffer.h"
39 static u32 bank1start
= 0x00080000;
41 int str9x_register_commands(struct command_context_s
*cmd_ctx
);
42 int str9x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
43 int str9x_erase(struct flash_bank_s
*bank
, int first
, int last
);
44 int str9x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
45 int str9x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
46 int str9x_probe(struct flash_bank_s
*bank
);
47 int str9x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
48 int str9x_protect_check(struct flash_bank_s
*bank
);
49 int str9x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
51 int str9x_handle_flash_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 flash_driver_t str9x_flash
=
56 .register_commands
= str9x_register_commands
,
57 .flash_bank_command
= str9x_flash_bank_command
,
59 .protect
= str9x_protect
,
62 .auto_probe
= str9x_probe
,
63 .erase_check
= default_flash_blank_check
,
64 .protect_check
= str9x_protect_check
,
68 int str9x_register_commands(struct command_context_s
*cmd_ctx
)
70 command_t
*str9x_cmd
= register_command(cmd_ctx
, NULL
, "str9x", NULL
, COMMAND_ANY
, NULL
);
72 register_command(cmd_ctx
, str9x_cmd
, "flash_config", str9x_handle_flash_config_command
, COMMAND_EXEC
,
73 "configure str9 flash controller");
78 int str9x_build_block_list(struct flash_bank_s
*bank
)
80 str9x_flash_bank_t
*str9x_info
= bank
->driver_priv
;
84 int b0_sectors
= 0, b1_sectors
= 0;
87 /* set if we have large flash str9 */
88 str9x_info
->variant
= 0;
89 str9x_info
->bank1
= 0;
100 bank1start
= 0x00100000;
101 str9x_info
->variant
= 1;
105 bank1start
= 0x00200000;
106 str9x_info
->variant
= 1;
110 str9x_info
->variant
= 1;
111 str9x_info
->bank1
= 1;
113 bank1start
= bank
->base
;
116 str9x_info
->bank1
= 1;
118 bank1start
= bank
->base
;
121 LOG_ERROR("BUG: unknown bank->size encountered");
125 num_sectors
= b0_sectors
+ b1_sectors
;
127 bank
->num_sectors
= num_sectors
;
128 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
129 str9x_info
->sector_bits
= malloc(sizeof(u32
) * num_sectors
);
133 for (i
= 0; i
< b0_sectors
; i
++)
135 bank
->sectors
[num_sectors
].offset
= offset
;
136 bank
->sectors
[num_sectors
].size
= 0x10000;
137 offset
+= bank
->sectors
[i
].size
;
138 bank
->sectors
[num_sectors
].is_erased
= -1;
139 bank
->sectors
[num_sectors
].is_protected
= 1;
140 str9x_info
->sector_bits
[num_sectors
++] = (1<<i
);
143 for (i
= 0; i
< b1_sectors
; i
++)
145 bank
->sectors
[num_sectors
].offset
= offset
;
146 bank
->sectors
[num_sectors
].size
= str9x_info
->variant
== 0 ? 0x2000 : 0x4000;
147 offset
+= bank
->sectors
[i
].size
;
148 bank
->sectors
[num_sectors
].is_erased
= -1;
149 bank
->sectors
[num_sectors
].is_protected
= 1;
150 if (str9x_info
->variant
)
151 str9x_info
->sector_bits
[num_sectors
++] = (1<<i
);
153 str9x_info
->sector_bits
[num_sectors
++] = (1<<(i
+8));
159 /* flash bank str9x <base> <size> 0 0 <target#>
161 int str9x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
163 str9x_flash_bank_t
*str9x_info
;
167 LOG_WARNING("incomplete flash_bank str9x configuration");
168 return ERROR_FLASH_BANK_INVALID
;
171 str9x_info
= malloc(sizeof(str9x_flash_bank_t
));
172 bank
->driver_priv
= str9x_info
;
174 str9x_build_block_list(bank
);
176 str9x_info
->write_algorithm
= NULL
;
181 int str9x_protect_check(struct flash_bank_s
*bank
)
183 str9x_flash_bank_t
*str9x_info
= bank
->driver_priv
;
184 target_t
*target
= bank
->target
;
190 if (bank
->target
->state
!= TARGET_HALTED
)
192 return ERROR_TARGET_NOT_HALTED
;
195 /* read level one protection */
197 if (str9x_info
->variant
)
199 if (str9x_info
->bank1
)
201 adr
= bank1start
+ 0x18;
202 target_write_u16(target
, adr
, 0x90);
203 target_read_u16(target
, adr
, (u16
*)&status
);
207 adr
= bank1start
+ 0x14;
208 target_write_u16(target
, adr
, 0x90);
209 target_read_u32(target
, adr
, &status
);
214 adr
= bank1start
+ 0x10;
215 target_write_u16(target
, adr
, 0x90);
216 target_read_u16(target
, adr
, (u16
*)&status
);
219 /* read array command */
220 target_write_u16(target
, adr
, 0xFF);
222 for (i
= 0; i
< bank
->num_sectors
; i
++)
224 if (status
& str9x_info
->sector_bits
[i
])
225 bank
->sectors
[i
].is_protected
= 1;
227 bank
->sectors
[i
].is_protected
= 0;
233 int str9x_erase(struct flash_bank_s
*bank
, int first
, int last
)
235 target_t
*target
= bank
->target
;
241 if (bank
->target
->state
!= TARGET_HALTED
)
243 return ERROR_TARGET_NOT_HALTED
;
246 /* Check if we erase whole bank */
247 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
249 /* Optimize to run erase bank command instead of sector */
254 /* Erase sector command */
258 for (i
= first
; i
<= last
; i
++)
260 adr
= bank
->base
+ bank
->sectors
[i
].offset
;
263 target_write_u16(target
, adr
, erase_cmd
);
264 target_write_u16(target
, adr
, 0xD0);
267 target_write_u16(target
, adr
, 0x70);
270 target_read_u8(target
, adr
, &status
);
276 /* clear status, also clear read array */
277 target_write_u16(target
, adr
, 0x50);
279 /* read array command */
280 target_write_u16(target
, adr
, 0xFF);
284 LOG_ERROR("error erasing flash bank, status: 0x%x", status
);
285 return ERROR_FLASH_OPERATION_FAILED
;
288 /* If we ran erase bank command, we are finished */
289 if (erase_cmd
== 0x80)
293 for (i
= first
; i
<= last
; i
++)
294 bank
->sectors
[i
].is_erased
= 1;
299 int str9x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
301 target_t
*target
= bank
->target
;
306 if (bank
->target
->state
!= TARGET_HALTED
)
308 return ERROR_TARGET_NOT_HALTED
;
311 for (i
= first
; i
<= last
; i
++)
313 /* Level One Protection */
315 adr
= bank
->base
+ bank
->sectors
[i
].offset
;
317 target_write_u16(target
, adr
, 0x60);
319 target_write_u16(target
, adr
, 0x01);
321 target_write_u16(target
, adr
, 0xD0);
324 target_read_u8(target
, adr
, &status
);
326 /* clear status, also clear read array */
327 target_write_u16(target
, adr
, 0x50);
329 /* read array command */
330 target_write_u16(target
, adr
, 0xFF);
336 int str9x_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
338 str9x_flash_bank_t
*str9x_info
= bank
->driver_priv
;
339 target_t
*target
= bank
->target
;
340 u32 buffer_size
= 8192;
341 working_area_t
*source
;
342 u32 address
= bank
->base
+ offset
;
343 reg_param_t reg_params
[4];
344 armv4_5_algorithm_t armv4_5_info
;
345 int retval
= ERROR_OK
;
347 u32 str9x_flash_write_code
[] = {
349 0xe3c14003, /* bic r4, r1, #3 */
350 0xe3a03040, /* mov r3, #0x40 */
351 0xe1c430b0, /* strh r3, [r4, #0] */
352 0xe0d030b2, /* ldrh r3, [r0], #2 */
353 0xe0c130b2, /* strh r3, [r1], #2 */
354 0xe3a03070, /* mov r3, #0x70 */
355 0xe1c430b0, /* strh r3, [r4, #0] */
357 0xe5d43000, /* ldrb r3, [r4, #0] */
358 0xe3130080, /* tst r3, #0x80 */
359 0x0afffffc, /* beq busy */
360 0xe3a05050, /* mov r5, #0x50 */
361 0xe1c450b0, /* strh r5, [r4, #0] */
362 0xe3a050ff, /* mov r5, #0xFF */
363 0xe1c450b0, /* strh r5, [r4, #0] */
364 0xe3130012, /* tst r3, #0x12 */
365 0x1a000001, /* bne exit */
366 0xe2522001, /* subs r2, r2, #1 */
367 0x1affffed, /* bne write */
369 0xeafffffe, /* b exit */
372 /* flash write code */
373 if (target_alloc_working_area(target
, 4 * 19, &str9x_info
->write_algorithm
) != ERROR_OK
)
375 LOG_WARNING("no working area available, can't do block memory writes");
376 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
379 target_write_buffer(target
, str9x_info
->write_algorithm
->address
, 19 * 4, (u8
*)str9x_flash_write_code
);
382 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
385 if (buffer_size
<= 256)
387 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
388 if (str9x_info
->write_algorithm
)
389 target_free_working_area(target
, str9x_info
->write_algorithm
);
391 LOG_WARNING("no large enough working area available, can't do block memory writes");
392 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
396 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
397 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
398 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
400 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
401 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
402 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
403 init_reg_param(®_params
[3], "r3", 32, PARAM_IN
);
407 u32 thisrun_count
= (count
> (buffer_size
/ 2)) ? (buffer_size
/ 2) : count
;
409 target_write_buffer(target
, source
->address
, thisrun_count
* 2, buffer
);
411 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
412 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
413 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
415 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 4, reg_params
, str9x_info
->write_algorithm
->address
, str9x_info
->write_algorithm
->address
+ (18 * 4), 10000, &armv4_5_info
)) != ERROR_OK
)
417 LOG_ERROR("error executing str9x flash write algorithm");
418 retval
= ERROR_FLASH_OPERATION_FAILED
;
422 if (buf_get_u32(reg_params
[3].value
, 0, 32) != 0x80)
424 retval
= ERROR_FLASH_OPERATION_FAILED
;
428 buffer
+= thisrun_count
* 2;
429 address
+= thisrun_count
* 2;
430 count
-= thisrun_count
;
433 target_free_working_area(target
, source
);
434 target_free_working_area(target
, str9x_info
->write_algorithm
);
436 destroy_reg_param(®_params
[0]);
437 destroy_reg_param(®_params
[1]);
438 destroy_reg_param(®_params
[2]);
439 destroy_reg_param(®_params
[3]);
444 int str9x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
446 target_t
*target
= bank
->target
;
447 u32 words_remaining
= (count
/ 2);
448 u32 bytes_remaining
= (count
& 0x00000001);
449 u32 address
= bank
->base
+ offset
;
450 u32 bytes_written
= 0;
453 u32 check_address
= offset
;
457 if (bank
->target
->state
!= TARGET_HALTED
)
459 return ERROR_TARGET_NOT_HALTED
;
464 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset
);
465 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
468 for (i
= 0; i
< bank
->num_sectors
; i
++)
470 u32 sec_start
= bank
->sectors
[i
].offset
;
471 u32 sec_end
= sec_start
+ bank
->sectors
[i
].size
;
473 /* check if destination falls within the current sector */
474 if ((check_address
>= sec_start
) && (check_address
< sec_end
))
476 /* check if destination ends in the current sector */
477 if (offset
+ count
< sec_end
)
478 check_address
= offset
+ count
;
480 check_address
= sec_end
;
484 if (check_address
!= offset
+ count
)
485 return ERROR_FLASH_DST_OUT_OF_BANK
;
487 /* multiple half words (2-byte) to be programmed? */
488 if (words_remaining
> 0)
490 /* try using a block write */
491 if ((retval
= str9x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
493 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
495 /* if block write failed (no sufficient working area),
496 * we use normal (slow) single dword accesses */
497 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
499 else if (retval
== ERROR_FLASH_OPERATION_FAILED
)
501 LOG_ERROR("flash writing failed with error code: 0x%x", retval
);
502 return ERROR_FLASH_OPERATION_FAILED
;
507 buffer
+= words_remaining
* 2;
508 address
+= words_remaining
* 2;
513 while (words_remaining
> 0)
515 bank_adr
= address
& ~0x03;
517 /* write data command */
518 target_write_u16(target
, bank_adr
, 0x40);
519 target
->type
->write_memory(target
, address
, 2, 1, buffer
+ bytes_written
);
521 /* get status command */
522 target_write_u16(target
, bank_adr
, 0x70);
525 target_read_u8(target
, bank_adr
, &status
);
531 /* clear status reg and read array */
532 target_write_u16(target
, bank_adr
, 0x50);
533 target_write_u16(target
, bank_adr
, 0xFF);
536 return ERROR_FLASH_OPERATION_FAILED
;
537 else if (status
& 0x02)
538 return ERROR_FLASH_OPERATION_FAILED
;
547 u8 last_halfword
[2] = {0xff, 0xff};
550 while(bytes_remaining
> 0)
552 last_halfword
[i
++] = *(buffer
+ bytes_written
);
557 bank_adr
= address
& ~0x03;
559 /* write data comamnd */
560 target_write_u16(target
, bank_adr
, 0x40);
561 target
->type
->write_memory(target
, address
, 2, 1, last_halfword
);
563 /* query status command */
564 target_write_u16(target
, bank_adr
, 0x70);
567 target_read_u8(target
, bank_adr
, &status
);
573 /* clear status reg and read array */
574 target_write_u16(target
, bank_adr
, 0x50);
575 target_write_u16(target
, bank_adr
, 0xFF);
578 return ERROR_FLASH_OPERATION_FAILED
;
579 else if (status
& 0x02)
580 return ERROR_FLASH_OPERATION_FAILED
;
586 int str9x_probe(struct flash_bank_s
*bank
)
591 int str9x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
596 int str9x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
598 snprintf(buf
, buf_size
, "str9x flash driver info" );
602 int str9x_handle_flash_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
604 str9x_flash_bank_t
*str9x_info
;
606 target_t
*target
= NULL
;
610 return ERROR_COMMAND_SYNTAX_ERROR
;
613 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
616 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
620 str9x_info
= bank
->driver_priv
;
622 target
= bank
->target
;
624 if (bank
->target
->state
!= TARGET_HALTED
)
626 return ERROR_TARGET_NOT_HALTED
;
629 /* config flash controller */
630 target_write_u32(target
, FLASH_BBSR
, strtoul(args
[1], NULL
, 0));
631 target_write_u32(target
, FLASH_NBBSR
, strtoul(args
[2], NULL
, 0));
632 target_write_u32(target
, FLASH_BBADR
, (strtoul(args
[3], NULL
, 0) >> 2));
633 target_write_u32(target
, FLASH_NBBADR
, (strtoul(args
[4], NULL
, 0) >> 2));
635 /* set bit 18 instruction TCM order as per flash programming manual */
636 arm966e_write_cp15(target
, 62, 0x40000);
638 /* enable flash bank 1 */
639 target_write_u32(target
, FLASH_CR
, 0x18);
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