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e151fc573811ffd0bb6f6d4710eabeaa76c92865
[openocd.git] / src / flash / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28
29 #include "stm32x.h"
30 #include "flash.h"
31 #include "target.h"
32 #include "log.h"
33 #include "armv7m.h"
34 #include "algorithm.h"
35 #include "binarybuffer.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39
40 static int stm32x_register_commands(struct command_context_s *cmd_ctx);
41 static int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
42 static int stm32x_erase(struct flash_bank_s *bank, int first, int last);
43 static int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
44 static int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
45 static int stm32x_probe(struct flash_bank_s *bank);
46 static int stm32x_auto_probe(struct flash_bank_s *bank);
47 //static int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 static int stm32x_protect_check(struct flash_bank_s *bank);
49 static int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
50
51 static int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 static int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 static int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 static int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 static int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 static int stm32x_mass_erase(struct flash_bank_s *bank);
57
58 flash_driver_t stm32x_flash =
59 {
60 .name = "stm32x",
61 .register_commands = stm32x_register_commands,
62 .flash_bank_command = stm32x_flash_bank_command,
63 .erase = stm32x_erase,
64 .protect = stm32x_protect,
65 .write = stm32x_write,
66 .probe = stm32x_probe,
67 .auto_probe = stm32x_auto_probe,
68 .erase_check = default_flash_mem_blank_check,
69 .protect_check = stm32x_protect_check,
70 .info = stm32x_info
71 };
72
73 static int stm32x_register_commands(struct command_context_s *cmd_ctx)
74 {
75 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
76
77 register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
78 "lock device");
79 register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
80 "unlock protected device");
81 register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
82 "mass erase device");
83 register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
84 "read device option bytes");
85 register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
86 "write device option bytes");
87 return ERROR_OK;
88 }
89
90 /* flash bank stm32x <base> <size> 0 0 <target#>
91 */
92 static int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
93 {
94 stm32x_flash_bank_t *stm32x_info;
95
96 if (argc < 6)
97 {
98 LOG_WARNING("incomplete flash_bank stm32x configuration");
99 return ERROR_FLASH_BANK_INVALID;
100 }
101
102 stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
103 bank->driver_priv = stm32x_info;
104
105 stm32x_info->write_algorithm = NULL;
106 stm32x_info->probed = 0;
107
108 return ERROR_OK;
109 }
110
111 static u32 stm32x_get_flash_status(flash_bank_t *bank)
112 {
113 target_t *target = bank->target;
114 u32 status;
115
116 target_read_u32(target, STM32_FLASH_SR, &status);
117
118 return status;
119 }
120
121 static u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
122 {
123 target_t *target = bank->target;
124 u32 status;
125
126 /* wait for busy to clear */
127 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
128 {
129 LOG_DEBUG("status: 0x%x", status);
130 alive_sleep(1);
131 }
132 /* Clear but report errors */
133 if (status & (FLASH_WRPRTERR|FLASH_PGERR))
134 {
135 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR|FLASH_PGERR);
136 }
137 return status;
138 }
139
140 static int stm32x_read_options(struct flash_bank_s *bank)
141 {
142 u32 optiondata;
143 stm32x_flash_bank_t *stm32x_info = NULL;
144 target_t *target = bank->target;
145
146 stm32x_info = bank->driver_priv;
147
148 /* read current option bytes */
149 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
150
151 stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
152 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
153
154 if (optiondata & (1 << OPT_READOUT))
155 LOG_INFO("Device Security Bit Set");
156
157 /* each bit refers to a 4bank protection */
158 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
159
160 stm32x_info->option_bytes.protection[0] = (u16)optiondata;
161 stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
162 stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
163 stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
164
165 return ERROR_OK;
166 }
167
168 static int stm32x_erase_options(struct flash_bank_s *bank)
169 {
170 stm32x_flash_bank_t *stm32x_info = NULL;
171 target_t *target = bank->target;
172 u32 status;
173
174 stm32x_info = bank->driver_priv;
175
176 /* read current options */
177 stm32x_read_options(bank);
178
179 /* unlock flash registers */
180 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
181 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
182
183 /* unlock option flash registers */
184 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
185 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
186
187 /* erase option bytes */
188 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
189 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
190
191 status = stm32x_wait_status_busy(bank, 10);
192
193 if( status & FLASH_WRPRTERR )
194 return ERROR_FLASH_OPERATION_FAILED;
195 if( status & FLASH_PGERR )
196 return ERROR_FLASH_OPERATION_FAILED;
197
198 /* clear readout protection and complementary option bytes
199 * this will also force a device unlock if set */
200 stm32x_info->option_bytes.RDP = 0x5AA5;
201
202 return ERROR_OK;
203 }
204
205 static int stm32x_write_options(struct flash_bank_s *bank)
206 {
207 stm32x_flash_bank_t *stm32x_info = NULL;
208 target_t *target = bank->target;
209 u32 status;
210
211 stm32x_info = bank->driver_priv;
212
213 /* unlock flash registers */
214 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
215 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
216
217 /* unlock option flash registers */
218 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
219 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
220
221 /* program option bytes */
222 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
223
224 /* write user option byte */
225 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
226
227 status = stm32x_wait_status_busy(bank, 10);
228
229 if( status & FLASH_WRPRTERR )
230 return ERROR_FLASH_OPERATION_FAILED;
231 if( status & FLASH_PGERR )
232 return ERROR_FLASH_OPERATION_FAILED;
233
234 /* write protection byte 1 */
235 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
236
237 status = stm32x_wait_status_busy(bank, 10);
238
239 if( status & FLASH_WRPRTERR )
240 return ERROR_FLASH_OPERATION_FAILED;
241 if( status & FLASH_PGERR )
242 return ERROR_FLASH_OPERATION_FAILED;
243
244 /* write protection byte 2 */
245 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
246
247 status = stm32x_wait_status_busy(bank, 10);
248
249 if( status & FLASH_WRPRTERR )
250 return ERROR_FLASH_OPERATION_FAILED;
251 if( status & FLASH_PGERR )
252 return ERROR_FLASH_OPERATION_FAILED;
253
254 /* write protection byte 3 */
255 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
256
257 status = stm32x_wait_status_busy(bank, 10);
258
259 if( status & FLASH_WRPRTERR )
260 return ERROR_FLASH_OPERATION_FAILED;
261 if( status & FLASH_PGERR )
262 return ERROR_FLASH_OPERATION_FAILED;
263
264 /* write protection byte 4 */
265 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
266
267 status = stm32x_wait_status_busy(bank, 10);
268
269 if( status & FLASH_WRPRTERR )
270 return ERROR_FLASH_OPERATION_FAILED;
271 if( status & FLASH_PGERR )
272 return ERROR_FLASH_OPERATION_FAILED;
273
274 /* write readout protection bit */
275 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
276
277 status = stm32x_wait_status_busy(bank, 10);
278
279 if( status & FLASH_WRPRTERR )
280 return ERROR_FLASH_OPERATION_FAILED;
281 if( status & FLASH_PGERR )
282 return ERROR_FLASH_OPERATION_FAILED;
283
284 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
285
286 return ERROR_OK;
287 }
288
289 static int stm32x_protect_check(struct flash_bank_s *bank)
290 {
291 target_t *target = bank->target;
292 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
293
294 u32 protection;
295 int i, s;
296 int num_bits;
297 int set;
298
299 if (target->state != TARGET_HALTED)
300 {
301 LOG_ERROR("Target not halted");
302 return ERROR_TARGET_NOT_HALTED;
303 }
304
305 /* medium density - each bit refers to a 4bank protection
306 * high density - each bit refers to a 2bank protection */
307 target_read_u32(target, STM32_FLASH_WRPR, &protection);
308
309 /* medium density - each protection bit is for 4 * 1K pages
310 * high density - each protection bit is for 2 * 2K pages */
311 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
312
313 if (stm32x_info->ppage_size == 2)
314 {
315 /* high density flash */
316
317 set = 1;
318
319 if (protection & (1 << 31))
320 set = 0;
321
322 /* bit 31 controls sector 62 - 255 protection */
323 for (s = 62; s < bank->num_sectors; s++)
324 {
325 bank->sectors[s].is_protected = set;
326 }
327
328 if (bank->num_sectors > 61)
329 num_bits = 31;
330
331 for (i = 0; i < num_bits; i++)
332 {
333 set = 1;
334
335 if (protection & (1 << i))
336 set = 0;
337
338 for (s = 0; s < stm32x_info->ppage_size; s++)
339 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
340 }
341 }
342 else
343 {
344 /* medium density flash */
345 for (i = 0; i < num_bits; i++)
346 {
347 set = 1;
348
349 if( protection & (1 << i))
350 set = 0;
351
352 for (s = 0; s < stm32x_info->ppage_size; s++)
353 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
354 }
355 }
356
357 return ERROR_OK;
358 }
359
360 static int stm32x_erase(struct flash_bank_s *bank, int first, int last)
361 {
362 target_t *target = bank->target;
363 int i;
364 u32 status;
365
366 if (bank->target->state != TARGET_HALTED)
367 {
368 LOG_ERROR("Target not halted");
369 return ERROR_TARGET_NOT_HALTED;
370 }
371
372 if ((first == 0) && (last == (bank->num_sectors - 1)))
373 {
374 return stm32x_mass_erase(bank);
375 }
376
377 /* unlock flash registers */
378 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
379 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
380
381 for (i = first; i <= last; i++)
382 {
383 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
384 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
385 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
386
387 status = stm32x_wait_status_busy(bank, 10);
388
389 if( status & FLASH_WRPRTERR )
390 return ERROR_FLASH_OPERATION_FAILED;
391 if( status & FLASH_PGERR )
392 return ERROR_FLASH_OPERATION_FAILED;
393 bank->sectors[i].is_erased = 1;
394 }
395
396 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
397
398 return ERROR_OK;
399 }
400
401 static int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
402 {
403 stm32x_flash_bank_t *stm32x_info = NULL;
404 target_t *target = bank->target;
405 u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
406 int i, reg, bit;
407 int status;
408 u32 protection;
409
410 stm32x_info = bank->driver_priv;
411
412 if (target->state != TARGET_HALTED)
413 {
414 LOG_ERROR("Target not halted");
415 return ERROR_TARGET_NOT_HALTED;
416 }
417
418 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
419 {
420 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info->ppage_size);
421 return ERROR_FLASH_SECTOR_INVALID;
422 }
423
424 /* medium density - each bit refers to a 4bank protection
425 * high density - each bit refers to a 2bank protection */
426 target_read_u32(target, STM32_FLASH_WRPR, &protection);
427
428 prot_reg[0] = (u16)protection;
429 prot_reg[1] = (u16)(protection >> 8);
430 prot_reg[2] = (u16)(protection >> 16);
431 prot_reg[3] = (u16)(protection >> 24);
432
433 if (stm32x_info->ppage_size == 2)
434 {
435 /* high density flash */
436
437 /* bit 7 controls sector 62 - 255 protection */
438 if (last > 61)
439 {
440 if (set)
441 prot_reg[3] &= ~(1 << 7);
442 else
443 prot_reg[3] |= (1 << 7);
444 }
445
446 if (first > 61)
447 first = 62;
448 if (last > 61)
449 last = 61;
450
451 for (i = first; i <= last; i++)
452 {
453 reg = (i / stm32x_info->ppage_size) / 8;
454 bit = (i / stm32x_info->ppage_size) - (reg * 8);
455
456 if( set )
457 prot_reg[reg] &= ~(1 << bit);
458 else
459 prot_reg[reg] |= (1 << bit);
460 }
461 }
462 else
463 {
464 /* medium density flash */
465 for (i = first; i <= last; i++)
466 {
467 reg = (i / stm32x_info->ppage_size) / 8;
468 bit = (i / stm32x_info->ppage_size) - (reg * 8);
469
470 if( set )
471 prot_reg[reg] &= ~(1 << bit);
472 else
473 prot_reg[reg] |= (1 << bit);
474 }
475 }
476
477 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
478 return status;
479
480 stm32x_info->option_bytes.protection[0] = prot_reg[0];
481 stm32x_info->option_bytes.protection[1] = prot_reg[1];
482 stm32x_info->option_bytes.protection[2] = prot_reg[2];
483 stm32x_info->option_bytes.protection[3] = prot_reg[3];
484
485 return stm32x_write_options(bank);
486 }
487
488 static int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
489 {
490 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
491 target_t *target = bank->target;
492 u32 buffer_size = 16384;
493 working_area_t *source;
494 u32 address = bank->base + offset;
495 reg_param_t reg_params[4];
496 armv7m_algorithm_t armv7m_info;
497 int retval = ERROR_OK;
498
499 u8 stm32x_flash_write_code[] = {
500 /* write: */
501 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
502 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
503 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
504 0x23, 0x60, /* str r3, [r4, #0] */
505 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
506 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
507 /* busy: */
508 0x2B, 0x68, /* ldr r3, [r5, #0] */
509 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
510 0xFB, 0xD0, /* beq busy */
511 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
512 0x01, 0xD1, /* bne exit */
513 0x01, 0x3A, /* subs r2, r2, #1 */
514 0xED, 0xD1, /* bne write */
515 /* exit: */
516 0xFE, 0xE7, /* b exit */
517 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
518 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
519 };
520
521 /* flash write code */
522 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
523 {
524 LOG_WARNING("no working area available, can't do block memory writes");
525 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
526 };
527
528 if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code))!=ERROR_OK)
529 return retval;
530
531 /* memory buffer */
532 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
533 {
534 buffer_size /= 2;
535 if (buffer_size <= 256)
536 {
537 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
538 if (stm32x_info->write_algorithm)
539 target_free_working_area(target, stm32x_info->write_algorithm);
540
541 LOG_WARNING("no large enough working area available, can't do block memory writes");
542 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
543 }
544 };
545
546 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
547 armv7m_info.core_mode = ARMV7M_MODE_ANY;
548
549 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
550 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
551 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
552 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
553
554 while (count > 0)
555 {
556 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
557
558 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
559 break;
560
561 buf_set_u32(reg_params[0].value, 0, 32, source->address);
562 buf_set_u32(reg_params[1].value, 0, 32, address);
563 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
564
565 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
566 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
567 {
568 LOG_ERROR("error executing stm32x flash write algorithm");
569 retval = ERROR_FLASH_OPERATION_FAILED;
570 break;
571 }
572
573 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
574 {
575 LOG_ERROR("flash memory not erased before writing");
576 /* Clear but report errors */
577 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
578 retval = ERROR_FLASH_OPERATION_FAILED;
579 break;
580 }
581
582 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
583 {
584 LOG_ERROR("flash memory write protected");
585 /* Clear but report errors */
586 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
587 retval = ERROR_FLASH_OPERATION_FAILED;
588 break;
589 }
590
591 buffer += thisrun_count * 2;
592 address += thisrun_count * 2;
593 count -= thisrun_count;
594 }
595
596 target_free_working_area(target, source);
597 target_free_working_area(target, stm32x_info->write_algorithm);
598
599 destroy_reg_param(&reg_params[0]);
600 destroy_reg_param(&reg_params[1]);
601 destroy_reg_param(&reg_params[2]);
602 destroy_reg_param(&reg_params[3]);
603
604 return retval;
605 }
606
607 static int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
608 {
609 target_t *target = bank->target;
610 u32 words_remaining = (count / 2);
611 u32 bytes_remaining = (count & 0x00000001);
612 u32 address = bank->base + offset;
613 u32 bytes_written = 0;
614 u8 status;
615 int retval;
616
617 if (bank->target->state != TARGET_HALTED)
618 {
619 LOG_ERROR("Target not halted");
620 return ERROR_TARGET_NOT_HALTED;
621 }
622
623 if (offset & 0x1)
624 {
625 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset);
626 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
627 }
628
629 /* unlock flash registers */
630 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
631 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
632
633 /* multiple half words (2-byte) to be programmed? */
634 if (words_remaining > 0)
635 {
636 /* try using a block write */
637 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
638 {
639 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
640 {
641 /* if block write failed (no sufficient working area),
642 * we use normal (slow) single dword accesses */
643 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
644 }
645 else if (retval == ERROR_FLASH_OPERATION_FAILED)
646 {
647 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
648 return ERROR_FLASH_OPERATION_FAILED;
649 }
650 }
651 else
652 {
653 buffer += words_remaining * 2;
654 address += words_remaining * 2;
655 words_remaining = 0;
656 }
657 }
658
659 while (words_remaining > 0)
660 {
661 u16 value;
662 memcpy(&value, buffer + bytes_written, sizeof(u16));
663
664 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
665 target_write_u16(target, address, value);
666
667 status = stm32x_wait_status_busy(bank, 5);
668
669 if( status & FLASH_WRPRTERR )
670 {
671 LOG_ERROR("flash memory not erased before writing");
672 return ERROR_FLASH_OPERATION_FAILED;
673 }
674 if( status & FLASH_PGERR )
675 {
676 LOG_ERROR("flash memory write protected");
677 return ERROR_FLASH_OPERATION_FAILED;
678 }
679
680 bytes_written += 2;
681 words_remaining--;
682 address += 2;
683 }
684
685 if (bytes_remaining)
686 {
687 u16 value = 0xffff;
688 memcpy(&value, buffer + bytes_written, bytes_remaining);
689
690 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
691 target_write_u16(target, address, value);
692
693 status = stm32x_wait_status_busy(bank, 5);
694
695 if( status & FLASH_WRPRTERR )
696 {
697 LOG_ERROR("flash memory not erased before writing");
698 return ERROR_FLASH_OPERATION_FAILED;
699 }
700 if( status & FLASH_PGERR )
701 {
702 LOG_ERROR("flash memory write protected");
703 return ERROR_FLASH_OPERATION_FAILED;
704 }
705 }
706
707 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
708
709 return ERROR_OK;
710 }
711
712 static int stm32x_probe(struct flash_bank_s *bank)
713 {
714 target_t *target = bank->target;
715 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
716 int i;
717 u16 num_pages;
718 u32 device_id;
719 int page_size;
720
721 if (bank->target->state != TARGET_HALTED)
722 {
723 LOG_ERROR("Target not halted");
724 return ERROR_TARGET_NOT_HALTED;
725 }
726
727 stm32x_info->probed = 0;
728
729 /* read stm32 device id register */
730 target_read_u32(target, 0xE0042000, &device_id);
731 LOG_INFO( "device id = 0x%08x", device_id );
732
733 /* get flash size from target */
734 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
735 {
736 /* failed reading flash size, default to max target family */
737 num_pages = 0xffff;
738 }
739
740 if ((device_id & 0x7ff) == 0x410)
741 {
742 /* medium density - we have 1k pages
743 * 4 pages for a protection area */
744 page_size = 1024;
745 stm32x_info->ppage_size = 4;
746
747 /* check for early silicon */
748 if (num_pages == 0xffff)
749 {
750 /* number of sectors incorrect on revA */
751 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
752 num_pages = 128;
753 }
754 }
755 else if ((device_id & 0x7ff) == 0x412)
756 {
757 /* low density - we have 1k pages
758 * 4 pages for a protection area */
759 page_size = 1024;
760 stm32x_info->ppage_size = 4;
761
762 /* check for early silicon */
763 if (num_pages == 0xffff)
764 {
765 /* number of sectors incorrect on revA */
766 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 32k flash" );
767 num_pages = 32;
768 }
769 }
770 else if ((device_id & 0x7ff) == 0x414)
771 {
772 /* high density - we have 2k pages
773 * 2 pages for a protection area */
774 page_size = 2048;
775 stm32x_info->ppage_size = 2;
776
777 /* check for early silicon */
778 if (num_pages == 0xffff)
779 {
780 /* number of sectors incorrect on revZ */
781 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 512k flash" );
782 num_pages = 512;
783 }
784 }
785 else if ((device_id & 0x7ff) == 0x418)
786 {
787 /* connectivity line density - we have 1k pages
788 * 4 pages for a protection area */
789 page_size = 1024;
790 stm32x_info->ppage_size = 4;
791
792 /* check for early silicon */
793 if (num_pages == 0xffff)
794 {
795 /* number of sectors incorrect on revZ */
796 LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 256k flash" );
797 num_pages = 256;
798 }
799 }
800 else
801 {
802 LOG_WARNING( "Cannot identify target as a STM32 family." );
803 return ERROR_FLASH_OPERATION_FAILED;
804 }
805
806 LOG_INFO( "flash size = %dkbytes", num_pages );
807
808 /* calculate numbers of pages */
809 num_pages /= (page_size / 1024);
810
811 bank->base = 0x08000000;
812 bank->size = (num_pages * page_size);
813 bank->num_sectors = num_pages;
814 bank->sectors = malloc(sizeof(flash_sector_t) * num_pages);
815
816 for (i = 0; i < num_pages; i++)
817 {
818 bank->sectors[i].offset = i * page_size;
819 bank->sectors[i].size = page_size;
820 bank->sectors[i].is_erased = -1;
821 bank->sectors[i].is_protected = 1;
822 }
823
824 stm32x_info->probed = 1;
825
826 return ERROR_OK;
827 }
828
829 static int stm32x_auto_probe(struct flash_bank_s *bank)
830 {
831 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
832 if (stm32x_info->probed)
833 return ERROR_OK;
834 return stm32x_probe(bank);
835 }
836
837 #if 0
838 static int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
839 {
840 return ERROR_OK;
841 }
842 #endif
843
844 static int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
845 {
846 target_t *target = bank->target;
847 u32 device_id;
848 int printed;
849
850 /* read stm32 device id register */
851 target_read_u32(target, 0xE0042000, &device_id);
852
853 if ((device_id & 0x7ff) == 0x410)
854 {
855 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
856 buf += printed;
857 buf_size -= printed;
858
859 switch(device_id >> 16)
860 {
861 case 0x0000:
862 snprintf(buf, buf_size, "A");
863 break;
864
865 case 0x2000:
866 snprintf(buf, buf_size, "B");
867 break;
868
869 case 0x2001:
870 snprintf(buf, buf_size, "Z");
871 break;
872
873 case 0x2003:
874 snprintf(buf, buf_size, "Y");
875 break;
876
877 default:
878 snprintf(buf, buf_size, "unknown");
879 break;
880 }
881 }
882 else if ((device_id & 0x7ff) == 0x412)
883 {
884 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
885 buf += printed;
886 buf_size -= printed;
887
888 switch(device_id >> 16)
889 {
890 case 0x1000:
891 snprintf(buf, buf_size, "A");
892 break;
893
894 default:
895 snprintf(buf, buf_size, "unknown");
896 break;
897 }
898 }
899 else if ((device_id & 0x7ff) == 0x414)
900 {
901 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
902 buf += printed;
903 buf_size -= printed;
904
905 switch(device_id >> 16)
906 {
907 case 0x1000:
908 snprintf(buf, buf_size, "A");
909 break;
910
911 case 0x1001:
912 snprintf(buf, buf_size, "Z");
913 break;
914
915 default:
916 snprintf(buf, buf_size, "unknown");
917 break;
918 }
919 }
920 else if ((device_id & 0x7ff) == 0x418)
921 {
922 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
923 buf += printed;
924 buf_size -= printed;
925
926 switch(device_id >> 16)
927 {
928 case 0x1000:
929 snprintf(buf, buf_size, "A");
930 break;
931
932 default:
933 snprintf(buf, buf_size, "unknown");
934 break;
935 }
936 }
937 else
938 {
939 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
940 return ERROR_FLASH_OPERATION_FAILED;
941 }
942
943 return ERROR_OK;
944 }
945
946 static int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
947 {
948 flash_bank_t *bank;
949 target_t *target = NULL;
950 stm32x_flash_bank_t *stm32x_info = NULL;
951
952 if (argc < 1)
953 {
954 command_print(cmd_ctx, "stm32x lock <bank>");
955 return ERROR_OK;
956 }
957
958 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
959 if (!bank)
960 {
961 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
962 return ERROR_OK;
963 }
964
965 stm32x_info = bank->driver_priv;
966
967 target = bank->target;
968
969 if (target->state != TARGET_HALTED)
970 {
971 LOG_ERROR("Target not halted");
972 return ERROR_TARGET_NOT_HALTED;
973 }
974
975 if (stm32x_erase_options(bank) != ERROR_OK)
976 {
977 command_print(cmd_ctx, "stm32x failed to erase options");
978 return ERROR_OK;
979 }
980
981 /* set readout protection */
982 stm32x_info->option_bytes.RDP = 0;
983
984 if (stm32x_write_options(bank) != ERROR_OK)
985 {
986 command_print(cmd_ctx, "stm32x failed to lock device");
987 return ERROR_OK;
988 }
989
990 command_print(cmd_ctx, "stm32x locked");
991
992 return ERROR_OK;
993 }
994
995 static int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
996 {
997 flash_bank_t *bank;
998 target_t *target = NULL;
999 stm32x_flash_bank_t *stm32x_info = NULL;
1000
1001 if (argc < 1)
1002 {
1003 command_print(cmd_ctx, "stm32x unlock <bank>");
1004 return ERROR_OK;
1005 }
1006
1007 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1008 if (!bank)
1009 {
1010 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1011 return ERROR_OK;
1012 }
1013
1014 stm32x_info = bank->driver_priv;
1015
1016 target = bank->target;
1017
1018 if (target->state != TARGET_HALTED)
1019 {
1020 LOG_ERROR("Target not halted");
1021 return ERROR_TARGET_NOT_HALTED;
1022 }
1023
1024 if (stm32x_erase_options(bank) != ERROR_OK)
1025 {
1026 command_print(cmd_ctx, "stm32x failed to unlock device");
1027 return ERROR_OK;
1028 }
1029
1030 if (stm32x_write_options(bank) != ERROR_OK)
1031 {
1032 command_print(cmd_ctx, "stm32x failed to lock device");
1033 return ERROR_OK;
1034 }
1035
1036 command_print(cmd_ctx, "stm32x unlocked");
1037
1038 return ERROR_OK;
1039 }
1040
1041 static int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1042 {
1043 flash_bank_t *bank;
1044 u32 optionbyte;
1045 target_t *target = NULL;
1046 stm32x_flash_bank_t *stm32x_info = NULL;
1047
1048 if (argc < 1)
1049 {
1050 command_print(cmd_ctx, "stm32x options_read <bank>");
1051 return ERROR_OK;
1052 }
1053
1054 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1055 if (!bank)
1056 {
1057 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1058 return ERROR_OK;
1059 }
1060
1061 stm32x_info = bank->driver_priv;
1062
1063 target = bank->target;
1064
1065 if (target->state != TARGET_HALTED)
1066 {
1067 LOG_ERROR("Target not halted");
1068 return ERROR_TARGET_NOT_HALTED;
1069 }
1070
1071 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1072 command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
1073
1074 if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
1075 command_print(cmd_ctx, "Option Byte Complement Error");
1076
1077 if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
1078 command_print(cmd_ctx, "Readout Protection On");
1079 else
1080 command_print(cmd_ctx, "Readout Protection Off");
1081
1082 if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
1083 command_print(cmd_ctx, "Software Watchdog");
1084 else
1085 command_print(cmd_ctx, "Hardware Watchdog");
1086
1087 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
1088 command_print(cmd_ctx, "Stop: No reset generated");
1089 else
1090 command_print(cmd_ctx, "Stop: Reset generated");
1091
1092 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
1093 command_print(cmd_ctx, "Standby: No reset generated");
1094 else
1095 command_print(cmd_ctx, "Standby: Reset generated");
1096
1097 return ERROR_OK;
1098 }
1099
1100 static int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1101 {
1102 flash_bank_t *bank;
1103 target_t *target = NULL;
1104 stm32x_flash_bank_t *stm32x_info = NULL;
1105 u16 optionbyte = 0xF8;
1106
1107 if (argc < 4)
1108 {
1109 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
1110 return ERROR_OK;
1111 }
1112
1113 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1114 if (!bank)
1115 {
1116 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1117 return ERROR_OK;
1118 }
1119
1120 stm32x_info = bank->driver_priv;
1121
1122 target = bank->target;
1123
1124 if (target->state != TARGET_HALTED)
1125 {
1126 LOG_ERROR("Target not halted");
1127 return ERROR_TARGET_NOT_HALTED;
1128 }
1129
1130 if (strcmp(args[1], "SWWDG") == 0)
1131 {
1132 optionbyte |= (1<<0);
1133 }
1134 else
1135 {
1136 optionbyte &= ~(1<<0);
1137 }
1138
1139 if (strcmp(args[2], "NORSTSTNDBY") == 0)
1140 {
1141 optionbyte |= (1<<1);
1142 }
1143 else
1144 {
1145 optionbyte &= ~(1<<1);
1146 }
1147
1148 if (strcmp(args[3], "NORSTSTOP") == 0)
1149 {
1150 optionbyte |= (1<<2);
1151 }
1152 else
1153 {
1154 optionbyte &= ~(1<<2);
1155 }
1156
1157 if (stm32x_erase_options(bank) != ERROR_OK)
1158 {
1159 command_print(cmd_ctx, "stm32x failed to erase options");
1160 return ERROR_OK;
1161 }
1162
1163 stm32x_info->option_bytes.user_options = optionbyte;
1164
1165 if (stm32x_write_options(bank) != ERROR_OK)
1166 {
1167 command_print(cmd_ctx, "stm32x failed to write options");
1168 return ERROR_OK;
1169 }
1170
1171 command_print(cmd_ctx, "stm32x write options complete");
1172
1173 return ERROR_OK;
1174 }
1175
1176 static int stm32x_mass_erase(struct flash_bank_s *bank)
1177 {
1178 target_t *target = bank->target;
1179 u32 status;
1180
1181 if (target->state != TARGET_HALTED)
1182 {
1183 LOG_ERROR("Target not halted");
1184 return ERROR_TARGET_NOT_HALTED;
1185 }
1186
1187 /* unlock option flash registers */
1188 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1189 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1190
1191 /* mass erase flash memory */
1192 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1193 target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
1194
1195 status = stm32x_wait_status_busy(bank, 10);
1196
1197 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1198
1199 if( status & FLASH_WRPRTERR )
1200 {
1201 LOG_ERROR("stm32x device protected");
1202 return ERROR_OK;
1203 }
1204
1205 if( status & FLASH_PGERR )
1206 {
1207 LOG_ERROR("stm32x device programming failed");
1208 return ERROR_OK;
1209 }
1210
1211 return ERROR_OK;
1212 }
1213
1214 static int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1215 {
1216 flash_bank_t *bank;
1217 int i;
1218
1219 if (argc < 1)
1220 {
1221 command_print(cmd_ctx, "stm32x mass_erase <bank>");
1222 return ERROR_OK;
1223 }
1224
1225 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1226 if (!bank)
1227 {
1228 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1229 return ERROR_OK;
1230 }
1231
1232 if (stm32x_mass_erase(bank) == ERROR_OK)
1233 {
1234 /* set all sectors as erased */
1235 for (i = 0; i < bank->num_sectors; i++)
1236 {
1237 bank->sectors[i].is_erased = 1;
1238 }
1239
1240 command_print(cmd_ctx, "stm32x mass erase complete");
1241 }
1242 else
1243 {
1244 command_print(cmd_ctx, "stm32x mass erase failed");
1245 }
1246
1247 return ERROR_OK;
1248 }
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