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7039a3d41d012bc1d7995714b0b1a58d7b196b95
[openocd.git] / src / flash / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "stm32x.h"
27 #include "flash.h"
28 #include "target.h"
29 #include "log.h"
30 #include "armv7m.h"
31 #include "algorithm.h"
32 #include "binarybuffer.h"
33
34 #include <stdlib.h>
35 #include <string.h>
36
37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
42 int stm32x_probe(struct flash_bank_s *bank);
43 int stm32x_auto_probe(struct flash_bank_s *bank);
44 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int stm32x_protect_check(struct flash_bank_s *bank);
46 int stm32x_erase_check(struct flash_bank_s *bank);
47 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
48
49 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54
55 flash_driver_t stm32x_flash =
56 {
57 .name = "stm32x",
58 .register_commands = stm32x_register_commands,
59 .flash_bank_command = stm32x_flash_bank_command,
60 .erase = stm32x_erase,
61 .protect = stm32x_protect,
62 .write = stm32x_write,
63 .probe = stm32x_probe,
64 .auto_probe = stm32x_auto_probe,
65 .erase_check = stm32x_erase_check,
66 .protect_check = stm32x_protect_check,
67 .info = stm32x_info
68 };
69
70 int stm32x_register_commands(struct command_context_s *cmd_ctx)
71 {
72 command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
73
74 register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
75 "lock device");
76 register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
77 "unlock protected device");
78 register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
79 "mass erase device");
80 register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
81 "read device option bytes");
82 register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
83 "write device option bytes");
84 return ERROR_OK;
85 }
86
87 /* flash bank stm32x <base> <size> 0 0 <target#>
88 */
89 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
90 {
91 stm32x_flash_bank_t *stm32x_info;
92
93 if (argc < 6)
94 {
95 WARNING("incomplete flash_bank stm32x configuration");
96 return ERROR_FLASH_BANK_INVALID;
97 }
98
99 stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
100 bank->driver_priv = stm32x_info;
101
102 stm32x_info->write_algorithm = NULL;
103 stm32x_info->probed = 0;
104
105 return ERROR_OK;
106 }
107
108 u32 stm32x_get_flash_status(flash_bank_t *bank)
109 {
110 target_t *target = bank->target;
111 u32 status;
112
113 target_read_u32(target, STM32_FLASH_SR, &status);
114
115 return status;
116 }
117
118 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
119 {
120 u32 status;
121
122 /* wait for busy to clear */
123 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
124 {
125 DEBUG("status: 0x%x", status);
126 usleep(1000);
127 }
128
129 return status;
130 }
131
132 int stm32x_read_options(struct flash_bank_s *bank)
133 {
134 u32 optiondata;
135 stm32x_flash_bank_t *stm32x_info = NULL;
136 target_t *target = bank->target;
137
138 stm32x_info = bank->driver_priv;
139
140 /* read current option bytes */
141 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
142
143 stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
144 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
145
146 if (optiondata & (1 << OPT_READOUT))
147 INFO("Device Security Bit Set");
148
149 /* each bit refers to a 4bank protection */
150 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
151
152 stm32x_info->option_bytes.protection[0] = (u16)optiondata;
153 stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
154 stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
155 stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
156
157 return ERROR_OK;
158 }
159
160 int stm32x_erase_options(struct flash_bank_s *bank)
161 {
162 stm32x_flash_bank_t *stm32x_info = NULL;
163 target_t *target = bank->target;
164 u32 status;
165
166 stm32x_info = bank->driver_priv;
167
168 /* read current options */
169 stm32x_read_options(bank);
170
171 /* unlock flash registers */
172 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
173 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
174
175 /* unlock option flash registers */
176 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
177 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
178
179 /* erase option bytes */
180 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
181 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
182
183 status = stm32x_wait_status_busy(bank, 10);
184
185 if( status & FLASH_WRPRTERR )
186 return ERROR_FLASH_OPERATION_FAILED;
187 if( status & FLASH_PGERR )
188 return ERROR_FLASH_OPERATION_FAILED;
189
190 /* clear readout protection and complementary option bytes
191 * this will also force a device unlock if set */
192 stm32x_info->option_bytes.RDP = 0x5AA5;
193
194 return ERROR_OK;
195 }
196
197 int stm32x_write_options(struct flash_bank_s *bank)
198 {
199 stm32x_flash_bank_t *stm32x_info = NULL;
200 target_t *target = bank->target;
201 u32 status;
202
203 stm32x_info = bank->driver_priv;
204
205 /* unlock flash registers */
206 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
207 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
208
209 /* unlock option flash registers */
210 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
211 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
212
213 /* program option bytes */
214 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
215
216 /* write user option byte */
217 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
218
219 status = stm32x_wait_status_busy(bank, 10);
220
221 if( status & FLASH_WRPRTERR )
222 return ERROR_FLASH_OPERATION_FAILED;
223 if( status & FLASH_PGERR )
224 return ERROR_FLASH_OPERATION_FAILED;
225
226 /* write protection byte 1 */
227 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
228
229 status = stm32x_wait_status_busy(bank, 10);
230
231 if( status & FLASH_WRPRTERR )
232 return ERROR_FLASH_OPERATION_FAILED;
233 if( status & FLASH_PGERR )
234 return ERROR_FLASH_OPERATION_FAILED;
235
236 /* write protection byte 2 */
237 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
238
239 status = stm32x_wait_status_busy(bank, 10);
240
241 if( status & FLASH_WRPRTERR )
242 return ERROR_FLASH_OPERATION_FAILED;
243 if( status & FLASH_PGERR )
244 return ERROR_FLASH_OPERATION_FAILED;
245
246 /* write protection byte 3 */
247 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
248
249 status = stm32x_wait_status_busy(bank, 10);
250
251 if( status & FLASH_WRPRTERR )
252 return ERROR_FLASH_OPERATION_FAILED;
253 if( status & FLASH_PGERR )
254 return ERROR_FLASH_OPERATION_FAILED;
255
256 /* write protection byte 4 */
257 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
258
259 status = stm32x_wait_status_busy(bank, 10);
260
261 if( status & FLASH_WRPRTERR )
262 return ERROR_FLASH_OPERATION_FAILED;
263 if( status & FLASH_PGERR )
264 return ERROR_FLASH_OPERATION_FAILED;
265
266 /* write readout protection bit */
267 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
268
269 status = stm32x_wait_status_busy(bank, 10);
270
271 if( status & FLASH_WRPRTERR )
272 return ERROR_FLASH_OPERATION_FAILED;
273 if( status & FLASH_PGERR )
274 return ERROR_FLASH_OPERATION_FAILED;
275
276 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
277
278 return ERROR_OK;
279 }
280
281 int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
282 {
283 target_t *target = bank->target;
284 u8 *buffer;
285 int i;
286 int nBytes;
287
288 if ((first < 0) || (last > bank->num_sectors))
289 return ERROR_FLASH_SECTOR_INVALID;
290
291 if (target->state != TARGET_HALTED)
292 {
293 return ERROR_TARGET_NOT_HALTED;
294 }
295
296 buffer = malloc(256);
297
298 for (i = first; i <= last; i++)
299 {
300 bank->sectors[i].is_erased = 1;
301
302 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
303
304 for (nBytes = 0; nBytes < 256; nBytes++)
305 {
306 if (buffer[nBytes] != 0xFF)
307 {
308 bank->sectors[i].is_erased = 0;
309 break;
310 }
311 }
312 }
313
314 free(buffer);
315
316 return ERROR_OK;
317 }
318
319 int stm32x_protect_check(struct flash_bank_s *bank)
320 {
321 target_t *target = bank->target;
322
323 u32 protection;
324 int i, s;
325 int num_bits;
326
327 if (target->state != TARGET_HALTED)
328 {
329 return ERROR_TARGET_NOT_HALTED;
330 }
331
332 /* each bit refers to a 4bank protection */
333 target_read_u32(target, STM32_FLASH_WRPR, &protection);
334
335 /* each protection bit is for 4 1K pages */
336 num_bits = (bank->num_sectors / 4);
337
338 for (i = 0; i < num_bits; i++)
339 {
340 int set = 1;
341
342 if( protection & (1 << i))
343 set = 0;
344
345 for (s = 0; s < 4; s++)
346 bank->sectors[(i * 4) + s].is_protected = set;
347 }
348
349 return ERROR_OK;
350 }
351
352 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
353 {
354 target_t *target = bank->target;
355
356 int i;
357 u32 status;
358
359 if (target->state != TARGET_HALTED)
360 {
361 return ERROR_TARGET_NOT_HALTED;
362 }
363
364 /* unlock flash registers */
365 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
366 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
367
368 for (i = first; i <= last; i++)
369 {
370 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
371 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
372 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
373
374 status = stm32x_wait_status_busy(bank, 10);
375
376 if( status & FLASH_WRPRTERR )
377 return ERROR_FLASH_OPERATION_FAILED;
378 if( status & FLASH_PGERR )
379 return ERROR_FLASH_OPERATION_FAILED;
380 bank->sectors[i].is_erased = 1;
381 }
382
383 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
384
385 return ERROR_OK;
386 }
387
388 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
389 {
390 stm32x_flash_bank_t *stm32x_info = NULL;
391 target_t *target = bank->target;
392 u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
393 int i, reg, bit;
394 int status;
395 u32 protection;
396
397 stm32x_info = bank->driver_priv;
398
399 if (target->state != TARGET_HALTED)
400 {
401 return ERROR_TARGET_NOT_HALTED;
402 }
403
404 if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
405 {
406 WARNING("sector start/end incorrect - stm32 has 4K sector protection");
407 return ERROR_FLASH_SECTOR_INVALID;
408 }
409
410 /* each bit refers to a 4bank protection */
411 target_read_u32(target, STM32_FLASH_WRPR, &protection);
412
413 prot_reg[0] = (u16)protection;
414 prot_reg[1] = (u16)(protection >> 8);
415 prot_reg[2] = (u16)(protection >> 16);
416 prot_reg[3] = (u16)(protection >> 24);
417
418 for (i = first; i <= last; i++)
419 {
420 reg = (i / 4) / 8;
421 bit = (i / 4) - (reg * 8);
422
423 if( set )
424 prot_reg[reg] &= ~(1 << bit);
425 else
426 prot_reg[reg] |= (1 << bit);
427 }
428
429 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
430 return status;
431
432 stm32x_info->option_bytes.protection[0] = prot_reg[0];
433 stm32x_info->option_bytes.protection[1] = prot_reg[1];
434 stm32x_info->option_bytes.protection[2] = prot_reg[2];
435 stm32x_info->option_bytes.protection[3] = prot_reg[3];
436
437 return stm32x_write_options(bank);
438 }
439
440 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
441 {
442 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
443 target_t *target = bank->target;
444 u32 buffer_size = 8192;
445 working_area_t *source;
446 u32 address = bank->base + offset;
447 reg_param_t reg_params[4];
448 armv7m_algorithm_t armv7m_info;
449 int retval = ERROR_OK;
450
451 u8 stm32x_flash_write_code[] = {
452 /* write: */
453 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
454 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
455 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
456 0x23, 0x60, /* str r3, [r4, #0] */
457 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
458 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
459 /* busy: */
460 0x2B, 0x68, /* ldr r3, [r5, #0] */
461 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
462 0xFB, 0xD0, /* beq busy */
463 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
464 0x01, 0xD1, /* bne exit */
465 0x01, 0x3A, /* subs r2, r2, #1 */
466 0xED, 0xD1, /* bne write */
467 /* exit: */
468 0xFE, 0xE7, /* b exit */
469 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
470 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
471 };
472
473 /* flash write code */
474 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
475 {
476 WARNING("no working area available, can't do block memory writes");
477 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
478 };
479
480 target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
481
482 /* memory buffer */
483 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
484 {
485 buffer_size /= 2;
486 if (buffer_size <= 256)
487 {
488 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
489 if (stm32x_info->write_algorithm)
490 target_free_working_area(target, stm32x_info->write_algorithm);
491
492 WARNING("no large enough working area available, can't do block memory writes");
493 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
494 }
495 };
496
497 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
498 armv7m_info.core_mode = ARMV7M_MODE_ANY;
499 armv7m_info.core_state = ARMV7M_STATE_THUMB;
500
501 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
502 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
503 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
504 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
505
506 while (count > 0)
507 {
508 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
509
510 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
511
512 buf_set_u32(reg_params[0].value, 0, 32, source->address);
513 buf_set_u32(reg_params[1].value, 0, 32, address);
514 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
515
516 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
517 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
518 {
519 ERROR("error executing str7x flash write algorithm");
520 break;
521 }
522
523 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
524 {
525 retval = ERROR_FLASH_OPERATION_FAILED;
526 break;
527 }
528
529 buffer += thisrun_count * 2;
530 address += thisrun_count * 2;
531 count -= thisrun_count;
532 }
533
534 target_free_working_area(target, source);
535 target_free_working_area(target, stm32x_info->write_algorithm);
536
537 destroy_reg_param(&reg_params[0]);
538 destroy_reg_param(&reg_params[1]);
539 destroy_reg_param(&reg_params[2]);
540 destroy_reg_param(&reg_params[3]);
541
542 return retval;
543 }
544
545 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
546 {
547 target_t *target = bank->target;
548 u32 words_remaining = (count / 2);
549 u32 bytes_remaining = (count & 0x00000001);
550 u32 address = bank->base + offset;
551 u32 bytes_written = 0;
552 u8 status;
553 u32 retval;
554
555 if (target->state != TARGET_HALTED)
556 {
557 return ERROR_TARGET_NOT_HALTED;
558 }
559
560 if (offset & 0x1)
561 {
562 WARNING("offset 0x%x breaks required 2-byte alignment", offset);
563 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
564 }
565
566 /* unlock flash registers */
567 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
568 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
569
570 /* multiple half words (2-byte) to be programmed? */
571 if (words_remaining > 0)
572 {
573 /* try using a block write */
574 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
575 {
576 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
577 {
578 /* if block write failed (no sufficient working area),
579 * we use normal (slow) single dword accesses */
580 WARNING("couldn't use block writes, falling back to single memory accesses");
581 }
582 else if (retval == ERROR_FLASH_OPERATION_FAILED)
583 {
584 ERROR("flash writing failed with error code: 0x%x", retval);
585 return ERROR_FLASH_OPERATION_FAILED;
586 }
587 }
588 else
589 {
590 buffer += words_remaining * 2;
591 address += words_remaining * 2;
592 words_remaining = 0;
593 }
594 }
595
596 while (words_remaining > 0)
597 {
598 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
599 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
600
601 status = stm32x_wait_status_busy(bank, 5);
602
603 if( status & FLASH_WRPRTERR )
604 return ERROR_FLASH_OPERATION_FAILED;
605 if( status & FLASH_PGERR )
606 return ERROR_FLASH_OPERATION_FAILED;
607
608 bytes_written += 2;
609 words_remaining--;
610 address += 2;
611 }
612
613 if (bytes_remaining)
614 {
615 u8 last_halfword[2] = {0xff, 0xff};
616 int i = 0;
617
618 while(bytes_remaining > 0)
619 {
620 last_halfword[i++] = *(buffer + bytes_written);
621 bytes_remaining--;
622 bytes_written++;
623 }
624
625 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
626 target_write_u16(target, address, *(u16*)last_halfword);
627
628 status = stm32x_wait_status_busy(bank, 5);
629
630 if( status & FLASH_WRPRTERR )
631 return ERROR_FLASH_OPERATION_FAILED;
632 if( status & FLASH_PGERR )
633 return ERROR_FLASH_OPERATION_FAILED;
634 }
635
636 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
637
638 return ERROR_OK;
639 }
640
641 int stm32x_probe(struct flash_bank_s *bank)
642 {
643 target_t *target = bank->target;
644 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
645 int i;
646 u16 num_sectors;
647 u32 device_id;
648
649 stm32x_info->probed = 0;
650
651 /* read stm32 device id register */
652 target_read_u32(target, 0xE0042000, &device_id);
653 INFO( "device id = 0x%08x", device_id );
654
655 if (!(device_id & 0x410))
656 {
657 WARNING( "Cannot identify target as a STM32 family." );
658 return ERROR_FLASH_OPERATION_FAILED;
659 }
660
661 /* get flash size from target */
662 target_read_u16(target, 0x1FFFF7E0, &num_sectors);
663 INFO( "flash size = %dkbytes", num_sectors );
664
665 bank->base = 0x08000000;
666 bank->size = num_sectors * 1024;
667 bank->num_sectors = num_sectors;
668 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
669
670 for (i = 0; i < num_sectors; i++)
671 {
672 bank->sectors[i].offset = i * 1024;
673 bank->sectors[i].size = 1024;
674 bank->sectors[i].is_erased = -1;
675 bank->sectors[i].is_protected = 1;
676 }
677
678 stm32x_info->probed = 1;
679
680 return ERROR_OK;
681 }
682
683 int stm32x_auto_probe(struct flash_bank_s *bank)
684 {
685 stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
686 if (stm32x_info->probed)
687 return ERROR_OK;
688 return stm32x_probe(bank);
689 }
690
691 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
692 {
693 return ERROR_OK;
694 }
695
696 int stm32x_erase_check(struct flash_bank_s *bank)
697 {
698 return stm32x_blank_check(bank, 0, bank->num_sectors - 1);
699 }
700
701 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
702 {
703 snprintf(buf, buf_size, "stm32x flash driver info" );
704 return ERROR_OK;
705 }
706
707 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
708 {
709 flash_bank_t *bank;
710 target_t *target = NULL;
711 stm32x_flash_bank_t *stm32x_info = NULL;
712
713 if (argc < 1)
714 {
715 command_print(cmd_ctx, "stm32x lock <bank>");
716 return ERROR_OK;
717 }
718
719 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
720 if (!bank)
721 {
722 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
723 return ERROR_OK;
724 }
725
726 stm32x_info = bank->driver_priv;
727
728 target = bank->target;
729
730 if (target->state != TARGET_HALTED)
731 {
732 return ERROR_TARGET_NOT_HALTED;
733 }
734
735 if (stm32x_erase_options(bank) != ERROR_OK)
736 {
737 command_print(cmd_ctx, "stm32x failed to erase options");
738 return ERROR_OK;
739 }
740
741 /* set readout protection */
742 stm32x_info->option_bytes.RDP = 0;
743
744 if (stm32x_write_options(bank) != ERROR_OK)
745 {
746 command_print(cmd_ctx, "stm32x failed to lock device");
747 return ERROR_OK;
748 }
749
750 command_print(cmd_ctx, "stm32x locked");
751
752 return ERROR_OK;
753 }
754
755 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
756 {
757 flash_bank_t *bank;
758 target_t *target = NULL;
759 stm32x_flash_bank_t *stm32x_info = NULL;
760
761 if (argc < 1)
762 {
763 command_print(cmd_ctx, "stm32x unlock <bank>");
764 return ERROR_OK;
765 }
766
767 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
768 if (!bank)
769 {
770 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
771 return ERROR_OK;
772 }
773
774 stm32x_info = bank->driver_priv;
775
776 target = bank->target;
777
778 if (target->state != TARGET_HALTED)
779 {
780 return ERROR_TARGET_NOT_HALTED;
781 }
782
783 if (stm32x_erase_options(bank) != ERROR_OK)
784 {
785 command_print(cmd_ctx, "stm32x failed to unlock device");
786 return ERROR_OK;
787 }
788
789 if (stm32x_write_options(bank) != ERROR_OK)
790 {
791 command_print(cmd_ctx, "stm32x failed to lock device");
792 return ERROR_OK;
793 }
794
795 command_print(cmd_ctx, "stm32x unlocked");
796
797 return ERROR_OK;
798 }
799
800 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
801 {
802 flash_bank_t *bank;
803 u32 optionbyte;
804 target_t *target = NULL;
805 stm32x_flash_bank_t *stm32x_info = NULL;
806
807 if (argc < 1)
808 {
809 command_print(cmd_ctx, "stm32x options_read <bank>");
810 return ERROR_OK;
811 }
812
813 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
814 if (!bank)
815 {
816 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
817 return ERROR_OK;
818 }
819
820 stm32x_info = bank->driver_priv;
821
822 target = bank->target;
823
824 if (target->state != TARGET_HALTED)
825 {
826 return ERROR_TARGET_NOT_HALTED;
827 }
828
829 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
830 command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
831
832 if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
833 command_print(cmd_ctx, "Option Byte Complement Error");
834
835 if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
836 command_print(cmd_ctx, "Readout Protection On");
837 else
838 command_print(cmd_ctx, "Readout Protection Off");
839
840 if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
841 command_print(cmd_ctx, "Software Watchdog");
842 else
843 command_print(cmd_ctx, "Hardware Watchdog");
844
845 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
846 command_print(cmd_ctx, "Stop: No reset generated");
847 else
848 command_print(cmd_ctx, "Stop: Reset generated");
849
850 if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
851 command_print(cmd_ctx, "Standby: No reset generated");
852 else
853 command_print(cmd_ctx, "Standby: Reset generated");
854
855 return ERROR_OK;
856 }
857
858 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
859 {
860 flash_bank_t *bank;
861 target_t *target = NULL;
862 stm32x_flash_bank_t *stm32x_info = NULL;
863 u16 optionbyte = 0xF8;
864
865 if (argc < 4)
866 {
867 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
868 return ERROR_OK;
869 }
870
871 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
872 if (!bank)
873 {
874 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
875 return ERROR_OK;
876 }
877
878 stm32x_info = bank->driver_priv;
879
880 target = bank->target;
881
882 if (target->state != TARGET_HALTED)
883 {
884 return ERROR_TARGET_NOT_HALTED;
885 }
886
887 if (strcmp(args[1], "SWWDG") == 0)
888 {
889 optionbyte |= (1<<0);
890 }
891 else
892 {
893 optionbyte &= ~(1<<0);
894 }
895
896 if (strcmp(args[2], "NORSTSTNDBY") == 0)
897 {
898 optionbyte |= (1<<1);
899 }
900 else
901 {
902 optionbyte &= ~(1<<1);
903 }
904
905 if (strcmp(args[3], "NORSTSTOP") == 0)
906 {
907 optionbyte |= (1<<2);
908 }
909 else
910 {
911 optionbyte &= ~(1<<2);
912 }
913
914 if (stm32x_erase_options(bank) != ERROR_OK)
915 {
916 command_print(cmd_ctx, "stm32x failed to erase options");
917 return ERROR_OK;
918 }
919
920 stm32x_info->option_bytes.user_options = optionbyte;
921
922 if (stm32x_write_options(bank) != ERROR_OK)
923 {
924 command_print(cmd_ctx, "stm32x failed to write options");
925 return ERROR_OK;
926 }
927
928 command_print(cmd_ctx, "stm32x write options complete");
929
930 return ERROR_OK;
931 }
932
933 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
934 {
935 target_t *target = NULL;
936 stm32x_flash_bank_t *stm32x_info = NULL;
937 flash_bank_t *bank;
938 u32 status;
939
940 if (argc < 1)
941 {
942 command_print(cmd_ctx, "stm32x mass_erase <bank>");
943 return ERROR_OK;
944 }
945
946 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
947 if (!bank)
948 {
949 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
950 return ERROR_OK;
951 }
952
953 stm32x_info = bank->driver_priv;
954
955 target = bank->target;
956
957 if (target->state != TARGET_HALTED)
958 {
959 return ERROR_TARGET_NOT_HALTED;
960 }
961
962 /* unlock option flash registers */
963 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
964 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
965
966 /* mass erase flash memory */
967 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
968 target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
969
970 status = stm32x_wait_status_busy(bank, 10);
971
972 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
973
974 if( status & FLASH_WRPRTERR )
975 {
976 command_print(cmd_ctx, "stm32x device protected");
977 return ERROR_OK;
978 }
979
980 if( status & FLASH_PGERR )
981 {
982 command_print(cmd_ctx, "stm32x device programming failed");
983 return ERROR_OK;
984 }
985
986 command_print(cmd_ctx, "stm32x mass erase complete");
987
988 return ERROR_OK;
989 }
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