1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
21 /***************************************************************************
22 * STELLARIS is tested on LM3S811
23 ***************************************************************************/
28 #include "replacements.h"
30 #include "stellaris.h"
31 #include "cortex_m3.h"
36 #include "binarybuffer.h"
43 #define DID0_VER(did0) ((did0>>28)&0x07)
44 int stellaris_register_commands(struct command_context_s
*cmd_ctx
);
45 int stellaris_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
46 int stellaris_erase(struct flash_bank_s
*bank
, int first
, int last
);
47 int stellaris_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
48 int stellaris_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
49 int stellaris_auto_probe(struct flash_bank_s
*bank
);
50 int stellaris_probe(struct flash_bank_s
*bank
);
51 int stellaris_erase_check(struct flash_bank_s
*bank
);
52 int stellaris_protect_check(struct flash_bank_s
*bank
);
53 int stellaris_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
55 int stellaris_read_part_info(struct flash_bank_s
*bank
);
56 u32
stellaris_get_flash_status(flash_bank_t
*bank
);
57 void stellaris_set_flash_mode(flash_bank_t
*bank
,int mode
);
58 u32
stellaris_wait_status_busy(flash_bank_t
*bank
, u32 waitbits
, int timeout
);
60 int stellaris_read_part_info(struct flash_bank_s
*bank
);
62 flash_driver_t stellaris_flash
=
65 .register_commands
= stellaris_register_commands
,
66 .flash_bank_command
= stellaris_flash_bank_command
,
67 .erase
= stellaris_erase
,
68 .protect
= stellaris_protect
,
69 .write
= stellaris_write
,
70 .probe
= stellaris_probe
,
71 .auto_probe
= stellaris_auto_probe
,
72 .erase_check
= stellaris_erase_check
,
73 .protect_check
= stellaris_protect_check
,
74 .info
= stellaris_info
204 char * StellarisClassname
[2] =
210 /***************************************************************************
211 * openocd command interface *
212 ***************************************************************************/
214 /* flash_bank stellaris <base> <size> 0 0 <target#>
216 int stellaris_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
218 stellaris_flash_bank_t
*stellaris_info
;
222 WARNING("incomplete flash_bank stellaris configuration");
223 return ERROR_FLASH_BANK_INVALID
;
226 stellaris_info
= calloc(sizeof(stellaris_flash_bank_t
),1);
228 bank
->driver_priv
= stellaris_info
;
230 stellaris_info
->target_name
= "Unknown target";
232 /* part wasn't probed for info yet */
233 stellaris_info
->did1
= 0;
235 /* TODO Use an optional main oscillator clock rate in kHz from arg[6] */
239 int stellaris_register_commands(struct command_context_s
*cmd_ctx
)
242 command_t *stellaris_cmd = register_command(cmd_ctx, NULL, "stellaris", NULL, COMMAND_ANY, NULL);
243 register_command(cmd_ctx, stellaris_cmd, "gpnvm", stellaris_handle_gpnvm_command, COMMAND_EXEC,
244 "stellaris gpnvm <num> <bit> set|clear, set or clear stellaris gpnvm bit");
249 int stellaris_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
251 int printed
, device_class
;
252 stellaris_flash_bank_t
*stellaris_info
= bank
->driver_priv
;
254 stellaris_read_part_info(bank
);
256 if (stellaris_info
->did1
== 0)
258 printed
= snprintf(buf
, buf_size
, "Cannot identify target as a Stellaris\n");
261 return ERROR_FLASH_OPERATION_FAILED
;
264 if (DID0_VER(stellaris_info
->did0
)>0)
266 device_class
= (stellaris_info
->did0
>>16)&0xFF;
272 printed
= snprintf(buf
, buf_size
, "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
273 device_class
, StellarisClassname
[device_class
], stellaris_info
->target_name
,
274 'A' + (stellaris_info
->did0
>>8)&0xFF, (stellaris_info
->did0
)&0xFF);
278 printed
= snprintf(buf
, buf_size
, "did1: 0x%8.8x, arch: 0x%4.4x, eproc: %s, ramsize:%ik, flashsize: %ik\n",
279 stellaris_info
->did1
, stellaris_info
->did1
, "ARMV7M", (1+(stellaris_info
->dc0
>>16)&0xFFFF)/4, (1+stellaris_info
->dc0
&0xFFFF)*2);
283 printed
= snprintf(buf
, buf_size
, "master clock(estimated): %ikHz, rcc is 0x%x \n", stellaris_info
->mck_freq
/ 1000, stellaris_info
->rcc
);
287 if (stellaris_info
->num_lockbits
>0) {
288 printed
= snprintf(buf
, buf_size
, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", stellaris_info
->pagesize
, stellaris_info
->num_lockbits
, stellaris_info
->lockbits
,stellaris_info
->num_pages
/stellaris_info
->num_lockbits
);
295 /***************************************************************************
296 * chip identification and status *
297 ***************************************************************************/
299 u32
stellaris_get_flash_status(flash_bank_t
*bank
)
301 target_t
*target
= bank
->target
;
304 target_read_u32(target
, FLASH_CONTROL_BASE
|FLASH_FMC
, &fmc
);
309 /** Read clock configuration and set stellaris_info->usec_clocks*/
311 void stellaris_read_clock_info(flash_bank_t
*bank
)
313 stellaris_flash_bank_t
*stellaris_info
= bank
->driver_priv
;
314 target_t
*target
= bank
->target
;
315 u32 rcc
, pllcfg
, sysdiv
, usesysdiv
, bypass
, oscsrc
;
316 unsigned long mainfreq
;
318 target_read_u32(target
, SCB_BASE
|RCC
, &rcc
);
319 DEBUG("Stellaris RCC %x",rcc
);
320 target_read_u32(target
, SCB_BASE
|PLLCFG
, &pllcfg
);
321 DEBUG("Stellaris PLLCFG %x",pllcfg
);
322 stellaris_info
->rcc
= rcc
;
324 sysdiv
= (rcc
>>23)&0xF;
325 usesysdiv
= (rcc
>>22)&0x1;
326 bypass
= (rcc
>>11)&0x1;
327 oscsrc
= (rcc
>>4)&0x3;
328 /* xtal = (rcc>>6)&0xF; */
332 mainfreq
= 6000000; /* Default xtal */
335 mainfreq
= 22500000; /* Internal osc. 15 MHz +- 50% */
338 mainfreq
= 5625000; /* Internal osc. / 4 */
341 WARNING("Invalid oscsrc (3) in rcc register");
347 mainfreq
= 200000000; /* PLL out frec */
350 stellaris_info
->mck_freq
= mainfreq
/(1+sysdiv
);
352 stellaris_info
->mck_freq
= mainfreq
;
354 /* Forget old flash timing */
355 stellaris_set_flash_mode(bank
,0);
358 /* Setup the timimg registers */
359 void stellaris_set_flash_mode(flash_bank_t
*bank
,int mode
)
361 stellaris_flash_bank_t
*stellaris_info
= bank
->driver_priv
;
362 target_t
*target
= bank
->target
;
364 u32 usecrl
= (stellaris_info
->mck_freq
/1000000ul-1);
365 DEBUG("usecrl = %i",usecrl
);
366 target_write_u32(target
, SCB_BASE
|USECRL
, usecrl
);
370 u32
stellaris_wait_status_busy(flash_bank_t
*bank
, u32 waitbits
, int timeout
)
374 /* Stellaris waits for cmdbit to clear */
375 while (((status
= stellaris_get_flash_status(bank
)) & waitbits
) && (timeout
-- > 0))
377 DEBUG("status: 0x%x", status
);
381 /* Flash errors are reflected in the FLASH_CRIS register */
387 /* Send one command to the flash controller */
388 int stellaris_flash_command(struct flash_bank_s
*bank
,u8 cmd
,u16 pagen
)
391 target_t
*target
= bank
->target
;
393 fmc
= FMC_WRKEY
| cmd
;
394 target_write_u32(target
, FLASH_CONTROL_BASE
|FLASH_FMC
, fmc
);
395 DEBUG("Flash command: 0x%x", fmc
);
397 if (stellaris_wait_status_busy(bank
, cmd
, 100))
399 return ERROR_FLASH_OPERATION_FAILED
;
405 /* Read device id register, main clock frequency register and fill in driver info structure */
406 int stellaris_read_part_info(struct flash_bank_s
*bank
)
408 stellaris_flash_bank_t
*stellaris_info
= bank
->driver_priv
;
409 target_t
*target
= bank
->target
;
410 u32 did0
,did1
, ver
, fam
, status
;
413 /* Read and parse chip identification register */
414 target_read_u32(target
, SCB_BASE
|DID0
, &did0
);
415 target_read_u32(target
, SCB_BASE
|DID1
, &did1
);
416 target_read_u32(target
, SCB_BASE
|DC0
, &stellaris_info
->dc0
);
417 target_read_u32(target
, SCB_BASE
|DC1
, &stellaris_info
->dc1
);
418 DEBUG("did0 0x%x, did1 0x%x, dc0 0x%x, dc1 0x%x",did0
, did1
, stellaris_info
->dc0
,stellaris_info
->dc1
);
421 if((ver
!= 0) && (ver
!= 1))
423 WARNING("Unknown did0 version, cannot identify target");
424 return ERROR_FLASH_OPERATION_FAILED
;
429 WARNING("Cannot identify target as a Stellaris");
430 return ERROR_FLASH_OPERATION_FAILED
;
434 fam
= (did1
>> 24) & 0xF;
435 if(((ver
!= 0) && (ver
!= 1)) || (fam
!= 0))
437 WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
440 for (i
=0;StellarisParts
[i
].partno
;i
++)
442 if (StellarisParts
[i
].partno
==((did1
>>16)&0xFF))
446 stellaris_info
->target_name
= StellarisParts
[i
].partname
;
448 stellaris_info
->did0
= did0
;
449 stellaris_info
->did1
= did1
;
451 stellaris_info
->num_lockbits
= 1+stellaris_info
->dc0
&0xFFFF;
452 stellaris_info
->num_pages
= 2*(1+stellaris_info
->dc0
&0xFFFF);
453 stellaris_info
->pagesize
= 1024;
454 bank
->size
= 1024*stellaris_info
->num_pages
;
455 stellaris_info
->pages_in_lockregion
= 2;
456 target_read_u32(target
, SCB_BASE
|FMPPE
, &stellaris_info
->lockbits
);
458 /* Read main and master clock freqency register */
459 stellaris_read_clock_info(bank
);
461 status
= stellaris_get_flash_status(bank
);
466 /***************************************************************************
468 ***************************************************************************/
470 int stellaris_erase_check(struct flash_bank_s
*bank
)
474 stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
475 target_t *target = bank->target;
483 int stellaris_protect_check(struct flash_bank_s
*bank
)
487 stellaris_flash_bank_t
*stellaris_info
= bank
->driver_priv
;
489 if (bank
->target
->state
!= TARGET_HALTED
)
491 return ERROR_TARGET_NOT_HALTED
;
494 if (stellaris_info
->did1
== 0)
496 stellaris_read_part_info(bank
);
499 if (stellaris_info
->did1
== 0)
501 WARNING("Cannot identify target as an AT91SAM");
502 return ERROR_FLASH_OPERATION_FAILED
;
505 status
= stellaris_get_flash_status(bank
);
506 stellaris_info
->lockbits
= status
>> 16;
511 int stellaris_erase(struct flash_bank_s
*bank
, int first
, int last
)
514 u32 flash_fmc
, flash_cris
;
515 stellaris_flash_bank_t
*stellaris_info
= bank
->driver_priv
;
516 target_t
*target
= bank
->target
;
518 if (bank
->target
->state
!= TARGET_HALTED
)
520 return ERROR_TARGET_NOT_HALTED
;
523 if (stellaris_info
->did1
== 0)
525 stellaris_read_part_info(bank
);
528 if (stellaris_info
->did1
== 0)
530 WARNING("Cannot identify target as Stellaris");
531 return ERROR_FLASH_OPERATION_FAILED
;
534 if ((first
< 0) || (last
< first
) || (last
>= stellaris_info
->num_pages
))
536 return ERROR_FLASH_SECTOR_INVALID
;
539 /* Configure the flash controller timing */
540 stellaris_read_clock_info(bank
);
541 stellaris_set_flash_mode(bank
,0);
543 /* Clear and disable flash programming interrupts */
544 target_write_u32(target
, FLASH_CIM
, 0);
545 target_write_u32(target
, FLASH_MISC
, PMISC
|AMISC
);
547 if ((first
== 0) && (last
== (stellaris_info
->num_pages
-1)))
549 target_write_u32(target
, FLASH_FMA
, 0);
550 target_write_u32(target
, FLASH_FMC
, FMC_WRKEY
| FMC_MERASE
);
551 /* Wait until erase complete */
554 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
556 while(flash_fmc
& FMC_MERASE
);
558 /* if device has > 128k, then second erase cycle is needed */
559 if(stellaris_info
->num_pages
* stellaris_info
->pagesize
> 0x20000)
561 target_write_u32(target
, FLASH_FMA
, 0x20000);
562 target_write_u32(target
, FLASH_FMC
, FMC_WRKEY
| FMC_MERASE
);
563 /* Wait until erase complete */
566 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
568 while(flash_fmc
& FMC_MERASE
);
574 for (banknr
=first
;banknr
<=last
;banknr
++)
576 /* Address is first word in page */
577 target_write_u32(target
, FLASH_FMA
, banknr
*stellaris_info
->pagesize
);
578 /* Write erase command */
579 target_write_u32(target
, FLASH_FMC
, FMC_WRKEY
| FMC_ERASE
);
580 /* Wait until erase complete */
583 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
585 while(flash_fmc
& FMC_ERASE
);
587 /* Check acess violations */
588 target_read_u32(target
, FLASH_CRIS
, &flash_cris
);
589 if(flash_cris
& (AMASK
))
591 WARNING("Error erasing flash page %i, flash_cris 0x%x", banknr
, flash_cris
);
592 target_write_u32(target
, FLASH_CRIS
, 0);
593 return ERROR_FLASH_OPERATION_FAILED
;
600 int stellaris_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
602 u32 fmppe
, flash_fmc
, flash_cris
;
605 stellaris_flash_bank_t
*stellaris_info
= bank
->driver_priv
;
606 target_t
*target
= bank
->target
;
608 if (bank
->target
->state
!= TARGET_HALTED
)
610 return ERROR_TARGET_NOT_HALTED
;
613 if ((first
< 0) || (last
< first
) || (last
>= stellaris_info
->num_lockbits
))
615 return ERROR_FLASH_SECTOR_INVALID
;
618 if (stellaris_info
->did1
== 0)
620 stellaris_read_part_info(bank
);
623 if (stellaris_info
->did1
== 0)
625 WARNING("Cannot identify target as an Stellaris MCU");
626 return ERROR_FLASH_OPERATION_FAILED
;
629 /* Configure the flash controller timing */
630 stellaris_read_clock_info(bank
);
631 stellaris_set_flash_mode(bank
,0);
633 fmppe
= stellaris_info
->lockbits
;
634 for (lockregion
=first
;lockregion
<=last
;lockregion
++)
637 fmppe
&= ~(1<<lockregion
);
639 fmppe
|= (1<<lockregion
);
642 /* Clear and disable flash programming interrupts */
643 target_write_u32(target
, FLASH_CIM
, 0);
644 target_write_u32(target
, FLASH_MISC
, PMISC
|AMISC
);
646 DEBUG("fmppe 0x%x",fmppe
);
647 target_write_u32(target
, SCB_BASE
|FMPPE
, fmppe
);
649 target_write_u32(target
, FLASH_FMA
, 1);
650 /* Write commit command */
651 /* TODO safety check, sice this cannot be undone */
652 WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
653 /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
654 /* Wait until erase complete */
657 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
659 while(flash_fmc
& FMC_COMT
);
661 /* Check acess violations */
662 target_read_u32(target
, FLASH_CRIS
, &flash_cris
);
663 if(flash_cris
& (AMASK
))
665 WARNING("Error setting flash page protection, flash_cris 0x%x", flash_cris
);
666 target_write_u32(target
, FLASH_CRIS
, 0);
667 return ERROR_FLASH_OPERATION_FAILED
;
670 target_read_u32(target
, SCB_BASE
|FMPPE
, &stellaris_info
->lockbits
);
675 u8 stellaris_write_code
[] =
680 r1 = destination address
681 r2 = bytecount (in) - endaddr (work)
684 r3 = pFLASH_CTRL_BASE
690 0x07,0x4B, /* ldr r3,pFLASH_CTRL_BASE */
691 0x08,0x4C, /* ldr r4,FLASHWRITECMD */
692 0x01,0x25, /* movs r5, 1 */
693 0x00,0x26, /* movs r6, #0 */
695 0x19,0x60, /* str r1, [r3, #0] */
696 0x87,0x59, /* ldr r7, [r0, r6] */
697 0x5F,0x60, /* str r7, [r3, #4] */
698 0x9C,0x60, /* str r4, [r3, #8] */
700 0x9F,0x68, /* ldr r7, [r3, #8] */
701 0x2F,0x42, /* tst r7, r5 */
702 0xFC,0xD1, /* bne waitloop */
703 0x04,0x31, /* adds r1, r1, #4 */
704 0x04,0x36, /* adds r6, r6, #4 */
705 0x96,0x42, /* cmp r6, r2 */
706 0xF4,0xD1, /* bne mainloop */
707 0x00,0xBE, /* bkpt #0 */
708 /* pFLASH_CTRL_BASE: */
709 0x00,0xD0,0x0F,0x40, /* .word 0x400FD000 */
711 0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */
714 int stellaris_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 wcount
)
716 target_t
*target
= bank
->target
;
717 u32 buffer_size
= 8192;
718 working_area_t
*source
;
719 working_area_t
*write_algorithm
;
720 u32 address
= bank
->base
+ offset
;
721 reg_param_t reg_params
[8];
722 armv7m_algorithm_t armv7m_info
;
725 DEBUG("(bank=%08X buffer=%08X offset=%08X wcount=%08X)",
726 (unsigned int)bank
, (unsigned int)buffer
, offset
, wcount
);
728 /* flash write code */
729 if (target_alloc_working_area(target
, sizeof(stellaris_write_code
), &write_algorithm
) != ERROR_OK
)
731 WARNING("no working area available, can't do block memory writes");
732 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
735 target_write_buffer(target
, write_algorithm
->address
, sizeof(stellaris_write_code
), stellaris_write_code
);
738 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
740 DEBUG("called target_alloc_working_area(target=%08X buffer_size=%08X source=%08X)",
741 (unsigned int)target
, buffer_size
, (unsigned int)source
);
743 if (buffer_size
<= 256)
745 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
747 target_free_working_area(target
, write_algorithm
);
749 WARNING("no large enough working area available, can't do block memory writes");
750 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
754 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
755 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
756 armv7m_info
.core_state
= ARMV7M_STATE_THUMB
;
758 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
759 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
760 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
761 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
762 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
763 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
764 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
765 init_reg_param(®_params
[7], "r7", 32, PARAM_OUT
);
769 u32 thisrun_count
= (wcount
> (buffer_size
/ 4)) ? (buffer_size
/ 4) : wcount
;
771 target_write_buffer(target
, source
->address
, thisrun_count
* 4, buffer
);
773 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
774 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
775 buf_set_u32(reg_params
[2].value
, 0, 32, 4*thisrun_count
);
776 WARNING("Algorithm flash write %i words to 0x%x, %i remaining",thisrun_count
,address
, wcount
);
777 DEBUG("Algorithm flash write %i words to 0x%x, %i remaining",thisrun_count
,address
, wcount
);
778 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 3, reg_params
, write_algorithm
->address
, write_algorithm
->address
+ sizeof(stellaris_write_code
)-10, 10000, &armv7m_info
)) != ERROR_OK
)
780 ERROR("error executing stellaris flash write algorithm");
781 target_free_working_area(target
, source
);
782 destroy_reg_param(®_params
[0]);
783 destroy_reg_param(®_params
[1]);
784 destroy_reg_param(®_params
[2]);
785 return ERROR_FLASH_OPERATION_FAILED
;
788 buffer
+= thisrun_count
* 4;
789 address
+= thisrun_count
* 4;
790 wcount
-= thisrun_count
;
794 target_free_working_area(target
, write_algorithm
);
795 target_free_working_area(target
, source
);
797 destroy_reg_param(®_params
[0]);
798 destroy_reg_param(®_params
[1]);
799 destroy_reg_param(®_params
[2]);
800 destroy_reg_param(®_params
[3]);
801 destroy_reg_param(®_params
[4]);
802 destroy_reg_param(®_params
[5]);
803 destroy_reg_param(®_params
[6]);
804 destroy_reg_param(®_params
[7]);
809 int stellaris_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
811 stellaris_flash_bank_t
*stellaris_info
= bank
->driver_priv
;
812 target_t
*target
= bank
->target
;
813 u32 address
= offset
;
814 u32 flash_cris
,flash_fmc
;
817 if (bank
->target
->state
!= TARGET_HALTED
)
819 return ERROR_TARGET_NOT_HALTED
;
822 DEBUG("(bank=%08X buffer=%08X offset=%08X count=%08X)",
823 (unsigned int)bank
, (unsigned int)buffer
, offset
, count
);
825 if (stellaris_info
->did1
== 0)
827 stellaris_read_part_info(bank
);
830 if (stellaris_info
->did1
== 0)
832 WARNING("Cannot identify target as a Stellaris processor");
833 return ERROR_FLASH_OPERATION_FAILED
;
836 if((offset
& 3) || (count
& 3))
838 WARNING("offset size must be word aligned");
839 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
842 if (offset
+ count
> bank
->size
)
843 return ERROR_FLASH_DST_OUT_OF_BANK
;
845 /* Configure the flash controller timing */
846 stellaris_read_clock_info(bank
);
847 stellaris_set_flash_mode(bank
,0);
850 /* Clear and disable flash programming interrupts */
851 target_write_u32(target
, FLASH_CIM
, 0);
852 target_write_u32(target
, FLASH_MISC
, PMISC
|AMISC
);
854 /* multiple words to be programmed? */
857 /* try using a block write */
858 if ((retval
= stellaris_write_block(bank
, buffer
, offset
, count
/4)) != ERROR_OK
)
860 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
862 /* if block write failed (no sufficient working area),
863 * we use normal (slow) single dword accesses */
864 WARNING("couldn't use block writes, falling back to single memory accesses");
866 else if (retval
== ERROR_FLASH_OPERATION_FAILED
)
868 /* if an error occured, we examine the reason, and quit */
869 target_read_u32(target
, FLASH_CRIS
, &flash_cris
);
871 ERROR("flash writing failed with CRIS: 0x%x", flash_cris
);
872 return ERROR_FLASH_OPERATION_FAILED
;
878 address
+= count
* 4;
887 if (!(address
&0xff)) DEBUG("0x%x",address
);
888 /* Program one word */
889 target_write_u32(target
, FLASH_FMA
, address
);
890 target_write_buffer(target
, FLASH_FMD
, 4, buffer
);
891 target_write_u32(target
, FLASH_FMC
, FMC_WRKEY
| FMC_WRITE
);
892 /* DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
893 /* Wait until write complete */
896 target_read_u32(target
, FLASH_FMC
, &flash_fmc
);
898 while(flash_fmc
& FMC_WRITE
);
903 /* Check acess violations */
904 target_read_u32(target
, FLASH_CRIS
, &flash_cris
);
905 if(flash_cris
& (AMASK
))
907 DEBUG("flash_cris 0x%x", flash_cris
);
908 return ERROR_FLASH_OPERATION_FAILED
;
914 int stellaris_probe(struct flash_bank_s
*bank
)
916 /* we can't probe on an stellaris
917 * if this is an stellaris, it has the configured flash
920 if (bank
->target
->state
!= TARGET_HALTED
)
922 return ERROR_TARGET_NOT_HALTED
;
925 /* stellaris_read_part_info() already takes care about error checking and reporting */
926 return stellaris_read_part_info(bank
);
929 int stellaris_auto_probe(struct flash_bank_s
*bank
)
931 stellaris_flash_bank_t
*stellaris_info
= bank
->driver_priv
;
932 if (stellaris_info
->did1
)
934 return stellaris_probe(bank
);
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