82c717ac36614b2502fb3b473efba693de27fdf7
[openocd.git] / src / flash / orion_nand.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Marvell Semiconductors, Inc. *
3 * Written by Nicolas Pitre <nico at marvell.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 /*
22 * NAND controller interface for Marvell Orion/Kirkwood SoCs.
23 */
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "arm_nandio.h"
30 #include "armv4_5.h"
31
32
33 struct orion_nand_controller
34 {
35 struct target_s *target;
36
37 struct arm_nand_data io;
38
39 uint32_t cmd;
40 uint32_t addr;
41 uint32_t data;
42 };
43
44 #define CHECK_HALTED \
45 do { \
46 if (target->state != TARGET_HALTED) { \
47 LOG_ERROR("NAND flash access requires halted target"); \
48 return ERROR_NAND_OPERATION_FAILED; \
49 } \
50 } while (0)
51
52 static int orion_nand_command(struct nand_device_s *nand, uint8_t command)
53 {
54 struct orion_nand_controller *hw = nand->controller_priv;
55 target_t *target = hw->target;
56
57 CHECK_HALTED;
58 target_write_u8(target, hw->cmd, command);
59 return ERROR_OK;
60 }
61
62 static int orion_nand_address(struct nand_device_s *nand, uint8_t address)
63 {
64 struct orion_nand_controller *hw = nand->controller_priv;
65 target_t *target = hw->target;
66
67 CHECK_HALTED;
68 target_write_u8(target, hw->addr, address);
69 return ERROR_OK;
70 }
71
72 static int orion_nand_read(struct nand_device_s *nand, void *data)
73 {
74 struct orion_nand_controller *hw = nand->controller_priv;
75 target_t *target = hw->target;
76
77 CHECK_HALTED;
78 target_read_u8(target, hw->data, data);
79 return ERROR_OK;
80 }
81
82 static int orion_nand_write(struct nand_device_s *nand, uint16_t data)
83 {
84 struct orion_nand_controller *hw = nand->controller_priv;
85 target_t *target = hw->target;
86
87 CHECK_HALTED;
88 target_write_u8(target, hw->data, data);
89 return ERROR_OK;
90 }
91
92 static int orion_nand_slow_block_write(struct nand_device_s *nand, uint8_t *data, int size)
93 {
94 while (size--)
95 orion_nand_write(nand, *data++);
96 return ERROR_OK;
97 }
98
99 static int orion_nand_fast_block_write(struct nand_device_s *nand, uint8_t *data, int size)
100 {
101 struct orion_nand_controller *hw = nand->controller_priv;
102 int retval;
103
104 hw->io.chunk_size = nand->page_size;
105
106 retval = arm_nandwrite(&hw->io, data, size);
107 if (retval == ERROR_NAND_NO_BUFFER)
108 retval = orion_nand_slow_block_write(nand, data, size);
109
110 return retval;
111 }
112
113 static int orion_nand_reset(struct nand_device_s *nand)
114 {
115 return orion_nand_command(nand, NAND_CMD_RESET);
116 }
117
118 static int orion_nand_controller_ready(struct nand_device_s *nand, int timeout)
119 {
120 return 1;
121 }
122
123 static int orion_nand_register_commands(struct command_context_s *cmd_ctx)
124 {
125 return ERROR_OK;
126 }
127
128 NAND_DEVICE_COMMAND_HANDLER(orion_nand_device_command)
129 {
130 struct orion_nand_controller *hw;
131 uint32_t base;
132 uint8_t ale, cle;
133
134 if (argc != 3) {
135 LOG_ERROR("arguments must be: <target_id> <NAND_address>\n");
136 return ERROR_NAND_DEVICE_INVALID;
137 }
138
139 hw = calloc(1, sizeof(*hw));
140 if (!hw) {
141 LOG_ERROR("no memory for nand controller\n");
142 return ERROR_NAND_DEVICE_INVALID;
143 }
144
145 nand->controller_priv = hw;
146 hw->target = get_target(args[1]);
147 if (!hw->target) {
148 LOG_ERROR("target '%s' not defined", args[1]);
149 free(hw);
150 return ERROR_NAND_DEVICE_INVALID;
151 }
152
153 COMMAND_PARSE_NUMBER(u32, args[2], base);
154 cle = 0;
155 ale = 1;
156
157 hw->data = base;
158 hw->cmd = base + (1 << cle);
159 hw->addr = base + (1 << ale);
160
161 hw->io.target = hw->target;
162 hw->io.data = hw->data;
163
164 return ERROR_OK;
165 }
166
167 static int orion_nand_init(struct nand_device_s *nand)
168 {
169 return ERROR_OK;
170 }
171
172 struct nand_flash_controller orion_nand_controller =
173 {
174 .name = "orion",
175 .command = orion_nand_command,
176 .address = orion_nand_address,
177 .read_data = orion_nand_read,
178 .write_data = orion_nand_write,
179 .write_block_data = orion_nand_fast_block_write,
180 .reset = orion_nand_reset,
181 .controller_ready = orion_nand_controller_ready,
182 .nand_device_command = orion_nand_device_command,
183 .register_commands = orion_nand_register_commands,
184 .init = orion_nand_init,
185 };
186