1 /***************************************************************************
2 * Copyright (C) 2007,2008 by Christopher Kilgour *
3 * techie |_at_| whiterocker |_dot_| com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
28 /* ----------------------------------------------------------------------
29 Internal Support, Helpers
30 ---------------------------------------------------------------------- */
32 static const struct flash_sector TMS470R1A256_SECTORS
[] = {
33 {0x00000000, 0x00002000, -1, -1},
34 {0x00002000, 0x00002000, -1, -1},
35 {0x00004000, 0x00002000, -1, -1},
36 {0x00006000, 0x00002000, -1, -1},
37 {0x00008000, 0x00008000, -1, -1},
38 {0x00010000, 0x00008000, -1, -1},
39 {0x00018000, 0x00008000, -1, -1},
40 {0x00020000, 0x00008000, -1, -1},
41 {0x00028000, 0x00008000, -1, -1},
42 {0x00030000, 0x00008000, -1, -1},
43 {0x00038000, 0x00002000, -1, -1},
44 {0x0003A000, 0x00002000, -1, -1},
45 {0x0003C000, 0x00002000, -1, -1},
46 {0x0003E000, 0x00002000, -1, -1},
49 #define TMS470R1A256_NUM_SECTORS \
50 ARRAY_SIZE(TMS470R1A256_SECTORS)
52 static const struct flash_sector TMS470R1A288_BANK0_SECTORS
[] = {
53 {0x00000000, 0x00002000, -1, -1},
54 {0x00002000, 0x00002000, -1, -1},
55 {0x00004000, 0x00002000, -1, -1},
56 {0x00006000, 0x00002000, -1, -1},
59 #define TMS470R1A288_BANK0_NUM_SECTORS \
60 ARRAY_SIZE(TMS470R1A288_BANK0_SECTORS)
62 static const struct flash_sector TMS470R1A288_BANK1_SECTORS
[] = {
63 {0x00040000, 0x00010000, -1, -1},
64 {0x00050000, 0x00010000, -1, -1},
65 {0x00060000, 0x00010000, -1, -1},
66 {0x00070000, 0x00010000, -1, -1},
69 #define TMS470R1A288_BANK1_NUM_SECTORS \
70 ARRAY_SIZE(TMS470R1A288_BANK1_SECTORS)
72 static const struct flash_sector TMS470R1A384_BANK0_SECTORS
[] = {
73 {0x00000000, 0x00002000, -1, -1},
74 {0x00002000, 0x00002000, -1, -1},
75 {0x00004000, 0x00004000, -1, -1},
76 {0x00008000, 0x00004000, -1, -1},
77 {0x0000C000, 0x00004000, -1, -1},
78 {0x00010000, 0x00004000, -1, -1},
79 {0x00014000, 0x00004000, -1, -1},
80 {0x00018000, 0x00002000, -1, -1},
81 {0x0001C000, 0x00002000, -1, -1},
82 {0x0001E000, 0x00002000, -1, -1},
85 #define TMS470R1A384_BANK0_NUM_SECTORS \
86 ARRAY_SIZE(TMS470R1A384_BANK0_SECTORS)
88 static const struct flash_sector TMS470R1A384_BANK1_SECTORS
[] = {
89 {0x00020000, 0x00008000, -1, -1},
90 {0x00028000, 0x00008000, -1, -1},
91 {0x00030000, 0x00008000, -1, -1},
92 {0x00038000, 0x00008000, -1, -1},
95 #define TMS470R1A384_BANK1_NUM_SECTORS \
96 ARRAY_SIZE(TMS470R1A384_BANK1_SECTORS)
98 static const struct flash_sector TMS470R1A384_BANK2_SECTORS
[] = {
99 {0x00040000, 0x00008000, -1, -1},
100 {0x00048000, 0x00008000, -1, -1},
101 {0x00050000, 0x00008000, -1, -1},
102 {0x00058000, 0x00008000, -1, -1},
105 #define TMS470R1A384_BANK2_NUM_SECTORS \
106 ARRAY_SIZE(TMS470R1A384_BANK2_SECTORS)
108 /* ---------------------------------------------------------------------- */
110 static int tms470_read_part_info(struct flash_bank
*bank
)
112 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
113 struct target
*target
= bank
->target
;
114 uint32_t device_ident_reg
;
115 uint32_t silicon_version
;
116 uint32_t technology_family
;
118 uint32_t part_number
;
121 /* we shall not rely on the caller in this test, this function allocates memory,
122 thus and executing the code more than once may cause memory leak */
123 if (tms470_info
->device_ident_reg
)
126 /* read and parse the device identification register */
127 target_read_u32(target
, 0xFFFFFFF0, &device_ident_reg
);
129 LOG_INFO("device_ident_reg = 0x%08" PRIx32
"", device_ident_reg
);
131 if ((device_ident_reg
& 7) == 0)
133 LOG_WARNING("Cannot identify target as a TMS470 family.");
134 return ERROR_FLASH_OPERATION_FAILED
;
137 silicon_version
= (device_ident_reg
>> 12) & 0xF;
138 technology_family
= (device_ident_reg
>> 11) & 1;
139 rom_flash
= (device_ident_reg
>> 10) & 1;
140 part_number
= (device_ident_reg
>> 3) & 0x7f;
145 bank
->sectors
= NULL
;
149 * If the part number is known, determine if the flash bank is valid
150 * based on the base address being within the known flash bank
151 * ranges. Then fixup/complete the remaining fields of the flash
157 part_name
= "TMS470R1A256";
159 if (bank
->base
>= 0x00040000)
161 LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32
".", part_name
, bank
->base
);
162 return ERROR_FLASH_OPERATION_FAILED
;
164 tms470_info
->ordinal
= 0;
165 bank
->base
= 0x00000000;
166 bank
->size
= 256 * 1024;
167 bank
->num_sectors
= TMS470R1A256_NUM_SECTORS
;
168 bank
->sectors
= malloc(sizeof(TMS470R1A256_SECTORS
));
171 return ERROR_FLASH_OPERATION_FAILED
;
173 (void)memcpy(bank
->sectors
, TMS470R1A256_SECTORS
, sizeof(TMS470R1A256_SECTORS
));
177 part_name
= "TMS470R1A288";
179 if (bank
->base
< 0x00008000)
181 tms470_info
->ordinal
= 0;
182 bank
->base
= 0x00000000;
183 bank
->size
= 32 * 1024;
184 bank
->num_sectors
= TMS470R1A288_BANK0_NUM_SECTORS
;
185 bank
->sectors
= malloc(sizeof(TMS470R1A288_BANK0_SECTORS
));
188 return ERROR_FLASH_OPERATION_FAILED
;
190 (void)memcpy(bank
->sectors
, TMS470R1A288_BANK0_SECTORS
, sizeof(TMS470R1A288_BANK0_SECTORS
));
192 else if ((bank
->base
>= 0x00040000) && (bank
->base
< 0x00080000))
194 tms470_info
->ordinal
= 1;
195 bank
->base
= 0x00040000;
196 bank
->size
= 256 * 1024;
197 bank
->num_sectors
= TMS470R1A288_BANK1_NUM_SECTORS
;
198 bank
->sectors
= malloc(sizeof(TMS470R1A288_BANK1_SECTORS
));
201 return ERROR_FLASH_OPERATION_FAILED
;
203 (void)memcpy(bank
->sectors
, TMS470R1A288_BANK1_SECTORS
, sizeof(TMS470R1A288_BANK1_SECTORS
));
207 LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32
".", part_name
, bank
->base
);
208 return ERROR_FLASH_OPERATION_FAILED
;
213 part_name
= "TMS470R1A384";
215 if (bank
->base
< 0x00020000)
217 tms470_info
->ordinal
= 0;
218 bank
->base
= 0x00000000;
219 bank
->size
= 128 * 1024;
220 bank
->num_sectors
= TMS470R1A384_BANK0_NUM_SECTORS
;
221 bank
->sectors
= malloc(sizeof(TMS470R1A384_BANK0_SECTORS
));
224 return ERROR_FLASH_OPERATION_FAILED
;
226 (void)memcpy(bank
->sectors
, TMS470R1A384_BANK0_SECTORS
, sizeof(TMS470R1A384_BANK0_SECTORS
));
228 else if ((bank
->base
>= 0x00020000) && (bank
->base
< 0x00040000))
230 tms470_info
->ordinal
= 1;
231 bank
->base
= 0x00020000;
232 bank
->size
= 128 * 1024;
233 bank
->num_sectors
= TMS470R1A384_BANK1_NUM_SECTORS
;
234 bank
->sectors
= malloc(sizeof(TMS470R1A384_BANK1_SECTORS
));
237 return ERROR_FLASH_OPERATION_FAILED
;
239 (void)memcpy(bank
->sectors
, TMS470R1A384_BANK1_SECTORS
, sizeof(TMS470R1A384_BANK1_SECTORS
));
241 else if ((bank
->base
>= 0x00040000) && (bank
->base
< 0x00060000))
243 tms470_info
->ordinal
= 2;
244 bank
->base
= 0x00040000;
245 bank
->size
= 128 * 1024;
246 bank
->num_sectors
= TMS470R1A384_BANK2_NUM_SECTORS
;
247 bank
->sectors
= malloc(sizeof(TMS470R1A384_BANK2_SECTORS
));
250 return ERROR_FLASH_OPERATION_FAILED
;
252 (void)memcpy(bank
->sectors
, TMS470R1A384_BANK2_SECTORS
, sizeof(TMS470R1A384_BANK2_SECTORS
));
256 LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32
".", part_name
, bank
->base
);
257 return ERROR_FLASH_OPERATION_FAILED
;
262 LOG_WARNING("Could not identify part 0x%02x as a member of the TMS470 family.", (unsigned)part_number
);
263 return ERROR_FLASH_OPERATION_FAILED
;
266 /* turn off memory selects */
267 target_write_u32(target
, 0xFFFFFFE4, 0x00000000);
268 target_write_u32(target
, 0xFFFFFFE0, 0x00000000);
270 bank
->chip_width
= 32;
271 bank
->bus_width
= 32;
273 LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
275 (int)(silicon_version
),
276 (technology_family
? "1.8v" : "3.3v"),
277 (rom_flash
? "rom" : "flash"));
279 tms470_info
->device_ident_reg
= device_ident_reg
;
280 tms470_info
->silicon_version
= silicon_version
;
281 tms470_info
->technology_family
= technology_family
;
282 tms470_info
->rom_flash
= rom_flash
;
283 tms470_info
->part_number
= part_number
;
284 tms470_info
->part_name
= part_name
;
287 * Disable reset on address access violation.
289 target_write_u32(target
, 0xFFFFFFE0, 0x00004007);
294 /* ---------------------------------------------------------------------- */
296 static uint32_t keysSet
= 0;
297 static uint32_t flashKeys
[4];
299 COMMAND_HANDLER(tms470_handle_flash_keyset_command
)
303 command_print(CMD_CTX
, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
304 return ERROR_INVALID_ARGUMENTS
;
306 else if (CMD_ARGC
== 4)
310 for (i
= 0; i
< 4; i
++)
312 int start
= (0 == strncmp(CMD_ARGV
[i
], "0x", 2)) ? 2 : 0;
314 if (1 != sscanf(&CMD_ARGV
[i
][start
], "%" SCNx32
"", &flashKeys
[i
]))
316 command_print(CMD_CTX
, "could not process flash key %s", CMD_ARGV
[i
]);
317 LOG_ERROR("could not process flash key %s", CMD_ARGV
[i
]);
318 return ERROR_INVALID_ARGUMENTS
;
324 else if (CMD_ARGC
!= 0)
326 command_print(CMD_CTX
, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
327 return ERROR_INVALID_ARGUMENTS
;
332 command_print(CMD_CTX
, "using flash keys 0x%08" PRIx32
", 0x%08" PRIx32
", 0x%08" PRIx32
", 0x%08" PRIx32
"",
333 flashKeys
[0], flashKeys
[1], flashKeys
[2], flashKeys
[3]);
337 command_print(CMD_CTX
, "flash keys not set");
343 static const uint32_t FLASH_KEYS_ALL_ONES
[] = { 0xFFFFFFFF, 0xFFFFFFFF,
344 0xFFFFFFFF, 0xFFFFFFFF,
347 static const uint32_t FLASH_KEYS_ALL_ZEROS
[] = { 0x00000000, 0x00000000,
348 0x00000000, 0x00000000,
351 static const uint32_t FLASH_KEYS_MIX1
[] = { 0xf0fff0ff, 0xf0fff0ff,
352 0xf0fff0ff, 0xf0fff0ff
355 static const uint32_t FLASH_KEYS_MIX2
[] = { 0x0000ffff, 0x0000ffff,
356 0x0000ffff, 0x0000ffff
359 /* ---------------------------------------------------------------------- */
361 static int oscMHz
= 12;
363 COMMAND_HANDLER(tms470_handle_osc_megahertz_command
)
367 command_print(CMD_CTX
, "tms470 osc_megahertz <MHz>");
368 return ERROR_INVALID_ARGUMENTS
;
370 else if (CMD_ARGC
== 1)
372 sscanf(CMD_ARGV
[0], "%d", &oscMHz
);
377 LOG_ERROR("osc_megahertz must be positive and non-zero!");
378 command_print(CMD_CTX
, "osc_megahertz must be positive and non-zero!");
380 return ERROR_INVALID_ARGUMENTS
;
383 command_print(CMD_CTX
, "osc_megahertz=%d", oscMHz
);
388 /* ---------------------------------------------------------------------- */
390 static int plldis
= 0;
392 COMMAND_HANDLER(tms470_handle_plldis_command
)
396 command_print(CMD_CTX
, "tms470 plldis <0 | 1>");
397 return ERROR_INVALID_ARGUMENTS
;
399 else if (CMD_ARGC
== 1)
401 sscanf(CMD_ARGV
[0], "%d", &plldis
);
402 plldis
= plldis
? 1 : 0;
405 command_print(CMD_CTX
, "plldis=%d", plldis
);
410 /* ---------------------------------------------------------------------- */
412 static int tms470_check_flash_unlocked(struct target
* target
)
416 target_read_u32(target
, 0xFFE89C08, &fmbbusy
);
417 LOG_INFO("tms470 fmbbusy = 0x%08" PRIx32
" -> %s", fmbbusy
, fmbbusy
& 0x8000 ? "unlocked" : "LOCKED");
418 return fmbbusy
& 0x8000 ? ERROR_OK
: ERROR_FLASH_OPERATION_FAILED
;
421 /* ---------------------------------------------------------------------- */
423 static int tms470_try_flash_keys(struct target
* target
, const uint32_t * key_set
)
425 uint32_t glbctrl
, fmmstat
;
426 int retval
= ERROR_FLASH_OPERATION_FAILED
;
429 target_read_u32(target
, 0xFFFFFFDC, &glbctrl
);
430 target_write_u32(target
, 0xFFFFFFDC, glbctrl
| 0x10);
432 /* only perform the key match when 3VSTAT is clear */
433 target_read_u32(target
, 0xFFE8BC0C, &fmmstat
);
434 if (!(fmmstat
& 0x08))
437 uint32_t fmbptr
, fmbac2
, orig_fmregopt
;
439 target_write_u32(target
, 0xFFE8BC04, fmmstat
& ~0x07);
441 /* wait for pump ready */
444 target_read_u32(target
, 0xFFE8A814, &fmbptr
);
447 while (!(fmbptr
& 0x0200));
449 /* force max wait states */
450 target_read_u32(target
, 0xFFE88004, &fmbac2
);
451 target_write_u32(target
, 0xFFE88004, fmbac2
| 0xff);
453 /* save current access mode, force normal read mode */
454 target_read_u32(target
, 0xFFE89C00, &orig_fmregopt
);
455 target_write_u32(target
, 0xFFE89C00, 0x00);
457 for (i
= 0; i
< 4; i
++)
461 /* There is no point displaying the value of tmp, it is
462 * filtered by the chip. The purpose of this read is to
463 * prime the unlocking logic rather than read out the value.
465 target_read_u32(target
, 0x00001FF0 + 4 * i
, &tmp
);
467 LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32
"", key_set
[i
]);
468 target_write_u32(target
, 0xFFE89C0C, key_set
[i
]);
471 if (ERROR_OK
== tms470_check_flash_unlocked(target
))
474 * There seems to be a side-effect of reading the FMPKEY
475 * register in that it re-enables the protection. So we
478 for (i
= 0; i
< 4; i
++)
482 target_read_u32(target
, 0x00001FF0 + 4 * i
, &tmp
);
483 target_write_u32(target
, 0xFFE89C0C, key_set
[i
]);
488 /* restore settings */
489 target_write_u32(target
, 0xFFE89C00, orig_fmregopt
);
490 target_write_u32(target
, 0xFFE88004, fmbac2
);
493 /* clear config bit */
494 target_write_u32(target
, 0xFFFFFFDC, glbctrl
);
499 /* ---------------------------------------------------------------------- */
501 static int tms470_unlock_flash(struct flash_bank
*bank
)
503 struct target
*target
= bank
->target
;
504 const uint32_t *p_key_sets
[5];
505 unsigned i
, key_set_count
;
510 p_key_sets
[0] = flashKeys
;
511 p_key_sets
[1] = FLASH_KEYS_ALL_ONES
;
512 p_key_sets
[2] = FLASH_KEYS_ALL_ZEROS
;
513 p_key_sets
[3] = FLASH_KEYS_MIX1
;
514 p_key_sets
[4] = FLASH_KEYS_MIX2
;
519 p_key_sets
[0] = FLASH_KEYS_ALL_ONES
;
520 p_key_sets
[1] = FLASH_KEYS_ALL_ZEROS
;
521 p_key_sets
[2] = FLASH_KEYS_MIX1
;
522 p_key_sets
[3] = FLASH_KEYS_MIX2
;
525 for (i
= 0; i
< key_set_count
; i
++)
527 if (tms470_try_flash_keys(target
, p_key_sets
[i
]) == ERROR_OK
)
529 LOG_INFO("tms470 flash is unlocked");
534 LOG_WARNING("tms470 could not unlock flash memory protection level 2");
535 return ERROR_FLASH_OPERATION_FAILED
;
538 /* ---------------------------------------------------------------------- */
540 static int tms470_flash_initialize_internal_state_machine(struct flash_bank
*bank
)
542 uint32_t fmmac2
, fmmac1
, fmmaxep
, k
, delay
, glbctrl
, sysclk
;
543 struct target
*target
= bank
->target
;
544 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
545 int result
= ERROR_OK
;
548 * Select the desired bank to be programmed by writing BANK[2:0] of
551 target_read_u32(target
, 0xFFE8BC04, &fmmac2
);
553 fmmac2
|= (tms470_info
->ordinal
& 7);
554 target_write_u32(target
, 0xFFE8BC04, fmmac2
);
555 LOG_DEBUG("set fmmac2 = 0x%04" PRIx32
"", fmmac2
);
558 * Disable level 1 sector protection by setting bit 15 of FMMAC1.
560 target_read_u32(target
, 0xFFE8BC00, &fmmac1
);
562 target_write_u32(target
, 0xFFE8BC00, fmmac1
);
563 LOG_DEBUG("set fmmac1 = 0x%04" PRIx32
"", fmmac1
);
568 target_write_u32(target
, 0xFFE8BC10, 0x2fc0);
569 LOG_DEBUG("set fmtcreg = 0x2fc0");
574 target_write_u32(target
, 0xFFE8A07C, 50);
575 LOG_DEBUG("set fmmaxpp = 50");
578 * MAXCP = 0xf000 + 2000
580 target_write_u32(target
, 0xFFE8A084, 0xf000 + 2000);
581 LOG_DEBUG("set fmmaxcp = 0x%04x", 0xf000 + 2000);
586 target_read_u32(target
, 0xFFE8A080, &fmmaxep
);
587 if (fmmaxep
== 0xf000)
589 fmmaxep
= 0xf000 + 4095;
590 target_write_u32(target
, 0xFFE8A80C, 0x9964);
591 LOG_DEBUG("set fmptr3 = 0x9964");
595 fmmaxep
= 0xa000 + 4095;
596 target_write_u32(target
, 0xFFE8A80C, 0x9b64);
597 LOG_DEBUG("set fmptr3 = 0x9b64");
599 target_write_u32(target
, 0xFFE8A080, fmmaxep
);
600 LOG_DEBUG("set fmmaxep = 0x%04" PRIx32
"", fmmaxep
);
605 target_write_u32(target
, 0xFFE8A810, 0xa000);
606 LOG_DEBUG("set fmptr4 = 0xa000");
609 * FMPESETUP, delay parameter selected based on clock frequency.
611 * According to the TI App Note SPNU257 and flashing code, delay is
612 * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
613 * clock is usually derived from the ZPLL module, and selected by
616 target_read_u32(target
, 0xFFFFFFDC, &glbctrl
);
617 sysclk
= (plldis
? 1 : (glbctrl
& 0x08) ? 4 : 8) * oscMHz
/ (1 + (glbctrl
& 7));
618 delay
= (sysclk
> 10) ? (sysclk
+ 1) / 2 : 5;
619 target_write_u32(target
, 0xFFE8A018, (delay
<< 4) | (delay
<< 8));
620 LOG_DEBUG("set fmpsetup = 0x%04" PRIx32
"", (delay
<< 4) | (delay
<< 8));
623 * FMPVEVACCESS, based on delay.
625 k
= delay
| (delay
<< 8);
626 target_write_u32(target
, 0xFFE8A05C, k
);
627 LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32
"", k
);
630 * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
633 target_write_u32(target
, 0xFFE8A034, k
);
634 LOG_DEBUG("set fmpchold = 0x%04" PRIx32
"", k
);
635 target_write_u32(target
, 0xFFE8A040, k
);
636 LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32
"", k
);
637 target_write_u32(target
, 0xFFE8A024, k
);
638 LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32
"", k
);
641 * FMCVACCESS, based on delay.
644 target_write_u32(target
, 0xFFE8A060, k
);
645 LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32
"", k
);
648 * FMCSETUP, based on delay.
650 k
= 0x3000 | delay
* 20;
651 target_write_u32(target
, 0xFFE8A020, k
);
652 LOG_DEBUG("set fmcsetup = 0x%04" PRIx32
"", k
);
655 * FMEHOLD, based on delay.
657 k
= (delay
* 20) << 2;
658 target_write_u32(target
, 0xFFE8A038, k
);
659 LOG_DEBUG("set fmehold = 0x%04" PRIx32
"", k
);
662 * PWIDTH, CWIDTH, EWIDTH, based on delay.
664 target_write_u32(target
, 0xFFE8A050, delay
* 8);
665 LOG_DEBUG("set fmpwidth = 0x%04" PRIx32
"", delay
* 8);
666 target_write_u32(target
, 0xFFE8A058, delay
* 1000);
667 LOG_DEBUG("set fmcwidth = 0x%04" PRIx32
"", delay
* 1000);
668 target_write_u32(target
, 0xFFE8A054, delay
* 5400);
669 LOG_DEBUG("set fmewidth = 0x%04" PRIx32
"", delay
* 5400);
674 /* ---------------------------------------------------------------------- */
676 static int tms470_flash_status(struct flash_bank
*bank
)
678 struct target
*target
= bank
->target
;
679 int result
= ERROR_OK
;
682 target_read_u32(target
, 0xFFE8BC0C, &fmmstat
);
683 LOG_DEBUG("set fmmstat = 0x%04" PRIx32
"", fmmstat
);
685 if (fmmstat
& 0x0080)
687 LOG_WARNING("tms470 flash command: erase still active after busy clear.");
688 result
= ERROR_FLASH_OPERATION_FAILED
;
691 if (fmmstat
& 0x0040)
693 LOG_WARNING("tms470 flash command: program still active after busy clear.");
694 result
= ERROR_FLASH_OPERATION_FAILED
;
697 if (fmmstat
& 0x0020)
699 LOG_WARNING("tms470 flash command: invalid data command.");
700 result
= ERROR_FLASH_OPERATION_FAILED
;
703 if (fmmstat
& 0x0010)
705 LOG_WARNING("tms470 flash command: program, erase or validate sector failed.");
706 result
= ERROR_FLASH_OPERATION_FAILED
;
709 if (fmmstat
& 0x0008)
711 LOG_WARNING("tms470 flash command: voltage instability detected.");
712 result
= ERROR_FLASH_OPERATION_FAILED
;
715 if (fmmstat
& 0x0006)
717 LOG_WARNING("tms470 flash command: command suspend detected.");
718 result
= ERROR_FLASH_OPERATION_FAILED
;
721 if (fmmstat
& 0x0001)
723 LOG_WARNING("tms470 flash command: sector was locked.");
724 result
= ERROR_FLASH_OPERATION_FAILED
;
730 /* ---------------------------------------------------------------------- */
732 static int tms470_erase_sector(struct flash_bank
*bank
, int sector
)
734 uint32_t glbctrl
, orig_fmregopt
, fmbsea
, fmbseb
, fmmstat
;
735 struct target
*target
= bank
->target
;
736 uint32_t flashAddr
= bank
->base
+ bank
->sectors
[sector
].offset
;
737 int result
= ERROR_OK
;
740 * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
741 * module) to enable writing to the flash registers }.
743 target_read_u32(target
, 0xFFFFFFDC, &glbctrl
);
744 target_write_u32(target
, 0xFFFFFFDC, glbctrl
| 0x10);
745 LOG_DEBUG("set glbctrl = 0x%08" PRIx32
"", glbctrl
| 0x10);
747 /* Force normal read mode. */
748 target_read_u32(target
, 0xFFE89C00, &orig_fmregopt
);
749 target_write_u32(target
, 0xFFE89C00, 0);
750 LOG_DEBUG("set fmregopt = 0x%08x", 0);
752 (void)tms470_flash_initialize_internal_state_machine(bank
);
755 * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
756 * protection for the particular sector to be erased/written.
760 target_read_u32(target
, 0xFFE88008, &fmbsea
);
761 target_write_u32(target
, 0xFFE88008, fmbsea
| (1 << sector
));
762 LOG_DEBUG("set fmbsea = 0x%04" PRIx32
"", fmbsea
| (1 << sector
));
766 target_read_u32(target
, 0xFFE8800C, &fmbseb
);
767 target_write_u32(target
, 0xFFE8800C, fmbseb
| (1 << (sector
- 16)));
768 LOG_DEBUG("set fmbseb = 0x%04" PRIx32
"", fmbseb
| (1 << (sector
- 16)));
770 bank
->sectors
[sector
].is_protected
= 0;
773 * clear status regiser, sent erase command, kickoff erase
775 target_write_u16(target
, flashAddr
, 0x0040);
776 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32
"=0x0040", flashAddr
);
777 target_write_u16(target
, flashAddr
, 0x0020);
778 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32
"=0x0020", flashAddr
);
779 target_write_u16(target
, flashAddr
, 0xffff);
780 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32
"=0xffff", flashAddr
);
783 * Monitor FMMSTAT, busy until clear, then check and other flags for
784 * ultimate result of the operation.
788 target_read_u32(target
, 0xFFE8BC0C, &fmmstat
);
789 if (fmmstat
& 0x0100)
794 while (fmmstat
& 0x0100);
796 result
= tms470_flash_status(bank
);
800 target_write_u32(target
, 0xFFE88008, fmbsea
);
801 LOG_DEBUG("set fmbsea = 0x%04" PRIx32
"", fmbsea
);
802 bank
->sectors
[sector
].is_protected
= fmbsea
& (1 << sector
) ? 0 : 1;
806 target_write_u32(target
, 0xFFE8800C, fmbseb
);
807 LOG_DEBUG("set fmbseb = 0x%04" PRIx32
"", fmbseb
);
808 bank
->sectors
[sector
].is_protected
= fmbseb
& (1 << (sector
- 16)) ? 0 : 1;
810 target_write_u32(target
, 0xFFE89C00, orig_fmregopt
);
811 LOG_DEBUG("set fmregopt = 0x%08" PRIx32
"", orig_fmregopt
);
812 target_write_u32(target
, 0xFFFFFFDC, glbctrl
);
813 LOG_DEBUG("set glbctrl = 0x%08" PRIx32
"", glbctrl
);
815 if (result
== ERROR_OK
)
817 bank
->sectors
[sector
].is_erased
= 1;
823 /* ----------------------------------------------------------------------
824 Implementation of Flash Driver Interfaces
825 ---------------------------------------------------------------------- */
827 static const struct command_registration tms470_any_command_handlers
[] = {
829 .name
= "flash_keyset",
830 .handler
= tms470_handle_flash_keyset_command
,
832 .help
= "tms470 flash_keyset <key0> <key1> <key2> <key3>",
835 .name
= "osc_megahertz",
836 .handler
= tms470_handle_osc_megahertz_command
,
838 .help
= "tms470 osc_megahertz <MHz>",
842 .handler
= tms470_handle_plldis_command
,
844 .help
= "tms470 plldis <0/1>",
846 COMMAND_REGISTRATION_DONE
848 static const struct command_registration tms470_command_handlers
[] = {
852 .help
= "TI tms470 flash command group",
853 .chain
= tms470_any_command_handlers
,
855 COMMAND_REGISTRATION_DONE
858 /* ---------------------------------------------------------------------- */
860 static int tms470_erase(struct flash_bank
*bank
, int first
, int last
)
862 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
863 int sector
, result
= ERROR_OK
;
865 if (bank
->target
->state
!= TARGET_HALTED
)
867 LOG_ERROR("Target not halted");
868 return ERROR_TARGET_NOT_HALTED
;
871 tms470_read_part_info(bank
);
873 if ((first
< 0) || (first
>= bank
->num_sectors
) || (last
< 0) || (last
>= bank
->num_sectors
) || (first
> last
))
875 LOG_ERROR("Sector range %d to %d invalid.", first
, last
);
876 return ERROR_FLASH_SECTOR_INVALID
;
879 result
= tms470_unlock_flash(bank
);
880 if (result
!= ERROR_OK
)
885 for (sector
= first
; sector
<= last
; sector
++)
887 LOG_INFO("Erasing tms470 bank %d sector %d...", tms470_info
->ordinal
, sector
);
889 result
= tms470_erase_sector(bank
, sector
);
891 if (result
!= ERROR_OK
)
893 LOG_ERROR("tms470 could not erase flash sector.");
898 LOG_INFO("sector erased successfully.");
905 /* ---------------------------------------------------------------------- */
907 static int tms470_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
909 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
910 struct target
*target
= bank
->target
;
911 uint32_t fmmac2
, fmbsea
, fmbseb
;
914 if (target
->state
!= TARGET_HALTED
)
916 LOG_ERROR("Target not halted");
917 return ERROR_TARGET_NOT_HALTED
;
920 tms470_read_part_info(bank
);
922 if ((first
< 0) || (first
>= bank
->num_sectors
) || (last
< 0) || (last
>= bank
->num_sectors
) || (first
> last
))
924 LOG_ERROR("Sector range %d to %d invalid.", first
, last
);
925 return ERROR_FLASH_SECTOR_INVALID
;
928 /* enable the appropriate bank */
929 target_read_u32(target
, 0xFFE8BC04, &fmmac2
);
930 target_write_u32(target
, 0xFFE8BC04, (fmmac2
& ~7) | tms470_info
->ordinal
);
932 /* get the original sector proection flags for this bank */
933 target_read_u32(target
, 0xFFE88008, &fmbsea
);
934 target_read_u32(target
, 0xFFE8800C, &fmbseb
);
936 for (sector
= 0; sector
< bank
->num_sectors
; sector
++)
940 fmbsea
= set
? fmbsea
& ~(1 << sector
) : fmbsea
| (1 << sector
);
941 bank
->sectors
[sector
].is_protected
= set
? 1 : 0;
945 fmbseb
= set
? fmbseb
& ~(1 << (sector
- 16)) : fmbseb
| (1 << (sector
- 16));
946 bank
->sectors
[sector
].is_protected
= set
? 1 : 0;
950 /* update the protection bits */
951 target_write_u32(target
, 0xFFE88008, fmbsea
);
952 target_write_u32(target
, 0xFFE8800C, fmbseb
);
957 /* ---------------------------------------------------------------------- */
959 static int tms470_write(struct flash_bank
*bank
, uint8_t * buffer
, uint32_t offset
, uint32_t count
)
961 struct target
*target
= bank
->target
;
962 uint32_t glbctrl
, fmbac2
, orig_fmregopt
, fmbsea
, fmbseb
, fmmaxpp
, fmmstat
;
963 int result
= ERROR_OK
;
966 if (target
->state
!= TARGET_HALTED
)
968 LOG_ERROR("Target not halted");
969 return ERROR_TARGET_NOT_HALTED
;
972 tms470_read_part_info(bank
);
974 LOG_INFO("Writing %" PRId32
" bytes starting at 0x%08" PRIx32
"", count
, bank
->base
+ offset
);
977 target_read_u32(target
, 0xFFFFFFDC, &glbctrl
);
978 target_write_u32(target
, 0xFFFFFFDC, glbctrl
| 0x10);
980 (void)tms470_flash_initialize_internal_state_machine(bank
);
982 /* force max wait states */
983 target_read_u32(target
, 0xFFE88004, &fmbac2
);
984 target_write_u32(target
, 0xFFE88004, fmbac2
| 0xff);
986 /* save current access mode, force normal read mode */
987 target_read_u32(target
, 0xFFE89C00, &orig_fmregopt
);
988 target_write_u32(target
, 0xFFE89C00, 0x00);
991 * Disable Level 1 protection for all sectors to be erased/written.
993 target_read_u32(target
, 0xFFE88008, &fmbsea
);
994 target_write_u32(target
, 0xFFE88008, 0xffff);
995 target_read_u32(target
, 0xFFE8800C, &fmbseb
);
996 target_write_u32(target
, 0xFFE8800C, 0xffff);
999 target_read_u32(target
, 0xFFE8A07C, &fmmaxpp
);
1001 for (i
= 0; i
< count
; i
+= 2)
1003 uint32_t addr
= bank
->base
+ offset
+ i
;
1004 uint16_t word
= (((uint16_t) buffer
[i
]) << 8) | (uint16_t) buffer
[i
+ 1];
1008 LOG_INFO("writing 0x%04x at 0x%08" PRIx32
"", word
, addr
);
1010 /* clear status register */
1011 target_write_u16(target
, addr
, 0x0040);
1012 /* program flash command */
1013 target_write_u16(target
, addr
, 0x0010);
1014 /* burn the 16-bit word (big-endian) */
1015 target_write_u16(target
, addr
, word
);
1018 * Monitor FMMSTAT, busy until clear, then check and other flags
1019 * for ultimate result of the operation.
1023 target_read_u32(target
, 0xFFE8BC0C, &fmmstat
);
1024 if (fmmstat
& 0x0100)
1029 while (fmmstat
& 0x0100);
1031 if (fmmstat
& 0x3ff)
1033 LOG_ERROR("fmstat = 0x%04" PRIx32
"", fmmstat
);
1034 LOG_ERROR("Could not program word 0x%04x at address 0x%08" PRIx32
".", word
, addr
);
1035 result
= ERROR_FLASH_OPERATION_FAILED
;
1041 LOG_INFO("skipping 0xffff at 0x%08" PRIx32
"", addr
);
1046 target_write_u32(target
, 0xFFE88008, fmbsea
);
1047 target_write_u32(target
, 0xFFE8800C, fmbseb
);
1048 target_write_u32(target
, 0xFFE88004, fmbac2
);
1049 target_write_u32(target
, 0xFFE89C00, orig_fmregopt
);
1050 target_write_u32(target
, 0xFFFFFFDC, glbctrl
);
1055 /* ---------------------------------------------------------------------- */
1057 static int tms470_probe(struct flash_bank
*bank
)
1059 if (bank
->target
->state
!= TARGET_HALTED
)
1061 LOG_WARNING("Cannot communicate... target not halted.");
1062 return ERROR_TARGET_NOT_HALTED
;
1065 return tms470_read_part_info(bank
);
1068 static int tms470_auto_probe(struct flash_bank
*bank
)
1070 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
1072 if (tms470_info
->device_ident_reg
)
1074 return tms470_probe(bank
);
1077 /* ---------------------------------------------------------------------- */
1079 static int tms470_erase_check(struct flash_bank
*bank
)
1081 struct target
*target
= bank
->target
;
1082 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
1083 int sector
, result
= ERROR_OK
;
1084 uint32_t fmmac2
, fmbac2
, glbctrl
, orig_fmregopt
;
1085 static uint8_t buffer
[64 * 1024];
1087 if (target
->state
!= TARGET_HALTED
)
1089 LOG_ERROR("Target not halted");
1090 return ERROR_TARGET_NOT_HALTED
;
1093 if (!tms470_info
->device_ident_reg
)
1095 tms470_read_part_info(bank
);
1099 target_read_u32(target
, 0xFFFFFFDC, &glbctrl
);
1100 target_write_u32(target
, 0xFFFFFFDC, glbctrl
| 0x10);
1102 /* save current access mode, force normal read mode */
1103 target_read_u32(target
, 0xFFE89C00, &orig_fmregopt
);
1104 target_write_u32(target
, 0xFFE89C00, 0x00);
1106 /* enable the appropriate bank */
1107 target_read_u32(target
, 0xFFE8BC04, &fmmac2
);
1108 target_write_u32(target
, 0xFFE8BC04, (fmmac2
& ~7) | tms470_info
->ordinal
);
1111 target_write_u32(target
, 0xFFE8BC10, 0x2fc0);
1113 /* clear TEZ in fmbrdy */
1114 target_write_u32(target
, 0xFFE88010, 0x0b);
1116 /* save current wait states, force max */
1117 target_read_u32(target
, 0xFFE88004, &fmbac2
);
1118 target_write_u32(target
, 0xFFE88004, fmbac2
| 0xff);
1121 * The TI primitives inspect the flash memory by reading one 32-bit
1122 * word at a time. Here we read an entire sector and inspect it in
1123 * an attempt to reduce the JTAG overhead.
1125 for (sector
= 0; sector
< bank
->num_sectors
; sector
++)
1127 if (bank
->sectors
[sector
].is_erased
!= 1)
1129 uint32_t i
, addr
= bank
->base
+ bank
->sectors
[sector
].offset
;
1131 LOG_INFO("checking flash bank %d sector %d", tms470_info
->ordinal
, sector
);
1133 target_read_buffer(target
, addr
, bank
->sectors
[sector
].size
, buffer
);
1135 bank
->sectors
[sector
].is_erased
= 1;
1136 for (i
= 0; i
< bank
->sectors
[sector
].size
; i
++)
1138 if (buffer
[i
] != 0xff)
1140 LOG_WARNING("tms470 bank %d, sector %d, not erased.", tms470_info
->ordinal
, sector
);
1141 LOG_WARNING("at location 0x%08" PRIx32
": flash data is 0x%02x.", addr
+ i
, buffer
[i
]);
1143 bank
->sectors
[sector
].is_erased
= 0;
1148 if (bank
->sectors
[sector
].is_erased
!= 1)
1150 result
= ERROR_FLASH_SECTOR_NOT_ERASED
;
1155 LOG_INFO("sector erased");
1159 /* reset TEZ, wait states, read mode, GLBCTRL.4 */
1160 target_write_u32(target
, 0xFFE88010, 0x0f);
1161 target_write_u32(target
, 0xFFE88004, fmbac2
);
1162 target_write_u32(target
, 0xFFE89C00, orig_fmregopt
);
1163 target_write_u32(target
, 0xFFFFFFDC, glbctrl
);
1168 /* ---------------------------------------------------------------------- */
1170 static int tms470_protect_check(struct flash_bank
*bank
)
1172 struct target
*target
= bank
->target
;
1173 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
1174 int sector
, result
= ERROR_OK
;
1175 uint32_t fmmac2
, fmbsea
, fmbseb
;
1177 if (target
->state
!= TARGET_HALTED
)
1179 LOG_ERROR("Target not halted");
1180 return ERROR_TARGET_NOT_HALTED
;
1183 if (!tms470_info
->device_ident_reg
)
1185 tms470_read_part_info(bank
);
1188 /* enable the appropriate bank */
1189 target_read_u32(target
, 0xFFE8BC04, &fmmac2
);
1190 target_write_u32(target
, 0xFFE8BC04, (fmmac2
& ~7) | tms470_info
->ordinal
);
1192 target_read_u32(target
, 0xFFE88008, &fmbsea
);
1193 target_read_u32(target
, 0xFFE8800C, &fmbseb
);
1195 for (sector
= 0; sector
< bank
->num_sectors
; sector
++)
1201 protected = fmbsea
& (1 << sector
) ? 0 : 1;
1202 bank
->sectors
[sector
].is_protected
= protected;
1206 protected = fmbseb
& (1 << (sector
- 16)) ? 0 : 1;
1207 bank
->sectors
[sector
].is_protected
= protected;
1210 LOG_DEBUG("bank %d sector %d is %s", tms470_info
->ordinal
, sector
, protected ? "protected" : "not protected");
1216 /* ---------------------------------------------------------------------- */
1218 static int tms470_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1221 struct tms470_flash_bank
*tms470_info
= bank
->driver_priv
;
1223 if (!tms470_info
->device_ident_reg
)
1225 tms470_read_part_info(bank
);
1228 if (!tms470_info
->device_ident_reg
)
1230 (void)snprintf(buf
, buf_size
, "Cannot identify target as a TMS470\n");
1231 return ERROR_FLASH_OPERATION_FAILED
;
1234 used
+= snprintf(buf
, buf_size
, "\ntms470 information: Chip is %s\n", tms470_info
->part_name
);
1238 used
+= snprintf(buf
, buf_size
, "Flash protection level 2 is %s\n", tms470_check_flash_unlocked(bank
->target
) == ERROR_OK
? "disabled" : "enabled");
1245 /* ---------------------------------------------------------------------- */
1248 * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
1252 FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command
)
1254 bank
->driver_priv
= malloc(sizeof(struct tms470_flash_bank
));
1256 if (!bank
->driver_priv
)
1258 return ERROR_FLASH_OPERATION_FAILED
;
1261 (void)memset(bank
->driver_priv
, 0, sizeof(struct tms470_flash_bank
));
1266 struct flash_driver tms470_flash
= {
1268 .commands
= tms470_command_handlers
,
1269 .flash_bank_command
= tms470_flash_bank_command
,
1270 .erase
= tms470_erase
,
1271 .protect
= tms470_protect
,
1272 .write
= tms470_write
,
1273 .read
= default_flash_read
,
1274 .probe
= tms470_probe
,
1275 .auto_probe
= tms470_auto_probe
,
1276 .erase_check
= tms470_erase_check
,
1277 .protect_check
= tms470_protect_check
,
1278 .info
= tms470_info
,