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ebdcde7b86375aba4df497ee7a33be8a8a581feb
[openocd.git] / src / flash / nor / stm32x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "stm32x.h"
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
32
33
34 static int stm32x_mass_erase(struct flash_bank *bank);
35
36 /* flash bank stm32x <base> <size> 0 0 <target#>
37 */
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
39 {
40 struct stm32x_flash_bank *stm32x_info;
41
42 if (CMD_ARGC < 6)
43 {
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
46 }
47
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49 bank->driver_priv = stm32x_info;
50
51 stm32x_info->write_algorithm = NULL;
52 stm32x_info->probed = 0;
53
54 return ERROR_OK;
55 }
56
57 static uint32_t stm32x_get_flash_status(struct flash_bank *bank)
58 {
59 struct target *target = bank->target;
60 uint32_t status;
61
62 target_read_u32(target, STM32_FLASH_SR, &status);
63
64 return status;
65 }
66
67 static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
68 {
69 struct target *target = bank->target;
70 uint32_t status;
71
72 /* wait for busy to clear */
73 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
74 {
75 LOG_DEBUG("status: 0x%" PRIx32 "", status);
76 alive_sleep(1);
77 }
78 /* Clear but report errors */
79 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
80 {
81 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
82 }
83 return status;
84 }
85
86 static int stm32x_read_options(struct flash_bank *bank)
87 {
88 uint32_t optiondata;
89 struct stm32x_flash_bank *stm32x_info = NULL;
90 struct target *target = bank->target;
91
92 stm32x_info = bank->driver_priv;
93
94 /* read current option bytes */
95 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
96
97 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
98 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
99
100 if (optiondata & (1 << OPT_READOUT))
101 LOG_INFO("Device Security Bit Set");
102
103 /* each bit refers to a 4bank protection */
104 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
105
106 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
107 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
108 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
109 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
110
111 return ERROR_OK;
112 }
113
114 static int stm32x_erase_options(struct flash_bank *bank)
115 {
116 struct stm32x_flash_bank *stm32x_info = NULL;
117 struct target *target = bank->target;
118 uint32_t status;
119
120 stm32x_info = bank->driver_priv;
121
122 /* read current options */
123 stm32x_read_options(bank);
124
125 /* unlock flash registers */
126 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
127 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
128
129 /* unlock option flash registers */
130 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
131 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
132
133 /* erase option bytes */
134 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
135 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
136
137 status = stm32x_wait_status_busy(bank, 10);
138
139 if (status & FLASH_WRPRTERR)
140 return ERROR_FLASH_OPERATION_FAILED;
141 if (status & FLASH_PGERR)
142 return ERROR_FLASH_OPERATION_FAILED;
143
144 /* clear readout protection and complementary option bytes
145 * this will also force a device unlock if set */
146 stm32x_info->option_bytes.RDP = 0x5AA5;
147
148 return ERROR_OK;
149 }
150
151 static int stm32x_write_options(struct flash_bank *bank)
152 {
153 struct stm32x_flash_bank *stm32x_info = NULL;
154 struct target *target = bank->target;
155 uint32_t status;
156
157 stm32x_info = bank->driver_priv;
158
159 /* unlock flash registers */
160 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
161 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
162
163 /* unlock option flash registers */
164 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
165 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
166
167 /* program option bytes */
168 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
169
170 /* write user option byte */
171 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
172
173 status = stm32x_wait_status_busy(bank, 10);
174
175 if (status & FLASH_WRPRTERR)
176 return ERROR_FLASH_OPERATION_FAILED;
177 if (status & FLASH_PGERR)
178 return ERROR_FLASH_OPERATION_FAILED;
179
180 /* write protection byte 1 */
181 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
182
183 status = stm32x_wait_status_busy(bank, 10);
184
185 if (status & FLASH_WRPRTERR)
186 return ERROR_FLASH_OPERATION_FAILED;
187 if (status & FLASH_PGERR)
188 return ERROR_FLASH_OPERATION_FAILED;
189
190 /* write protection byte 2 */
191 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
192
193 status = stm32x_wait_status_busy(bank, 10);
194
195 if (status & FLASH_WRPRTERR)
196 return ERROR_FLASH_OPERATION_FAILED;
197 if (status & FLASH_PGERR)
198 return ERROR_FLASH_OPERATION_FAILED;
199
200 /* write protection byte 3 */
201 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
202
203 status = stm32x_wait_status_busy(bank, 10);
204
205 if (status & FLASH_WRPRTERR)
206 return ERROR_FLASH_OPERATION_FAILED;
207 if (status & FLASH_PGERR)
208 return ERROR_FLASH_OPERATION_FAILED;
209
210 /* write protection byte 4 */
211 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
212
213 status = stm32x_wait_status_busy(bank, 10);
214
215 if (status & FLASH_WRPRTERR)
216 return ERROR_FLASH_OPERATION_FAILED;
217 if (status & FLASH_PGERR)
218 return ERROR_FLASH_OPERATION_FAILED;
219
220 /* write readout protection bit */
221 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
222
223 status = stm32x_wait_status_busy(bank, 10);
224
225 if (status & FLASH_WRPRTERR)
226 return ERROR_FLASH_OPERATION_FAILED;
227 if (status & FLASH_PGERR)
228 return ERROR_FLASH_OPERATION_FAILED;
229
230 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
231
232 return ERROR_OK;
233 }
234
235 static int stm32x_protect_check(struct flash_bank *bank)
236 {
237 struct target *target = bank->target;
238 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
239
240 uint32_t protection;
241 int i, s;
242 int num_bits;
243 int set;
244
245 if (target->state != TARGET_HALTED)
246 {
247 LOG_ERROR("Target not halted");
248 return ERROR_TARGET_NOT_HALTED;
249 }
250
251 /* medium density - each bit refers to a 4bank protection
252 * high density - each bit refers to a 2bank protection */
253 target_read_u32(target, STM32_FLASH_WRPR, &protection);
254
255 /* medium density - each protection bit is for 4 * 1K pages
256 * high density - each protection bit is for 2 * 2K pages */
257 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
258
259 if (stm32x_info->ppage_size == 2)
260 {
261 /* high density flash/connectivity line protection */
262
263 set = 1;
264
265 if (protection & (1 << 31))
266 set = 0;
267
268 /* bit 31 controls sector 62 - 255 protection for high density
269 * bit 31 controls sector 62 - 127 protection for connectivity line */
270 for (s = 62; s < bank->num_sectors; s++)
271 {
272 bank->sectors[s].is_protected = set;
273 }
274
275 if (bank->num_sectors > 61)
276 num_bits = 31;
277
278 for (i = 0; i < num_bits; i++)
279 {
280 set = 1;
281
282 if (protection & (1 << i))
283 set = 0;
284
285 for (s = 0; s < stm32x_info->ppage_size; s++)
286 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
287 }
288 }
289 else
290 {
291 /* low/medium density flash protection */
292 for (i = 0; i < num_bits; i++)
293 {
294 set = 1;
295
296 if (protection & (1 << i))
297 set = 0;
298
299 for (s = 0; s < stm32x_info->ppage_size; s++)
300 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
301 }
302 }
303
304 return ERROR_OK;
305 }
306
307 static int stm32x_erase(struct flash_bank *bank, int first, int last)
308 {
309 struct target *target = bank->target;
310 int i;
311 uint32_t status;
312
313 if (bank->target->state != TARGET_HALTED)
314 {
315 LOG_ERROR("Target not halted");
316 return ERROR_TARGET_NOT_HALTED;
317 }
318
319 if ((first == 0) && (last == (bank->num_sectors - 1)))
320 {
321 return stm32x_mass_erase(bank);
322 }
323
324 /* unlock flash registers */
325 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
326 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
327
328 for (i = first; i <= last; i++)
329 {
330 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
331 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
332 target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
333
334 status = stm32x_wait_status_busy(bank, 10);
335
336 if (status & FLASH_WRPRTERR)
337 return ERROR_FLASH_OPERATION_FAILED;
338 if (status & FLASH_PGERR)
339 return ERROR_FLASH_OPERATION_FAILED;
340 bank->sectors[i].is_erased = 1;
341 }
342
343 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
344
345 return ERROR_OK;
346 }
347
348 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
349 {
350 struct stm32x_flash_bank *stm32x_info = NULL;
351 struct target *target = bank->target;
352 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
353 int i, reg, bit;
354 int status;
355 uint32_t protection;
356
357 stm32x_info = bank->driver_priv;
358
359 if (target->state != TARGET_HALTED)
360 {
361 LOG_ERROR("Target not halted");
362 return ERROR_TARGET_NOT_HALTED;
363 }
364
365 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
366 {
367 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary", stm32x_info->ppage_size);
368 return ERROR_FLASH_SECTOR_INVALID;
369 }
370
371 /* medium density - each bit refers to a 4bank protection
372 * high density - each bit refers to a 2bank protection */
373 target_read_u32(target, STM32_FLASH_WRPR, &protection);
374
375 prot_reg[0] = (uint16_t)protection;
376 prot_reg[1] = (uint16_t)(protection >> 8);
377 prot_reg[2] = (uint16_t)(protection >> 16);
378 prot_reg[3] = (uint16_t)(protection >> 24);
379
380 if (stm32x_info->ppage_size == 2)
381 {
382 /* high density flash */
383
384 /* bit 7 controls sector 62 - 255 protection */
385 if (last > 61)
386 {
387 if (set)
388 prot_reg[3] &= ~(1 << 7);
389 else
390 prot_reg[3] |= (1 << 7);
391 }
392
393 if (first > 61)
394 first = 62;
395 if (last > 61)
396 last = 61;
397
398 for (i = first; i <= last; i++)
399 {
400 reg = (i / stm32x_info->ppage_size) / 8;
401 bit = (i / stm32x_info->ppage_size) - (reg * 8);
402
403 if (set)
404 prot_reg[reg] &= ~(1 << bit);
405 else
406 prot_reg[reg] |= (1 << bit);
407 }
408 }
409 else
410 {
411 /* medium density flash */
412 for (i = first; i <= last; i++)
413 {
414 reg = (i / stm32x_info->ppage_size) / 8;
415 bit = (i / stm32x_info->ppage_size) - (reg * 8);
416
417 if (set)
418 prot_reg[reg] &= ~(1 << bit);
419 else
420 prot_reg[reg] |= (1 << bit);
421 }
422 }
423
424 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
425 return status;
426
427 stm32x_info->option_bytes.protection[0] = prot_reg[0];
428 stm32x_info->option_bytes.protection[1] = prot_reg[1];
429 stm32x_info->option_bytes.protection[2] = prot_reg[2];
430 stm32x_info->option_bytes.protection[3] = prot_reg[3];
431
432 return stm32x_write_options(bank);
433 }
434
435 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
436 {
437 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
438 struct target *target = bank->target;
439 uint32_t buffer_size = 16384;
440 struct working_area *source;
441 uint32_t address = bank->base + offset;
442 struct reg_param reg_params[4];
443 struct armv7m_algorithm armv7m_info;
444 int retval = ERROR_OK;
445
446 uint8_t stm32x_flash_write_code[] = {
447 /* write: */
448 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
449 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
450 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
451 0x23, 0x60, /* str r3, [r4, #0] */
452 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
453 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
454 /* busy: */
455 0x2B, 0x68, /* ldr r3, [r5, #0] */
456 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
457 0xFB, 0xD0, /* beq busy */
458 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
459 0x01, 0xD1, /* bne exit */
460 0x01, 0x3A, /* subs r2, r2, #1 */
461 0xED, 0xD1, /* bne write */
462 0x00, 0xBE, /* bkpt #0 */
463 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
464 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
465 };
466
467 /* flash write code */
468 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
469 {
470 LOG_WARNING("no working area available, can't do block memory writes");
471 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
472 };
473
474 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
475 return retval;
476
477 /* memory buffer */
478 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
479 {
480 buffer_size /= 2;
481 if (buffer_size <= 256)
482 {
483 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
484 if (stm32x_info->write_algorithm)
485 target_free_working_area(target, stm32x_info->write_algorithm);
486
487 LOG_WARNING("no large enough working area available, can't do block memory writes");
488 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
489 }
490 };
491
492 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
493 armv7m_info.core_mode = ARMV7M_MODE_ANY;
494
495 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
496 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
497 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
498 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
499
500 while (count > 0)
501 {
502 uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
503
504 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer)) != ERROR_OK)
505 break;
506
507 buf_set_u32(reg_params[0].value, 0, 32, source->address);
508 buf_set_u32(reg_params[1].value, 0, 32, address);
509 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
510
511 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
512 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
513 {
514 LOG_ERROR("error executing stm32x flash write algorithm");
515 retval = ERROR_FLASH_OPERATION_FAILED;
516 break;
517 }
518
519 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
520 {
521 LOG_ERROR("flash memory not erased before writing");
522 /* Clear but report errors */
523 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
524 retval = ERROR_FLASH_OPERATION_FAILED;
525 break;
526 }
527
528 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
529 {
530 LOG_ERROR("flash memory write protected");
531 /* Clear but report errors */
532 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
533 retval = ERROR_FLASH_OPERATION_FAILED;
534 break;
535 }
536
537 buffer += thisrun_count * 2;
538 address += thisrun_count * 2;
539 count -= thisrun_count;
540 }
541
542 target_free_working_area(target, source);
543 target_free_working_area(target, stm32x_info->write_algorithm);
544
545 destroy_reg_param(&reg_params[0]);
546 destroy_reg_param(&reg_params[1]);
547 destroy_reg_param(&reg_params[2]);
548 destroy_reg_param(&reg_params[3]);
549
550 return retval;
551 }
552
553 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
554 {
555 struct target *target = bank->target;
556 uint32_t words_remaining = (count / 2);
557 uint32_t bytes_remaining = (count & 0x00000001);
558 uint32_t address = bank->base + offset;
559 uint32_t bytes_written = 0;
560 uint8_t status;
561 int retval;
562
563 if (bank->target->state != TARGET_HALTED)
564 {
565 LOG_ERROR("Target not halted");
566 return ERROR_TARGET_NOT_HALTED;
567 }
568
569 if (offset & 0x1)
570 {
571 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
572 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
573 }
574
575 /* unlock flash registers */
576 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
577 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
578
579 /* multiple half words (2-byte) to be programmed? */
580 if (words_remaining > 0)
581 {
582 /* try using a block write */
583 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
584 {
585 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
586 {
587 /* if block write failed (no sufficient working area),
588 * we use normal (slow) single dword accesses */
589 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
590 }
591 else if (retval == ERROR_FLASH_OPERATION_FAILED)
592 {
593 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
594 return ERROR_FLASH_OPERATION_FAILED;
595 }
596 }
597 else
598 {
599 buffer += words_remaining * 2;
600 address += words_remaining * 2;
601 words_remaining = 0;
602 }
603 }
604
605 while (words_remaining > 0)
606 {
607 uint16_t value;
608 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
609
610 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
611 target_write_u16(target, address, value);
612
613 status = stm32x_wait_status_busy(bank, 5);
614
615 if (status & FLASH_WRPRTERR)
616 {
617 LOG_ERROR("flash memory not erased before writing");
618 return ERROR_FLASH_OPERATION_FAILED;
619 }
620 if (status & FLASH_PGERR)
621 {
622 LOG_ERROR("flash memory write protected");
623 return ERROR_FLASH_OPERATION_FAILED;
624 }
625
626 bytes_written += 2;
627 words_remaining--;
628 address += 2;
629 }
630
631 if (bytes_remaining)
632 {
633 uint16_t value = 0xffff;
634 memcpy(&value, buffer + bytes_written, bytes_remaining);
635
636 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
637 target_write_u16(target, address, value);
638
639 status = stm32x_wait_status_busy(bank, 5);
640
641 if (status & FLASH_WRPRTERR)
642 {
643 LOG_ERROR("flash memory not erased before writing");
644 return ERROR_FLASH_OPERATION_FAILED;
645 }
646 if (status & FLASH_PGERR)
647 {
648 LOG_ERROR("flash memory write protected");
649 return ERROR_FLASH_OPERATION_FAILED;
650 }
651 }
652
653 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
654
655 return ERROR_OK;
656 }
657
658 static int stm32x_probe(struct flash_bank *bank)
659 {
660 struct target *target = bank->target;
661 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
662 int i;
663 uint16_t num_pages;
664 uint32_t device_id;
665 int page_size;
666
667 if (bank->target->state != TARGET_HALTED)
668 {
669 LOG_ERROR("Target not halted");
670 return ERROR_TARGET_NOT_HALTED;
671 }
672
673 stm32x_info->probed = 0;
674
675 /* read stm32 device id register */
676 target_read_u32(target, 0xE0042000, &device_id);
677 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
678
679 /* get flash size from target */
680 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
681 {
682 /* failed reading flash size, default to max target family */
683 num_pages = 0xffff;
684 }
685
686 if ((device_id & 0x7ff) == 0x410)
687 {
688 /* medium density - we have 1k pages
689 * 4 pages for a protection area */
690 page_size = 1024;
691 stm32x_info->ppage_size = 4;
692
693 /* check for early silicon */
694 if (num_pages == 0xffff)
695 {
696 /* number of sectors incorrect on revA */
697 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
698 num_pages = 128;
699 }
700 }
701 else if ((device_id & 0x7ff) == 0x412)
702 {
703 /* low density - we have 1k pages
704 * 4 pages for a protection area */
705 page_size = 1024;
706 stm32x_info->ppage_size = 4;
707
708 /* check for early silicon */
709 if (num_pages == 0xffff)
710 {
711 /* number of sectors incorrect on revA */
712 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
713 num_pages = 32;
714 }
715 }
716 else if ((device_id & 0x7ff) == 0x414)
717 {
718 /* high density - we have 2k pages
719 * 2 pages for a protection area */
720 page_size = 2048;
721 stm32x_info->ppage_size = 2;
722
723 /* check for early silicon */
724 if (num_pages == 0xffff)
725 {
726 /* number of sectors incorrect on revZ */
727 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
728 num_pages = 512;
729 }
730 }
731 else if ((device_id & 0x7ff) == 0x418)
732 {
733 /* connectivity line density - we have 2k pages
734 * 2 pages for a protection area */
735 page_size = 2048;
736 stm32x_info->ppage_size = 2;
737
738 /* check for early silicon */
739 if (num_pages == 0xffff)
740 {
741 /* number of sectors incorrect on revZ */
742 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
743 num_pages = 256;
744 }
745 }
746 else if ((device_id & 0x7ff) == 0x420)
747 {
748 /* value line density - we have 1k pages
749 * 4 pages for a protection area */
750 page_size = 1024;
751 stm32x_info->ppage_size = 4;
752
753 /* check for early silicon */
754 if (num_pages == 0xffff)
755 {
756 /* number of sectors may be incorrrect on early silicon */
757 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
758 num_pages = 128;
759 }
760 }
761 else
762 {
763 LOG_WARNING("Cannot identify target as a STM32 family.");
764 return ERROR_FLASH_OPERATION_FAILED;
765 }
766
767 LOG_INFO("flash size = %dkbytes", num_pages);
768
769 /* calculate numbers of pages */
770 num_pages /= (page_size / 1024);
771
772 bank->base = 0x08000000;
773 bank->size = (num_pages * page_size);
774 bank->num_sectors = num_pages;
775 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
776
777 for (i = 0; i < num_pages; i++)
778 {
779 bank->sectors[i].offset = i * page_size;
780 bank->sectors[i].size = page_size;
781 bank->sectors[i].is_erased = -1;
782 bank->sectors[i].is_protected = 1;
783 }
784
785 stm32x_info->probed = 1;
786
787 return ERROR_OK;
788 }
789
790 static int stm32x_auto_probe(struct flash_bank *bank)
791 {
792 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
793 if (stm32x_info->probed)
794 return ERROR_OK;
795 return stm32x_probe(bank);
796 }
797
798 #if 0
799 COMMAND_HANDLER(stm32x_handle_part_id_command)
800 {
801 return ERROR_OK;
802 }
803 #endif
804
805 static int stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
806 {
807 struct target *target = bank->target;
808 uint32_t device_id;
809 int printed;
810
811 /* read stm32 device id register */
812 target_read_u32(target, 0xE0042000, &device_id);
813
814 if ((device_id & 0x7ff) == 0x410)
815 {
816 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
817 buf += printed;
818 buf_size -= printed;
819
820 switch (device_id >> 16)
821 {
822 case 0x0000:
823 snprintf(buf, buf_size, "A");
824 break;
825
826 case 0x2000:
827 snprintf(buf, buf_size, "B");
828 break;
829
830 case 0x2001:
831 snprintf(buf, buf_size, "Z");
832 break;
833
834 case 0x2003:
835 snprintf(buf, buf_size, "Y");
836 break;
837
838 default:
839 snprintf(buf, buf_size, "unknown");
840 break;
841 }
842 }
843 else if ((device_id & 0x7ff) == 0x412)
844 {
845 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
846 buf += printed;
847 buf_size -= printed;
848
849 switch (device_id >> 16)
850 {
851 case 0x1000:
852 snprintf(buf, buf_size, "A");
853 break;
854
855 default:
856 snprintf(buf, buf_size, "unknown");
857 break;
858 }
859 }
860 else if ((device_id & 0x7ff) == 0x414)
861 {
862 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
863 buf += printed;
864 buf_size -= printed;
865
866 switch (device_id >> 16)
867 {
868 case 0x1000:
869 snprintf(buf, buf_size, "A");
870 break;
871
872 case 0x1001:
873 snprintf(buf, buf_size, "Z");
874 break;
875
876 default:
877 snprintf(buf, buf_size, "unknown");
878 break;
879 }
880 }
881 else if ((device_id & 0x7ff) == 0x418)
882 {
883 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
884 buf += printed;
885 buf_size -= printed;
886
887 switch (device_id >> 16)
888 {
889 case 0x1000:
890 snprintf(buf, buf_size, "A");
891 break;
892
893 case 0x1001:
894 snprintf(buf, buf_size, "Z");
895 break;
896
897 default:
898 snprintf(buf, buf_size, "unknown");
899 break;
900 }
901 }
902 else if ((device_id & 0x7ff) == 0x420)
903 {
904 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
905 buf += printed;
906 buf_size -= printed;
907
908 switch (device_id >> 16)
909 {
910 case 0x1000:
911 snprintf(buf, buf_size, "A");
912 break;
913
914 case 0x1001:
915 snprintf(buf, buf_size, "Z");
916 break;
917
918 default:
919 snprintf(buf, buf_size, "unknown");
920 break;
921 }
922 }
923 else
924 {
925 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
926 return ERROR_FLASH_OPERATION_FAILED;
927 }
928
929 return ERROR_OK;
930 }
931
932 COMMAND_HANDLER(stm32x_handle_lock_command)
933 {
934 struct target *target = NULL;
935 struct stm32x_flash_bank *stm32x_info = NULL;
936
937 if (CMD_ARGC < 1)
938 {
939 command_print(CMD_CTX, "stm32x lock <bank>");
940 return ERROR_OK;
941 }
942
943 struct flash_bank *bank;
944 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
945 if (ERROR_OK != retval)
946 return retval;
947
948 stm32x_info = bank->driver_priv;
949
950 target = bank->target;
951
952 if (target->state != TARGET_HALTED)
953 {
954 LOG_ERROR("Target not halted");
955 return ERROR_TARGET_NOT_HALTED;
956 }
957
958 if (stm32x_erase_options(bank) != ERROR_OK)
959 {
960 command_print(CMD_CTX, "stm32x failed to erase options");
961 return ERROR_OK;
962 }
963
964 /* set readout protection */
965 stm32x_info->option_bytes.RDP = 0;
966
967 if (stm32x_write_options(bank) != ERROR_OK)
968 {
969 command_print(CMD_CTX, "stm32x failed to lock device");
970 return ERROR_OK;
971 }
972
973 command_print(CMD_CTX, "stm32x locked");
974
975 return ERROR_OK;
976 }
977
978 COMMAND_HANDLER(stm32x_handle_unlock_command)
979 {
980 struct target *target = NULL;
981 struct stm32x_flash_bank *stm32x_info = NULL;
982
983 if (CMD_ARGC < 1)
984 {
985 command_print(CMD_CTX, "stm32x unlock <bank>");
986 return ERROR_OK;
987 }
988
989 struct flash_bank *bank;
990 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
991 if (ERROR_OK != retval)
992 return retval;
993
994 stm32x_info = bank->driver_priv;
995
996 target = bank->target;
997
998 if (target->state != TARGET_HALTED)
999 {
1000 LOG_ERROR("Target not halted");
1001 return ERROR_TARGET_NOT_HALTED;
1002 }
1003
1004 if (stm32x_erase_options(bank) != ERROR_OK)
1005 {
1006 command_print(CMD_CTX, "stm32x failed to unlock device");
1007 return ERROR_OK;
1008 }
1009
1010 if (stm32x_write_options(bank) != ERROR_OK)
1011 {
1012 command_print(CMD_CTX, "stm32x failed to lock device");
1013 return ERROR_OK;
1014 }
1015
1016 command_print(CMD_CTX, "stm32x unlocked.\n"
1017 "INFO: a reset or power cycle is required "
1018 "for the new settings to take effect.");
1019
1020 return ERROR_OK;
1021 }
1022
1023 COMMAND_HANDLER(stm32x_handle_options_read_command)
1024 {
1025 uint32_t optionbyte;
1026 struct target *target = NULL;
1027 struct stm32x_flash_bank *stm32x_info = NULL;
1028
1029 if (CMD_ARGC < 1)
1030 {
1031 command_print(CMD_CTX, "stm32x options_read <bank>");
1032 return ERROR_OK;
1033 }
1034
1035 struct flash_bank *bank;
1036 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1037 if (ERROR_OK != retval)
1038 return retval;
1039
1040 stm32x_info = bank->driver_priv;
1041
1042 target = bank->target;
1043
1044 if (target->state != TARGET_HALTED)
1045 {
1046 LOG_ERROR("Target not halted");
1047 return ERROR_TARGET_NOT_HALTED;
1048 }
1049
1050 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1051 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1052
1053 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1054 command_print(CMD_CTX, "Option Byte Complement Error");
1055
1056 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1057 command_print(CMD_CTX, "Readout Protection On");
1058 else
1059 command_print(CMD_CTX, "Readout Protection Off");
1060
1061 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1062 command_print(CMD_CTX, "Software Watchdog");
1063 else
1064 command_print(CMD_CTX, "Hardware Watchdog");
1065
1066 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1067 command_print(CMD_CTX, "Stop: No reset generated");
1068 else
1069 command_print(CMD_CTX, "Stop: Reset generated");
1070
1071 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1072 command_print(CMD_CTX, "Standby: No reset generated");
1073 else
1074 command_print(CMD_CTX, "Standby: Reset generated");
1075
1076 return ERROR_OK;
1077 }
1078
1079 COMMAND_HANDLER(stm32x_handle_options_write_command)
1080 {
1081 struct target *target = NULL;
1082 struct stm32x_flash_bank *stm32x_info = NULL;
1083 uint16_t optionbyte = 0xF8;
1084
1085 if (CMD_ARGC < 4)
1086 {
1087 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1088 return ERROR_OK;
1089 }
1090
1091 struct flash_bank *bank;
1092 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1093 if (ERROR_OK != retval)
1094 return retval;
1095
1096 stm32x_info = bank->driver_priv;
1097
1098 target = bank->target;
1099
1100 if (target->state != TARGET_HALTED)
1101 {
1102 LOG_ERROR("Target not halted");
1103 return ERROR_TARGET_NOT_HALTED;
1104 }
1105
1106 /* REVISIT: ignores some options which we will display...
1107 * and doesn't insist on the specified syntax.
1108 */
1109
1110 /* OPT_RDWDGSW */
1111 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1112 {
1113 optionbyte |= (1 << 0);
1114 }
1115 else /* REVISIT must be "HWWDG" then ... */
1116 {
1117 optionbyte &= ~(1 << 0);
1118 }
1119
1120 /* OPT_RDRSTSTDBY */
1121 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1122 {
1123 optionbyte |= (1 << 1);
1124 }
1125 else /* REVISIT must be "RSTSTNDBY" then ... */
1126 {
1127 optionbyte &= ~(1 << 1);
1128 }
1129
1130 /* OPT_RDRSTSTOP */
1131 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1132 {
1133 optionbyte |= (1 << 2);
1134 }
1135 else /* REVISIT must be "RSTSTOP" then ... */
1136 {
1137 optionbyte &= ~(1 << 2);
1138 }
1139
1140 if (stm32x_erase_options(bank) != ERROR_OK)
1141 {
1142 command_print(CMD_CTX, "stm32x failed to erase options");
1143 return ERROR_OK;
1144 }
1145
1146 stm32x_info->option_bytes.user_options = optionbyte;
1147
1148 if (stm32x_write_options(bank) != ERROR_OK)
1149 {
1150 command_print(CMD_CTX, "stm32x failed to write options");
1151 return ERROR_OK;
1152 }
1153
1154 command_print(CMD_CTX, "stm32x write options complete.\n"
1155 "INFO: a reset or power cycle is required "
1156 "for the new settings to take effect.");
1157
1158 return ERROR_OK;
1159 }
1160
1161 static int stm32x_mass_erase(struct flash_bank *bank)
1162 {
1163 struct target *target = bank->target;
1164 uint32_t status;
1165
1166 if (target->state != TARGET_HALTED)
1167 {
1168 LOG_ERROR("Target not halted");
1169 return ERROR_TARGET_NOT_HALTED;
1170 }
1171
1172 /* unlock option flash registers */
1173 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1174 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1175
1176 /* mass erase flash memory */
1177 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1178 target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1179
1180 status = stm32x_wait_status_busy(bank, 10);
1181
1182 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1183
1184 if (status & FLASH_WRPRTERR)
1185 {
1186 LOG_ERROR("stm32x device protected");
1187 return ERROR_OK;
1188 }
1189
1190 if (status & FLASH_PGERR)
1191 {
1192 LOG_ERROR("stm32x device programming failed");
1193 return ERROR_OK;
1194 }
1195
1196 return ERROR_OK;
1197 }
1198
1199 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1200 {
1201 int i;
1202
1203 if (CMD_ARGC < 1)
1204 {
1205 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1206 return ERROR_OK;
1207 }
1208
1209 struct flash_bank *bank;
1210 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1211 if (ERROR_OK != retval)
1212 return retval;
1213
1214 if (stm32x_mass_erase(bank) == ERROR_OK)
1215 {
1216 /* set all sectors as erased */
1217 for (i = 0; i < bank->num_sectors; i++)
1218 {
1219 bank->sectors[i].is_erased = 1;
1220 }
1221
1222 command_print(CMD_CTX, "stm32x mass erase complete");
1223 }
1224 else
1225 {
1226 command_print(CMD_CTX, "stm32x mass erase failed");
1227 }
1228
1229 return ERROR_OK;
1230 }
1231
1232 static const struct command_registration stm32x_exec_command_handlers[] = {
1233 {
1234 .name = "lock",
1235 .handler = stm32x_handle_lock_command,
1236 .mode = COMMAND_EXEC,
1237 .usage = "bank_id",
1238 .help = "Lock entire flash device.",
1239 },
1240 {
1241 .name = "unlock",
1242 .handler = stm32x_handle_unlock_command,
1243 .mode = COMMAND_EXEC,
1244 .usage = "bank_id",
1245 .help = "Unlock entire protected flash device.",
1246 },
1247 {
1248 .name = "mass_erase",
1249 .handler = stm32x_handle_mass_erase_command,
1250 .mode = COMMAND_EXEC,
1251 .usage = "bank_id",
1252 .help = "Erase entire flash device.",
1253 },
1254 {
1255 .name = "options_read",
1256 .handler = stm32x_handle_options_read_command,
1257 .mode = COMMAND_EXEC,
1258 .usage = "bank_id",
1259 .help = "Read and display device option byte.",
1260 },
1261 {
1262 .name = "options_write",
1263 .handler = stm32x_handle_options_write_command,
1264 .mode = COMMAND_EXEC,
1265 .usage = "bank_id ('SWWDG'|'HWWDG') "
1266 "('RSTSTNDBY'|'NORSTSTNDBY') "
1267 "('RSTSTOP'|'NORSTSTOP')",
1268 .help = "Replace bits in device option byte.",
1269 },
1270 COMMAND_REGISTRATION_DONE
1271 };
1272 static const struct command_registration stm32x_command_handlers[] = {
1273 {
1274 .name = "stm32x",
1275 .mode = COMMAND_ANY,
1276 .help = "stm32x flash command group",
1277 .chain = stm32x_exec_command_handlers,
1278 },
1279 COMMAND_REGISTRATION_DONE
1280 };
1281
1282 struct flash_driver stm32x_flash = {
1283 .name = "stm32x",
1284 .commands = stm32x_command_handlers,
1285 .flash_bank_command = stm32x_flash_bank_command,
1286 .erase = stm32x_erase,
1287 .protect = stm32x_protect,
1288 .write = stm32x_write,
1289 .probe = stm32x_probe,
1290 .auto_probe = stm32x_auto_probe,
1291 .erase_check = default_flash_mem_blank_check,
1292 .protect_check = stm32x_protect_check,
1293 .info = stm32x_info,
1294 };
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