1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
34 static int stm32x_mass_erase(struct flash_bank
*bank
);
36 /* flash bank stm32x <base> <size> 0 0 <target#>
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
40 struct stm32x_flash_bank
*stm32x_info
;
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID
;
48 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
49 bank
->driver_priv
= stm32x_info
;
51 stm32x_info
->write_algorithm
= NULL
;
52 stm32x_info
->probed
= 0;
57 static int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
59 struct target
*target
= bank
->target
;
60 return target_read_u32(target
, STM32_FLASH_SR
, status
);
63 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
65 struct target
*target
= bank
->target
;
67 int retval
= ERROR_OK
;
69 /* wait for busy to clear */
72 retval
= stm32x_get_flash_status(bank
, &status
);
73 if (retval
!= ERROR_OK
)
75 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
76 if ((status
& FLASH_BSY
) == 0)
80 LOG_ERROR("timed out waiting for flash");
86 if (status
& FLASH_WRPRTERR
)
88 LOG_ERROR("stm32x device protected");
92 if (status
& FLASH_PGERR
)
94 LOG_ERROR("stm32x device programming failed");
98 /* Clear but report errors */
99 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
))
101 /* If this operation fails, we ignore it and report the original
104 target_write_u32(target
, STM32_FLASH_SR
, FLASH_WRPRTERR
| FLASH_PGERR
);
109 static int stm32x_read_options(struct flash_bank
*bank
)
112 struct stm32x_flash_bank
*stm32x_info
= NULL
;
113 struct target
*target
= bank
->target
;
115 stm32x_info
= bank
->driver_priv
;
117 /* read current option bytes */
118 int retval
= target_read_u32(target
, STM32_FLASH_OBR
, &optiondata
);
119 if (retval
!= ERROR_OK
)
122 stm32x_info
->option_bytes
.user_options
= (uint16_t)0xFFF8 | ((optiondata
>> 2) & 0x07);
123 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
125 if (optiondata
& (1 << OPT_READOUT
))
126 LOG_INFO("Device Security Bit Set");
128 /* each bit refers to a 4bank protection */
129 retval
= target_read_u32(target
, STM32_FLASH_WRPR
, &optiondata
);
130 if (retval
!= ERROR_OK
)
133 stm32x_info
->option_bytes
.protection
[0] = (uint16_t)optiondata
;
134 stm32x_info
->option_bytes
.protection
[1] = (uint16_t)(optiondata
>> 8);
135 stm32x_info
->option_bytes
.protection
[2] = (uint16_t)(optiondata
>> 16);
136 stm32x_info
->option_bytes
.protection
[3] = (uint16_t)(optiondata
>> 24);
141 static int stm32x_erase_options(struct flash_bank
*bank
)
143 struct stm32x_flash_bank
*stm32x_info
= NULL
;
144 struct target
*target
= bank
->target
;
146 stm32x_info
= bank
->driver_priv
;
148 /* read current options */
149 stm32x_read_options(bank
);
151 /* unlock flash registers */
152 int retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
153 if (retval
!= ERROR_OK
)
156 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
157 if (retval
!= ERROR_OK
)
160 /* unlock option flash registers */
161 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
162 if (retval
!= ERROR_OK
)
164 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
165 if (retval
!= ERROR_OK
)
168 /* erase option bytes */
169 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
| FLASH_OPTWRE
);
170 if (retval
!= ERROR_OK
)
172 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
173 if (retval
!= ERROR_OK
)
176 retval
= stm32x_wait_status_busy(bank
, 10);
177 if (retval
!= ERROR_OK
)
180 /* clear readout protection and complementary option bytes
181 * this will also force a device unlock if set */
182 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
187 static int stm32x_write_options(struct flash_bank
*bank
)
189 struct stm32x_flash_bank
*stm32x_info
= NULL
;
190 struct target
*target
= bank
->target
;
192 stm32x_info
= bank
->driver_priv
;
194 /* unlock flash registers */
195 int retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
196 if (retval
!= ERROR_OK
)
198 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
199 if (retval
!= ERROR_OK
)
202 /* unlock option flash registers */
203 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY1
);
204 if (retval
!= ERROR_OK
)
206 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, KEY2
);
207 if (retval
!= ERROR_OK
)
210 /* program option bytes */
211 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_OPTPG
| FLASH_OPTWRE
);
212 if (retval
!= ERROR_OK
)
215 /* write user option byte */
216 retval
= target_write_u16(target
, STM32_OB_USER
, stm32x_info
->option_bytes
.user_options
);
217 if (retval
!= ERROR_OK
)
220 retval
= stm32x_wait_status_busy(bank
, 10);
221 if (retval
!= ERROR_OK
)
224 /* write protection byte 1 */
225 retval
= target_write_u16(target
, STM32_OB_WRP0
, stm32x_info
->option_bytes
.protection
[0]);
226 if (retval
!= ERROR_OK
)
229 retval
= stm32x_wait_status_busy(bank
, 10);
230 if (retval
!= ERROR_OK
)
233 /* write protection byte 2 */
234 retval
= target_write_u16(target
, STM32_OB_WRP1
, stm32x_info
->option_bytes
.protection
[1]);
235 if (retval
!= ERROR_OK
)
238 retval
= stm32x_wait_status_busy(bank
, 10);
239 if (retval
!= ERROR_OK
)
242 /* write protection byte 3 */
243 retval
= target_write_u16(target
, STM32_OB_WRP2
, stm32x_info
->option_bytes
.protection
[2]);
244 if (retval
!= ERROR_OK
)
247 retval
= stm32x_wait_status_busy(bank
, 10);
248 if (retval
!= ERROR_OK
)
251 /* write protection byte 4 */
252 retval
= target_write_u16(target
, STM32_OB_WRP3
, stm32x_info
->option_bytes
.protection
[3]);
253 if (retval
!= ERROR_OK
)
256 retval
= stm32x_wait_status_busy(bank
, 10);
257 if (retval
!= ERROR_OK
)
260 /* write readout protection bit */
261 retval
= target_write_u16(target
, STM32_OB_RDP
, stm32x_info
->option_bytes
.RDP
);
262 if (retval
!= ERROR_OK
)
265 retval
= stm32x_wait_status_busy(bank
, 10);
266 if (retval
!= ERROR_OK
)
269 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
270 if (retval
!= ERROR_OK
)
276 static int stm32x_protect_check(struct flash_bank
*bank
)
278 struct target
*target
= bank
->target
;
279 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
286 if (target
->state
!= TARGET_HALTED
)
288 LOG_ERROR("Target not halted");
289 return ERROR_TARGET_NOT_HALTED
;
292 /* medium density - each bit refers to a 4bank protection
293 * high density - each bit refers to a 2bank protection */
294 int retval
= target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
295 if (retval
!= ERROR_OK
)
298 /* medium density - each protection bit is for 4 * 1K pages
299 * high density - each protection bit is for 2 * 2K pages */
300 num_bits
= (bank
->num_sectors
/ stm32x_info
->ppage_size
);
302 if (stm32x_info
->ppage_size
== 2)
304 /* high density flash/connectivity line protection */
308 if (protection
& (1 << 31))
311 /* bit 31 controls sector 62 - 255 protection for high density
312 * bit 31 controls sector 62 - 127 protection for connectivity line */
313 for (s
= 62; s
< bank
->num_sectors
; s
++)
315 bank
->sectors
[s
].is_protected
= set
;
318 if (bank
->num_sectors
> 61)
321 for (i
= 0; i
< num_bits
; i
++)
325 if (protection
& (1 << i
))
328 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
329 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
334 /* low/medium density flash protection */
335 for (i
= 0; i
< num_bits
; i
++)
339 if (protection
& (1 << i
))
342 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
343 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
350 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
352 struct target
*target
= bank
->target
;
355 if (bank
->target
->state
!= TARGET_HALTED
)
357 LOG_ERROR("Target not halted");
358 return ERROR_TARGET_NOT_HALTED
;
361 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
363 return stm32x_mass_erase(bank
);
366 /* unlock flash registers */
367 int retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
368 if (retval
!= ERROR_OK
)
370 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
371 if (retval
!= ERROR_OK
)
374 for (i
= first
; i
<= last
; i
++)
376 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
);
377 if (retval
!= ERROR_OK
)
379 retval
= target_write_u32(target
, STM32_FLASH_AR
, bank
->base
+ bank
->sectors
[i
].offset
);
380 if (retval
!= ERROR_OK
)
382 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_PER
| FLASH_STRT
);
383 if (retval
!= ERROR_OK
)
386 retval
= stm32x_wait_status_busy(bank
, 100);
387 if (retval
!= ERROR_OK
)
390 bank
->sectors
[i
].is_erased
= 1;
393 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
394 if (retval
!= ERROR_OK
)
400 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
402 struct stm32x_flash_bank
*stm32x_info
= NULL
;
403 struct target
*target
= bank
->target
;
404 uint16_t prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
409 stm32x_info
= bank
->driver_priv
;
411 if (target
->state
!= TARGET_HALTED
)
413 LOG_ERROR("Target not halted");
414 return ERROR_TARGET_NOT_HALTED
;
417 if ((first
&& (first
% stm32x_info
->ppage_size
)) || ((last
+ 1) &&
418 (last
+ 1) % stm32x_info
->ppage_size
))
420 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary",
421 stm32x_info
->ppage_size
);
422 return ERROR_FLASH_SECTOR_INVALID
;
425 /* medium density - each bit refers to a 4bank protection
426 * high density - each bit refers to a 2bank protection */
427 int retval
= target_read_u32(target
, STM32_FLASH_WRPR
, &protection
);
428 if (retval
!= ERROR_OK
)
431 prot_reg
[0] = (uint16_t)protection
;
432 prot_reg
[1] = (uint16_t)(protection
>> 8);
433 prot_reg
[2] = (uint16_t)(protection
>> 16);
434 prot_reg
[3] = (uint16_t)(protection
>> 24);
436 if (stm32x_info
->ppage_size
== 2)
438 /* high density flash */
440 /* bit 7 controls sector 62 - 255 protection */
444 prot_reg
[3] &= ~(1 << 7);
446 prot_reg
[3] |= (1 << 7);
454 for (i
= first
; i
<= last
; i
++)
456 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
457 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
460 prot_reg
[reg
] &= ~(1 << bit
);
462 prot_reg
[reg
] |= (1 << bit
);
467 /* medium density flash */
468 for (i
= first
; i
<= last
; i
++)
470 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
471 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
474 prot_reg
[reg
] &= ~(1 << bit
);
476 prot_reg
[reg
] |= (1 << bit
);
480 if ((status
= stm32x_erase_options(bank
)) != ERROR_OK
)
483 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
484 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
485 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
486 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
488 return stm32x_write_options(bank
);
491 static int stm32x_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
492 uint32_t offset
, uint32_t count
)
494 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
495 struct target
*target
= bank
->target
;
496 uint32_t buffer_size
= 16384;
497 struct working_area
*source
;
498 uint32_t address
= bank
->base
+ offset
;
499 struct reg_param reg_params
[4];
500 struct armv7m_algorithm armv7m_info
;
501 int retval
= ERROR_OK
;
503 /* see contib/loaders/flash/stm32x.s for src */
505 static const uint8_t stm32x_flash_write_code
[] = {
507 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
508 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
509 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
510 0x23, 0x60, /* str r3, [r4, #0] */
511 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
512 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
514 0x2B, 0x68, /* ldr r3, [r5, #0] */
515 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
516 0xFB, 0xD0, /* beq busy */
517 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
518 0x01, 0xD1, /* bne exit */
519 0x01, 0x3A, /* subs r2, r2, #1 */
520 0xED, 0xD1, /* bne write */
522 0x00, 0xBE, /* bkpt #0 */
523 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
524 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
527 /* flash write code */
528 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
529 &stm32x_info
->write_algorithm
) != ERROR_OK
)
531 LOG_WARNING("no working area available, can't do block memory writes");
532 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
535 if ((retval
= target_write_buffer(target
, stm32x_info
->write_algorithm
->address
,
536 sizeof(stm32x_flash_write_code
),
537 (uint8_t*)stm32x_flash_write_code
)) != ERROR_OK
)
541 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
544 if (buffer_size
<= 256)
546 /* if we already allocated the writing code, but failed to get a
547 * buffer, free the algorithm */
548 if (stm32x_info
->write_algorithm
)
549 target_free_working_area(target
, stm32x_info
->write_algorithm
);
551 LOG_WARNING("no large enough working area available, can't do block memory writes");
552 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
556 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
557 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
559 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
560 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
561 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
562 init_reg_param(®_params
[3], "r3", 32, PARAM_IN
);
566 uint32_t thisrun_count
= (count
> (buffer_size
/ 2)) ?
567 (buffer_size
/ 2) : count
;
569 if ((retval
= target_write_buffer(target
, source
->address
,
570 thisrun_count
* 2, buffer
)) != ERROR_OK
)
573 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
574 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
575 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
);
577 if ((retval
= target_run_algorithm(target
, 0, NULL
, 4, reg_params
,
578 stm32x_info
->write_algorithm
->address
,
580 10000, &armv7m_info
)) != ERROR_OK
)
582 LOG_ERROR("error executing stm32x flash write algorithm");
586 if (buf_get_u32(reg_params
[3].value
, 0, 32) & FLASH_PGERR
)
588 LOG_ERROR("flash memory not erased before writing");
589 /* Clear but report errors */
590 target_write_u32(target
, STM32_FLASH_SR
, FLASH_PGERR
);
595 if (buf_get_u32(reg_params
[3].value
, 0, 32) & FLASH_WRPRTERR
)
597 LOG_ERROR("flash memory write protected");
598 /* Clear but report errors */
599 target_write_u32(target
, STM32_FLASH_SR
, FLASH_WRPRTERR
);
604 buffer
+= thisrun_count
* 2;
605 address
+= thisrun_count
* 2;
606 count
-= thisrun_count
;
609 target_free_working_area(target
, source
);
610 target_free_working_area(target
, stm32x_info
->write_algorithm
);
612 destroy_reg_param(®_params
[0]);
613 destroy_reg_param(®_params
[1]);
614 destroy_reg_param(®_params
[2]);
615 destroy_reg_param(®_params
[3]);
620 static int stm32x_write(struct flash_bank
*bank
, uint8_t *buffer
,
621 uint32_t offset
, uint32_t count
)
623 struct target
*target
= bank
->target
;
624 uint32_t words_remaining
= (count
/ 2);
625 uint32_t bytes_remaining
= (count
& 0x00000001);
626 uint32_t address
= bank
->base
+ offset
;
627 uint32_t bytes_written
= 0;
630 if (bank
->target
->state
!= TARGET_HALTED
)
632 LOG_ERROR("Target not halted");
633 return ERROR_TARGET_NOT_HALTED
;
638 LOG_WARNING("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
639 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
642 /* unlock flash registers */
643 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
644 if (retval
!= ERROR_OK
)
646 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
647 if (retval
!= ERROR_OK
)
650 /* multiple half words (2-byte) to be programmed? */
651 if (words_remaining
> 0)
653 /* try using a block write */
654 if ((retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
)) != ERROR_OK
)
656 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
658 /* if block write failed (no sufficient working area),
659 * we use normal (slow) single dword accesses */
660 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
665 buffer
+= words_remaining
* 2;
666 address
+= words_remaining
* 2;
671 while (words_remaining
> 0)
674 memcpy(&value
, buffer
+ bytes_written
, sizeof(uint16_t));
676 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
677 if (retval
!= ERROR_OK
)
679 retval
= target_write_u16(target
, address
, value
);
680 if (retval
!= ERROR_OK
)
683 retval
= stm32x_wait_status_busy(bank
, 5);
684 if (retval
!= ERROR_OK
)
694 uint16_t value
= 0xffff;
695 memcpy(&value
, buffer
+ bytes_written
, bytes_remaining
);
697 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_PG
);
698 if (retval
!= ERROR_OK
)
700 retval
= target_write_u16(target
, address
, value
);
701 if (retval
!= ERROR_OK
)
704 retval
= stm32x_wait_status_busy(bank
, 5);
705 if (retval
!= ERROR_OK
)
709 return target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
712 static int stm32x_probe(struct flash_bank
*bank
)
714 struct target
*target
= bank
->target
;
715 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
721 stm32x_info
->probed
= 0;
723 /* read stm32 device id register */
724 int retval
= target_read_u32(target
, 0xE0042000, &device_id
);
725 if (retval
!= ERROR_OK
)
727 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
729 /* get flash size from target. */
730 retval
= target_read_u16(target
, 0x1FFFF7E0, &num_pages
);
731 if (retval
!= ERROR_OK
)
733 LOG_WARNING("failed reading flash size, default to max target family");
734 /* failed reading flash size, default to max target family */
738 if ((device_id
& 0x7ff) == 0x410)
740 /* medium density - we have 1k pages
741 * 4 pages for a protection area */
743 stm32x_info
->ppage_size
= 4;
745 /* check for early silicon */
746 if (num_pages
== 0xffff)
748 /* number of sectors incorrect on revA */
749 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
753 else if ((device_id
& 0x7ff) == 0x412)
755 /* low density - we have 1k pages
756 * 4 pages for a protection area */
758 stm32x_info
->ppage_size
= 4;
760 /* check for early silicon */
761 if (num_pages
== 0xffff)
763 /* number of sectors incorrect on revA */
764 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
768 else if ((device_id
& 0x7ff) == 0x414)
770 /* high density - we have 2k pages
771 * 2 pages for a protection area */
773 stm32x_info
->ppage_size
= 2;
775 /* check for early silicon */
776 if (num_pages
== 0xffff)
778 /* number of sectors incorrect on revZ */
779 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
783 else if ((device_id
& 0x7ff) == 0x418)
785 /* connectivity line density - we have 2k pages
786 * 2 pages for a protection area */
788 stm32x_info
->ppage_size
= 2;
790 /* check for early silicon */
791 if (num_pages
== 0xffff)
793 /* number of sectors incorrect on revZ */
794 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
798 else if ((device_id
& 0x7ff) == 0x420)
800 /* value line density - we have 1k pages
801 * 4 pages for a protection area */
803 stm32x_info
->ppage_size
= 4;
805 /* check for early silicon */
806 if (num_pages
== 0xffff)
808 /* number of sectors may be incorrrect on early silicon */
809 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
815 LOG_WARNING("Cannot identify target as a STM32 family.");
819 LOG_INFO("flash size = %dkbytes", num_pages
);
821 /* calculate numbers of pages */
822 num_pages
/= (page_size
/ 1024);
827 bank
->sectors
= NULL
;
830 bank
->base
= 0x08000000;
831 bank
->size
= (num_pages
* page_size
);
832 bank
->num_sectors
= num_pages
;
833 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
835 for (i
= 0; i
< num_pages
; i
++)
837 bank
->sectors
[i
].offset
= i
* page_size
;
838 bank
->sectors
[i
].size
= page_size
;
839 bank
->sectors
[i
].is_erased
= -1;
840 bank
->sectors
[i
].is_protected
= 1;
843 stm32x_info
->probed
= 1;
848 static int stm32x_auto_probe(struct flash_bank
*bank
)
850 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
851 if (stm32x_info
->probed
)
853 return stm32x_probe(bank
);
857 COMMAND_HANDLER(stm32x_handle_part_id_command
)
863 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
865 struct target
*target
= bank
->target
;
869 /* read stm32 device id register */
870 int retval
= target_read_u32(target
, 0xE0042000, &device_id
);
871 if (retval
!= ERROR_OK
)
874 if ((device_id
& 0x7ff) == 0x410)
876 printed
= snprintf(buf
, buf_size
, "stm32x (Medium Density) - Rev: ");
880 switch (device_id
>> 16)
883 snprintf(buf
, buf_size
, "A");
887 snprintf(buf
, buf_size
, "B");
891 snprintf(buf
, buf_size
, "Z");
895 snprintf(buf
, buf_size
, "Y");
899 snprintf(buf
, buf_size
, "unknown");
903 else if ((device_id
& 0x7ff) == 0x412)
905 printed
= snprintf(buf
, buf_size
, "stm32x (Low Density) - Rev: ");
909 switch (device_id
>> 16)
912 snprintf(buf
, buf_size
, "A");
916 snprintf(buf
, buf_size
, "unknown");
920 else if ((device_id
& 0x7ff) == 0x414)
922 printed
= snprintf(buf
, buf_size
, "stm32x (High Density) - Rev: ");
926 switch (device_id
>> 16)
929 snprintf(buf
, buf_size
, "A");
933 snprintf(buf
, buf_size
, "Z");
937 snprintf(buf
, buf_size
, "unknown");
941 else if ((device_id
& 0x7ff) == 0x418)
943 printed
= snprintf(buf
, buf_size
, "stm32x (Connectivity) - Rev: ");
947 switch (device_id
>> 16)
950 snprintf(buf
, buf_size
, "A");
954 snprintf(buf
, buf_size
, "Z");
958 snprintf(buf
, buf_size
, "unknown");
962 else if ((device_id
& 0x7ff) == 0x420)
964 printed
= snprintf(buf
, buf_size
, "stm32x (Value) - Rev: ");
968 switch (device_id
>> 16)
971 snprintf(buf
, buf_size
, "A");
975 snprintf(buf
, buf_size
, "Z");
979 snprintf(buf
, buf_size
, "unknown");
985 snprintf(buf
, buf_size
, "Cannot identify target as a stm32x\n");
992 COMMAND_HANDLER(stm32x_handle_lock_command
)
994 struct target
*target
= NULL
;
995 struct stm32x_flash_bank
*stm32x_info
= NULL
;
999 command_print(CMD_CTX
, "stm32x lock <bank>");
1003 struct flash_bank
*bank
;
1004 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1005 if (ERROR_OK
!= retval
)
1008 stm32x_info
= bank
->driver_priv
;
1010 target
= bank
->target
;
1012 if (target
->state
!= TARGET_HALTED
)
1014 LOG_ERROR("Target not halted");
1015 return ERROR_TARGET_NOT_HALTED
;
1018 if (stm32x_erase_options(bank
) != ERROR_OK
)
1020 command_print(CMD_CTX
, "stm32x failed to erase options");
1024 /* set readout protection */
1025 stm32x_info
->option_bytes
.RDP
= 0;
1027 if (stm32x_write_options(bank
) != ERROR_OK
)
1029 command_print(CMD_CTX
, "stm32x failed to lock device");
1033 command_print(CMD_CTX
, "stm32x locked");
1038 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1040 struct target
*target
= NULL
;
1041 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1045 command_print(CMD_CTX
, "stm32x unlock <bank>");
1049 struct flash_bank
*bank
;
1050 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1051 if (ERROR_OK
!= retval
)
1054 stm32x_info
= bank
->driver_priv
;
1056 target
= bank
->target
;
1058 if (target
->state
!= TARGET_HALTED
)
1060 LOG_ERROR("Target not halted");
1061 return ERROR_TARGET_NOT_HALTED
;
1064 if (stm32x_erase_options(bank
) != ERROR_OK
)
1066 command_print(CMD_CTX
, "stm32x failed to unlock device");
1070 if (stm32x_write_options(bank
) != ERROR_OK
)
1072 command_print(CMD_CTX
, "stm32x failed to lock device");
1076 command_print(CMD_CTX
, "stm32x unlocked.\n"
1077 "INFO: a reset or power cycle is required "
1078 "for the new settings to take effect.");
1083 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1085 uint32_t optionbyte
;
1086 struct target
*target
= NULL
;
1087 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1091 command_print(CMD_CTX
, "stm32x options_read <bank>");
1095 struct flash_bank
*bank
;
1096 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1097 if (ERROR_OK
!= retval
)
1100 stm32x_info
= bank
->driver_priv
;
1102 target
= bank
->target
;
1104 if (target
->state
!= TARGET_HALTED
)
1106 LOG_ERROR("Target not halted");
1107 return ERROR_TARGET_NOT_HALTED
;
1110 retval
= target_read_u32(target
, STM32_FLASH_OBR
, &optionbyte
);
1111 if (retval
!= ERROR_OK
)
1113 command_print(CMD_CTX
, "Option Byte: 0x%" PRIx32
"", optionbyte
);
1115 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_ERROR
, 1))
1116 command_print(CMD_CTX
, "Option Byte Complement Error");
1118 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_READOUT
, 1))
1119 command_print(CMD_CTX
, "Readout Protection On");
1121 command_print(CMD_CTX
, "Readout Protection Off");
1123 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_RDWDGSW
, 1))
1124 command_print(CMD_CTX
, "Software Watchdog");
1126 command_print(CMD_CTX
, "Hardware Watchdog");
1128 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_RDRSTSTOP
, 1))
1129 command_print(CMD_CTX
, "Stop: No reset generated");
1131 command_print(CMD_CTX
, "Stop: Reset generated");
1133 if (buf_get_u32((uint8_t*)&optionbyte
, OPT_RDRSTSTDBY
, 1))
1134 command_print(CMD_CTX
, "Standby: No reset generated");
1136 command_print(CMD_CTX
, "Standby: Reset generated");
1141 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1143 struct target
*target
= NULL
;
1144 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1145 uint16_t optionbyte
= 0xF8;
1149 command_print(CMD_CTX
, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1153 struct flash_bank
*bank
;
1154 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1155 if (ERROR_OK
!= retval
)
1158 stm32x_info
= bank
->driver_priv
;
1160 target
= bank
->target
;
1162 if (target
->state
!= TARGET_HALTED
)
1164 LOG_ERROR("Target not halted");
1165 return ERROR_TARGET_NOT_HALTED
;
1168 /* REVISIT: ignores some options which we will display...
1169 * and doesn't insist on the specified syntax.
1173 if (strcmp(CMD_ARGV
[1], "SWWDG") == 0)
1175 optionbyte
|= (1 << 0);
1177 else /* REVISIT must be "HWWDG" then ... */
1179 optionbyte
&= ~(1 << 0);
1182 /* OPT_RDRSTSTDBY */
1183 if (strcmp(CMD_ARGV
[2], "NORSTSTNDBY") == 0)
1185 optionbyte
|= (1 << 1);
1187 else /* REVISIT must be "RSTSTNDBY" then ... */
1189 optionbyte
&= ~(1 << 1);
1193 if (strcmp(CMD_ARGV
[3], "NORSTSTOP") == 0)
1195 optionbyte
|= (1 << 2);
1197 else /* REVISIT must be "RSTSTOP" then ... */
1199 optionbyte
&= ~(1 << 2);
1202 if (stm32x_erase_options(bank
) != ERROR_OK
)
1204 command_print(CMD_CTX
, "stm32x failed to erase options");
1208 stm32x_info
->option_bytes
.user_options
= optionbyte
;
1210 if (stm32x_write_options(bank
) != ERROR_OK
)
1212 command_print(CMD_CTX
, "stm32x failed to write options");
1216 command_print(CMD_CTX
, "stm32x write options complete.\n"
1217 "INFO: a reset or power cycle is required "
1218 "for the new settings to take effect.");
1223 static int stm32x_mass_erase(struct flash_bank
*bank
)
1225 struct target
*target
= bank
->target
;
1227 if (target
->state
!= TARGET_HALTED
)
1229 LOG_ERROR("Target not halted");
1230 return ERROR_TARGET_NOT_HALTED
;
1233 /* unlock option flash registers */
1234 int retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
1235 if (retval
!= ERROR_OK
)
1237 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
1238 if (retval
!= ERROR_OK
)
1241 /* mass erase flash memory */
1242 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
);
1243 if (retval
!= ERROR_OK
)
1245 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_MER
| FLASH_STRT
);
1246 if (retval
!= ERROR_OK
)
1249 retval
= stm32x_wait_status_busy(bank
, 100);
1250 if (retval
!= ERROR_OK
)
1253 retval
= target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
1254 if (retval
!= ERROR_OK
)
1260 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1266 command_print(CMD_CTX
, "stm32x mass_erase <bank>");
1270 struct flash_bank
*bank
;
1271 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1272 if (ERROR_OK
!= retval
)
1275 retval
= stm32x_mass_erase(bank
);
1276 if (retval
== ERROR_OK
)
1278 /* set all sectors as erased */
1279 for (i
= 0; i
< bank
->num_sectors
; i
++)
1281 bank
->sectors
[i
].is_erased
= 1;
1284 command_print(CMD_CTX
, "stm32x mass erase complete");
1288 command_print(CMD_CTX
, "stm32x mass erase failed");
1294 static const struct command_registration stm32x_exec_command_handlers
[] = {
1297 .handler
= stm32x_handle_lock_command
,
1298 .mode
= COMMAND_EXEC
,
1300 .help
= "Lock entire flash device.",
1304 .handler
= stm32x_handle_unlock_command
,
1305 .mode
= COMMAND_EXEC
,
1307 .help
= "Unlock entire protected flash device.",
1310 .name
= "mass_erase",
1311 .handler
= stm32x_handle_mass_erase_command
,
1312 .mode
= COMMAND_EXEC
,
1314 .help
= "Erase entire flash device.",
1317 .name
= "options_read",
1318 .handler
= stm32x_handle_options_read_command
,
1319 .mode
= COMMAND_EXEC
,
1321 .help
= "Read and display device option byte.",
1324 .name
= "options_write",
1325 .handler
= stm32x_handle_options_write_command
,
1326 .mode
= COMMAND_EXEC
,
1327 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1328 "('RSTSTNDBY'|'NORSTSTNDBY') "
1329 "('RSTSTOP'|'NORSTSTOP')",
1330 .help
= "Replace bits in device option byte.",
1332 COMMAND_REGISTRATION_DONE
1335 static const struct command_registration stm32x_command_handlers
[] = {
1338 .mode
= COMMAND_ANY
,
1339 .help
= "stm32x flash command group",
1340 .chain
= stm32x_exec_command_handlers
,
1342 COMMAND_REGISTRATION_DONE
1345 struct flash_driver stm32x_flash
= {
1347 .commands
= stm32x_command_handlers
,
1348 .flash_bank_command
= stm32x_flash_bank_command
,
1349 .erase
= stm32x_erase
,
1350 .protect
= stm32x_protect
,
1351 .write
= stm32x_write
,
1352 .read
= default_flash_read
,
1353 .probe
= stm32x_probe
,
1354 .auto_probe
= stm32x_auto_probe
,
1355 .erase_check
= default_flash_mem_blank_check
,
1356 .protect_check
= stm32x_protect_check
,
1357 .info
= get_stm32x_info
,
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