1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33 #include <target/cortex_m.h>
35 /* stm32lx flash register locations */
37 #define FLASH_ACR 0x00
38 #define FLASH_PECR 0x04
39 #define FLASH_PDKEYR 0x08
40 #define FLASH_PEKEYR 0x0C
41 #define FLASH_PRGKEYR 0x10
42 #define FLASH_OPTKEYR 0x14
44 #define FLASH_OBR 0x1C
45 #define FLASH_WRPR 0x20
48 #define FLASH_ACR__LATENCY (1<<0)
49 #define FLASH_ACR__PRFTEN (1<<1)
50 #define FLASH_ACR__ACC64 (1<<2)
51 #define FLASH_ACR__SLEEP_PD (1<<3)
52 #define FLASH_ACR__RUN_PD (1<<4)
55 #define FLASH_PECR__PELOCK (1<<0)
56 #define FLASH_PECR__PRGLOCK (1<<1)
57 #define FLASH_PECR__OPTLOCK (1<<2)
58 #define FLASH_PECR__PROG (1<<3)
59 #define FLASH_PECR__DATA (1<<4)
60 #define FLASH_PECR__FTDW (1<<8)
61 #define FLASH_PECR__ERASE (1<<9)
62 #define FLASH_PECR__FPRG (1<<10)
63 #define FLASH_PECR__EOPIE (1<<16)
64 #define FLASH_PECR__ERRIE (1<<17)
65 #define FLASH_PECR__OBL_LAUNCH (1<<18)
68 #define FLASH_SR__BSY (1<<0)
69 #define FLASH_SR__EOP (1<<1)
70 #define FLASH_SR__ENDHV (1<<2)
71 #define FLASH_SR__READY (1<<3)
72 #define FLASH_SR__WRPERR (1<<8)
73 #define FLASH_SR__PGAERR (1<<9)
74 #define FLASH_SR__SIZERR (1<<10)
75 #define FLASH_SR__OPTVERR (1<<11)
78 #define PEKEY1 0x89ABCDEF
79 #define PEKEY2 0x02030405
80 #define PRGKEY1 0x8C9DAEBF
81 #define PRGKEY2 0x13141516
82 #define OPTKEY1 0xFBEAD9C8
83 #define OPTKEY2 0x24252627
86 #define DBGMCU_IDCODE 0xE0042000
87 #define DBGMCU_IDCODE_L0 0x40015800
90 #define FLASH_SECTOR_SIZE 4096
91 #define FLASH_BANK0_ADDRESS 0x08000000
94 #define OPTION_BYTES_ADDRESS 0x1FF80000
96 #define OPTION_BYTE_0_PR1 0xFFFF0000
97 #define OPTION_BYTE_0_PR0 0xFF5500AA
99 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
);
100 static int stm32lx_lock_program_memory(struct flash_bank
*bank
);
101 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
);
102 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
);
103 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
);
104 static int stm32lx_lock(struct flash_bank
*bank
);
105 static int stm32lx_unlock(struct flash_bank
*bank
);
106 static int stm32lx_mass_erase(struct flash_bank
*bank
);
107 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank
*bank
, int timeout
);
108 static int stm32lx_update_part_info(struct flash_bank
*bank
, uint16_t flash_size_in_kb
);
115 struct stm32lx_part_info
{
117 const char *device_str
;
118 const struct stm32lx_rev
*revs
;
120 unsigned int page_size
;
121 unsigned int pages_per_sector
;
122 uint16_t max_flash_size_kb
;
123 uint16_t first_bank_size_kb
; /* used when has_dual_banks is true */
126 uint32_t flash_base
; /* Flash controller registers location */
127 uint32_t fsize_base
; /* Location of FSIZE register */
130 struct stm32lx_flash_bank
{
133 uint32_t user_bank_size
;
136 struct stm32lx_part_info part_info
;
139 static const struct stm32lx_rev stm32_416_revs
[] = {
140 { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1038, "W" }, { 0x1078, "V" },
142 static const struct stm32lx_rev stm32_417_revs
[] = {
143 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }
145 static const struct stm32lx_rev stm32_425_revs
[] = {
146 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" },
148 static const struct stm32lx_rev stm32_427_revs
[] = {
149 { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" },
151 static const struct stm32lx_rev stm32_429_revs
[] = {
152 { 0x1000, "A" }, { 0x1018, "Z" },
154 static const struct stm32lx_rev stm32_436_revs
[] = {
155 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
157 static const struct stm32lx_rev stm32_437_revs
[] = {
160 static const struct stm32lx_rev stm32_447_revs
[] = {
161 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Z" },
163 static const struct stm32lx_rev stm32_457_revs
[] = {
164 { 0x1000, "A" }, { 0x1008, "Z" },
167 static const struct stm32lx_part_info stm32lx_parts
[] = {
170 .revs
= stm32_416_revs
,
171 .num_revs
= ARRAY_SIZE(stm32_416_revs
),
172 .device_str
= "STM32L1xx (Cat.1 - Low/Medium Density)",
174 .pages_per_sector
= 16,
175 .max_flash_size_kb
= 128,
176 .has_dual_banks
= false,
177 .flash_base
= 0x40023C00,
178 .fsize_base
= 0x1FF8004C,
182 .revs
= stm32_417_revs
,
183 .num_revs
= ARRAY_SIZE(stm32_417_revs
),
184 .device_str
= "STM32L0xx (Cat. 3)",
186 .pages_per_sector
= 32,
187 .max_flash_size_kb
= 64,
188 .has_dual_banks
= false,
189 .flash_base
= 0x40022000,
190 .fsize_base
= 0x1FF8007C,
194 .revs
= stm32_425_revs
,
195 .num_revs
= ARRAY_SIZE(stm32_425_revs
),
196 .device_str
= "STM32L0xx (Cat. 2)",
198 .pages_per_sector
= 32,
199 .max_flash_size_kb
= 32,
200 .has_dual_banks
= false,
201 .flash_base
= 0x40022000,
202 .fsize_base
= 0x1FF8007C,
206 .revs
= stm32_427_revs
,
207 .num_revs
= ARRAY_SIZE(stm32_427_revs
),
208 .device_str
= "STM32L1xx (Cat.3 - Medium+ Density)",
210 .pages_per_sector
= 16,
211 .max_flash_size_kb
= 256,
212 .has_dual_banks
= false,
213 .flash_base
= 0x40023C00,
214 .fsize_base
= 0x1FF800CC,
218 .revs
= stm32_429_revs
,
219 .num_revs
= ARRAY_SIZE(stm32_429_revs
),
220 .device_str
= "STM32L1xx (Cat.2)",
222 .pages_per_sector
= 16,
223 .max_flash_size_kb
= 128,
224 .has_dual_banks
= false,
225 .flash_base
= 0x40023C00,
226 .fsize_base
= 0x1FF8004C,
230 .revs
= stm32_436_revs
,
231 .num_revs
= ARRAY_SIZE(stm32_436_revs
),
232 .device_str
= "STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
234 .pages_per_sector
= 16,
235 .max_flash_size_kb
= 384,
236 .first_bank_size_kb
= 192,
237 .has_dual_banks
= true,
238 .flash_base
= 0x40023C00,
239 .fsize_base
= 0x1FF800CC,
243 .revs
= stm32_437_revs
,
244 .num_revs
= ARRAY_SIZE(stm32_437_revs
),
245 .device_str
= "STM32L1xx (Cat.5/Cat.6)",
247 .pages_per_sector
= 16,
248 .max_flash_size_kb
= 512,
249 .first_bank_size_kb
= 0, /* determined in runtime */
250 .has_dual_banks
= true,
251 .flash_base
= 0x40023C00,
252 .fsize_base
= 0x1FF800CC,
256 .revs
= stm32_447_revs
,
257 .num_revs
= ARRAY_SIZE(stm32_447_revs
),
258 .device_str
= "STM32L0xx (Cat.5)",
260 .pages_per_sector
= 32,
261 .max_flash_size_kb
= 192,
262 .first_bank_size_kb
= 0, /* determined in runtime */
263 .has_dual_banks
= false, /* determined in runtime */
264 .flash_base
= 0x40022000,
265 .fsize_base
= 0x1FF8007C,
269 .revs
= stm32_457_revs
,
270 .num_revs
= ARRAY_SIZE(stm32_457_revs
),
271 .device_str
= "STM32L0xx (Cat.1)",
273 .pages_per_sector
= 32,
274 .max_flash_size_kb
= 16,
275 .has_dual_banks
= false,
276 .flash_base
= 0x40022000,
277 .fsize_base
= 0x1FF8007C,
281 /* flash bank stm32lx <base> <size> 0 0 <target#>
283 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command
)
285 struct stm32lx_flash_bank
*stm32lx_info
;
287 return ERROR_COMMAND_SYNTAX_ERROR
;
289 /* Create the bank structure */
290 stm32lx_info
= calloc(1, sizeof(*stm32lx_info
));
292 /* Check allocation */
293 if (stm32lx_info
== NULL
) {
294 LOG_ERROR("failed to allocate bank structure");
298 bank
->driver_priv
= stm32lx_info
;
300 stm32lx_info
->probed
= 0;
301 stm32lx_info
->user_bank_size
= bank
->size
;
303 /* the stm32l erased value is 0x00 */
304 bank
->default_padded_value
= bank
->erased_value
= 0x00;
309 COMMAND_HANDLER(stm32lx_handle_mass_erase_command
)
314 return ERROR_COMMAND_SYNTAX_ERROR
;
316 struct flash_bank
*bank
;
317 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
318 if (ERROR_OK
!= retval
)
321 retval
= stm32lx_mass_erase(bank
);
322 if (retval
== ERROR_OK
) {
323 /* set all sectors as erased */
324 for (i
= 0; i
< bank
->num_sectors
; i
++)
325 bank
->sectors
[i
].is_erased
= 1;
327 command_print(CMD_CTX
, "stm32lx mass erase complete");
329 command_print(CMD_CTX
, "stm32lx mass erase failed");
335 COMMAND_HANDLER(stm32lx_handle_lock_command
)
338 return ERROR_COMMAND_SYNTAX_ERROR
;
340 struct flash_bank
*bank
;
341 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
342 if (ERROR_OK
!= retval
)
345 retval
= stm32lx_lock(bank
);
347 if (retval
== ERROR_OK
)
348 command_print(CMD_CTX
, "STM32Lx locked, takes effect after power cycle.");
350 command_print(CMD_CTX
, "STM32Lx lock failed");
355 COMMAND_HANDLER(stm32lx_handle_unlock_command
)
358 return ERROR_COMMAND_SYNTAX_ERROR
;
360 struct flash_bank
*bank
;
361 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
362 if (ERROR_OK
!= retval
)
365 retval
= stm32lx_unlock(bank
);
367 if (retval
== ERROR_OK
)
368 command_print(CMD_CTX
, "STM32Lx unlocked, takes effect after power cycle.");
370 command_print(CMD_CTX
, "STM32Lx unlock failed");
375 static int stm32lx_protect_check(struct flash_bank
*bank
)
378 struct target
*target
= bank
->target
;
379 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
384 * Read the WRPR word, and check each bit (corresponding to each
387 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_WRPR
,
389 if (retval
!= ERROR_OK
)
392 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
394 bank
->sectors
[i
].is_protected
= 1;
396 bank
->sectors
[i
].is_protected
= 0;
401 static int stm32lx_erase(struct flash_bank
*bank
, int first
, int last
)
406 * It could be possible to do a mass erase if all sectors must be
407 * erased, but it is not implemented yet.
410 if (bank
->target
->state
!= TARGET_HALTED
) {
411 LOG_ERROR("Target not halted");
412 return ERROR_TARGET_NOT_HALTED
;
416 * Loop over the selected sectors and erase them
418 for (int i
= first
; i
<= last
; i
++) {
419 retval
= stm32lx_erase_sector(bank
, i
);
420 if (retval
!= ERROR_OK
)
422 bank
->sectors
[i
].is_erased
= 1;
427 static int stm32lx_protect(struct flash_bank
*bank
, int set
, int first
,
430 LOG_WARNING("protection of the STM32L flash is not implemented");
434 static int stm32lx_write_half_pages(struct flash_bank
*bank
, const uint8_t *buffer
,
435 uint32_t offset
, uint32_t count
)
437 struct target
*target
= bank
->target
;
438 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
440 uint32_t hp_nb
= stm32lx_info
->part_info
.page_size
/ 2;
441 uint32_t buffer_size
= 16384;
442 struct working_area
*write_algorithm
;
443 struct working_area
*source
;
444 uint32_t address
= bank
->base
+ offset
;
446 struct reg_param reg_params
[3];
447 struct armv7m_algorithm armv7m_info
;
449 int retval
= ERROR_OK
;
451 /* see contib/loaders/flash/stm32lx.S for src */
453 static const uint8_t stm32lx_flash_write_code
[] = {
454 0x92, 0x00, 0x8A, 0x18, 0x01, 0xE0, 0x08, 0xC9, 0x08, 0xC0, 0x91, 0x42, 0xFB, 0xD1, 0x00, 0xBE
457 /* Make sure we're performing a half-page aligned write. */
459 LOG_ERROR("The byte count must be %" PRIu32
"B-aligned but count is %" PRIi32
"B)", hp_nb
, count
);
463 /* flash write code */
464 if (target_alloc_working_area(target
, sizeof(stm32lx_flash_write_code
),
465 &write_algorithm
) != ERROR_OK
) {
466 LOG_DEBUG("no working area for block memory writes");
467 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
470 /* Write the flashing code */
471 retval
= target_write_buffer(target
,
472 write_algorithm
->address
,
473 sizeof(stm32lx_flash_write_code
),
474 stm32lx_flash_write_code
);
475 if (retval
!= ERROR_OK
) {
476 target_free_working_area(target
, write_algorithm
);
480 /* Allocate half pages memory */
481 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
482 if (buffer_size
> 1024)
487 if (buffer_size
<= stm32lx_info
->part_info
.page_size
) {
488 /* we already allocated the writing code, but failed to get a
489 * buffer, free the algorithm */
490 target_free_working_area(target
, write_algorithm
);
492 LOG_WARNING("no large enough working area available, can't do block memory writes");
493 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
497 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
498 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
499 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
500 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
501 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
503 /* Enable half-page write */
504 retval
= stm32lx_enable_write_half_page(bank
);
505 if (retval
!= ERROR_OK
) {
506 target_free_working_area(target
, source
);
507 target_free_working_area(target
, write_algorithm
);
509 destroy_reg_param(®_params
[0]);
510 destroy_reg_param(®_params
[1]);
511 destroy_reg_param(®_params
[2]);
515 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
516 if (armv7m
== NULL
) {
518 /* something is very wrong if armv7m is NULL */
519 LOG_ERROR("unable to get armv7m target");
523 /* save any DEMCR flags and configure target to catch any Hard Faults */
524 uint32_t demcr_save
= armv7m
->demcr
;
525 armv7m
->demcr
= VC_HARDERR
;
527 /* Loop while there are bytes to write */
530 this_count
= (count
> buffer_size
) ? buffer_size
: count
;
532 /* Write the next half pages */
533 retval
= target_write_buffer(target
, source
->address
, this_count
, buffer
);
534 if (retval
!= ERROR_OK
)
537 /* 4: Store useful information in the registers */
538 /* the destination address of the copy (R0) */
539 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
540 /* The source address of the copy (R1) */
541 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
542 /* The length of the copy (R2) */
543 buf_set_u32(reg_params
[2].value
, 0, 32, this_count
/ 4);
545 /* 5: Execute the bunch of code */
546 retval
= target_run_algorithm(target
, 0, NULL
, sizeof(reg_params
)
547 / sizeof(*reg_params
), reg_params
,
548 write_algorithm
->address
, 0, 10000, &armv7m_info
);
549 if (retval
!= ERROR_OK
)
552 /* check for Hard Fault */
553 if (armv7m
->exception_number
== 3)
556 /* 6: Wait while busy */
557 retval
= stm32lx_wait_until_bsy_clear(bank
);
558 if (retval
!= ERROR_OK
)
561 buffer
+= this_count
;
562 address
+= this_count
;
566 /* restore previous flags */
567 armv7m
->demcr
= demcr_save
;
569 if (armv7m
->exception_number
== 3) {
571 /* the stm32l15x devices seem to have an issue when blank.
572 * if a ram loader is executed on a blank device it will
573 * Hard Fault, this issue does not happen for a already programmed device.
574 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
575 * The workaround of handling the Hard Fault exception does work, but makes the
576 * loader more complicated, as a compromise we manually write the pages, programming time
577 * is reduced by 50% using this slower method.
580 LOG_WARNING("Couldn't use loader, falling back to page memory writes");
584 this_count
= (count
> hp_nb
) ? hp_nb
: count
;
586 /* Write the next half pages */
587 retval
= target_write_buffer(target
, address
, this_count
, buffer
);
588 if (retval
!= ERROR_OK
)
591 /* Wait while busy */
592 retval
= stm32lx_wait_until_bsy_clear(bank
);
593 if (retval
!= ERROR_OK
)
596 buffer
+= this_count
;
597 address
+= this_count
;
602 if (retval
== ERROR_OK
)
603 retval
= stm32lx_lock_program_memory(bank
);
605 target_free_working_area(target
, source
);
606 target_free_working_area(target
, write_algorithm
);
608 destroy_reg_param(®_params
[0]);
609 destroy_reg_param(®_params
[1]);
610 destroy_reg_param(®_params
[2]);
615 static int stm32lx_write(struct flash_bank
*bank
, const uint8_t *buffer
,
616 uint32_t offset
, uint32_t count
)
618 struct target
*target
= bank
->target
;
619 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
621 uint32_t hp_nb
= stm32lx_info
->part_info
.page_size
/ 2;
622 uint32_t halfpages_number
;
623 uint32_t bytes_remaining
= 0;
624 uint32_t address
= bank
->base
+ offset
;
625 uint32_t bytes_written
= 0;
628 if (bank
->target
->state
!= TARGET_HALTED
) {
629 LOG_ERROR("Target not halted");
630 return ERROR_TARGET_NOT_HALTED
;
634 LOG_ERROR("offset 0x%" PRIx32
" breaks required 4-byte alignment", offset
);
635 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
638 retval
= stm32lx_unlock_program_memory(bank
);
639 if (retval
!= ERROR_OK
)
642 /* first we need to write any unaligned head bytes upto
643 * the next 128 byte page */
646 bytes_remaining
= MIN(count
, hp_nb
- (offset
% hp_nb
));
648 while (bytes_remaining
> 0) {
649 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
651 /* copy remaining bytes into the write buffer */
652 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
653 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
655 retval
= target_write_buffer(target
, address
, 4, value
);
656 if (retval
!= ERROR_OK
)
657 goto reset_pg_and_lock
;
659 bytes_written
+= bytes_to_write
;
660 bytes_remaining
-= bytes_to_write
;
663 retval
= stm32lx_wait_until_bsy_clear(bank
);
664 if (retval
!= ERROR_OK
)
665 goto reset_pg_and_lock
;
668 offset
+= bytes_written
;
669 count
-= bytes_written
;
671 /* this should always pass this check here */
672 assert((offset
% hp_nb
) == 0);
674 /* calculate half pages */
675 halfpages_number
= count
/ hp_nb
;
677 if (halfpages_number
) {
678 retval
= stm32lx_write_half_pages(bank
, buffer
+ bytes_written
, offset
, hp_nb
* halfpages_number
);
679 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
680 /* attempt slow memory writes */
681 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
682 halfpages_number
= 0;
684 if (retval
!= ERROR_OK
)
689 /* write any remaining bytes */
690 uint32_t page_bytes_written
= hp_nb
* halfpages_number
;
691 bytes_written
+= page_bytes_written
;
692 address
+= page_bytes_written
;
693 bytes_remaining
= count
- page_bytes_written
;
695 retval
= stm32lx_unlock_program_memory(bank
);
696 if (retval
!= ERROR_OK
)
699 while (bytes_remaining
> 0) {
700 uint8_t value
[4] = {0xff, 0xff, 0xff, 0xff};
702 /* copy remaining bytes into the write buffer */
703 uint32_t bytes_to_write
= MIN(4, bytes_remaining
);
704 memcpy(value
, buffer
+ bytes_written
, bytes_to_write
);
706 retval
= target_write_buffer(target
, address
, 4, value
);
707 if (retval
!= ERROR_OK
)
708 goto reset_pg_and_lock
;
710 bytes_written
+= bytes_to_write
;
711 bytes_remaining
-= bytes_to_write
;
714 retval
= stm32lx_wait_until_bsy_clear(bank
);
715 if (retval
!= ERROR_OK
)
716 goto reset_pg_and_lock
;
720 retval2
= stm32lx_lock_program_memory(bank
);
721 if (retval
== ERROR_OK
)
727 static int stm32lx_read_id_code(struct target
*target
, uint32_t *id
)
729 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
731 if (armv7m
->arm
.is_armv6m
== true)
732 retval
= target_read_u32(target
, DBGMCU_IDCODE_L0
, id
);
734 /* read stm32 device id register */
735 retval
= target_read_u32(target
, DBGMCU_IDCODE
, id
);
739 static int stm32lx_probe(struct flash_bank
*bank
)
741 struct target
*target
= bank
->target
;
742 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
744 uint16_t flash_size_in_kb
;
746 uint32_t base_address
= FLASH_BANK0_ADDRESS
;
747 uint32_t second_bank_base
;
750 stm32lx_info
->probed
= 0;
752 int retval
= stm32lx_read_id_code(bank
->target
, &device_id
);
753 if (retval
!= ERROR_OK
)
756 stm32lx_info
->idcode
= device_id
;
758 LOG_DEBUG("device id = 0x%08" PRIx32
"", device_id
);
760 for (n
= 0; n
< ARRAY_SIZE(stm32lx_parts
); n
++) {
761 if ((device_id
& 0xfff) == stm32lx_parts
[n
].id
) {
762 stm32lx_info
->part_info
= stm32lx_parts
[n
];
767 if (n
== ARRAY_SIZE(stm32lx_parts
)) {
768 LOG_WARNING("Cannot identify target as a STM32L family.");
771 LOG_INFO("Device: %s", stm32lx_info
->part_info
.device_str
);
774 stm32lx_info
->flash_base
= stm32lx_info
->part_info
.flash_base
;
776 /* Get the flash size from target. */
777 retval
= target_read_u16(target
, stm32lx_info
->part_info
.fsize_base
,
780 /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
781 * or 256K, respectively. Please see RM0038 r8 or newer and refer to
783 if (retval
== ERROR_OK
&& (device_id
& 0xfff) == 0x436) {
784 if (flash_size_in_kb
== 0)
785 flash_size_in_kb
= 384;
786 else if (flash_size_in_kb
== 1)
787 flash_size_in_kb
= 256;
790 /* 0x429 devices only use the lowest 8 bits of the flash size register */
791 if (retval
== ERROR_OK
&& (device_id
& 0xfff) == 0x429) {
792 flash_size_in_kb
&= 0xff;
795 /* Failed reading flash size or flash size invalid (early silicon),
796 * default to max target family */
797 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
798 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
799 stm32lx_info
->part_info
.max_flash_size_kb
);
800 flash_size_in_kb
= stm32lx_info
->part_info
.max_flash_size_kb
;
801 } else if (flash_size_in_kb
> stm32lx_info
->part_info
.max_flash_size_kb
) {
802 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
803 flash_size_in_kb
, stm32lx_info
->part_info
.max_flash_size_kb
,
804 stm32lx_info
->part_info
.max_flash_size_kb
);
805 flash_size_in_kb
= stm32lx_info
->part_info
.max_flash_size_kb
;
808 /* Overwrite default dual-bank configuration */
809 retval
= stm32lx_update_part_info(bank
, flash_size_in_kb
);
810 if (retval
!= ERROR_OK
)
813 if (stm32lx_info
->part_info
.has_dual_banks
) {
814 /* Use the configured base address to determine if this is the first or second flash bank.
815 * Verify that the base address is reasonably correct and determine the flash bank size
817 second_bank_base
= base_address
+
818 stm32lx_info
->part_info
.first_bank_size_kb
* 1024;
819 if (bank
->base
== second_bank_base
|| !bank
->base
) {
820 /* This is the second bank */
821 base_address
= second_bank_base
;
822 flash_size_in_kb
= flash_size_in_kb
-
823 stm32lx_info
->part_info
.first_bank_size_kb
;
824 } else if (bank
->base
== base_address
) {
825 /* This is the first bank */
826 flash_size_in_kb
= stm32lx_info
->part_info
.first_bank_size_kb
;
828 LOG_WARNING("STM32L flash bank base address config is incorrect."
829 " 0x%" PRIx32
" but should rather be 0x%" PRIx32
" or 0x%" PRIx32
,
830 bank
->base
, base_address
, second_bank_base
);
833 LOG_INFO("STM32L flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32
,
834 bank
->bank_number
, flash_size_in_kb
, base_address
);
836 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32
, flash_size_in_kb
, base_address
);
839 /* if the user sets the size manually then ignore the probed value
840 * this allows us to work around devices that have a invalid flash size register value */
841 if (stm32lx_info
->user_bank_size
) {
842 flash_size_in_kb
= stm32lx_info
->user_bank_size
/ 1024;
843 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb
);
846 /* calculate numbers of sectors (4kB per sector) */
847 int num_sectors
= (flash_size_in_kb
* 1024) / FLASH_SECTOR_SIZE
;
851 bank
->sectors
= NULL
;
854 bank
->size
= flash_size_in_kb
* 1024;
855 bank
->base
= base_address
;
856 bank
->num_sectors
= num_sectors
;
857 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
858 if (bank
->sectors
== NULL
) {
859 LOG_ERROR("failed to allocate bank sectors");
863 for (i
= 0; i
< num_sectors
; i
++) {
864 bank
->sectors
[i
].offset
= i
* FLASH_SECTOR_SIZE
;
865 bank
->sectors
[i
].size
= FLASH_SECTOR_SIZE
;
866 bank
->sectors
[i
].is_erased
= -1;
867 bank
->sectors
[i
].is_protected
= 1;
870 stm32lx_info
->probed
= 1;
875 static int stm32lx_auto_probe(struct flash_bank
*bank
)
877 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
879 if (stm32lx_info
->probed
)
882 return stm32lx_probe(bank
);
885 /* This method must return a string displaying information about the bank */
886 static int stm32lx_get_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
888 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
889 const struct stm32lx_part_info
*info
= &stm32lx_info
->part_info
;
890 uint16_t rev_id
= stm32lx_info
->idcode
>> 16;
891 const char *rev_str
= NULL
;
893 if (!stm32lx_info
->probed
) {
894 int retval
= stm32lx_probe(bank
);
895 if (retval
!= ERROR_OK
) {
896 snprintf(buf
, buf_size
,
897 "Unable to find bank information.");
902 for (unsigned int i
= 0; i
< info
->num_revs
; i
++)
903 if (rev_id
== info
->revs
[i
].rev
)
904 rev_str
= info
->revs
[i
].str
;
906 if (rev_str
!= NULL
) {
907 snprintf(buf
, buf_size
,
909 info
->device_str
, rev_str
);
911 snprintf(buf
, buf_size
,
912 "%s - Rev: unknown (0x%04x)",
913 info
->device_str
, rev_id
);
919 static const struct command_registration stm32lx_exec_command_handlers
[] = {
921 .name
= "mass_erase",
922 .handler
= stm32lx_handle_mass_erase_command
,
923 .mode
= COMMAND_EXEC
,
925 .help
= "Erase entire flash device. including available EEPROM",
929 .handler
= stm32lx_handle_lock_command
,
930 .mode
= COMMAND_EXEC
,
932 .help
= "Increase the readout protection to Level 1.",
936 .handler
= stm32lx_handle_unlock_command
,
937 .mode
= COMMAND_EXEC
,
939 .help
= "Lower the readout protection from Level 1 to 0.",
941 COMMAND_REGISTRATION_DONE
944 static const struct command_registration stm32lx_command_handlers
[] = {
948 .help
= "stm32lx flash command group",
950 .chain
= stm32lx_exec_command_handlers
,
952 COMMAND_REGISTRATION_DONE
955 struct flash_driver stm32lx_flash
= {
957 .commands
= stm32lx_command_handlers
,
958 .flash_bank_command
= stm32lx_flash_bank_command
,
959 .erase
= stm32lx_erase
,
960 .protect
= stm32lx_protect
,
961 .write
= stm32lx_write
,
962 .read
= default_flash_read
,
963 .probe
= stm32lx_probe
,
964 .auto_probe
= stm32lx_auto_probe
,
965 .erase_check
= default_flash_blank_check
,
966 .protect_check
= stm32lx_protect_check
,
967 .info
= stm32lx_get_info
,
970 /* Static methods implementation */
971 static int stm32lx_unlock_program_memory(struct flash_bank
*bank
)
973 struct target
*target
= bank
->target
;
974 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
979 * Unlocking the program memory is done by unlocking the PECR,
980 * then by writing the 2 PRGKEY to the PRGKEYR register
983 /* check flash is not already unlocked */
984 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
986 if (retval
!= ERROR_OK
)
989 if ((reg32
& FLASH_PECR__PRGLOCK
) == 0)
992 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
993 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
,
995 if (retval
!= ERROR_OK
)
998 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
,
1000 if (retval
!= ERROR_OK
)
1003 /* Make sure it worked */
1004 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1006 if (retval
!= ERROR_OK
)
1009 if (reg32
& FLASH_PECR__PELOCK
) {
1010 LOG_ERROR("PELOCK is not cleared :(");
1011 return ERROR_FLASH_OPERATION_FAILED
;
1014 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PRGKEYR
,
1016 if (retval
!= ERROR_OK
)
1018 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PRGKEYR
,
1020 if (retval
!= ERROR_OK
)
1023 /* Make sure it worked */
1024 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1026 if (retval
!= ERROR_OK
)
1029 if (reg32
& FLASH_PECR__PRGLOCK
) {
1030 LOG_ERROR("PRGLOCK is not cleared :(");
1031 return ERROR_FLASH_OPERATION_FAILED
;
1037 static int stm32lx_enable_write_half_page(struct flash_bank
*bank
)
1039 struct target
*target
= bank
->target
;
1040 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1045 * Unlock the program memory, then set the FPRG bit in the PECR register.
1047 retval
= stm32lx_unlock_program_memory(bank
);
1048 if (retval
!= ERROR_OK
)
1051 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1053 if (retval
!= ERROR_OK
)
1056 reg32
|= FLASH_PECR__FPRG
;
1057 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1059 if (retval
!= ERROR_OK
)
1062 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1064 if (retval
!= ERROR_OK
)
1067 reg32
|= FLASH_PECR__PROG
;
1068 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1074 static int stm32lx_lock_program_memory(struct flash_bank
*bank
)
1076 struct target
*target
= bank
->target
;
1077 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1081 /* To lock the program memory, simply set the lock bit and lock PECR */
1083 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1085 if (retval
!= ERROR_OK
)
1088 reg32
|= FLASH_PECR__PRGLOCK
;
1089 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1091 if (retval
!= ERROR_OK
)
1094 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1096 if (retval
!= ERROR_OK
)
1099 reg32
|= FLASH_PECR__PELOCK
;
1100 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1102 if (retval
!= ERROR_OK
)
1108 static int stm32lx_erase_sector(struct flash_bank
*bank
, int sector
)
1110 struct target
*target
= bank
->target
;
1111 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1116 * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
1117 * first unlock the memory, loop over the pages of this sector
1118 * and write 0x0 to its first word.
1121 retval
= stm32lx_unlock_program_memory(bank
);
1122 if (retval
!= ERROR_OK
)
1125 for (int page
= 0; page
< (int)stm32lx_info
->part_info
.pages_per_sector
;
1127 reg32
= FLASH_PECR__PROG
| FLASH_PECR__ERASE
;
1128 retval
= target_write_u32(target
,
1129 stm32lx_info
->flash_base
+ FLASH_PECR
, reg32
);
1130 if (retval
!= ERROR_OK
)
1133 retval
= stm32lx_wait_until_bsy_clear(bank
);
1134 if (retval
!= ERROR_OK
)
1137 uint32_t addr
= bank
->base
+ bank
->sectors
[sector
].offset
+ (page
1138 * stm32lx_info
->part_info
.page_size
);
1139 retval
= target_write_u32(target
, addr
, 0x0);
1140 if (retval
!= ERROR_OK
)
1143 retval
= stm32lx_wait_until_bsy_clear(bank
);
1144 if (retval
!= ERROR_OK
)
1148 retval
= stm32lx_lock_program_memory(bank
);
1149 if (retval
!= ERROR_OK
)
1155 static inline int stm32lx_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
1157 struct target
*target
= bank
->target
;
1158 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1160 return target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_SR
, status
);
1163 static int stm32lx_wait_until_bsy_clear(struct flash_bank
*bank
)
1165 return stm32lx_wait_until_bsy_clear_timeout(bank
, 100);
1168 static int stm32lx_unlock_options_bytes(struct flash_bank
*bank
)
1170 struct target
*target
= bank
->target
;
1171 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1176 * Unlocking the options bytes is done by unlocking the PECR,
1177 * then by writing the 2 FLASH_PEKEYR to the FLASH_OPTKEYR register
1180 /* check flash is not already unlocked */
1181 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
, ®32
);
1182 if (retval
!= ERROR_OK
)
1185 if ((reg32
& FLASH_PECR__OPTLOCK
) == 0)
1188 if ((reg32
& FLASH_PECR__PELOCK
) != 0) {
1190 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
, PEKEY1
);
1191 if (retval
!= ERROR_OK
)
1194 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PEKEYR
, PEKEY2
);
1195 if (retval
!= ERROR_OK
)
1199 /* To unlock the PECR write the 2 OPTKEY to the FLASH_OPTKEYR register */
1200 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_OPTKEYR
, OPTKEY1
);
1201 if (retval
!= ERROR_OK
)
1204 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_OPTKEYR
, OPTKEY2
);
1205 if (retval
!= ERROR_OK
)
1211 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank
*bank
, int timeout
)
1213 struct target
*target
= bank
->target
;
1214 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1216 int retval
= ERROR_OK
;
1218 /* wait for busy to clear */
1220 retval
= stm32lx_get_flash_status(bank
, &status
);
1221 if (retval
!= ERROR_OK
)
1224 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
1225 if ((status
& FLASH_SR__BSY
) == 0)
1228 if (timeout
-- <= 0) {
1229 LOG_ERROR("timed out waiting for flash");
1235 if (status
& FLASH_SR__WRPERR
) {
1236 LOG_ERROR("access denied / write protected");
1237 retval
= ERROR_FAIL
;
1240 if (status
& FLASH_SR__PGAERR
) {
1241 LOG_ERROR("invalid program address");
1242 retval
= ERROR_FAIL
;
1245 /* Clear but report errors */
1246 if (status
& FLASH_SR__OPTVERR
) {
1247 /* If this operation fails, we ignore it and report the original retval */
1248 target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_SR
, status
& FLASH_SR__OPTVERR
);
1254 static int stm32lx_obl_launch(struct flash_bank
*bank
)
1256 struct target
*target
= bank
->target
;
1257 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1260 /* This will fail as the target gets immediately rebooted */
1261 target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
,
1262 FLASH_PECR__OBL_LAUNCH
);
1266 target_halt(target
);
1267 retval
= target_poll(target
);
1268 } while (--tries
> 0 &&
1269 (retval
!= ERROR_OK
|| target
->state
!= TARGET_HALTED
));
1271 return tries
? ERROR_OK
: ERROR_FAIL
;
1274 static int stm32lx_lock(struct flash_bank
*bank
)
1277 struct target
*target
= bank
->target
;
1279 if (target
->state
!= TARGET_HALTED
) {
1280 LOG_ERROR("Target not halted");
1281 return ERROR_TARGET_NOT_HALTED
;
1284 retval
= stm32lx_unlock_options_bytes(bank
);
1285 if (retval
!= ERROR_OK
)
1288 /* set the RDP protection level to 1 */
1289 retval
= target_write_u32(target
, OPTION_BYTES_ADDRESS
, OPTION_BYTE_0_PR1
);
1290 if (retval
!= ERROR_OK
)
1296 static int stm32lx_unlock(struct flash_bank
*bank
)
1299 struct target
*target
= bank
->target
;
1301 if (target
->state
!= TARGET_HALTED
) {
1302 LOG_ERROR("Target not halted");
1303 return ERROR_TARGET_NOT_HALTED
;
1306 retval
= stm32lx_unlock_options_bytes(bank
);
1307 if (retval
!= ERROR_OK
)
1310 /* set the RDP protection level to 0 */
1311 retval
= target_write_u32(target
, OPTION_BYTES_ADDRESS
, OPTION_BYTE_0_PR0
);
1312 if (retval
!= ERROR_OK
)
1315 retval
= stm32lx_wait_until_bsy_clear_timeout(bank
, 30000);
1316 if (retval
!= ERROR_OK
)
1322 static int stm32lx_mass_erase(struct flash_bank
*bank
)
1325 struct target
*target
= bank
->target
;
1326 struct stm32lx_flash_bank
*stm32lx_info
= NULL
;
1329 if (target
->state
!= TARGET_HALTED
) {
1330 LOG_ERROR("Target not halted");
1331 return ERROR_TARGET_NOT_HALTED
;
1334 stm32lx_info
= bank
->driver_priv
;
1336 retval
= stm32lx_lock(bank
);
1337 if (retval
!= ERROR_OK
)
1340 retval
= stm32lx_obl_launch(bank
);
1341 if (retval
!= ERROR_OK
)
1344 retval
= stm32lx_unlock(bank
);
1345 if (retval
!= ERROR_OK
)
1348 retval
= stm32lx_obl_launch(bank
);
1349 if (retval
!= ERROR_OK
)
1352 retval
= target_read_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
, ®32
);
1353 if (retval
!= ERROR_OK
)
1356 retval
= target_write_u32(target
, stm32lx_info
->flash_base
+ FLASH_PECR
, reg32
| FLASH_PECR__OPTLOCK
);
1357 if (retval
!= ERROR_OK
)
1363 static int stm32lx_update_part_info(struct flash_bank
*bank
, uint16_t flash_size_in_kb
)
1365 struct stm32lx_flash_bank
*stm32lx_info
= bank
->driver_priv
;
1367 switch (stm32lx_info
->part_info
.id
) {
1368 case 0x447: /* STM32L0xx (Cat.5) devices */
1369 if (flash_size_in_kb
== 192 || flash_size_in_kb
== 128) {
1370 stm32lx_info
->part_info
.first_bank_size_kb
= flash_size_in_kb
/ 2;
1371 stm32lx_info
->part_info
.has_dual_banks
= true;
1374 case 0x437: /* STM32L1xx (Cat.5/Cat.6) */
1375 stm32lx_info
->part_info
.first_bank_size_kb
= flash_size_in_kb
/ 2;
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