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[openocd.git] / src / flash / nor / stm32lx.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Clement Burin des Roziers *
9 * clement.burin-des-roziers@hikob.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33 #include <target/cortex_m.h>
34
35 /* stm32lx flash register locations */
36
37 #define FLASH_ACR 0x00
38 #define FLASH_PECR 0x04
39 #define FLASH_PDKEYR 0x08
40 #define FLASH_PEKEYR 0x0C
41 #define FLASH_PRGKEYR 0x10
42 #define FLASH_OPTKEYR 0x14
43 #define FLASH_SR 0x18
44 #define FLASH_OBR 0x1C
45 #define FLASH_WRPR 0x20
46
47 /* FLASH_ACR bites */
48 #define FLASH_ACR__LATENCY (1<<0)
49 #define FLASH_ACR__PRFTEN (1<<1)
50 #define FLASH_ACR__ACC64 (1<<2)
51 #define FLASH_ACR__SLEEP_PD (1<<3)
52 #define FLASH_ACR__RUN_PD (1<<4)
53
54 /* FLASH_PECR bits */
55 #define FLASH_PECR__PELOCK (1<<0)
56 #define FLASH_PECR__PRGLOCK (1<<1)
57 #define FLASH_PECR__OPTLOCK (1<<2)
58 #define FLASH_PECR__PROG (1<<3)
59 #define FLASH_PECR__DATA (1<<4)
60 #define FLASH_PECR__FTDW (1<<8)
61 #define FLASH_PECR__ERASE (1<<9)
62 #define FLASH_PECR__FPRG (1<<10)
63 #define FLASH_PECR__EOPIE (1<<16)
64 #define FLASH_PECR__ERRIE (1<<17)
65 #define FLASH_PECR__OBL_LAUNCH (1<<18)
66
67 /* FLASH_SR bits */
68 #define FLASH_SR__BSY (1<<0)
69 #define FLASH_SR__EOP (1<<1)
70 #define FLASH_SR__ENDHV (1<<2)
71 #define FLASH_SR__READY (1<<3)
72 #define FLASH_SR__WRPERR (1<<8)
73 #define FLASH_SR__PGAERR (1<<9)
74 #define FLASH_SR__SIZERR (1<<10)
75 #define FLASH_SR__OPTVERR (1<<11)
76
77 /* Unlock keys */
78 #define PEKEY1 0x89ABCDEF
79 #define PEKEY2 0x02030405
80 #define PRGKEY1 0x8C9DAEBF
81 #define PRGKEY2 0x13141516
82 #define OPTKEY1 0xFBEAD9C8
83 #define OPTKEY2 0x24252627
84
85 /* other registers */
86 #define DBGMCU_IDCODE 0xE0042000
87 #define DBGMCU_IDCODE_L0 0x40015800
88
89 /* Constants */
90 #define FLASH_SECTOR_SIZE 4096
91 #define FLASH_BANK0_ADDRESS 0x08000000
92
93 /* option bytes */
94 #define OPTION_BYTES_ADDRESS 0x1FF80000
95
96 #define OPTION_BYTE_0_PR1 0xFFFF0000
97 #define OPTION_BYTE_0_PR0 0xFF5500AA
98
99 static int stm32lx_unlock_program_memory(struct flash_bank *bank);
100 static int stm32lx_lock_program_memory(struct flash_bank *bank);
101 static int stm32lx_enable_write_half_page(struct flash_bank *bank);
102 static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
103 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
104 static int stm32lx_lock(struct flash_bank *bank);
105 static int stm32lx_unlock(struct flash_bank *bank);
106 static int stm32lx_mass_erase(struct flash_bank *bank);
107 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout);
108 static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb);
109
110 struct stm32lx_rev {
111 uint16_t rev;
112 const char *str;
113 };
114
115 struct stm32lx_part_info {
116 uint16_t id;
117 const char *device_str;
118 const struct stm32lx_rev *revs;
119 size_t num_revs;
120 unsigned int page_size;
121 unsigned int pages_per_sector;
122 uint16_t max_flash_size_kb;
123 uint16_t first_bank_size_kb; /* used when has_dual_banks is true */
124 bool has_dual_banks;
125
126 uint32_t flash_base; /* Flash controller registers location */
127 uint32_t fsize_base; /* Location of FSIZE register */
128 };
129
130 struct stm32lx_flash_bank {
131 bool probed;
132 uint32_t idcode;
133 uint32_t user_bank_size;
134 uint32_t flash_base;
135
136 struct stm32lx_part_info part_info;
137 };
138
139 static const struct stm32lx_rev stm32_416_revs[] = {
140 { 0x1000, "A" }, { 0x1008, "Y" }, { 0x1038, "W" }, { 0x1078, "V" },
141 };
142 static const struct stm32lx_rev stm32_417_revs[] = {
143 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" }, { 0x1038, "X" }
144 };
145 static const struct stm32lx_rev stm32_425_revs[] = {
146 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Y" },
147 };
148 static const struct stm32lx_rev stm32_427_revs[] = {
149 { 0x1000, "A" }, { 0x1018, "Y" }, { 0x1038, "X" }, { 0x10f8, "V" },
150 };
151 static const struct stm32lx_rev stm32_429_revs[] = {
152 { 0x1000, "A" }, { 0x1018, "Z" },
153 };
154 static const struct stm32lx_rev stm32_436_revs[] = {
155 { 0x1000, "A" }, { 0x1008, "Z" }, { 0x1018, "Y" },
156 };
157 static const struct stm32lx_rev stm32_437_revs[] = {
158 { 0x1000, "A" },
159 };
160 static const struct stm32lx_rev stm32_447_revs[] = {
161 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2008, "Z" },
162 };
163 static const struct stm32lx_rev stm32_457_revs[] = {
164 { 0x1000, "A" }, { 0x1008, "Z" },
165 };
166
167 static const struct stm32lx_part_info stm32lx_parts[] = {
168 {
169 .id = 0x416,
170 .revs = stm32_416_revs,
171 .num_revs = ARRAY_SIZE(stm32_416_revs),
172 .device_str = "STM32L1xx (Cat.1 - Low/Medium Density)",
173 .page_size = 256,
174 .pages_per_sector = 16,
175 .max_flash_size_kb = 128,
176 .has_dual_banks = false,
177 .flash_base = 0x40023C00,
178 .fsize_base = 0x1FF8004C,
179 },
180 {
181 .id = 0x417,
182 .revs = stm32_417_revs,
183 .num_revs = ARRAY_SIZE(stm32_417_revs),
184 .device_str = "STM32L0xx (Cat. 3)",
185 .page_size = 128,
186 .pages_per_sector = 32,
187 .max_flash_size_kb = 64,
188 .has_dual_banks = false,
189 .flash_base = 0x40022000,
190 .fsize_base = 0x1FF8007C,
191 },
192 {
193 .id = 0x425,
194 .revs = stm32_425_revs,
195 .num_revs = ARRAY_SIZE(stm32_425_revs),
196 .device_str = "STM32L0xx (Cat. 2)",
197 .page_size = 128,
198 .pages_per_sector = 32,
199 .max_flash_size_kb = 32,
200 .has_dual_banks = false,
201 .flash_base = 0x40022000,
202 .fsize_base = 0x1FF8007C,
203 },
204 {
205 .id = 0x427,
206 .revs = stm32_427_revs,
207 .num_revs = ARRAY_SIZE(stm32_427_revs),
208 .device_str = "STM32L1xx (Cat.3 - Medium+ Density)",
209 .page_size = 256,
210 .pages_per_sector = 16,
211 .max_flash_size_kb = 256,
212 .has_dual_banks = false,
213 .flash_base = 0x40023C00,
214 .fsize_base = 0x1FF800CC,
215 },
216 {
217 .id = 0x429,
218 .revs = stm32_429_revs,
219 .num_revs = ARRAY_SIZE(stm32_429_revs),
220 .device_str = "STM32L1xx (Cat.2)",
221 .page_size = 256,
222 .pages_per_sector = 16,
223 .max_flash_size_kb = 128,
224 .has_dual_banks = false,
225 .flash_base = 0x40023C00,
226 .fsize_base = 0x1FF8004C,
227 },
228 {
229 .id = 0x436,
230 .revs = stm32_436_revs,
231 .num_revs = ARRAY_SIZE(stm32_436_revs),
232 .device_str = "STM32L1xx (Cat.4/Cat.3 - Medium+/High Density)",
233 .page_size = 256,
234 .pages_per_sector = 16,
235 .max_flash_size_kb = 384,
236 .first_bank_size_kb = 192,
237 .has_dual_banks = true,
238 .flash_base = 0x40023C00,
239 .fsize_base = 0x1FF800CC,
240 },
241 {
242 .id = 0x437,
243 .revs = stm32_437_revs,
244 .num_revs = ARRAY_SIZE(stm32_437_revs),
245 .device_str = "STM32L1xx (Cat.5/Cat.6)",
246 .page_size = 256,
247 .pages_per_sector = 16,
248 .max_flash_size_kb = 512,
249 .first_bank_size_kb = 0, /* determined in runtime */
250 .has_dual_banks = true,
251 .flash_base = 0x40023C00,
252 .fsize_base = 0x1FF800CC,
253 },
254 {
255 .id = 0x447,
256 .revs = stm32_447_revs,
257 .num_revs = ARRAY_SIZE(stm32_447_revs),
258 .device_str = "STM32L0xx (Cat.5)",
259 .page_size = 128,
260 .pages_per_sector = 32,
261 .max_flash_size_kb = 192,
262 .first_bank_size_kb = 0, /* determined in runtime */
263 .has_dual_banks = false, /* determined in runtime */
264 .flash_base = 0x40022000,
265 .fsize_base = 0x1FF8007C,
266 },
267 {
268 .id = 0x457,
269 .revs = stm32_457_revs,
270 .num_revs = ARRAY_SIZE(stm32_457_revs),
271 .device_str = "STM32L0xx (Cat.1)",
272 .page_size = 128,
273 .pages_per_sector = 32,
274 .max_flash_size_kb = 16,
275 .has_dual_banks = false,
276 .flash_base = 0x40022000,
277 .fsize_base = 0x1FF8007C,
278 },
279 };
280
281 /* flash bank stm32lx <base> <size> 0 0 <target#>
282 */
283 FLASH_BANK_COMMAND_HANDLER(stm32lx_flash_bank_command)
284 {
285 struct stm32lx_flash_bank *stm32lx_info;
286 if (CMD_ARGC < 6)
287 return ERROR_COMMAND_SYNTAX_ERROR;
288
289 /* Create the bank structure */
290 stm32lx_info = calloc(1, sizeof(*stm32lx_info));
291
292 /* Check allocation */
293 if (stm32lx_info == NULL) {
294 LOG_ERROR("failed to allocate bank structure");
295 return ERROR_FAIL;
296 }
297
298 bank->driver_priv = stm32lx_info;
299
300 stm32lx_info->probed = false;
301 stm32lx_info->user_bank_size = bank->size;
302
303 /* the stm32l erased value is 0x00 */
304 bank->default_padded_value = bank->erased_value = 0x00;
305
306 return ERROR_OK;
307 }
308
309 COMMAND_HANDLER(stm32lx_handle_mass_erase_command)
310 {
311 if (CMD_ARGC < 1)
312 return ERROR_COMMAND_SYNTAX_ERROR;
313
314 struct flash_bank *bank;
315 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
316 if (ERROR_OK != retval)
317 return retval;
318
319 retval = stm32lx_mass_erase(bank);
320 if (retval == ERROR_OK) {
321 /* set all sectors as erased */
322 for (unsigned int i = 0; i < bank->num_sectors; i++)
323 bank->sectors[i].is_erased = 1;
324
325 command_print(CMD, "stm32lx mass erase complete");
326 } else {
327 command_print(CMD, "stm32lx mass erase failed");
328 }
329
330 return retval;
331 }
332
333 COMMAND_HANDLER(stm32lx_handle_lock_command)
334 {
335 if (CMD_ARGC < 1)
336 return ERROR_COMMAND_SYNTAX_ERROR;
337
338 struct flash_bank *bank;
339 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
340 if (ERROR_OK != retval)
341 return retval;
342
343 retval = stm32lx_lock(bank);
344
345 if (retval == ERROR_OK)
346 command_print(CMD, "STM32Lx locked, takes effect after power cycle.");
347 else
348 command_print(CMD, "STM32Lx lock failed");
349
350 return retval;
351 }
352
353 COMMAND_HANDLER(stm32lx_handle_unlock_command)
354 {
355 if (CMD_ARGC < 1)
356 return ERROR_COMMAND_SYNTAX_ERROR;
357
358 struct flash_bank *bank;
359 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
360 if (ERROR_OK != retval)
361 return retval;
362
363 retval = stm32lx_unlock(bank);
364
365 if (retval == ERROR_OK)
366 command_print(CMD, "STM32Lx unlocked, takes effect after power cycle.");
367 else
368 command_print(CMD, "STM32Lx unlock failed");
369
370 return retval;
371 }
372
373 static int stm32lx_protect_check(struct flash_bank *bank)
374 {
375 int retval;
376 struct target *target = bank->target;
377 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
378
379 uint32_t wrpr;
380
381 /*
382 * Read the WRPR word, and check each bit (corresponding to each
383 * flash sector
384 */
385 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_WRPR,
386 &wrpr);
387 if (retval != ERROR_OK)
388 return retval;
389
390 for (unsigned int i = 0; i < bank->num_sectors; i++) {
391 if (wrpr & (1 << i))
392 bank->sectors[i].is_protected = 1;
393 else
394 bank->sectors[i].is_protected = 0;
395 }
396 return ERROR_OK;
397 }
398
399 static int stm32lx_erase(struct flash_bank *bank, unsigned int first,
400 unsigned int last)
401 {
402 int retval;
403
404 /*
405 * It could be possible to do a mass erase if all sectors must be
406 * erased, but it is not implemented yet.
407 */
408
409 if (bank->target->state != TARGET_HALTED) {
410 LOG_ERROR("Target not halted");
411 return ERROR_TARGET_NOT_HALTED;
412 }
413
414 /*
415 * Loop over the selected sectors and erase them
416 */
417 for (unsigned int i = first; i <= last; i++) {
418 retval = stm32lx_erase_sector(bank, i);
419 if (retval != ERROR_OK)
420 return retval;
421 bank->sectors[i].is_erased = 1;
422 }
423 return ERROR_OK;
424 }
425
426 static int stm32lx_write_half_pages(struct flash_bank *bank, const uint8_t *buffer,
427 uint32_t offset, uint32_t count)
428 {
429 struct target *target = bank->target;
430 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
431
432 uint32_t hp_nb = stm32lx_info->part_info.page_size / 2;
433 uint32_t buffer_size = 16384;
434 struct working_area *write_algorithm;
435 struct working_area *source;
436 uint32_t address = bank->base + offset;
437
438 struct reg_param reg_params[3];
439 struct armv7m_algorithm armv7m_info;
440
441 int retval = ERROR_OK;
442
443 static const uint8_t stm32lx_flash_write_code[] = {
444 #include "../../../contrib/loaders/flash/stm32/stm32lx.inc"
445 };
446
447 /* Make sure we're performing a half-page aligned write. */
448 if (count % hp_nb) {
449 LOG_ERROR("The byte count must be %" PRIu32 "B-aligned but count is %" PRIu32 "B)", hp_nb, count);
450 return ERROR_FAIL;
451 }
452
453 /* flash write code */
454 if (target_alloc_working_area(target, sizeof(stm32lx_flash_write_code),
455 &write_algorithm) != ERROR_OK) {
456 LOG_DEBUG("no working area for block memory writes");
457 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
458 }
459
460 /* Write the flashing code */
461 retval = target_write_buffer(target,
462 write_algorithm->address,
463 sizeof(stm32lx_flash_write_code),
464 stm32lx_flash_write_code);
465 if (retval != ERROR_OK) {
466 target_free_working_area(target, write_algorithm);
467 return retval;
468 }
469
470 /* Allocate half pages memory */
471 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
472 if (buffer_size > 1024)
473 buffer_size -= 1024;
474 else
475 buffer_size /= 2;
476
477 if (buffer_size <= stm32lx_info->part_info.page_size) {
478 /* we already allocated the writing code, but failed to get a
479 * buffer, free the algorithm */
480 target_free_working_area(target, write_algorithm);
481
482 LOG_WARNING("no large enough working area available, can't do block memory writes");
483 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
484 }
485 }
486
487 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
488 armv7m_info.core_mode = ARM_MODE_THREAD;
489 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
490 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
491 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
492
493 /* Enable half-page write */
494 retval = stm32lx_enable_write_half_page(bank);
495 if (retval != ERROR_OK) {
496 target_free_working_area(target, source);
497 target_free_working_area(target, write_algorithm);
498
499 destroy_reg_param(&reg_params[0]);
500 destroy_reg_param(&reg_params[1]);
501 destroy_reg_param(&reg_params[2]);
502 return retval;
503 }
504
505 struct armv7m_common *armv7m = target_to_armv7m(target);
506 if (armv7m == NULL) {
507
508 /* something is very wrong if armv7m is NULL */
509 LOG_ERROR("unable to get armv7m target");
510 return retval;
511 }
512
513 /* save any DEMCR flags and configure target to catch any Hard Faults */
514 uint32_t demcr_save = armv7m->demcr;
515 armv7m->demcr = VC_HARDERR;
516
517 /* Loop while there are bytes to write */
518 while (count > 0) {
519 uint32_t this_count;
520 this_count = (count > buffer_size) ? buffer_size : count;
521
522 /* Write the next half pages */
523 retval = target_write_buffer(target, source->address, this_count, buffer);
524 if (retval != ERROR_OK)
525 break;
526
527 /* 4: Store useful information in the registers */
528 /* the destination address of the copy (R0) */
529 buf_set_u32(reg_params[0].value, 0, 32, address);
530 /* The source address of the copy (R1) */
531 buf_set_u32(reg_params[1].value, 0, 32, source->address);
532 /* The length of the copy (R2) */
533 buf_set_u32(reg_params[2].value, 0, 32, this_count / 4);
534
535 /* 5: Execute the bunch of code */
536 retval = target_run_algorithm(target, 0, NULL, sizeof(reg_params)
537 / sizeof(*reg_params), reg_params,
538 write_algorithm->address, 0, 10000, &armv7m_info);
539 if (retval != ERROR_OK)
540 break;
541
542 /* check for Hard Fault */
543 if (armv7m->exception_number == 3)
544 break;
545
546 /* 6: Wait while busy */
547 retval = stm32lx_wait_until_bsy_clear(bank);
548 if (retval != ERROR_OK)
549 break;
550
551 buffer += this_count;
552 address += this_count;
553 count -= this_count;
554 }
555
556 /* restore previous flags */
557 armv7m->demcr = demcr_save;
558
559 if (armv7m->exception_number == 3) {
560
561 /* the stm32l15x devices seem to have an issue when blank.
562 * if a ram loader is executed on a blank device it will
563 * Hard Fault, this issue does not happen for a already programmed device.
564 * A related issue is described in the stm32l151xx errata (Doc ID 17721 Rev 6 - 2.1.3).
565 * The workaround of handling the Hard Fault exception does work, but makes the
566 * loader more complicated, as a compromise we manually write the pages, programming time
567 * is reduced by 50% using this slower method.
568 */
569
570 LOG_WARNING("Couldn't use loader, falling back to page memory writes");
571
572 while (count > 0) {
573 uint32_t this_count;
574 this_count = (count > hp_nb) ? hp_nb : count;
575
576 /* Write the next half pages */
577 retval = target_write_buffer(target, address, this_count, buffer);
578 if (retval != ERROR_OK)
579 break;
580
581 /* Wait while busy */
582 retval = stm32lx_wait_until_bsy_clear(bank);
583 if (retval != ERROR_OK)
584 break;
585
586 buffer += this_count;
587 address += this_count;
588 count -= this_count;
589 }
590 }
591
592 if (retval == ERROR_OK)
593 retval = stm32lx_lock_program_memory(bank);
594
595 target_free_working_area(target, source);
596 target_free_working_area(target, write_algorithm);
597
598 destroy_reg_param(&reg_params[0]);
599 destroy_reg_param(&reg_params[1]);
600 destroy_reg_param(&reg_params[2]);
601
602 return retval;
603 }
604
605 static int stm32lx_write(struct flash_bank *bank, const uint8_t *buffer,
606 uint32_t offset, uint32_t count)
607 {
608 struct target *target = bank->target;
609 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
610
611 uint32_t hp_nb = stm32lx_info->part_info.page_size / 2;
612 uint32_t halfpages_number;
613 uint32_t bytes_remaining = 0;
614 uint32_t address = bank->base + offset;
615 uint32_t bytes_written = 0;
616 int retval, retval2;
617
618 if (bank->target->state != TARGET_HALTED) {
619 LOG_ERROR("Target not halted");
620 return ERROR_TARGET_NOT_HALTED;
621 }
622
623 if (offset & 0x3) {
624 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
625 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
626 }
627
628 retval = stm32lx_unlock_program_memory(bank);
629 if (retval != ERROR_OK)
630 return retval;
631
632 /* first we need to write any unaligned head bytes up to
633 * the next 128 byte page */
634
635 if (offset % hp_nb)
636 bytes_remaining = MIN(count, hp_nb - (offset % hp_nb));
637
638 while (bytes_remaining > 0) {
639 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
640
641 /* copy remaining bytes into the write buffer */
642 uint32_t bytes_to_write = MIN(4, bytes_remaining);
643 memcpy(value, buffer + bytes_written, bytes_to_write);
644
645 retval = target_write_buffer(target, address, 4, value);
646 if (retval != ERROR_OK)
647 goto reset_pg_and_lock;
648
649 bytes_written += bytes_to_write;
650 bytes_remaining -= bytes_to_write;
651 address += 4;
652
653 retval = stm32lx_wait_until_bsy_clear(bank);
654 if (retval != ERROR_OK)
655 goto reset_pg_and_lock;
656 }
657
658 offset += bytes_written;
659 count -= bytes_written;
660
661 /* this should always pass this check here */
662 assert((offset % hp_nb) == 0);
663
664 /* calculate half pages */
665 halfpages_number = count / hp_nb;
666
667 if (halfpages_number) {
668 retval = stm32lx_write_half_pages(bank, buffer + bytes_written, offset, hp_nb * halfpages_number);
669 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
670 /* attempt slow memory writes */
671 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
672 halfpages_number = 0;
673 } else {
674 if (retval != ERROR_OK)
675 return ERROR_FAIL;
676 }
677 }
678
679 /* write any remaining bytes */
680 uint32_t page_bytes_written = hp_nb * halfpages_number;
681 bytes_written += page_bytes_written;
682 address += page_bytes_written;
683 bytes_remaining = count - page_bytes_written;
684
685 retval = stm32lx_unlock_program_memory(bank);
686 if (retval != ERROR_OK)
687 return retval;
688
689 while (bytes_remaining > 0) {
690 uint8_t value[4] = {0xff, 0xff, 0xff, 0xff};
691
692 /* copy remaining bytes into the write buffer */
693 uint32_t bytes_to_write = MIN(4, bytes_remaining);
694 memcpy(value, buffer + bytes_written, bytes_to_write);
695
696 retval = target_write_buffer(target, address, 4, value);
697 if (retval != ERROR_OK)
698 goto reset_pg_and_lock;
699
700 bytes_written += bytes_to_write;
701 bytes_remaining -= bytes_to_write;
702 address += 4;
703
704 retval = stm32lx_wait_until_bsy_clear(bank);
705 if (retval != ERROR_OK)
706 goto reset_pg_and_lock;
707 }
708
709 reset_pg_and_lock:
710 retval2 = stm32lx_lock_program_memory(bank);
711 if (retval == ERROR_OK)
712 retval = retval2;
713
714 return retval;
715 }
716
717 static int stm32lx_read_id_code(struct target *target, uint32_t *id)
718 {
719 struct armv7m_common *armv7m = target_to_armv7m(target);
720 int retval;
721 if (armv7m->arm.is_armv6m == true)
722 retval = target_read_u32(target, DBGMCU_IDCODE_L0, id);
723 else
724 /* read stm32 device id register */
725 retval = target_read_u32(target, DBGMCU_IDCODE, id);
726 return retval;
727 }
728
729 static int stm32lx_probe(struct flash_bank *bank)
730 {
731 struct target *target = bank->target;
732 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
733 uint16_t flash_size_in_kb;
734 uint32_t device_id;
735 uint32_t base_address = FLASH_BANK0_ADDRESS;
736 uint32_t second_bank_base;
737 unsigned int n;
738
739 stm32lx_info->probed = false;
740
741 int retval = stm32lx_read_id_code(bank->target, &device_id);
742 if (retval != ERROR_OK)
743 return retval;
744
745 stm32lx_info->idcode = device_id;
746
747 LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
748
749 for (n = 0; n < ARRAY_SIZE(stm32lx_parts); n++) {
750 if ((device_id & 0xfff) == stm32lx_parts[n].id) {
751 stm32lx_info->part_info = stm32lx_parts[n];
752 break;
753 }
754 }
755
756 if (n == ARRAY_SIZE(stm32lx_parts)) {
757 LOG_ERROR("Cannot identify target as an STM32 L0 or L1 family device.");
758 return ERROR_FAIL;
759 } else {
760 LOG_INFO("Device: %s", stm32lx_info->part_info.device_str);
761 }
762
763 stm32lx_info->flash_base = stm32lx_info->part_info.flash_base;
764
765 /* Get the flash size from target. */
766 retval = target_read_u16(target, stm32lx_info->part_info.fsize_base,
767 &flash_size_in_kb);
768
769 /* 0x436 devices report their flash size as a 0 or 1 code indicating 384K
770 * or 256K, respectively. Please see RM0038 r8 or newer and refer to
771 * section 30.1.1. */
772 if (retval == ERROR_OK && (device_id & 0xfff) == 0x436) {
773 if (flash_size_in_kb == 0)
774 flash_size_in_kb = 384;
775 else if (flash_size_in_kb == 1)
776 flash_size_in_kb = 256;
777 }
778
779 /* 0x429 devices only use the lowest 8 bits of the flash size register */
780 if (retval == ERROR_OK && (device_id & 0xfff) == 0x429) {
781 flash_size_in_kb &= 0xff;
782 }
783
784 /* Failed reading flash size or flash size invalid (early silicon),
785 * default to max target family */
786 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
787 LOG_WARNING("STM32L flash size failed, probe inaccurate - assuming %dk flash",
788 stm32lx_info->part_info.max_flash_size_kb);
789 flash_size_in_kb = stm32lx_info->part_info.max_flash_size_kb;
790 } else if (flash_size_in_kb > stm32lx_info->part_info.max_flash_size_kb) {
791 LOG_WARNING("STM32L probed flash size assumed incorrect since FLASH_SIZE=%dk > %dk, - assuming %dk flash",
792 flash_size_in_kb, stm32lx_info->part_info.max_flash_size_kb,
793 stm32lx_info->part_info.max_flash_size_kb);
794 flash_size_in_kb = stm32lx_info->part_info.max_flash_size_kb;
795 }
796
797 /* Overwrite default dual-bank configuration */
798 retval = stm32lx_update_part_info(bank, flash_size_in_kb);
799 if (retval != ERROR_OK)
800 return ERROR_FAIL;
801
802 if (stm32lx_info->part_info.has_dual_banks) {
803 /* Use the configured base address to determine if this is the first or second flash bank.
804 * Verify that the base address is reasonably correct and determine the flash bank size
805 */
806 second_bank_base = base_address +
807 stm32lx_info->part_info.first_bank_size_kb * 1024;
808 if (bank->base == second_bank_base || !bank->base) {
809 /* This is the second bank */
810 base_address = second_bank_base;
811 flash_size_in_kb = flash_size_in_kb -
812 stm32lx_info->part_info.first_bank_size_kb;
813 } else if (bank->base == base_address) {
814 /* This is the first bank */
815 flash_size_in_kb = stm32lx_info->part_info.first_bank_size_kb;
816 } else {
817 LOG_WARNING("STM32L flash bank base address config is incorrect. "
818 TARGET_ADDR_FMT " but should rather be 0x%" PRIx32
819 " or 0x%" PRIx32,
820 bank->base, base_address, second_bank_base);
821 return ERROR_FAIL;
822 }
823 LOG_INFO("STM32L flash has dual banks. Bank (%u) size is %dkb, base address is 0x%" PRIx32,
824 bank->bank_number, flash_size_in_kb, base_address);
825 } else {
826 LOG_INFO("STM32L flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
827 }
828
829 /* if the user sets the size manually then ignore the probed value
830 * this allows us to work around devices that have a invalid flash size register value */
831 if (stm32lx_info->user_bank_size) {
832 flash_size_in_kb = stm32lx_info->user_bank_size / 1024;
833 LOG_INFO("ignoring flash probed value, using configured bank size: %dkbytes", flash_size_in_kb);
834 }
835
836 /* calculate numbers of sectors (4kB per sector) */
837 unsigned int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
838
839 free(bank->sectors);
840
841 bank->size = flash_size_in_kb * 1024;
842 bank->base = base_address;
843 bank->num_sectors = num_sectors;
844 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
845 if (bank->sectors == NULL) {
846 LOG_ERROR("failed to allocate bank sectors");
847 return ERROR_FAIL;
848 }
849
850 for (unsigned int i = 0; i < num_sectors; i++) {
851 bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
852 bank->sectors[i].size = FLASH_SECTOR_SIZE;
853 bank->sectors[i].is_erased = -1;
854 bank->sectors[i].is_protected = -1;
855 }
856
857 stm32lx_info->probed = true;
858
859 return ERROR_OK;
860 }
861
862 static int stm32lx_auto_probe(struct flash_bank *bank)
863 {
864 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
865
866 if (stm32lx_info->probed)
867 return ERROR_OK;
868
869 return stm32lx_probe(bank);
870 }
871
872 /* This method must return a string displaying information about the bank */
873 static int stm32lx_get_info(struct flash_bank *bank, char *buf, int buf_size)
874 {
875 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
876 const struct stm32lx_part_info *info = &stm32lx_info->part_info;
877 uint16_t rev_id = stm32lx_info->idcode >> 16;
878 const char *rev_str = NULL;
879
880 if (!stm32lx_info->probed) {
881 int retval = stm32lx_probe(bank);
882 if (retval != ERROR_OK) {
883 snprintf(buf, buf_size,
884 "Unable to find bank information.");
885 return retval;
886 }
887 }
888
889 for (unsigned int i = 0; i < info->num_revs; i++)
890 if (rev_id == info->revs[i].rev)
891 rev_str = info->revs[i].str;
892
893 if (rev_str != NULL) {
894 snprintf(buf, buf_size,
895 "%s - Rev: %s",
896 info->device_str, rev_str);
897 } else {
898 snprintf(buf, buf_size,
899 "%s - Rev: unknown (0x%04x)",
900 info->device_str, rev_id);
901 }
902
903 return ERROR_OK;
904 }
905
906 static const struct command_registration stm32lx_exec_command_handlers[] = {
907 {
908 .name = "mass_erase",
909 .handler = stm32lx_handle_mass_erase_command,
910 .mode = COMMAND_EXEC,
911 .usage = "bank_id",
912 .help = "Erase entire flash device. including available EEPROM",
913 },
914 {
915 .name = "lock",
916 .handler = stm32lx_handle_lock_command,
917 .mode = COMMAND_EXEC,
918 .usage = "bank_id",
919 .help = "Increase the readout protection to Level 1.",
920 },
921 {
922 .name = "unlock",
923 .handler = stm32lx_handle_unlock_command,
924 .mode = COMMAND_EXEC,
925 .usage = "bank_id",
926 .help = "Lower the readout protection from Level 1 to 0.",
927 },
928 COMMAND_REGISTRATION_DONE
929 };
930
931 static const struct command_registration stm32lx_command_handlers[] = {
932 {
933 .name = "stm32lx",
934 .mode = COMMAND_ANY,
935 .help = "stm32lx flash command group",
936 .usage = "",
937 .chain = stm32lx_exec_command_handlers,
938 },
939 COMMAND_REGISTRATION_DONE
940 };
941
942 const struct flash_driver stm32lx_flash = {
943 .name = "stm32lx",
944 .commands = stm32lx_command_handlers,
945 .flash_bank_command = stm32lx_flash_bank_command,
946 .erase = stm32lx_erase,
947 .write = stm32lx_write,
948 .read = default_flash_read,
949 .probe = stm32lx_probe,
950 .auto_probe = stm32lx_auto_probe,
951 .erase_check = default_flash_blank_check,
952 .protect_check = stm32lx_protect_check,
953 .info = stm32lx_get_info,
954 .free_driver_priv = default_flash_free_driver_priv,
955 };
956
957 /* Static methods implementation */
958 static int stm32lx_unlock_program_memory(struct flash_bank *bank)
959 {
960 struct target *target = bank->target;
961 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
962 int retval;
963 uint32_t reg32;
964
965 /*
966 * Unlocking the program memory is done by unlocking the PECR,
967 * then by writing the 2 PRGKEY to the PRGKEYR register
968 */
969
970 /* check flash is not already unlocked */
971 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
972 &reg32);
973 if (retval != ERROR_OK)
974 return retval;
975
976 if ((reg32 & FLASH_PECR__PRGLOCK) == 0)
977 return ERROR_OK;
978
979 /* To unlock the PECR write the 2 PEKEY to the PEKEYR register */
980 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
981 PEKEY1);
982 if (retval != ERROR_OK)
983 return retval;
984
985 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR,
986 PEKEY2);
987 if (retval != ERROR_OK)
988 return retval;
989
990 /* Make sure it worked */
991 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
992 &reg32);
993 if (retval != ERROR_OK)
994 return retval;
995
996 if (reg32 & FLASH_PECR__PELOCK) {
997 LOG_ERROR("PELOCK is not cleared :(");
998 return ERROR_FLASH_OPERATION_FAILED;
999 }
1000
1001 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
1002 PRGKEY1);
1003 if (retval != ERROR_OK)
1004 return retval;
1005 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR,
1006 PRGKEY2);
1007 if (retval != ERROR_OK)
1008 return retval;
1009
1010 /* Make sure it worked */
1011 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1012 &reg32);
1013 if (retval != ERROR_OK)
1014 return retval;
1015
1016 if (reg32 & FLASH_PECR__PRGLOCK) {
1017 LOG_ERROR("PRGLOCK is not cleared :(");
1018 return ERROR_FLASH_OPERATION_FAILED;
1019 }
1020
1021 return ERROR_OK;
1022 }
1023
1024 static int stm32lx_enable_write_half_page(struct flash_bank *bank)
1025 {
1026 struct target *target = bank->target;
1027 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1028 int retval;
1029 uint32_t reg32;
1030
1031 /**
1032 * Unlock the program memory, then set the FPRG bit in the PECR register.
1033 */
1034 retval = stm32lx_unlock_program_memory(bank);
1035 if (retval != ERROR_OK)
1036 return retval;
1037
1038 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1039 &reg32);
1040 if (retval != ERROR_OK)
1041 return retval;
1042
1043 reg32 |= FLASH_PECR__FPRG;
1044 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1045 reg32);
1046 if (retval != ERROR_OK)
1047 return retval;
1048
1049 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1050 &reg32);
1051 if (retval != ERROR_OK)
1052 return retval;
1053
1054 reg32 |= FLASH_PECR__PROG;
1055 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1056 reg32);
1057
1058 return retval;
1059 }
1060
1061 static int stm32lx_lock_program_memory(struct flash_bank *bank)
1062 {
1063 struct target *target = bank->target;
1064 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1065 int retval;
1066 uint32_t reg32;
1067
1068 /* To lock the program memory, simply set the lock bit and lock PECR */
1069
1070 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1071 &reg32);
1072 if (retval != ERROR_OK)
1073 return retval;
1074
1075 reg32 |= FLASH_PECR__PRGLOCK;
1076 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1077 reg32);
1078 if (retval != ERROR_OK)
1079 return retval;
1080
1081 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1082 &reg32);
1083 if (retval != ERROR_OK)
1084 return retval;
1085
1086 reg32 |= FLASH_PECR__PELOCK;
1087 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1088 reg32);
1089 if (retval != ERROR_OK)
1090 return retval;
1091
1092 return ERROR_OK;
1093 }
1094
1095 static int stm32lx_erase_sector(struct flash_bank *bank, int sector)
1096 {
1097 struct target *target = bank->target;
1098 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1099 int retval;
1100 uint32_t reg32;
1101
1102 /*
1103 * To erase a sector (i.e. stm32lx_info->part_info.pages_per_sector pages),
1104 * first unlock the memory, loop over the pages of this sector
1105 * and write 0x0 to its first word.
1106 */
1107
1108 retval = stm32lx_unlock_program_memory(bank);
1109 if (retval != ERROR_OK)
1110 return retval;
1111
1112 for (int page = 0; page < (int)stm32lx_info->part_info.pages_per_sector;
1113 page++) {
1114 reg32 = FLASH_PECR__PROG | FLASH_PECR__ERASE;
1115 retval = target_write_u32(target,
1116 stm32lx_info->flash_base + FLASH_PECR, reg32);
1117 if (retval != ERROR_OK)
1118 return retval;
1119
1120 retval = stm32lx_wait_until_bsy_clear(bank);
1121 if (retval != ERROR_OK)
1122 return retval;
1123
1124 uint32_t addr = bank->base + bank->sectors[sector].offset + (page
1125 * stm32lx_info->part_info.page_size);
1126 retval = target_write_u32(target, addr, 0x0);
1127 if (retval != ERROR_OK)
1128 return retval;
1129
1130 retval = stm32lx_wait_until_bsy_clear(bank);
1131 if (retval != ERROR_OK)
1132 return retval;
1133 }
1134
1135 retval = stm32lx_lock_program_memory(bank);
1136 if (retval != ERROR_OK)
1137 return retval;
1138
1139 return ERROR_OK;
1140 }
1141
1142 static inline int stm32lx_get_flash_status(struct flash_bank *bank, uint32_t *status)
1143 {
1144 struct target *target = bank->target;
1145 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1146
1147 return target_read_u32(target, stm32lx_info->flash_base + FLASH_SR, status);
1148 }
1149
1150 static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank)
1151 {
1152 return stm32lx_wait_until_bsy_clear_timeout(bank, 100);
1153 }
1154
1155 static int stm32lx_unlock_options_bytes(struct flash_bank *bank)
1156 {
1157 struct target *target = bank->target;
1158 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1159 int retval;
1160 uint32_t reg32;
1161
1162 /*
1163 * Unlocking the options bytes is done by unlocking the PECR,
1164 * then by writing the 2 FLASH_PEKEYR to the FLASH_OPTKEYR register
1165 */
1166
1167 /* check flash is not already unlocked */
1168 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
1169 if (retval != ERROR_OK)
1170 return retval;
1171
1172 if ((reg32 & FLASH_PECR__OPTLOCK) == 0)
1173 return ERROR_OK;
1174
1175 if ((reg32 & FLASH_PECR__PELOCK) != 0) {
1176
1177 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY1);
1178 if (retval != ERROR_OK)
1179 return retval;
1180
1181 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, PEKEY2);
1182 if (retval != ERROR_OK)
1183 return retval;
1184 }
1185
1186 /* To unlock the PECR write the 2 OPTKEY to the FLASH_OPTKEYR register */
1187 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY1);
1188 if (retval != ERROR_OK)
1189 return retval;
1190
1191 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_OPTKEYR, OPTKEY2);
1192 if (retval != ERROR_OK)
1193 return retval;
1194
1195 return ERROR_OK;
1196 }
1197
1198 static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int timeout)
1199 {
1200 struct target *target = bank->target;
1201 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1202 uint32_t status;
1203 int retval = ERROR_OK;
1204
1205 /* wait for busy to clear */
1206 for (;;) {
1207 retval = stm32lx_get_flash_status(bank, &status);
1208 if (retval != ERROR_OK)
1209 return retval;
1210
1211 LOG_DEBUG("status: 0x%" PRIx32 "", status);
1212 if ((status & FLASH_SR__BSY) == 0)
1213 break;
1214
1215 if (timeout-- <= 0) {
1216 LOG_ERROR("timed out waiting for flash");
1217 return ERROR_FAIL;
1218 }
1219 alive_sleep(1);
1220 }
1221
1222 if (status & FLASH_SR__WRPERR) {
1223 LOG_ERROR("access denied / write protected");
1224 retval = ERROR_FAIL;
1225 }
1226
1227 if (status & FLASH_SR__PGAERR) {
1228 LOG_ERROR("invalid program address");
1229 retval = ERROR_FAIL;
1230 }
1231
1232 /* Clear but report errors */
1233 if (status & FLASH_SR__OPTVERR) {
1234 /* If this operation fails, we ignore it and report the original retval */
1235 target_write_u32(target, stm32lx_info->flash_base + FLASH_SR, status & FLASH_SR__OPTVERR);
1236 }
1237
1238 return retval;
1239 }
1240
1241 static int stm32lx_obl_launch(struct flash_bank *bank)
1242 {
1243 struct target *target = bank->target;
1244 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1245 int retval;
1246
1247 /* This will fail as the target gets immediately rebooted */
1248 target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
1249 FLASH_PECR__OBL_LAUNCH);
1250
1251 size_t tries = 10;
1252 do {
1253 target_halt(target);
1254 retval = target_poll(target);
1255 } while (--tries > 0 &&
1256 (retval != ERROR_OK || target->state != TARGET_HALTED));
1257
1258 return tries ? ERROR_OK : ERROR_FAIL;
1259 }
1260
1261 static int stm32lx_lock(struct flash_bank *bank)
1262 {
1263 int retval;
1264 struct target *target = bank->target;
1265
1266 if (target->state != TARGET_HALTED) {
1267 LOG_ERROR("Target not halted");
1268 return ERROR_TARGET_NOT_HALTED;
1269 }
1270
1271 retval = stm32lx_unlock_options_bytes(bank);
1272 if (retval != ERROR_OK)
1273 return retval;
1274
1275 /* set the RDP protection level to 1 */
1276 retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR1);
1277 if (retval != ERROR_OK)
1278 return retval;
1279
1280 return ERROR_OK;
1281 }
1282
1283 static int stm32lx_unlock(struct flash_bank *bank)
1284 {
1285 int retval;
1286 struct target *target = bank->target;
1287
1288 if (target->state != TARGET_HALTED) {
1289 LOG_ERROR("Target not halted");
1290 return ERROR_TARGET_NOT_HALTED;
1291 }
1292
1293 retval = stm32lx_unlock_options_bytes(bank);
1294 if (retval != ERROR_OK)
1295 return retval;
1296
1297 /* set the RDP protection level to 0 */
1298 retval = target_write_u32(target, OPTION_BYTES_ADDRESS, OPTION_BYTE_0_PR0);
1299 if (retval != ERROR_OK)
1300 return retval;
1301
1302 retval = stm32lx_wait_until_bsy_clear_timeout(bank, 30000);
1303 if (retval != ERROR_OK)
1304 return retval;
1305
1306 return ERROR_OK;
1307 }
1308
1309 static int stm32lx_mass_erase(struct flash_bank *bank)
1310 {
1311 int retval;
1312 struct target *target = bank->target;
1313 struct stm32lx_flash_bank *stm32lx_info = NULL;
1314 uint32_t reg32;
1315
1316 if (target->state != TARGET_HALTED) {
1317 LOG_ERROR("Target not halted");
1318 return ERROR_TARGET_NOT_HALTED;
1319 }
1320
1321 stm32lx_info = bank->driver_priv;
1322
1323 retval = stm32lx_lock(bank);
1324 if (retval != ERROR_OK)
1325 return retval;
1326
1327 retval = stm32lx_obl_launch(bank);
1328 if (retval != ERROR_OK)
1329 return retval;
1330
1331 retval = stm32lx_unlock(bank);
1332 if (retval != ERROR_OK)
1333 return retval;
1334
1335 retval = stm32lx_obl_launch(bank);
1336 if (retval != ERROR_OK)
1337 return retval;
1338
1339 retval = target_read_u32(target, stm32lx_info->flash_base + FLASH_PECR, &reg32);
1340 if (retval != ERROR_OK)
1341 return retval;
1342
1343 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, reg32 | FLASH_PECR__OPTLOCK);
1344 if (retval != ERROR_OK)
1345 return retval;
1346
1347 return ERROR_OK;
1348 }
1349
1350 static int stm32lx_update_part_info(struct flash_bank *bank, uint16_t flash_size_in_kb)
1351 {
1352 struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
1353
1354 switch (stm32lx_info->part_info.id) {
1355 case 0x447: /* STM32L0xx (Cat.5) devices */
1356 if (flash_size_in_kb == 192 || flash_size_in_kb == 128) {
1357 stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
1358 stm32lx_info->part_info.has_dual_banks = true;
1359 }
1360 break;
1361 case 0x437: /* STM32L1xx (Cat.5/Cat.6) */
1362 stm32lx_info->part_info.first_bank_size_kb = flash_size_in_kb / 2;
1363 break;
1364 }
1365
1366 return ERROR_OK;
1367 }
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