Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
flash/stm32l4x: support STM32C0x devices
[openocd.git] / src / flash / nor / stm32l4x.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2015 by Uwe Bonnes *
5 * bon@elektron.ikp.physik.tu-darmstadt.de *
6 * *
7 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
8 * tarek.bouchkati@gmail.com *
9 ***************************************************************************/
10
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14
15 #include "imp.h"
16 #include <helper/align.h>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <target/algorithm.h>
20 #include <target/arm_adi_v5.h>
21 #include <target/cortex_m.h>
22 #include "stm32l4x.h"
23
24 /* STM32L4xxx series for reference.
25 *
26 * RM0351 (STM32L4x5/STM32L4x6)
27 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
28 *
29 * RM0394 (STM32L43x/44x/45x/46x)
30 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
31 *
32 * RM0432 (STM32L4R/4Sxx)
33 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
34 *
35 * STM32L476RG Datasheet (for erase timing)
36 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
37 *
38 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
39 * an option byte is available to map all sectors to the first bank.
40 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
41 * handlers do!
42 *
43 * RM0394 devices have a single bank only.
44 *
45 * RM0432 devices have single and dual bank operating modes.
46 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
47 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
48 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
49 *
50 * Bank mode is controlled by two different bits in option bytes register.
51 * - for STM32L4R/Sxx
52 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
53 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
54 * - for STM32L4P5/Q5x
55 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
56 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
57 */
58
59 /* STM32WBxxx series for reference.
60 *
61 * RM0434 (STM32WB55/WB35x)
62 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
63 *
64 * RM0471 (STM32WB50/WB30x)
65 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
66 *
67 * RM0473 (STM32WB15x)
68 * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
69 *
70 * RM0478 (STM32WB10x)
71 * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
72 */
73
74 /* STM32WLxxx series for reference.
75 *
76 * RM0461 (STM32WLEx)
77 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
78 *
79 * RM0453 (STM32WL5x)
80 * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
81 */
82
83 /* STM32C0xxx series for reference.
84 *
85 * RM0490 (STM32C0x1)
86 * http://www.st.com/resource/en/reference_manual/dm00781702.pdf
87 */
88
89 /* STM32G0xxx series for reference.
90 *
91 * RM0444 (STM32G0x1)
92 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
93 *
94 * RM0454 (STM32G0x0)
95 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
96 */
97
98 /* STM32G4xxx series for reference.
99 *
100 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
101 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
102 *
103 * Cat. 2 devices have single bank only, page size is 2kByte.
104 *
105 * Cat. 3 devices have single and dual bank operating modes,
106 * Page size is 2kByte (dual mode) or 4kByte (single mode).
107 *
108 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
109 * Both banks are treated as a single OpenOCD bank.
110 *
111 * Cat. 4 devices have single bank only, page size is 2kByte.
112 */
113
114 /* STM32L5xxx series for reference.
115 *
116 * RM0428 (STM32L552xx/STM32L562xx)
117 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
118 */
119
120 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
121
122 #define FLASH_ERASE_TIMEOUT 250
123 #define FLASH_WRITE_TIMEOUT 50
124
125
126 /* relevant STM32L4 flags ****************************************************/
127 #define F_NONE 0
128 /* this flag indicates if the device flash is with dual bank architecture */
129 #define F_HAS_DUAL_BANK BIT(0)
130 /* this flags is used for dual bank devices only, it indicates if the
131 * 4 WRPxx are usable if the device is configured in single-bank mode */
132 #define F_USE_ALL_WRPXX BIT(1)
133 /* this flag indicates if the device embeds a TrustZone security feature */
134 #define F_HAS_TZ BIT(2)
135 /* this flag indicates if the device has the same flash registers as STM32L5 */
136 #define F_HAS_L5_FLASH_REGS BIT(3)
137 /* this flag indicates that programming should be done in quad-word
138 * the default programming word size is double-word */
139 #define F_QUAD_WORD_PROG BIT(4)
140 /* end of STM32L4 flags ******************************************************/
141
142
143 enum stm32l4_flash_reg_index {
144 STM32_FLASH_ACR_INDEX,
145 STM32_FLASH_KEYR_INDEX,
146 STM32_FLASH_OPTKEYR_INDEX,
147 STM32_FLASH_SR_INDEX,
148 STM32_FLASH_CR_INDEX,
149 /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
150 * so it uses the C2CR for flash operations and CR for checking locks and locking */
151 STM32_FLASH_CR_WLK_INDEX, /* FLASH_CR_WITH_LOCK */
152 STM32_FLASH_OPTR_INDEX,
153 STM32_FLASH_WRP1AR_INDEX,
154 STM32_FLASH_WRP1BR_INDEX,
155 STM32_FLASH_WRP2AR_INDEX,
156 STM32_FLASH_WRP2BR_INDEX,
157 STM32_FLASH_REG_INDEX_NUM,
158 };
159
160 enum stm32l4_rdp {
161 RDP_LEVEL_0 = 0xAA,
162 RDP_LEVEL_0_5 = 0x55, /* for devices with TrustZone enabled */
163 RDP_LEVEL_1 = 0x00,
164 RDP_LEVEL_2 = 0xCC
165 };
166
167 static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
168 [STM32_FLASH_ACR_INDEX] = 0x000,
169 [STM32_FLASH_KEYR_INDEX] = 0x008,
170 [STM32_FLASH_OPTKEYR_INDEX] = 0x00C,
171 [STM32_FLASH_SR_INDEX] = 0x010,
172 [STM32_FLASH_CR_INDEX] = 0x014,
173 [STM32_FLASH_OPTR_INDEX] = 0x020,
174 [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
175 [STM32_FLASH_WRP1BR_INDEX] = 0x030,
176 [STM32_FLASH_WRP2AR_INDEX] = 0x04C,
177 [STM32_FLASH_WRP2BR_INDEX] = 0x050,
178 };
179
180 static const uint32_t stm32wl_cpu2_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
181 [STM32_FLASH_ACR_INDEX] = 0x000,
182 [STM32_FLASH_KEYR_INDEX] = 0x008,
183 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
184 [STM32_FLASH_SR_INDEX] = 0x060,
185 [STM32_FLASH_CR_INDEX] = 0x064,
186 [STM32_FLASH_CR_WLK_INDEX] = 0x014,
187 [STM32_FLASH_OPTR_INDEX] = 0x020,
188 [STM32_FLASH_WRP1AR_INDEX] = 0x02C,
189 [STM32_FLASH_WRP1BR_INDEX] = 0x030,
190 };
191
192 static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
193 [STM32_FLASH_ACR_INDEX] = 0x000,
194 [STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
195 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
196 [STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
197 [STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
198 [STM32_FLASH_OPTR_INDEX] = 0x040,
199 [STM32_FLASH_WRP1AR_INDEX] = 0x058,
200 [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
201 [STM32_FLASH_WRP2AR_INDEX] = 0x068,
202 [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
203 };
204
205 static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
206 [STM32_FLASH_ACR_INDEX] = 0x000,
207 [STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
208 [STM32_FLASH_OPTKEYR_INDEX] = 0x010,
209 [STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
210 [STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
211 [STM32_FLASH_OPTR_INDEX] = 0x040,
212 [STM32_FLASH_WRP1AR_INDEX] = 0x058,
213 [STM32_FLASH_WRP1BR_INDEX] = 0x05C,
214 [STM32_FLASH_WRP2AR_INDEX] = 0x068,
215 [STM32_FLASH_WRP2BR_INDEX] = 0x06C,
216 };
217
218 struct stm32l4_rev {
219 const uint16_t rev;
220 const char *str;
221 };
222
223 struct stm32l4_part_info {
224 uint16_t id;
225 const char *device_str;
226 const struct stm32l4_rev *revs;
227 const size_t num_revs;
228 const uint16_t max_flash_size_kb;
229 const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
230 const uint32_t flash_regs_base;
231 const uint32_t fsize_addr;
232 const uint32_t otp_base;
233 const uint32_t otp_size;
234 };
235
236 struct stm32l4_flash_bank {
237 bool probed;
238 uint32_t idcode;
239 unsigned int bank1_sectors;
240 bool dual_bank_mode;
241 int hole_sectors;
242 uint32_t user_bank_size;
243 uint32_t data_width;
244 uint32_t cr_bker_mask;
245 uint32_t sr_bsy_mask;
246 uint32_t wrpxxr_mask;
247 const struct stm32l4_part_info *part_info;
248 uint32_t flash_regs_base;
249 const uint32_t *flash_regs;
250 bool otp_enabled;
251 enum stm32l4_rdp rdp;
252 bool tzen;
253 uint32_t optr;
254 };
255
256 enum stm32_bank_id {
257 STM32_BANK1,
258 STM32_BANK2,
259 STM32_ALL_BANKS
260 };
261
262 struct stm32l4_wrp {
263 enum stm32l4_flash_reg_index reg_idx;
264 uint32_t value;
265 bool used;
266 int first;
267 int last;
268 int offset;
269 };
270
271 /* human readable list of families this drivers supports (sorted alphabetically) */
272 static const char *device_families = "STM32C0/G0/G4/L4/L4+/L5/U5/WB/WL";
273
274 static const struct stm32l4_rev stm32l47_l48xx_revs[] = {
275 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
276 };
277
278 static const struct stm32l4_rev stm32l43_l44xx_revs[] = {
279 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
280 };
281
282
283 static const struct stm32l4_rev stm32c01xx_revs[] = {
284 { 0x1000, "A" }, { 0x1001, "Z" },
285 };
286
287 static const struct stm32l4_rev stm32c03xx_revs[] = {
288 { 0x1000, "A" }, { 0x1001, "Z" },
289 };
290
291 static const struct stm32l4_rev stm32g05_g06xx_revs[] = {
292 { 0x1000, "A" },
293 };
294
295 static const struct stm32l4_rev stm32_g07_g08xx_revs[] = {
296 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
297 };
298
299 static const struct stm32l4_rev stm32l49_l4axx_revs[] = {
300 { 0x1000, "A" }, { 0x2000, "B" },
301 };
302
303 static const struct stm32l4_rev stm32l45_l46xx_revs[] = {
304 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
305 };
306
307 static const struct stm32l4_rev stm32l41_l42xx_revs[] = {
308 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
309 };
310
311 static const struct stm32l4_rev stm32g03_g04xx_revs[] = {
312 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
313 };
314
315 static const struct stm32l4_rev stm32g0b_g0cxx_revs[] = {
316 { 0x1000, "A" },
317 };
318
319 static const struct stm32l4_rev stm32g43_g44xx_revs[] = {
320 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
321 };
322
323 static const struct stm32l4_rev stm32g47_g48xx_revs[] = {
324 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
325 };
326
327 static const struct stm32l4_rev stm32l4r_l4sxx_revs[] = {
328 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
329 };
330
331 static const struct stm32l4_rev stm32l4p_l4qxx_revs[] = {
332 { 0x1001, "Z" },
333 };
334
335 static const struct stm32l4_rev stm32l55_l56xx_revs[] = {
336 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
337 };
338
339 static const struct stm32l4_rev stm32g49_g4axx_revs[] = {
340 { 0x1000, "A" },
341 };
342
343 static const struct stm32l4_rev stm32u57_u58xx_revs[] = {
344 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
345 { 0x2001, "X" }, { 0x3000, "C" },
346 };
347
348 static const struct stm32l4_rev stm32wb1xx_revs[] = {
349 { 0x1000, "A" }, { 0x2000, "B" },
350 };
351
352 static const struct stm32l4_rev stm32wb5xx_revs[] = {
353 { 0x2001, "2.1" },
354 };
355
356 static const struct stm32l4_rev stm32wb3xx_revs[] = {
357 { 0x1000, "A" },
358 };
359
360 static const struct stm32l4_rev stm32wle_wl5xx_revs[] = {
361 { 0x1000, "1.0" },
362 };
363
364 static const struct stm32l4_part_info stm32l4_parts[] = {
365 {
366 .id = DEVID_STM32L47_L48XX,
367 .revs = stm32l47_l48xx_revs,
368 .num_revs = ARRAY_SIZE(stm32l47_l48xx_revs),
369 .device_str = "STM32L47/L48xx",
370 .max_flash_size_kb = 1024,
371 .flags = F_HAS_DUAL_BANK,
372 .flash_regs_base = 0x40022000,
373 .fsize_addr = 0x1FFF75E0,
374 .otp_base = 0x1FFF7000,
375 .otp_size = 1024,
376 },
377 {
378 .id = DEVID_STM32L43_L44XX,
379 .revs = stm32l43_l44xx_revs,
380 .num_revs = ARRAY_SIZE(stm32l43_l44xx_revs),
381 .device_str = "STM32L43/L44xx",
382 .max_flash_size_kb = 256,
383 .flags = F_NONE,
384 .flash_regs_base = 0x40022000,
385 .fsize_addr = 0x1FFF75E0,
386 .otp_base = 0x1FFF7000,
387 .otp_size = 1024,
388 },
389 {
390 .id = DEVID_STM32C01XX,
391 .revs = stm32c01xx_revs,
392 .num_revs = ARRAY_SIZE(stm32c01xx_revs),
393 .device_str = "STM32C01xx",
394 .max_flash_size_kb = 32,
395 .flags = F_NONE,
396 .flash_regs_base = 0x40022000,
397 .fsize_addr = 0x1FFF75A0,
398 .otp_base = 0x1FFF7000,
399 .otp_size = 1024,
400 },
401 {
402 .id = DEVID_STM32C03XX,
403 .revs = stm32c03xx_revs,
404 .num_revs = ARRAY_SIZE(stm32c03xx_revs),
405 .device_str = "STM32C03xx",
406 .max_flash_size_kb = 32,
407 .flags = F_NONE,
408 .flash_regs_base = 0x40022000,
409 .fsize_addr = 0x1FFF75A0,
410 .otp_base = 0x1FFF7000,
411 .otp_size = 1024,
412 },
413 {
414 .id = DEVID_STM32G05_G06XX,
415 .revs = stm32g05_g06xx_revs,
416 .num_revs = ARRAY_SIZE(stm32g05_g06xx_revs),
417 .device_str = "STM32G05/G06xx",
418 .max_flash_size_kb = 64,
419 .flags = F_NONE,
420 .flash_regs_base = 0x40022000,
421 .fsize_addr = 0x1FFF75E0,
422 .otp_base = 0x1FFF7000,
423 .otp_size = 1024,
424 },
425 {
426 .id = DEVID_STM32G07_G08XX,
427 .revs = stm32_g07_g08xx_revs,
428 .num_revs = ARRAY_SIZE(stm32_g07_g08xx_revs),
429 .device_str = "STM32G07/G08xx",
430 .max_flash_size_kb = 128,
431 .flags = F_NONE,
432 .flash_regs_base = 0x40022000,
433 .fsize_addr = 0x1FFF75E0,
434 .otp_base = 0x1FFF7000,
435 .otp_size = 1024,
436 },
437 {
438 .id = DEVID_STM32L49_L4AXX,
439 .revs = stm32l49_l4axx_revs,
440 .num_revs = ARRAY_SIZE(stm32l49_l4axx_revs),
441 .device_str = "STM32L49/L4Axx",
442 .max_flash_size_kb = 1024,
443 .flags = F_HAS_DUAL_BANK,
444 .flash_regs_base = 0x40022000,
445 .fsize_addr = 0x1FFF75E0,
446 .otp_base = 0x1FFF7000,
447 .otp_size = 1024,
448 },
449 {
450 .id = DEVID_STM32L45_L46XX,
451 .revs = stm32l45_l46xx_revs,
452 .num_revs = ARRAY_SIZE(stm32l45_l46xx_revs),
453 .device_str = "STM32L45/L46xx",
454 .max_flash_size_kb = 512,
455 .flags = F_NONE,
456 .flash_regs_base = 0x40022000,
457 .fsize_addr = 0x1FFF75E0,
458 .otp_base = 0x1FFF7000,
459 .otp_size = 1024,
460 },
461 {
462 .id = DEVID_STM32L41_L42XX,
463 .revs = stm32l41_l42xx_revs,
464 .num_revs = ARRAY_SIZE(stm32l41_l42xx_revs),
465 .device_str = "STM32L41/L42xx",
466 .max_flash_size_kb = 128,
467 .flags = F_NONE,
468 .flash_regs_base = 0x40022000,
469 .fsize_addr = 0x1FFF75E0,
470 .otp_base = 0x1FFF7000,
471 .otp_size = 1024,
472 },
473 {
474 .id = DEVID_STM32G03_G04XX,
475 .revs = stm32g03_g04xx_revs,
476 .num_revs = ARRAY_SIZE(stm32g03_g04xx_revs),
477 .device_str = "STM32G03x/G04xx",
478 .max_flash_size_kb = 64,
479 .flags = F_NONE,
480 .flash_regs_base = 0x40022000,
481 .fsize_addr = 0x1FFF75E0,
482 .otp_base = 0x1FFF7000,
483 .otp_size = 1024,
484 },
485 {
486 .id = DEVID_STM32G0B_G0CXX,
487 .revs = stm32g0b_g0cxx_revs,
488 .num_revs = ARRAY_SIZE(stm32g0b_g0cxx_revs),
489 .device_str = "STM32G0B/G0Cx",
490 .max_flash_size_kb = 512,
491 .flags = F_HAS_DUAL_BANK,
492 .flash_regs_base = 0x40022000,
493 .fsize_addr = 0x1FFF75E0,
494 .otp_base = 0x1FFF7000,
495 .otp_size = 1024,
496 },
497 {
498 .id = DEVID_STM32G43_G44XX,
499 .revs = stm32g43_g44xx_revs,
500 .num_revs = ARRAY_SIZE(stm32g43_g44xx_revs),
501 .device_str = "STM32G43/G44xx",
502 .max_flash_size_kb = 128,
503 .flags = F_NONE,
504 .flash_regs_base = 0x40022000,
505 .fsize_addr = 0x1FFF75E0,
506 .otp_base = 0x1FFF7000,
507 .otp_size = 1024,
508 },
509 {
510 .id = DEVID_STM32G47_G48XX,
511 .revs = stm32g47_g48xx_revs,
512 .num_revs = ARRAY_SIZE(stm32g47_g48xx_revs),
513 .device_str = "STM32G47/G48xx",
514 .max_flash_size_kb = 512,
515 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
516 .flash_regs_base = 0x40022000,
517 .fsize_addr = 0x1FFF75E0,
518 .otp_base = 0x1FFF7000,
519 .otp_size = 1024,
520 },
521 {
522 .id = DEVID_STM32L4R_L4SXX,
523 .revs = stm32l4r_l4sxx_revs,
524 .num_revs = ARRAY_SIZE(stm32l4r_l4sxx_revs),
525 .device_str = "STM32L4R/L4Sxx",
526 .max_flash_size_kb = 2048,
527 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
528 .flash_regs_base = 0x40022000,
529 .fsize_addr = 0x1FFF75E0,
530 .otp_base = 0x1FFF7000,
531 .otp_size = 1024,
532 },
533 {
534 .id = DEVID_STM32L4P_L4QXX,
535 .revs = stm32l4p_l4qxx_revs,
536 .num_revs = ARRAY_SIZE(stm32l4p_l4qxx_revs),
537 .device_str = "STM32L4P/L4Qxx",
538 .max_flash_size_kb = 1024,
539 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
540 .flash_regs_base = 0x40022000,
541 .fsize_addr = 0x1FFF75E0,
542 .otp_base = 0x1FFF7000,
543 .otp_size = 1024,
544 },
545 {
546 .id = DEVID_STM32L55_L56XX,
547 .revs = stm32l55_l56xx_revs,
548 .num_revs = ARRAY_SIZE(stm32l55_l56xx_revs),
549 .device_str = "STM32L55/L56xx",
550 .max_flash_size_kb = 512,
551 .flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
552 .flash_regs_base = 0x40022000,
553 .fsize_addr = 0x0BFA05E0,
554 .otp_base = 0x0BFA0000,
555 .otp_size = 512,
556 },
557 {
558 .id = DEVID_STM32G49_G4AXX,
559 .revs = stm32g49_g4axx_revs,
560 .num_revs = ARRAY_SIZE(stm32g49_g4axx_revs),
561 .device_str = "STM32G49/G4Axx",
562 .max_flash_size_kb = 512,
563 .flags = F_NONE,
564 .flash_regs_base = 0x40022000,
565 .fsize_addr = 0x1FFF75E0,
566 .otp_base = 0x1FFF7000,
567 .otp_size = 1024,
568 },
569 {
570 .id = DEVID_STM32U57_U58XX,
571 .revs = stm32u57_u58xx_revs,
572 .num_revs = ARRAY_SIZE(stm32u57_u58xx_revs),
573 .device_str = "STM32U57/U58xx",
574 .max_flash_size_kb = 2048,
575 .flags = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
576 .flash_regs_base = 0x40022000,
577 .fsize_addr = 0x0BFA07A0,
578 .otp_base = 0x0BFA0000,
579 .otp_size = 512,
580 },
581 {
582 .id = DEVID_STM32WB1XX,
583 .revs = stm32wb1xx_revs,
584 .num_revs = ARRAY_SIZE(stm32wb1xx_revs),
585 .device_str = "STM32WB1x",
586 .max_flash_size_kb = 320,
587 .flags = F_NONE,
588 .flash_regs_base = 0x58004000,
589 .fsize_addr = 0x1FFF75E0,
590 .otp_base = 0x1FFF7000,
591 .otp_size = 1024,
592 },
593 {
594 .id = DEVID_STM32WB5XX,
595 .revs = stm32wb5xx_revs,
596 .num_revs = ARRAY_SIZE(stm32wb5xx_revs),
597 .device_str = "STM32WB5x",
598 .max_flash_size_kb = 1024,
599 .flags = F_NONE,
600 .flash_regs_base = 0x58004000,
601 .fsize_addr = 0x1FFF75E0,
602 .otp_base = 0x1FFF7000,
603 .otp_size = 1024,
604 },
605 {
606 .id = DEVID_STM32WB3XX,
607 .revs = stm32wb3xx_revs,
608 .num_revs = ARRAY_SIZE(stm32wb3xx_revs),
609 .device_str = "STM32WB3x",
610 .max_flash_size_kb = 512,
611 .flags = F_NONE,
612 .flash_regs_base = 0x58004000,
613 .fsize_addr = 0x1FFF75E0,
614 .otp_base = 0x1FFF7000,
615 .otp_size = 1024,
616 },
617 {
618 .id = DEVID_STM32WLE_WL5XX,
619 .revs = stm32wle_wl5xx_revs,
620 .num_revs = ARRAY_SIZE(stm32wle_wl5xx_revs),
621 .device_str = "STM32WLE/WL5x",
622 .max_flash_size_kb = 256,
623 .flags = F_NONE,
624 .flash_regs_base = 0x58004000,
625 .fsize_addr = 0x1FFF75E0,
626 .otp_base = 0x1FFF7000,
627 .otp_size = 1024,
628 },
629 };
630
631 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
632 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
633 {
634 struct stm32l4_flash_bank *stm32l4_info;
635
636 if (CMD_ARGC < 6)
637 return ERROR_COMMAND_SYNTAX_ERROR;
638
639 /* fix-up bank base address: 0 is used for normal flash memory */
640 if (bank->base == 0)
641 bank->base = STM32_FLASH_BANK_BASE;
642
643 stm32l4_info = calloc(1, sizeof(struct stm32l4_flash_bank));
644 if (!stm32l4_info)
645 return ERROR_FAIL; /* Checkme: What better error to use?*/
646 bank->driver_priv = stm32l4_info;
647
648 stm32l4_info->probed = false;
649 stm32l4_info->otp_enabled = false;
650 stm32l4_info->user_bank_size = bank->size;
651
652 return ERROR_OK;
653 }
654
655 /* bitmap helper extension */
656 struct range {
657 unsigned int start;
658 unsigned int end;
659 };
660
661 static void bitmap_to_ranges(unsigned long *bitmap, unsigned int nbits,
662 struct range *ranges, unsigned int *ranges_count) {
663 *ranges_count = 0;
664 bool last_bit = 0, cur_bit;
665 for (unsigned int i = 0; i < nbits; i++) {
666 cur_bit = test_bit(i, bitmap);
667
668 if (cur_bit && !last_bit) {
669 (*ranges_count)++;
670 ranges[*ranges_count - 1].start = i;
671 ranges[*ranges_count - 1].end = i;
672 } else if (cur_bit && last_bit) {
673 /* update (increment) the end this range */
674 ranges[*ranges_count - 1].end = i;
675 }
676
677 last_bit = cur_bit;
678 }
679 }
680
681 static inline int range_print_one(struct range *range, char *str)
682 {
683 if (range->start == range->end)
684 return sprintf(str, "[%d]", range->start);
685
686 return sprintf(str, "[%d,%d]", range->start, range->end);
687 }
688
689 static char *range_print_alloc(struct range *ranges, unsigned int ranges_count)
690 {
691 /* each range will be printed like the following: [start,end]
692 * start and end, both are unsigned int, an unsigned int takes 10 characters max
693 * plus 3 characters for '[', ',' and ']'
694 * thus means each range can take maximum 23 character
695 * after each range we add a ' ' as separator and finally we need the '\0'
696 * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
697 char *str = calloc(1, ranges_count * (24 * sizeof(char)) + 1);
698 char *ptr = str;
699
700 for (unsigned int i = 0; i < ranges_count; i++) {
701 ptr += range_print_one(&(ranges[i]), ptr);
702
703 if (i < ranges_count - 1)
704 *(ptr++) = ' ';
705 }
706
707 return str;
708 }
709
710 /* end of bitmap helper extension */
711
712 static inline bool stm32l4_is_otp(struct flash_bank *bank)
713 {
714 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
715 return bank->base == stm32l4_info->part_info->otp_base;
716 }
717
718 static int stm32l4_otp_enable(struct flash_bank *bank, bool enable)
719 {
720 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
721
722 if (!stm32l4_is_otp(bank))
723 return ERROR_FAIL;
724
725 char *op_str = enable ? "enabled" : "disabled";
726
727 LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
728 bank->bank_number,
729 stm32l4_info->otp_enabled == enable ? "already " : "",
730 op_str);
731
732 stm32l4_info->otp_enabled = enable;
733
734 return ERROR_OK;
735 }
736
737 static inline bool stm32l4_otp_is_enabled(struct flash_bank *bank)
738 {
739 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
740 return stm32l4_info->otp_enabled;
741 }
742
743 static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
744 {
745 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
746
747 bool tzen = false;
748
749 if (stm32l4_info->part_info->flags & F_HAS_TZ)
750 tzen = (stm32l4_info->optr & FLASH_TZEN) != 0;
751
752 uint32_t rdp = stm32l4_info->optr & FLASH_RDP_MASK;
753
754 /* for devices without TrustZone:
755 * RDP level 0 and 2 values are to 0xAA and 0xCC
756 * Any other value corresponds to RDP level 1
757 * for devices with TrusZone:
758 * RDP level 0 and 2 values are 0xAA and 0xCC
759 * RDP level 0.5 value is 0x55 only if TZEN = 1
760 * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
761 */
762
763 if (rdp != RDP_LEVEL_0 && rdp != RDP_LEVEL_2) {
764 if (!tzen || (tzen && rdp != RDP_LEVEL_0_5))
765 rdp = RDP_LEVEL_1;
766 }
767
768 stm32l4_info->tzen = tzen;
769 stm32l4_info->rdp = rdp;
770 }
771
772 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
773 {
774 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
775 return stm32l4_info->flash_regs_base + reg_offset;
776 }
777
778 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
779 enum stm32l4_flash_reg_index reg_index)
780 {
781 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
782 return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
783 }
784
785 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
786 {
787 return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
788 }
789
790 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank *bank,
791 enum stm32l4_flash_reg_index reg_index, uint32_t *value)
792 {
793 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
794 return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
795 }
796
797 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
798 {
799 return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
800 }
801
802 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank *bank,
803 enum stm32l4_flash_reg_index reg_index, uint32_t value)
804 {
805 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
806 return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
807 }
808
809 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
810 {
811 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
812 uint32_t status;
813 int retval = ERROR_OK;
814
815 /* wait for busy to clear */
816 for (;;) {
817 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
818 if (retval != ERROR_OK)
819 return retval;
820 LOG_DEBUG("status: 0x%" PRIx32 "", status);
821 if ((status & stm32l4_info->sr_bsy_mask) == 0)
822 break;
823 if (timeout-- <= 0) {
824 LOG_ERROR("timed out waiting for flash");
825 return ERROR_FAIL;
826 }
827 alive_sleep(1);
828 }
829
830 if (status & FLASH_WRPERR) {
831 LOG_ERROR("stm32x device protected");
832 retval = ERROR_FAIL;
833 }
834
835 /* Clear but report errors */
836 if (status & FLASH_ERROR) {
837 if (retval == ERROR_OK)
838 retval = ERROR_FAIL;
839 /* If this operation fails, we ignore it and report the original
840 * retval
841 */
842 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status & FLASH_ERROR);
843 }
844
845 return retval;
846 }
847
848 /** set all FLASH_SECBB registers to the same value */
849 static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
850 {
851 /* This function should be used only with device with TrustZone, do just a security check */
852 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
853 assert(stm32l4_info->part_info->flags & F_HAS_TZ);
854
855 /* based on RM0438 Rev6 for STM32L5x devices:
856 * to modify a page block-based security attribution, it is recommended to
857 * 1- check that no flash operation is ongoing on the related page
858 * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
859 * this step is not need in case of JTAG direct access
860 */
861 int retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
862 if (retval != ERROR_OK)
863 return retval;
864
865 /* write SECBBxRy registers */
866 LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
867
868 const uint8_t secbb_regs[] = {
869 FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
870 FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
871 };
872
873
874 unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
875
876 /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
877 * then consider only the first half of secbb_regs
878 */
879 if (!stm32l4_info->dual_bank_mode)
880 num_secbb_regs /= 2;
881
882 for (unsigned int i = 0; i < num_secbb_regs; i++) {
883 retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
884 if (retval != ERROR_OK)
885 return retval;
886 }
887
888 return ERROR_OK;
889 }
890
891 static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank *bank)
892 {
893 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
894 return (stm32l4_info->flash_regs[STM32_FLASH_CR_WLK_INDEX]) ?
895 STM32_FLASH_CR_WLK_INDEX : STM32_FLASH_CR_INDEX;
896 }
897
898 static int stm32l4_unlock_reg(struct flash_bank *bank)
899 {
900 const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
901 uint32_t ctrl;
902
903 /* first check if not already unlocked
904 * otherwise writing on STM32_FLASH_KEYR will fail
905 */
906 int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
907 if (retval != ERROR_OK)
908 return retval;
909
910 if ((ctrl & FLASH_LOCK) == 0)
911 return ERROR_OK;
912
913 /* unlock flash registers */
914 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
915 if (retval != ERROR_OK)
916 return retval;
917
918 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
919 if (retval != ERROR_OK)
920 return retval;
921
922 retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
923 if (retval != ERROR_OK)
924 return retval;
925
926 if (ctrl & FLASH_LOCK) {
927 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
928 return ERROR_TARGET_FAILURE;
929 }
930
931 return ERROR_OK;
932 }
933
934 static int stm32l4_unlock_option_reg(struct flash_bank *bank)
935 {
936 const uint32_t flash_cr_index = stm32l4_get_flash_cr_with_lock_index(bank);
937 uint32_t ctrl;
938
939 int retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
940 if (retval != ERROR_OK)
941 return retval;
942
943 if ((ctrl & FLASH_OPTLOCK) == 0)
944 return ERROR_OK;
945
946 /* unlock option registers */
947 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
948 if (retval != ERROR_OK)
949 return retval;
950
951 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
952 if (retval != ERROR_OK)
953 return retval;
954
955 retval = stm32l4_read_flash_reg_by_index(bank, flash_cr_index, &ctrl);
956 if (retval != ERROR_OK)
957 return retval;
958
959 if (ctrl & FLASH_OPTLOCK) {
960 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
961 return ERROR_TARGET_FAILURE;
962 }
963
964 return ERROR_OK;
965 }
966
967 static int stm32l4_perform_obl_launch(struct flash_bank *bank)
968 {
969 int retval, retval2;
970
971 retval = stm32l4_unlock_reg(bank);
972 if (retval != ERROR_OK)
973 goto err_lock;
974
975 retval = stm32l4_unlock_option_reg(bank);
976 if (retval != ERROR_OK)
977 goto err_lock;
978
979 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
980 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
981 * "Note: If the read protection is set while the debugger is still
982 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
983 */
984
985 /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
986 /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
987 * then just ignore the returned value */
988 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH);
989
990 /* Need to re-probe after change */
991 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
992 stm32l4_info->probed = false;
993
994 err_lock:
995 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
996 FLASH_LOCK | FLASH_OPTLOCK);
997
998 if (retval != ERROR_OK)
999 return retval;
1000
1001 return retval2;
1002 }
1003
1004 static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
1005 uint32_t value, uint32_t mask)
1006 {
1007 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1008 uint32_t optiondata;
1009 int retval, retval2;
1010
1011 retval = stm32l4_read_flash_reg(bank, reg_offset, &optiondata);
1012 if (retval != ERROR_OK)
1013 return retval;
1014
1015 /* for STM32L5 and similar devices, use always non-secure
1016 * registers for option bytes programming */
1017 const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
1018 if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
1019 stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1020
1021 retval = stm32l4_unlock_reg(bank);
1022 if (retval != ERROR_OK)
1023 goto err_lock;
1024
1025 retval = stm32l4_unlock_option_reg(bank);
1026 if (retval != ERROR_OK)
1027 goto err_lock;
1028
1029 optiondata = (optiondata & ~mask) | (value & mask);
1030
1031 retval = stm32l4_write_flash_reg(bank, reg_offset, optiondata);
1032 if (retval != ERROR_OK)
1033 goto err_lock;
1034
1035 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OPTSTRT);
1036 if (retval != ERROR_OK)
1037 goto err_lock;
1038
1039 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1040
1041 err_lock:
1042 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank),
1043 FLASH_LOCK | FLASH_OPTLOCK);
1044 stm32l4_info->flash_regs = saved_flash_regs;
1045
1046 if (retval != ERROR_OK)
1047 return retval;
1048
1049 return retval2;
1050 }
1051
1052 static int stm32l4_get_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy,
1053 enum stm32l4_flash_reg_index reg_idx, int offset)
1054 {
1055 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1056 int ret;
1057
1058 wrpxy->reg_idx = reg_idx;
1059 wrpxy->offset = offset;
1060
1061 ret = stm32l4_read_flash_reg_by_index(bank, wrpxy->reg_idx , &wrpxy->value);
1062 if (ret != ERROR_OK)
1063 return ret;
1064
1065 wrpxy->first = (wrpxy->value & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1066 wrpxy->last = ((wrpxy->value >> 16) & stm32l4_info->wrpxxr_mask) + wrpxy->offset;
1067 wrpxy->used = wrpxy->first <= wrpxy->last;
1068
1069 return ERROR_OK;
1070 }
1071
1072 static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev_bank_id,
1073 struct stm32l4_wrp *wrpxy, unsigned int *n_wrp)
1074 {
1075 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1076 int ret;
1077
1078 *n_wrp = 0;
1079
1080 /* for single bank devices there is 2 WRP regions.
1081 * for dual bank devices there is 2 WRP regions per bank,
1082 * if configured as single bank only 2 WRP are usable
1083 * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1084 * note: this should be revised, if a device will have the SWAP banks option
1085 */
1086
1087 int wrp2y_sectors_offset = -1; /* -1 : unused */
1088
1089 /* if bank_id is BANK1 or ALL_BANKS */
1090 if (dev_bank_id != STM32_BANK2) {
1091 /* get FLASH_WRP1AR */
1092 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1AR_INDEX, 0);
1093 if (ret != ERROR_OK)
1094 return ret;
1095
1096 /* get WRP1BR */
1097 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP1BR_INDEX, 0);
1098 if (ret != ERROR_OK)
1099 return ret;
1100
1101 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1102 if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
1103 wrp2y_sectors_offset = 0;
1104 }
1105
1106 /* if bank_id is BANK2 or ALL_BANKS */
1107 if (dev_bank_id != STM32_BANK1 && stm32l4_info->dual_bank_mode)
1108 wrp2y_sectors_offset = stm32l4_info->bank1_sectors;
1109
1110 if (wrp2y_sectors_offset >= 0) {
1111 /* get WRP2AR */
1112 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2AR_INDEX, wrp2y_sectors_offset);
1113 if (ret != ERROR_OK)
1114 return ret;
1115
1116 /* get WRP2BR */
1117 ret = stm32l4_get_one_wrpxy(bank, &wrpxy[(*n_wrp)++], STM32_FLASH_WRP2BR_INDEX, wrp2y_sectors_offset);
1118 if (ret != ERROR_OK)
1119 return ret;
1120 }
1121
1122 return ERROR_OK;
1123 }
1124
1125 static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy)
1126 {
1127 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1128
1129 int wrp_start = wrpxy->first - wrpxy->offset;
1130 int wrp_end = wrpxy->last - wrpxy->offset;
1131
1132 uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
1133
1134 return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
1135 }
1136
1137 static int stm32l4_write_all_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *wrpxy, unsigned int n_wrp)
1138 {
1139 int ret;
1140
1141 for (unsigned int i = 0; i < n_wrp; i++) {
1142 ret = stm32l4_write_one_wrpxy(bank, &wrpxy[i]);
1143 if (ret != ERROR_OK)
1144 return ret;
1145 }
1146
1147 return ERROR_OK;
1148 }
1149
1150 static int stm32l4_protect_check(struct flash_bank *bank)
1151 {
1152 unsigned int n_wrp;
1153 struct stm32l4_wrp wrpxy[4];
1154
1155 int ret = stm32l4_get_all_wrpxy(bank, STM32_ALL_BANKS, wrpxy, &n_wrp);
1156 if (ret != ERROR_OK)
1157 return ret;
1158
1159 /* initialize all sectors as unprotected */
1160 for (unsigned int i = 0; i < bank->num_sectors; i++)
1161 bank->sectors[i].is_protected = 0;
1162
1163 /* now check WRPxy and mark the protected sectors */
1164 for (unsigned int i = 0; i < n_wrp; i++) {
1165 if (wrpxy[i].used) {
1166 for (int s = wrpxy[i].first; s <= wrpxy[i].last; s++)
1167 bank->sectors[s].is_protected = 1;
1168 }
1169 }
1170
1171 return ERROR_OK;
1172 }
1173
1174 static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
1175 unsigned int last)
1176 {
1177 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1178 int retval, retval2;
1179
1180 assert((first <= last) && (last < bank->num_sectors));
1181
1182 if (stm32l4_is_otp(bank)) {
1183 LOG_ERROR("cannot erase OTP memory");
1184 return ERROR_FLASH_OPER_UNSUPPORTED;
1185 }
1186
1187 if (bank->target->state != TARGET_HALTED) {
1188 LOG_ERROR("Target not halted");
1189 return ERROR_TARGET_NOT_HALTED;
1190 }
1191
1192 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1193 /* set all FLASH pages as secure */
1194 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
1195 if (retval != ERROR_OK) {
1196 /* restore all FLASH pages as non-secure */
1197 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1198 return retval;
1199 }
1200 }
1201
1202 retval = stm32l4_unlock_reg(bank);
1203 if (retval != ERROR_OK)
1204 goto err_lock;
1205
1206 /*
1207 Sector Erase
1208 To erase a sector, follow the procedure below:
1209 1. Check that no Flash memory operation is ongoing by
1210 checking the BSY bit in the FLASH_SR register
1211 2. Set the PER bit and select the page and bank
1212 you wish to erase in the FLASH_CR register
1213 3. Set the STRT bit in the FLASH_CR register
1214 4. Wait for the BSY bit to be cleared
1215 */
1216
1217 for (unsigned int i = first; i <= last; i++) {
1218 uint32_t erase_flags;
1219 erase_flags = FLASH_PER | FLASH_STRT;
1220
1221 if (i >= stm32l4_info->bank1_sectors) {
1222 uint8_t snb;
1223 snb = i - stm32l4_info->bank1_sectors;
1224 erase_flags |= snb << FLASH_PAGE_SHIFT | stm32l4_info->cr_bker_mask;
1225 } else
1226 erase_flags |= i << FLASH_PAGE_SHIFT;
1227 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, erase_flags);
1228 if (retval != ERROR_OK)
1229 break;
1230
1231 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1232 if (retval != ERROR_OK)
1233 break;
1234 }
1235
1236 err_lock:
1237 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
1238
1239 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1240 /* restore all FLASH pages as non-secure */
1241 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
1242 if (retval3 != ERROR_OK)
1243 return retval3;
1244 }
1245
1246 if (retval != ERROR_OK)
1247 return retval;
1248
1249 return retval2;
1250 }
1251
1252 static int stm32l4_protect_same_bank(struct flash_bank *bank, enum stm32_bank_id bank_id, int set,
1253 unsigned int first, unsigned int last)
1254 {
1255 unsigned int i;
1256
1257 /* check if the desired protection is already configured */
1258 for (i = first; i <= last; i++) {
1259 if (bank->sectors[i].is_protected != set)
1260 break;
1261 else if (i == last) {
1262 LOG_INFO("The specified sectors are already %s", set ? "protected" : "unprotected");
1263 return ERROR_OK;
1264 }
1265 }
1266
1267 /* all sectors from first to last (or part of them) could have different
1268 * protection other than the requested */
1269 unsigned int n_wrp;
1270 struct stm32l4_wrp wrpxy[4];
1271
1272 int ret = stm32l4_get_all_wrpxy(bank, bank_id, wrpxy, &n_wrp);
1273 if (ret != ERROR_OK)
1274 return ret;
1275
1276 /* use bitmap and range helpers to optimize the WRP usage */
1277 DECLARE_BITMAP(pages, bank->num_sectors);
1278 bitmap_zero(pages, bank->num_sectors);
1279
1280 for (i = 0; i < n_wrp; i++) {
1281 if (wrpxy[i].used) {
1282 for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
1283 set_bit(p, pages);
1284 }
1285 }
1286
1287 /* we have at most 'n_wrp' WRP areas
1288 * add one range if the user is trying to protect a fifth range */
1289 struct range ranges[n_wrp + 1];
1290 unsigned int ranges_count = 0;
1291
1292 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1293
1294 /* pretty-print the currently protected ranges */
1295 if (ranges_count > 0) {
1296 char *ranges_str = range_print_alloc(ranges, ranges_count);
1297 LOG_DEBUG("current protected areas: %s", ranges_str);
1298 free(ranges_str);
1299 } else
1300 LOG_DEBUG("current protected areas: none");
1301
1302 if (set) { /* flash protect */
1303 for (i = first; i <= last; i++)
1304 set_bit(i, pages);
1305 } else { /* flash unprotect */
1306 for (i = first; i <= last; i++)
1307 clear_bit(i, pages);
1308 }
1309
1310 /* check the ranges_count after the user request */
1311 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
1312
1313 /* pretty-print the requested areas for protection */
1314 if (ranges_count > 0) {
1315 char *ranges_str = range_print_alloc(ranges, ranges_count);
1316 LOG_DEBUG("requested areas for protection: %s", ranges_str);
1317 free(ranges_str);
1318 } else
1319 LOG_DEBUG("requested areas for protection: none");
1320
1321 if (ranges_count > n_wrp) {
1322 LOG_ERROR("cannot set the requested protection "
1323 "(only %u write protection areas are available)" , n_wrp);
1324 return ERROR_FAIL;
1325 }
1326
1327 /* re-init all WRPxy as disabled (first > last)*/
1328 for (i = 0; i < n_wrp; i++) {
1329 wrpxy[i].first = wrpxy[i].offset + 1;
1330 wrpxy[i].last = wrpxy[i].offset;
1331 }
1332
1333 /* then configure WRPxy areas */
1334 for (i = 0; i < ranges_count; i++) {
1335 wrpxy[i].first = ranges[i].start;
1336 wrpxy[i].last = ranges[i].end;
1337 }
1338
1339 /* finally write WRPxy registers */
1340 return stm32l4_write_all_wrpxy(bank, wrpxy, n_wrp);
1341 }
1342
1343 static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
1344 {
1345 struct target *target = bank->target;
1346 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1347
1348 if (stm32l4_is_otp(bank)) {
1349 LOG_ERROR("cannot protect/unprotect OTP memory");
1350 return ERROR_FLASH_OPER_UNSUPPORTED;
1351 }
1352
1353 if (target->state != TARGET_HALTED) {
1354 LOG_ERROR("Target not halted");
1355 return ERROR_TARGET_NOT_HALTED;
1356 }
1357
1358 /* refresh the sectors' protection */
1359 int ret = stm32l4_protect_check(bank);
1360 if (ret != ERROR_OK)
1361 return ret;
1362
1363 /* the requested sectors could be located into bank1 and/or bank2 */
1364 if (last < stm32l4_info->bank1_sectors) {
1365 return stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, last);
1366 } else if (first >= stm32l4_info->bank1_sectors) {
1367 return stm32l4_protect_same_bank(bank, STM32_BANK2, set, first, last);
1368 } else {
1369 ret = stm32l4_protect_same_bank(bank, STM32_BANK1, set, first, stm32l4_info->bank1_sectors - 1);
1370 if (ret != ERROR_OK)
1371 return ret;
1372
1373 return stm32l4_protect_same_bank(bank, STM32_BANK2, set, stm32l4_info->bank1_sectors, last);
1374 }
1375 }
1376
1377 /* count is the size divided by stm32l4_info->data_width */
1378 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
1379 uint32_t offset, uint32_t count)
1380 {
1381 struct target *target = bank->target;
1382 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1383 struct working_area *write_algorithm;
1384 struct working_area *source;
1385 uint32_t address = bank->base + offset;
1386 struct reg_param reg_params[5];
1387 struct armv7m_algorithm armv7m_info;
1388 int retval = ERROR_OK;
1389
1390 static const uint8_t stm32l4_flash_write_code[] = {
1391 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1392 };
1393
1394 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
1395 &write_algorithm) != ERROR_OK) {
1396 LOG_WARNING("no working area available, can't do block memory writes");
1397 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1398 }
1399
1400 retval = target_write_buffer(target, write_algorithm->address,
1401 sizeof(stm32l4_flash_write_code),
1402 stm32l4_flash_write_code);
1403 if (retval != ERROR_OK) {
1404 target_free_working_area(target, write_algorithm);
1405 return retval;
1406 }
1407
1408 /* data_width should be multiple of double-word */
1409 assert(stm32l4_info->data_width % 8 == 0);
1410 const size_t extra_size = sizeof(struct stm32l4_work_area);
1411 uint32_t buffer_size = target_get_working_area_avail(target) - extra_size;
1412 /* buffer_size should be multiple of stm32l4_info->data_width */
1413 buffer_size &= ~(stm32l4_info->data_width - 1);
1414
1415 if (buffer_size < 256) {
1416 LOG_WARNING("large enough working area not available, can't do block memory writes");
1417 target_free_working_area(target, write_algorithm);
1418 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1419 } else if (buffer_size > 16384) {
1420 /* probably won't benefit from more than 16k ... */
1421 buffer_size = 16384;
1422 }
1423
1424 if (target_alloc_working_area_try(target, buffer_size + extra_size, &source) != ERROR_OK) {
1425 LOG_ERROR("allocating working area failed");
1426 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1427 }
1428
1429 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
1430 armv7m_info.core_mode = ARM_MODE_THREAD;
1431
1432 /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1433 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* stm32l4_work_area ptr , status (out) */
1434 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
1435 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
1436 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (of stm32l4_info->data_width) */
1437
1438 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1439 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
1440 buf_set_u32(reg_params[2].value, 0, 32, address);
1441 buf_set_u32(reg_params[3].value, 0, 32, count);
1442
1443 /* write algo stack pointer */
1444 init_reg_param(&reg_params[4], "sp", 32, PARAM_OUT);
1445 buf_set_u32(reg_params[4].value, 0, 32, source->address +
1446 offsetof(struct stm32l4_work_area, stack) + LDR_STACK_SIZE);
1447
1448 struct stm32l4_loader_params loader_extra_params;
1449
1450 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_addr,
1451 stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX));
1452 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_cr_addr,
1453 stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX));
1454 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_word_size,
1455 stm32l4_info->data_width);
1456 target_buffer_set_u32(target, (uint8_t *) &loader_extra_params.flash_sr_bsy_mask,
1457 stm32l4_info->sr_bsy_mask);
1458
1459 retval = target_write_buffer(target, source->address, sizeof(loader_extra_params),
1460 (uint8_t *) &loader_extra_params);
1461 if (retval != ERROR_OK)
1462 return retval;
1463
1464 retval = target_run_flash_async_algorithm(target, buffer, count, stm32l4_info->data_width,
1465 0, NULL,
1466 ARRAY_SIZE(reg_params), reg_params,
1467 source->address + offsetof(struct stm32l4_work_area, fifo),
1468 source->size - offsetof(struct stm32l4_work_area, fifo),
1469 write_algorithm->address, 0,
1470 &armv7m_info);
1471
1472 if (retval == ERROR_FLASH_OPERATION_FAILED) {
1473 LOG_ERROR("error executing stm32l4 flash write algorithm");
1474
1475 uint32_t error;
1476 stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &error);
1477 error &= FLASH_ERROR;
1478
1479 if (error & FLASH_WRPERR)
1480 LOG_ERROR("flash memory write protected");
1481
1482 if (error != 0) {
1483 LOG_ERROR("flash write failed = %08" PRIx32, error);
1484 /* Clear but report errors */
1485 stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, error);
1486 retval = ERROR_FAIL;
1487 }
1488 }
1489
1490 target_free_working_area(target, source);
1491 target_free_working_area(target, write_algorithm);
1492
1493 destroy_reg_param(&reg_params[0]);
1494 destroy_reg_param(&reg_params[1]);
1495 destroy_reg_param(&reg_params[2]);
1496 destroy_reg_param(&reg_params[3]);
1497 destroy_reg_param(&reg_params[4]);
1498
1499 return retval;
1500 }
1501
1502 /* count is the size divided by stm32l4_info->data_width */
1503 static int stm32l4_write_block_without_loader(struct flash_bank *bank, const uint8_t *buffer,
1504 uint32_t offset, uint32_t count)
1505 {
1506 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1507 struct target *target = bank->target;
1508 uint32_t address = bank->base + offset;
1509 int retval = ERROR_OK;
1510
1511 /* wait for BSY bit */
1512 retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
1513 if (retval != ERROR_OK)
1514 return retval;
1515
1516 /* set PG in FLASH_CR */
1517 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_PG);
1518 if (retval != ERROR_OK)
1519 return retval;
1520
1521
1522 /* write directly to flash memory */
1523 const uint8_t *src = buffer;
1524 const uint32_t data_width_in_words = stm32l4_info->data_width / 4;
1525 while (count--) {
1526 retval = target_write_memory(target, address, 4, data_width_in_words, src);
1527 if (retval != ERROR_OK)
1528 return retval;
1529
1530 /* wait for BSY bit */
1531 retval = stm32l4_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
1532 if (retval != ERROR_OK)
1533 return retval;
1534
1535 src += stm32l4_info->data_width;
1536 address += stm32l4_info->data_width;
1537 }
1538
1539 /* reset PG in FLASH_CR */
1540 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, 0);
1541 if (retval != ERROR_OK)
1542 return retval;
1543
1544 return retval;
1545 }
1546
1547 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
1548 uint32_t offset, uint32_t count)
1549 {
1550 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1551 int retval = ERROR_OK, retval2;
1552
1553 if (stm32l4_is_otp(bank) && !stm32l4_otp_is_enabled(bank)) {
1554 LOG_ERROR("OTP memory is disabled for write commands");
1555 return ERROR_FAIL;
1556 }
1557
1558 if (bank->target->state != TARGET_HALTED) {
1559 LOG_ERROR("Target not halted");
1560 return ERROR_TARGET_NOT_HALTED;
1561 }
1562
1563 /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1564 assert(stm32l4_info->data_width % 8 == 0);
1565
1566 /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1567 * The flash infrastructure ensures it, do just a security check */
1568 assert(offset % stm32l4_info->data_width == 0);
1569 assert(count % stm32l4_info->data_width == 0);
1570
1571 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1572 * data to be written does not go into a gap:
1573 * suppose buffer is fully contained in bank from sector 0 to sector
1574 * num->sectors - 1 and sectors are ordered according to offset
1575 */
1576 struct flash_sector *head = &bank->sectors[0];
1577 struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
1578
1579 while ((head < tail) && (offset >= (head + 1)->offset)) {
1580 /* buffer does not intersect head nor gap behind head */
1581 head++;
1582 }
1583
1584 while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
1585 /* buffer does not intersect tail nor gap before tail */
1586 --tail;
1587 }
1588
1589 LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
1590 offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
1591
1592 /* Now check that there is no gap from head to tail, this should work
1593 * even for multiple or non-symmetric gaps
1594 */
1595 while (head < tail) {
1596 if (head->offset + head->size != (head + 1)->offset) {
1597 LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
1598 bank->base + head->offset + head->size,
1599 bank->base + (head + 1)->offset - 1);
1600 retval = ERROR_FLASH_DST_OUT_OF_BANK;
1601 }
1602 head++;
1603 }
1604
1605 if (retval != ERROR_OK)
1606 return retval;
1607
1608 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1609 /* set all FLASH pages as secure */
1610 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
1611 if (retval != ERROR_OK) {
1612 /* restore all FLASH pages as non-secure */
1613 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
1614 return retval;
1615 }
1616 }
1617
1618 retval = stm32l4_unlock_reg(bank);
1619 if (retval != ERROR_OK)
1620 goto err_lock;
1621
1622
1623 /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1624 * the debug is possible only in non-secure state.
1625 * Thus means the flashloader will run in non-secure mode,
1626 * and the workarea need to be in non-secure RAM */
1627 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0_5))
1628 LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1629
1630 /* first try to write using the loader, for better performance */
1631 retval = stm32l4_write_block(bank, buffer, offset,
1632 count / stm32l4_info->data_width);
1633
1634 /* if resources are not available write without a loader */
1635 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1636 LOG_WARNING("falling back to programming without a flash loader (slower)");
1637 retval = stm32l4_write_block_without_loader(bank, buffer, offset,
1638 count / stm32l4_info->data_width);
1639 }
1640
1641 err_lock:
1642 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
1643
1644 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1645 /* restore all FLASH pages as non-secure */
1646 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
1647 if (retval3 != ERROR_OK)
1648 return retval3;
1649 }
1650
1651 if (retval != ERROR_OK) {
1652 LOG_ERROR("block write failed");
1653 return retval;
1654 }
1655 return retval2;
1656 }
1657
1658 static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
1659 {
1660 int retval = ERROR_OK;
1661 struct target *target = bank->target;
1662
1663 /* try reading possible IDCODE registers, in the following order */
1664 uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
1665
1666 for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
1667 retval = target_read_u32(target, dbgmcu_idcode[i], id);
1668 if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
1669 return ERROR_OK;
1670 }
1671
1672 /* Workaround for STM32WL5x devices:
1673 * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1674 * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1675
1676 struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1677 if (!armv7m) {
1678 LOG_ERROR("Flash requires Cortex-M target");
1679 return ERROR_TARGET_INVALID;
1680 }
1681
1682 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1683 * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1684 if (cortex_m_get_partno_safe(target) == CORTEX_M0P_PARTNO &&
1685 armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
1686 uint32_t uid64_ids;
1687
1688 /* UID64 is contains
1689 * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1690 * - Bits 31:08 : STID (company ID) = 0x0080E1
1691 * - Bits 07:00 : DEVID (device ID) = 0x15
1692 *
1693 * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1694 */
1695 retval = target_read_u32(target, UID64_IDS, &uid64_ids);
1696 if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
1697 /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1698 *id = DEVID_STM32WLE_WL5XX;
1699 return ERROR_OK;
1700 }
1701 }
1702
1703 LOG_ERROR("can't get the device id");
1704 return (retval == ERROR_OK) ? ERROR_FAIL : retval;
1705 }
1706
1707 static const char *get_stm32l4_rev_str(struct flash_bank *bank)
1708 {
1709 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1710 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
1711 assert(part_info);
1712
1713 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1714 for (unsigned int i = 0; i < part_info->num_revs; i++) {
1715 if (rev_id == part_info->revs[i].rev)
1716 return part_info->revs[i].str;
1717 }
1718 return "'unknown'";
1719 }
1720
1721 static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
1722 {
1723 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1724 assert(stm32l4_info->part_info);
1725 return stm32l4_is_otp(bank) ? "OTP" :
1726 stm32l4_info->dual_bank_mode ? "Flash dual" :
1727 "Flash single";
1728 }
1729
1730 static int stm32l4_probe(struct flash_bank *bank)
1731 {
1732 struct target *target = bank->target;
1733 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
1734 const struct stm32l4_part_info *part_info;
1735 uint16_t flash_size_kb = 0xffff;
1736
1737 if (!target_was_examined(target)) {
1738 LOG_ERROR("Target not examined yet");
1739 return ERROR_TARGET_NOT_EXAMINED;
1740 }
1741
1742 struct armv7m_common *armv7m = target_to_armv7m_safe(target);
1743 if (!armv7m) {
1744 LOG_ERROR("Flash requires Cortex-M target");
1745 return ERROR_TARGET_INVALID;
1746 }
1747
1748 stm32l4_info->probed = false;
1749
1750 /* read stm32 device id registers */
1751 int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
1752 if (retval != ERROR_OK)
1753 return retval;
1754
1755 const uint32_t device_id = stm32l4_info->idcode & 0xFFF;
1756
1757 for (unsigned int n = 0; n < ARRAY_SIZE(stm32l4_parts); n++) {
1758 if (device_id == stm32l4_parts[n].id) {
1759 stm32l4_info->part_info = &stm32l4_parts[n];
1760 break;
1761 }
1762 }
1763
1764 if (!stm32l4_info->part_info) {
1765 LOG_WARNING("Cannot identify target as an %s family device.", device_families);
1766 return ERROR_FAIL;
1767 }
1768
1769 part_info = stm32l4_info->part_info;
1770 const char *rev_str = get_stm32l4_rev_str(bank);
1771 const uint16_t rev_id = stm32l4_info->idcode >> 16;
1772
1773 LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
1774 stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
1775
1776 stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
1777 stm32l4_info->data_width = (part_info->flags & F_QUAD_WORD_PROG) ? 16 : 8;
1778 stm32l4_info->cr_bker_mask = FLASH_BKER;
1779 stm32l4_info->sr_bsy_mask = FLASH_BSY;
1780
1781 /* Set flash write alignment boundaries.
1782 * Ask the flash infrastructure to ensure required alignment */
1783 bank->write_start_alignment = stm32l4_info->data_width;
1784 bank->write_end_alignment = stm32l4_info->data_width;
1785
1786 /* Initialize the flash registers layout */
1787 if (part_info->flags & F_HAS_L5_FLASH_REGS)
1788 stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
1789 else
1790 stm32l4_info->flash_regs = stm32l4_flash_regs;
1791
1792 /* read flash option register */
1793 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
1794 if (retval != ERROR_OK)
1795 return retval;
1796
1797 stm32l4_sync_rdp_tzen(bank);
1798
1799 /* for devices with TrustZone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1800 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
1801 if (part_info->flags & F_HAS_L5_FLASH_REGS) {
1802 stm32l4_info->flash_regs_base |= STM32L5_REGS_SEC_OFFSET;
1803 stm32l4_info->flash_regs = stm32l5_s_flash_regs;
1804 } else {
1805 LOG_ERROR("BUG: device supported incomplete");
1806 return ERROR_NOT_IMPLEMENTED;
1807 }
1808 }
1809
1810 if (part_info->flags & F_HAS_TZ)
1811 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1812 stm32l4_info->tzen,
1813 stm32l4_info->tzen ? "enabled" : "disabled");
1814
1815 LOG_INFO("RDP level %s (0x%02X)",
1816 stm32l4_info->rdp == RDP_LEVEL_0 ? "0" : stm32l4_info->rdp == RDP_LEVEL_0_5 ? "0.5" : "1",
1817 stm32l4_info->rdp);
1818
1819 if (stm32l4_is_otp(bank)) {
1820 bank->size = part_info->otp_size;
1821
1822 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT, bank->size, bank->base);
1823
1824 /* OTP memory is considered as one sector */
1825 free(bank->sectors);
1826 bank->num_sectors = 1;
1827 bank->sectors = alloc_block_array(0, part_info->otp_size, 1);
1828
1829 if (!bank->sectors) {
1830 LOG_ERROR("failed to allocate bank sectors");
1831 return ERROR_FAIL;
1832 }
1833
1834 stm32l4_info->probed = true;
1835 return ERROR_OK;
1836 } else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
1837 LOG_ERROR("invalid bank base address");
1838 return ERROR_FAIL;
1839 }
1840
1841 /* get flash size from target. */
1842 retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
1843
1844 /* failed reading flash size or flash size invalid (early silicon),
1845 * default to max target family */
1846 if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
1847 || flash_size_kb > part_info->max_flash_size_kb) {
1848 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1849 part_info->max_flash_size_kb);
1850 flash_size_kb = part_info->max_flash_size_kb;
1851 }
1852
1853 /* if the user sets the size manually then ignore the probed value
1854 * this allows us to work around devices that have a invalid flash size register value */
1855 if (stm32l4_info->user_bank_size) {
1856 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1857 flash_size_kb = stm32l4_info->user_bank_size / 1024;
1858 }
1859
1860 LOG_INFO("flash size = %d KiB", flash_size_kb);
1861
1862 /* did we assign a flash size? */
1863 assert((flash_size_kb != 0xffff) && flash_size_kb);
1864
1865 const bool is_max_flash_size = flash_size_kb == stm32l4_info->part_info->max_flash_size_kb;
1866
1867 stm32l4_info->bank1_sectors = 0;
1868 stm32l4_info->hole_sectors = 0;
1869
1870 int num_pages = 0;
1871 int page_size_kb = 0;
1872
1873 stm32l4_info->dual_bank_mode = false;
1874
1875 switch (device_id) {
1876 case DEVID_STM32L47_L48XX:
1877 case DEVID_STM32L49_L4AXX:
1878 /* if flash size is max (1M) the device is always dual bank
1879 * STM32L47/L48xx: has variants with 512K
1880 * STM32L49/L4Axx: has variants with 512 and 256
1881 * for these variants:
1882 * if DUAL_BANK = 0 -> single bank
1883 * else -> dual bank without gap
1884 * note: the page size is invariant
1885 */
1886 page_size_kb = 2;
1887 num_pages = flash_size_kb / page_size_kb;
1888 stm32l4_info->bank1_sectors = num_pages;
1889
1890 /* check DUAL_BANK option bit if the flash is less than 1M */
1891 if (is_max_flash_size || (stm32l4_info->optr & FLASH_L4_DUAL_BANK)) {
1892 stm32l4_info->dual_bank_mode = true;
1893 stm32l4_info->bank1_sectors = num_pages / 2;
1894 }
1895 break;
1896 case DEVID_STM32L43_L44XX:
1897 case DEVID_STM32C01XX:
1898 case DEVID_STM32C03XX:
1899 case DEVID_STM32G05_G06XX:
1900 case DEVID_STM32G07_G08XX:
1901 case DEVID_STM32L45_L46XX:
1902 case DEVID_STM32L41_L42XX:
1903 case DEVID_STM32G03_G04XX:
1904 case DEVID_STM32G43_G44XX:
1905 case DEVID_STM32G49_G4AXX:
1906 case DEVID_STM32WB1XX:
1907 /* single bank flash */
1908 page_size_kb = 2;
1909 num_pages = flash_size_kb / page_size_kb;
1910 stm32l4_info->bank1_sectors = num_pages;
1911 break;
1912 case DEVID_STM32G0B_G0CXX:
1913 /* single/dual bank depending on DUAL_BANK option bit */
1914 page_size_kb = 2;
1915 num_pages = flash_size_kb / page_size_kb;
1916 stm32l4_info->bank1_sectors = num_pages;
1917 stm32l4_info->cr_bker_mask = FLASH_BKER_G0;
1918
1919 /* check DUAL_BANK bit */
1920 if (stm32l4_info->optr & FLASH_G0_DUAL_BANK) {
1921 stm32l4_info->sr_bsy_mask = FLASH_BSY | FLASH_BSY2;
1922 stm32l4_info->dual_bank_mode = true;
1923 stm32l4_info->bank1_sectors = num_pages / 2;
1924 }
1925 break;
1926 case DEVID_STM32G47_G48XX:
1927 /* STM32G47/8 can be single/dual bank:
1928 * if DUAL_BANK = 0 -> single bank
1929 * else -> dual bank WITH gap
1930 */
1931 page_size_kb = 4;
1932 num_pages = flash_size_kb / page_size_kb;
1933 stm32l4_info->bank1_sectors = num_pages;
1934 if (stm32l4_info->optr & FLASH_G4_DUAL_BANK) {
1935 stm32l4_info->dual_bank_mode = true;
1936 page_size_kb = 2;
1937 num_pages = flash_size_kb / page_size_kb;
1938 stm32l4_info->bank1_sectors = num_pages / 2;
1939
1940 /* for devices with trimmed flash, there is a gap between both banks */
1941 stm32l4_info->hole_sectors =
1942 (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
1943 }
1944 break;
1945 case DEVID_STM32L4R_L4SXX:
1946 case DEVID_STM32L4P_L4QXX:
1947 /* STM32L4R/S can be single/dual bank:
1948 * if size = 2M check DBANK bit
1949 * if size = 1M check DB1M bit
1950 * STM32L4P/Q can be single/dual bank
1951 * if size = 1M check DBANK bit
1952 * if size = 512K check DB512K bit (same as DB1M bit)
1953 */
1954 page_size_kb = 8;
1955 num_pages = flash_size_kb / page_size_kb;
1956 stm32l4_info->bank1_sectors = num_pages;
1957 if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L4R_DBANK)) ||
1958 (!is_max_flash_size && (stm32l4_info->optr & FLASH_LRR_DB1M))) {
1959 stm32l4_info->dual_bank_mode = true;
1960 page_size_kb = 4;
1961 num_pages = flash_size_kb / page_size_kb;
1962 stm32l4_info->bank1_sectors = num_pages / 2;
1963 }
1964 break;
1965 case DEVID_STM32L55_L56XX:
1966 /* STM32L55/L56xx can be single/dual bank:
1967 * if size = 512K check DBANK bit
1968 * if size = 256K check DB256K bit
1969 *
1970 * default page size is 4kb, if DBANK = 1, the page size is 2kb.
1971 */
1972
1973 page_size_kb = (stm32l4_info->optr & FLASH_L5_DBANK) ? 2 : 4;
1974 num_pages = flash_size_kb / page_size_kb;
1975 stm32l4_info->bank1_sectors = num_pages;
1976
1977 if ((is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DBANK)) ||
1978 (!is_max_flash_size && (stm32l4_info->optr & FLASH_L5_DB256))) {
1979 stm32l4_info->dual_bank_mode = true;
1980 stm32l4_info->bank1_sectors = num_pages / 2;
1981 }
1982 break;
1983 case DEVID_STM32U57_U58XX:
1984 /* if flash size is max (2M) the device is always dual bank
1985 * otherwise check DUALBANK
1986 */
1987 page_size_kb = 8;
1988 num_pages = flash_size_kb / page_size_kb;
1989 stm32l4_info->bank1_sectors = num_pages;
1990 if (is_max_flash_size || (stm32l4_info->optr & FLASH_U5_DUALBANK)) {
1991 stm32l4_info->dual_bank_mode = true;
1992 stm32l4_info->bank1_sectors = num_pages / 2;
1993 }
1994 break;
1995 case DEVID_STM32WB5XX:
1996 case DEVID_STM32WB3XX:
1997 /* single bank flash */
1998 page_size_kb = 4;
1999 num_pages = flash_size_kb / page_size_kb;
2000 stm32l4_info->bank1_sectors = num_pages;
2001 break;
2002 case DEVID_STM32WLE_WL5XX:
2003 /* single bank flash */
2004 page_size_kb = 2;
2005 num_pages = flash_size_kb / page_size_kb;
2006 stm32l4_info->bank1_sectors = num_pages;
2007
2008 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
2009 * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
2010 if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)
2011 stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
2012 break;
2013 default:
2014 LOG_ERROR("unsupported device");
2015 return ERROR_FAIL;
2016 }
2017
2018 /* ensure that at least there is 1 flash sector / page */
2019 if (num_pages == 0) {
2020 if (stm32l4_info->user_bank_size)
2021 LOG_ERROR("The specified flash size is less than page size");
2022
2023 LOG_ERROR("Flash pages count cannot be zero");
2024 return ERROR_FAIL;
2025 }
2026
2027 LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
2028
2029 const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
2030
2031 if (gap_size_kb != 0) {
2032 LOG_INFO("gap detected from 0x%08x to 0x%08x",
2033 STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
2034 * page_size_kb * 1024,
2035 STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
2036 * page_size_kb + gap_size_kb) * 1024 - 1);
2037 }
2038
2039 /* number of significant bits in WRPxxR differs per device,
2040 * always right adjusted, on some devices non-implemented
2041 * bits read as '0', on others as '1' ...
2042 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
2043 */
2044
2045 /* use *max_flash_size* instead of actual size as the trimmed versions
2046 * certainly use the same number of bits
2047 */
2048 uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
2049
2050 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
2051 stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
2052 assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
2053 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
2054
2055 free(bank->sectors);
2056
2057 bank->size = (flash_size_kb + gap_size_kb) * 1024;
2058 bank->num_sectors = num_pages;
2059 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
2060 if (!bank->sectors) {
2061 LOG_ERROR("failed to allocate bank sectors");
2062 return ERROR_FAIL;
2063 }
2064
2065 for (unsigned int i = 0; i < bank->num_sectors; i++) {
2066 bank->sectors[i].offset = i * page_size_kb * 1024;
2067 /* in dual bank configuration, if there is a gap between banks
2068 * we fix up the sector offset to consider this gap */
2069 if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
2070 bank->sectors[i].offset += gap_size_kb * 1024;
2071 bank->sectors[i].size = page_size_kb * 1024;
2072 bank->sectors[i].is_erased = -1;
2073 bank->sectors[i].is_protected = 1;
2074 }
2075
2076 stm32l4_info->probed = true;
2077 return ERROR_OK;
2078 }
2079
2080 static int stm32l4_auto_probe(struct flash_bank *bank)
2081 {
2082 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2083 if (stm32l4_info->probed) {
2084 uint32_t optr_cur;
2085
2086 /* save flash_regs_base */
2087 uint32_t saved_flash_regs_base = stm32l4_info->flash_regs_base;
2088
2089 /* for devices with TrustZone, use NS flash registers to read OPTR */
2090 if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
2091 stm32l4_info->flash_regs_base &= ~STM32L5_REGS_SEC_OFFSET;
2092
2093 /* read flash option register and re-probe if optr value is changed */
2094 int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &optr_cur);
2095
2096 /* restore saved flash_regs_base */
2097 stm32l4_info->flash_regs_base = saved_flash_regs_base;
2098
2099 if (retval != ERROR_OK)
2100 return retval;
2101
2102 if (stm32l4_info->optr == optr_cur)
2103 return ERROR_OK;
2104 }
2105
2106 return stm32l4_probe(bank);
2107 }
2108
2109 static int get_stm32l4_info(struct flash_bank *bank, struct command_invocation *cmd)
2110 {
2111 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2112 const struct stm32l4_part_info *part_info = stm32l4_info->part_info;
2113
2114 if (part_info) {
2115 const uint16_t rev_id = stm32l4_info->idcode >> 16;
2116 command_print_sameline(cmd, "%s - Rev %s : 0x%04x", part_info->device_str,
2117 get_stm32l4_rev_str(bank), rev_id);
2118 if (stm32l4_info->probed)
2119 command_print_sameline(cmd, " - %s-bank", get_stm32l4_bank_type_str(bank));
2120 } else {
2121 command_print_sameline(cmd, "Cannot identify target as an %s device", device_families);
2122 }
2123
2124 return ERROR_OK;
2125 }
2126
2127 static int stm32l4_mass_erase(struct flash_bank *bank)
2128 {
2129 int retval, retval2;
2130 struct target *target = bank->target;
2131 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2132
2133 if (stm32l4_is_otp(bank)) {
2134 LOG_ERROR("cannot erase OTP memory");
2135 return ERROR_FLASH_OPER_UNSUPPORTED;
2136 }
2137
2138 uint32_t action = FLASH_MER1;
2139
2140 if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
2141 action |= FLASH_MER2;
2142
2143 if (target->state != TARGET_HALTED) {
2144 LOG_ERROR("Target not halted");
2145 return ERROR_TARGET_NOT_HALTED;
2146 }
2147
2148 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2149 /* set all FLASH pages as secure */
2150 retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
2151 if (retval != ERROR_OK) {
2152 /* restore all FLASH pages as non-secure */
2153 stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
2154 return retval;
2155 }
2156 }
2157
2158 retval = stm32l4_unlock_reg(bank);
2159 if (retval != ERROR_OK)
2160 goto err_lock;
2161
2162 /* mass erase flash memory */
2163 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT / 10);
2164 if (retval != ERROR_OK)
2165 goto err_lock;
2166
2167 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action);
2168 if (retval != ERROR_OK)
2169 goto err_lock;
2170
2171 retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action | FLASH_STRT);
2172 if (retval != ERROR_OK)
2173 goto err_lock;
2174
2175 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
2176
2177 err_lock:
2178 retval2 = stm32l4_write_flash_reg_by_index(bank, stm32l4_get_flash_cr_with_lock_index(bank), FLASH_LOCK);
2179
2180 if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
2181 /* restore all FLASH pages as non-secure */
2182 int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
2183 if (retval3 != ERROR_OK)
2184 return retval3;
2185 }
2186
2187 if (retval != ERROR_OK)
2188 return retval;
2189
2190 return retval2;
2191 }
2192
2193 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
2194 {
2195 if (CMD_ARGC < 1) {
2196 command_print(CMD, "stm32l4x mass_erase <STM32L4 bank>");
2197 return ERROR_COMMAND_SYNTAX_ERROR;
2198 }
2199
2200 struct flash_bank *bank;
2201 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2202 if (retval != ERROR_OK)
2203 return retval;
2204
2205 retval = stm32l4_mass_erase(bank);
2206 if (retval == ERROR_OK)
2207 command_print(CMD, "stm32l4x mass erase complete");
2208 else
2209 command_print(CMD, "stm32l4x mass erase failed");
2210
2211 return retval;
2212 }
2213
2214 COMMAND_HANDLER(stm32l4_handle_option_read_command)
2215 {
2216 if (CMD_ARGC < 2) {
2217 command_print(CMD, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
2218 return ERROR_COMMAND_SYNTAX_ERROR;
2219 }
2220
2221 struct flash_bank *bank;
2222 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2223 if (retval != ERROR_OK)
2224 return retval;
2225
2226 uint32_t reg_offset, reg_addr;
2227 uint32_t value = 0;
2228
2229 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2230 reg_addr = stm32l4_get_flash_reg(bank, reg_offset);
2231
2232 retval = stm32l4_read_flash_reg(bank, reg_offset, &value);
2233 if (retval != ERROR_OK)
2234 return retval;
2235
2236 command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
2237
2238 return retval;
2239 }
2240
2241 COMMAND_HANDLER(stm32l4_handle_option_write_command)
2242 {
2243 if (CMD_ARGC < 3) {
2244 command_print(CMD, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
2245 return ERROR_COMMAND_SYNTAX_ERROR;
2246 }
2247
2248 struct flash_bank *bank;
2249 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2250 if (retval != ERROR_OK)
2251 return retval;
2252
2253 uint32_t reg_offset;
2254 uint32_t value = 0;
2255 uint32_t mask = 0xFFFFFFFF;
2256
2257 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg_offset);
2258 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
2259
2260 if (CMD_ARGC > 3)
2261 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], mask);
2262
2263 command_print(CMD, "%s Option written.\n"
2264 "INFO: a reset or power cycle is required "
2265 "for the new settings to take effect.", bank->driver->name);
2266
2267 retval = stm32l4_write_option(bank, reg_offset, value, mask);
2268 return retval;
2269 }
2270
2271 COMMAND_HANDLER(stm32l4_handle_trustzone_command)
2272 {
2273 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2274 return ERROR_COMMAND_SYNTAX_ERROR;
2275
2276 struct flash_bank *bank;
2277 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2278 if (retval != ERROR_OK)
2279 return retval;
2280
2281 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2282 if (!(stm32l4_info->part_info->flags & F_HAS_TZ)) {
2283 LOG_ERROR("This device does not have a TrustZone");
2284 return ERROR_FAIL;
2285 }
2286
2287 retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &stm32l4_info->optr);
2288 if (retval != ERROR_OK)
2289 return retval;
2290
2291 stm32l4_sync_rdp_tzen(bank);
2292
2293 if (CMD_ARGC == 1) {
2294 /* only display the TZEN value */
2295 LOG_INFO("Global TrustZone Security is %s", stm32l4_info->tzen ? "enabled" : "disabled");
2296 return ERROR_OK;
2297 }
2298
2299 bool new_tzen;
2300 COMMAND_PARSE_ENABLE(CMD_ARGV[1], new_tzen);
2301
2302 if (new_tzen == stm32l4_info->tzen) {
2303 LOG_INFO("The requested TZEN is already programmed");
2304 return ERROR_OK;
2305 }
2306
2307 if (new_tzen) {
2308 if (stm32l4_info->rdp != RDP_LEVEL_0) {
2309 LOG_ERROR("TZEN can be set only when RDP level is 0");
2310 return ERROR_FAIL;
2311 }
2312 retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2313 FLASH_TZEN, FLASH_TZEN);
2314 } else {
2315 /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2316 * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2317 if (stm32l4_info->rdp != RDP_LEVEL_1 && stm32l4_info->rdp != RDP_LEVEL_0_5) {
2318 LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2319 return ERROR_FAIL;
2320 }
2321
2322 retval = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2323 RDP_LEVEL_0, FLASH_RDP_MASK | FLASH_TZEN);
2324 }
2325
2326 if (retval != ERROR_OK)
2327 return retval;
2328
2329 return stm32l4_perform_obl_launch(bank);
2330 }
2331
2332 COMMAND_HANDLER(stm32l4_handle_option_load_command)
2333 {
2334 if (CMD_ARGC != 1)
2335 return ERROR_COMMAND_SYNTAX_ERROR;
2336
2337 struct flash_bank *bank;
2338 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2339 if (retval != ERROR_OK)
2340 return retval;
2341
2342 retval = stm32l4_perform_obl_launch(bank);
2343 if (retval != ERROR_OK) {
2344 command_print(CMD, "stm32l4x option load failed");
2345 return retval;
2346 }
2347
2348
2349 command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
2350
2351 return ERROR_OK;
2352 }
2353
2354 COMMAND_HANDLER(stm32l4_handle_lock_command)
2355 {
2356 struct target *target = NULL;
2357
2358 if (CMD_ARGC < 1)
2359 return ERROR_COMMAND_SYNTAX_ERROR;
2360
2361 struct flash_bank *bank;
2362 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2363 if (retval != ERROR_OK)
2364 return retval;
2365
2366 if (stm32l4_is_otp(bank)) {
2367 LOG_ERROR("cannot lock/unlock OTP memory");
2368 return ERROR_FLASH_OPER_UNSUPPORTED;
2369 }
2370
2371 target = bank->target;
2372
2373 if (target->state != TARGET_HALTED) {
2374 LOG_ERROR("Target not halted");
2375 return ERROR_TARGET_NOT_HALTED;
2376 }
2377
2378 /* set readout protection level 1 by erasing the RDP option byte */
2379 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2380 if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2381 RDP_LEVEL_1, FLASH_RDP_MASK) != ERROR_OK) {
2382 command_print(CMD, "%s failed to lock device", bank->driver->name);
2383 return ERROR_OK;
2384 }
2385
2386 return ERROR_OK;
2387 }
2388
2389 COMMAND_HANDLER(stm32l4_handle_unlock_command)
2390 {
2391 struct target *target = NULL;
2392
2393 if (CMD_ARGC < 1)
2394 return ERROR_COMMAND_SYNTAX_ERROR;
2395
2396 struct flash_bank *bank;
2397 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2398 if (retval != ERROR_OK)
2399 return retval;
2400
2401 if (stm32l4_is_otp(bank)) {
2402 LOG_ERROR("cannot lock/unlock OTP memory");
2403 return ERROR_FLASH_OPER_UNSUPPORTED;
2404 }
2405
2406 target = bank->target;
2407
2408 if (target->state != TARGET_HALTED) {
2409 LOG_ERROR("Target not halted");
2410 return ERROR_TARGET_NOT_HALTED;
2411 }
2412
2413 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2414 if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
2415 RDP_LEVEL_0, FLASH_RDP_MASK) != ERROR_OK) {
2416 command_print(CMD, "%s failed to unlock device", bank->driver->name);
2417 return ERROR_OK;
2418 }
2419
2420 return ERROR_OK;
2421 }
2422
2423 COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
2424 {
2425 if (CMD_ARGC < 1 || CMD_ARGC > 2)
2426 return ERROR_COMMAND_SYNTAX_ERROR;
2427
2428 struct flash_bank *bank;
2429 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2430 if (retval != ERROR_OK)
2431 return retval;
2432
2433 if (stm32l4_is_otp(bank)) {
2434 LOG_ERROR("OTP memory does not have write protection areas");
2435 return ERROR_FLASH_OPER_UNSUPPORTED;
2436 }
2437
2438 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
2439 enum stm32_bank_id dev_bank_id = STM32_ALL_BANKS;
2440 if (CMD_ARGC == 2) {
2441 if (strcmp(CMD_ARGV[1], "bank1") == 0)
2442 dev_bank_id = STM32_BANK1;
2443 else if (strcmp(CMD_ARGV[1], "bank2") == 0)
2444 dev_bank_id = STM32_BANK2;
2445 else
2446 return ERROR_COMMAND_ARGUMENT_INVALID;
2447 }
2448
2449 if (dev_bank_id == STM32_BANK2) {
2450 if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
2451 LOG_ERROR("this device has no second bank");
2452 return ERROR_FAIL;
2453 } else if (!stm32l4_info->dual_bank_mode) {
2454 LOG_ERROR("this device is configured in single bank mode");
2455 return ERROR_FAIL;
2456 }
2457 }
2458
2459 int ret;
2460 unsigned int n_wrp, i;
2461 struct stm32l4_wrp wrpxy[4];
2462
2463 ret = stm32l4_get_all_wrpxy(bank, dev_bank_id, wrpxy, &n_wrp);
2464 if (ret != ERROR_OK)
2465 return ret;
2466
2467 /* use bitmap and range helpers to better describe protected areas */
2468 DECLARE_BITMAP(pages, bank->num_sectors);
2469 bitmap_zero(pages, bank->num_sectors);
2470
2471 for (i = 0; i < n_wrp; i++) {
2472 if (wrpxy[i].used) {
2473 for (int p = wrpxy[i].first; p <= wrpxy[i].last; p++)
2474 set_bit(p, pages);
2475 }
2476 }
2477
2478 /* we have at most 'n_wrp' WRP areas */
2479 struct range ranges[n_wrp];
2480 unsigned int ranges_count = 0;
2481
2482 bitmap_to_ranges(pages, bank->num_sectors, ranges, &ranges_count);
2483
2484 if (ranges_count > 0) {
2485 /* pretty-print the protected ranges */
2486 char *ranges_str = range_print_alloc(ranges, ranges_count);
2487 command_print(CMD, "protected areas: %s", ranges_str);
2488 free(ranges_str);
2489 } else
2490 command_print(CMD, "no protected areas");
2491
2492 return ERROR_OK;
2493 }
2494
2495 COMMAND_HANDLER(stm32l4_handle_otp_command)
2496 {
2497 if (CMD_ARGC < 2)
2498 return ERROR_COMMAND_SYNTAX_ERROR;
2499
2500 struct flash_bank *bank;
2501 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
2502 if (retval != ERROR_OK)
2503 return retval;
2504
2505 if (!stm32l4_is_otp(bank)) {
2506 command_print(CMD, "the specified bank is not an OTP memory");
2507 return ERROR_FAIL;
2508 }
2509 if (strcmp(CMD_ARGV[1], "enable") == 0)
2510 stm32l4_otp_enable(bank, true);
2511 else if (strcmp(CMD_ARGV[1], "disable") == 0)
2512 stm32l4_otp_enable(bank, false);
2513 else if (strcmp(CMD_ARGV[1], "show") == 0)
2514 command_print(CMD, "OTP memory bank #%d is %s for write commands.",
2515 bank->bank_number, stm32l4_otp_is_enabled(bank) ? "enabled" : "disabled");
2516 else
2517 return ERROR_COMMAND_SYNTAX_ERROR;
2518
2519 return ERROR_OK;
2520 }
2521
2522 static const struct command_registration stm32l4_exec_command_handlers[] = {
2523 {
2524 .name = "lock",
2525 .handler = stm32l4_handle_lock_command,
2526 .mode = COMMAND_EXEC,
2527 .usage = "bank_id",
2528 .help = "Lock entire flash device.",
2529 },
2530 {
2531 .name = "unlock",
2532 .handler = stm32l4_handle_unlock_command,
2533 .mode = COMMAND_EXEC,
2534 .usage = "bank_id",
2535 .help = "Unlock entire protected flash device.",
2536 },
2537 {
2538 .name = "mass_erase",
2539 .handler = stm32l4_handle_mass_erase_command,
2540 .mode = COMMAND_EXEC,
2541 .usage = "bank_id",
2542 .help = "Erase entire flash device.",
2543 },
2544 {
2545 .name = "option_read",
2546 .handler = stm32l4_handle_option_read_command,
2547 .mode = COMMAND_EXEC,
2548 .usage = "bank_id reg_offset",
2549 .help = "Read & Display device option bytes.",
2550 },
2551 {
2552 .name = "option_write",
2553 .handler = stm32l4_handle_option_write_command,
2554 .mode = COMMAND_EXEC,
2555 .usage = "bank_id reg_offset value mask",
2556 .help = "Write device option bit fields with provided value.",
2557 },
2558 {
2559 .name = "trustzone",
2560 .handler = stm32l4_handle_trustzone_command,
2561 .mode = COMMAND_EXEC,
2562 .usage = "<bank_id> [enable|disable]",
2563 .help = "Configure TrustZone security",
2564 },
2565 {
2566 .name = "wrp_info",
2567 .handler = stm32l4_handle_wrp_info_command,
2568 .mode = COMMAND_EXEC,
2569 .usage = "bank_id [bank1|bank2]",
2570 .help = "list the protected areas using WRP",
2571 },
2572 {
2573 .name = "option_load",
2574 .handler = stm32l4_handle_option_load_command,
2575 .mode = COMMAND_EXEC,
2576 .usage = "bank_id",
2577 .help = "Force re-load of device options (will cause device reset).",
2578 },
2579 {
2580 .name = "otp",
2581 .handler = stm32l4_handle_otp_command,
2582 .mode = COMMAND_EXEC,
2583 .usage = "<bank_id> <enable|disable|show>",
2584 .help = "OTP (One Time Programmable) memory write enable/disable",
2585 },
2586 COMMAND_REGISTRATION_DONE
2587 };
2588
2589 static const struct command_registration stm32l4_command_handlers[] = {
2590 {
2591 .name = "stm32l4x",
2592 .mode = COMMAND_ANY,
2593 .help = "stm32l4x flash command group",
2594 .usage = "",
2595 .chain = stm32l4_exec_command_handlers,
2596 },
2597 COMMAND_REGISTRATION_DONE
2598 };
2599
2600 const struct flash_driver stm32l4x_flash = {
2601 .name = "stm32l4x",
2602 .commands = stm32l4_command_handlers,
2603 .flash_bank_command = stm32l4_flash_bank_command,
2604 .erase = stm32l4_erase,
2605 .protect = stm32l4_protect,
2606 .write = stm32l4_write,
2607 .read = default_flash_read,
2608 .probe = stm32l4_probe,
2609 .auto_probe = stm32l4_auto_probe,
2610 .erase_check = default_flash_blank_check,
2611 .protect_check = stm32l4_protect_check,
2612 .info = get_stm32l4_info,
2613 .free_driver_priv = default_flash_free_driver_priv,
2614 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)