1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
24 #include <helper/binarybuffer.h>
25 #include <target/algorithm.h>
26 #include <target/armv7m.h>
28 /* STM32L4xxx series for reference.
30 * RM0351 (STM32L4x5/STM32L4x6)
31 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
33 * RM0394 (STM32L43x/44x/45x/46x)
34 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
36 * RM0432 (STM32L4R/4Sxx)
37 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
39 * STM32L476RG Datasheet (for erase timing)
40 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
42 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
43 * an option byte is available to map all sectors to the first bank.
44 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
47 * RM0394 devices have a single bank only.
49 * RM0432 devices have single and dual bank operating modes.
50 * The FLASH size is 1Mbyte or 2Mbyte.
51 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
53 * Bank mode is controlled by two different bits in option bytes register.
54 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
55 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
59 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
61 #define FLASH_ERASE_TIMEOUT 250
63 #define STM32_FLASH_BASE 0x40022000
64 #define STM32_FLASH_ACR 0x40022000
65 #define STM32_FLASH_KEYR 0x40022008
66 #define STM32_FLASH_OPTKEYR 0x4002200c
67 #define STM32_FLASH_SR 0x40022010
68 #define STM32_FLASH_CR 0x40022014
69 #define STM32_FLASH_OPTR 0x40022020
70 #define STM32_FLASH_WRP1AR 0x4002202c
71 #define STM32_FLASH_WRP1BR 0x40022030
72 #define STM32_FLASH_WRP2AR 0x4002204c
73 #define STM32_FLASH_WRP2BR 0x40022050
75 /* FLASH_CR register bits */
77 #define FLASH_PG (1 << 0)
78 #define FLASH_PER (1 << 1)
79 #define FLASH_MER1 (1 << 2)
80 #define FLASH_PAGE_SHIFT 3
81 #define FLASH_CR_BKER (1 << 11)
82 #define FLASH_MER2 (1 << 15)
83 #define FLASH_STRT (1 << 16)
84 #define FLASH_OPTSTRT (1 << 17)
85 #define FLASH_EOPIE (1 << 24)
86 #define FLASH_ERRIE (1 << 25)
87 #define FLASH_OBLLAUNCH (1 << 27)
88 #define FLASH_OPTLOCK (1 << 30)
89 #define FLASH_LOCK (1 << 31)
91 /* FLASH_SR register bits */
93 #define FLASH_BSY (1 << 16)
94 /* Fast programming not used => related errors not used*/
95 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
96 #define FLASH_SIZERR (1 << 6) /* Size error */
97 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
98 #define FLASH_WRPERR (1 << 4) /* Write protection error */
99 #define FLASH_PROGERR (1 << 3) /* Programming error */
100 #define FLASH_OPERR (1 << 1) /* Operation error */
101 #define FLASH_EOP (1 << 0) /* End of operation */
103 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
105 /* STM32_FLASH_OBR bit definitions (reading) */
107 #define OPT_DBANK_LE_1M (1 << 21) /* dual bank for devices up to 1M flash */
108 #define OPT_DBANK_GE_2M (1 << 22) /* dual bank for devices with 2M flash */
110 /* register unlock keys */
112 #define KEY1 0x45670123
113 #define KEY2 0xCDEF89AB
115 /* option register unlock key */
116 #define OPTKEY1 0x08192A3B
117 #define OPTKEY2 0x4C5D6E7F
119 #define RDP_LEVEL_0 0xAA
120 #define RDP_LEVEL_1 0xBB
121 #define RDP_LEVEL_2 0xCC
124 /* other registers */
125 #define DBGMCU_IDCODE 0xE0042000
126 #define FLASH_SIZE_REG 0x1FFF75E0
128 struct stm32l4_flash_bank
{
129 uint16_t bank2_start
;
133 /* flash bank stm32l4x <base> <size> 0 0 <target#>
135 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
137 struct stm32l4_flash_bank
*stm32l4_info
;
140 return ERROR_COMMAND_SYNTAX_ERROR
;
142 stm32l4_info
= malloc(sizeof(struct stm32l4_flash_bank
));
144 return ERROR_FAIL
; /* Checkme: What better error to use?*/
145 bank
->driver_priv
= stm32l4_info
;
147 stm32l4_info
->probed
= 0;
152 static inline int stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
157 static inline int stm32l4_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
159 struct target
*target
= bank
->target
;
160 return target_read_u32(
161 target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
164 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
166 struct target
*target
= bank
->target
;
168 int retval
= ERROR_OK
;
170 /* wait for busy to clear */
172 retval
= stm32l4_get_flash_status(bank
, &status
);
173 if (retval
!= ERROR_OK
)
175 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
176 if ((status
& FLASH_BSY
) == 0)
178 if (timeout
-- <= 0) {
179 LOG_ERROR("timed out waiting for flash");
186 if (status
& FLASH_WRPERR
) {
187 LOG_ERROR("stm32x device protected");
191 /* Clear but report errors */
192 if (status
& FLASH_ERROR
) {
193 if (retval
== ERROR_OK
)
195 /* If this operation fails, we ignore it and report the original
198 target_write_u32(target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_SR
),
199 status
& FLASH_ERROR
);
204 static int stm32l4_unlock_reg(struct target
*target
)
208 /* first check if not already unlocked
209 * otherwise writing on STM32_FLASH_KEYR will fail
211 int retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
212 if (retval
!= ERROR_OK
)
215 if ((ctrl
& FLASH_LOCK
) == 0)
218 /* unlock flash registers */
219 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
220 if (retval
!= ERROR_OK
)
223 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
224 if (retval
!= ERROR_OK
)
227 retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
228 if (retval
!= ERROR_OK
)
231 if (ctrl
& FLASH_LOCK
) {
232 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
233 return ERROR_TARGET_FAILURE
;
239 static int stm32l4_unlock_option_reg(struct target
*target
)
243 int retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
244 if (retval
!= ERROR_OK
)
247 if ((ctrl
& FLASH_OPTLOCK
) == 0)
250 /* unlock option registers */
251 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, OPTKEY1
);
252 if (retval
!= ERROR_OK
)
255 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, OPTKEY2
);
256 if (retval
!= ERROR_OK
)
259 retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
260 if (retval
!= ERROR_OK
)
263 if (ctrl
& FLASH_OPTLOCK
) {
264 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
265 return ERROR_TARGET_FAILURE
;
271 static int stm32l4_read_option(struct flash_bank
*bank
, uint32_t address
, uint32_t* value
)
273 struct target
*target
= bank
->target
;
274 return target_read_u32(target
, address
, value
);
277 static int stm32l4_write_option(struct flash_bank
*bank
, uint32_t address
, uint32_t value
, uint32_t mask
)
279 struct target
*target
= bank
->target
;
282 int retval
= target_read_u32(target
, address
, &optiondata
);
283 if (retval
!= ERROR_OK
)
286 retval
= stm32l4_unlock_reg(target
);
287 if (retval
!= ERROR_OK
)
290 retval
= stm32l4_unlock_option_reg(target
);
291 if (retval
!= ERROR_OK
)
294 optiondata
= (optiondata
& ~mask
) | (value
& mask
);
296 retval
= target_write_u32(target
, address
, optiondata
);
297 if (retval
!= ERROR_OK
)
300 retval
= target_write_u32(target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_OPTSTRT
);
301 if (retval
!= ERROR_OK
)
304 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
305 if (retval
!= ERROR_OK
)
311 static int stm32l4_protect_check(struct flash_bank
*bank
)
313 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
314 uint32_t wrp1ar
, wrp1br
, wrp2ar
, wrp2br
;
315 stm32l4_read_option(bank
, STM32_FLASH_WRP1AR
, &wrp1ar
);
316 stm32l4_read_option(bank
, STM32_FLASH_WRP1BR
, &wrp1br
);
317 stm32l4_read_option(bank
, STM32_FLASH_WRP2AR
, &wrp2ar
);
318 stm32l4_read_option(bank
, STM32_FLASH_WRP2BR
, &wrp2br
);
320 const uint8_t wrp1a_start
= wrp1ar
& 0xFF;
321 const uint8_t wrp1a_end
= (wrp1ar
>> 16) & 0xFF;
322 const uint8_t wrp1b_start
= wrp1br
& 0xFF;
323 const uint8_t wrp1b_end
= (wrp1br
>> 16) & 0xFF;
324 const uint8_t wrp2a_start
= wrp2ar
& 0xFF;
325 const uint8_t wrp2a_end
= (wrp2ar
>> 16) & 0xFF;
326 const uint8_t wrp2b_start
= wrp2br
& 0xFF;
327 const uint8_t wrp2b_end
= (wrp2br
>> 16) & 0xFF;
329 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
330 if (i
< stm32l4_info
->bank2_start
) {
331 if (((i
>= wrp1a_start
) &&
333 ((i
>= wrp1b_start
) &&
335 bank
->sectors
[i
].is_protected
= 1;
337 bank
->sectors
[i
].is_protected
= 0;
340 snb
= i
- stm32l4_info
->bank2_start
;
341 if (((snb
>= wrp2a_start
) &&
342 (snb
<= wrp2a_end
)) ||
343 ((snb
>= wrp2b_start
) &&
345 bank
->sectors
[i
].is_protected
= 1;
347 bank
->sectors
[i
].is_protected
= 0;
353 static int stm32l4_erase(struct flash_bank
*bank
, int first
, int last
)
355 struct target
*target
= bank
->target
;
358 assert(first
< bank
->num_sectors
);
359 assert(last
< bank
->num_sectors
);
361 if (bank
->target
->state
!= TARGET_HALTED
) {
362 LOG_ERROR("Target not halted");
363 return ERROR_TARGET_NOT_HALTED
;
367 retval
= stm32l4_unlock_reg(target
);
368 if (retval
!= ERROR_OK
)
373 To erase a sector, follow the procedure below:
374 1. Check that no Flash memory operation is ongoing by
375 checking the BSY bit in the FLASH_SR register
376 2. Set the PER bit and select the page and bank
377 you wish to erase in the FLASH_CR register
378 3. Set the STRT bit in the FLASH_CR register
379 4. Wait for the BSY bit to be cleared
381 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
383 for (i
= first
; i
<= last
; i
++) {
384 uint32_t erase_flags
;
385 erase_flags
= FLASH_PER
| FLASH_STRT
;
387 if (i
>= stm32l4_info
->bank2_start
) {
389 snb
= i
- stm32l4_info
->bank2_start
;
390 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| FLASH_CR_BKER
;
392 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
393 retval
= target_write_u32(target
,
394 stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
), erase_flags
);
395 if (retval
!= ERROR_OK
)
398 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
399 if (retval
!= ERROR_OK
)
402 bank
->sectors
[i
].is_erased
= 1;
405 retval
= target_write_u32(
406 target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
407 if (retval
!= ERROR_OK
)
413 static int stm32l4_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
415 struct target
*target
= bank
->target
;
416 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
418 if (target
->state
!= TARGET_HALTED
) {
419 LOG_ERROR("Target not halted");
420 return ERROR_TARGET_NOT_HALTED
;
425 uint32_t reg_value
= 0xFF; /* Default to bank un-protected */
426 if (last
>= stm32l4_info
->bank2_start
) {
428 uint8_t begin
= first
> stm32l4_info
->bank2_start
? first
: 0x00;
429 reg_value
= ((last
& 0xFF) << 16) | begin
;
432 ret
= stm32l4_write_option(bank
, STM32_FLASH_WRP2AR
, reg_value
, 0xffffffff);
435 reg_value
= 0xFF; /* Default to bank un-protected */
436 if (first
< stm32l4_info
->bank2_start
) {
438 uint8_t end
= last
>= stm32l4_info
->bank2_start
? 0xFF : last
;
439 reg_value
= (end
<< 16) | (first
& 0xFF);
442 ret
= stm32l4_write_option(bank
, STM32_FLASH_WRP1AR
, reg_value
, 0xffffffff);
448 /* Count is in halfwords */
449 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
450 uint32_t offset
, uint32_t count
)
452 struct target
*target
= bank
->target
;
453 uint32_t buffer_size
= 16384;
454 struct working_area
*write_algorithm
;
455 struct working_area
*source
;
456 uint32_t address
= bank
->base
+ offset
;
457 struct reg_param reg_params
[5];
458 struct armv7m_algorithm armv7m_info
;
459 int retval
= ERROR_OK
;
461 static const uint8_t stm32l4_flash_write_code
[] = {
462 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
465 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
466 &write_algorithm
) != ERROR_OK
) {
467 LOG_WARNING("no working area available, can't do block memory writes");
468 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
471 retval
= target_write_buffer(target
, write_algorithm
->address
,
472 sizeof(stm32l4_flash_write_code
),
473 stm32l4_flash_write_code
);
474 if (retval
!= ERROR_OK
) {
475 target_free_working_area(target
, write_algorithm
);
480 while (target_alloc_working_area_try(target
, buffer_size
, &source
) !=
483 if (buffer_size
<= 256) {
484 /* we already allocated the writing code, but failed to get a
485 * buffer, free the algorithm */
486 target_free_working_area(target
, write_algorithm
);
488 LOG_WARNING("large enough working area not available, can't do block memory writes");
489 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
493 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
494 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
496 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
497 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
498 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
499 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (double word-64bit) */
500 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash base */
502 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
503 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
504 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
505 buf_set_u32(reg_params
[3].value
, 0, 32, count
/ 4);
506 buf_set_u32(reg_params
[4].value
, 0, 32, STM32_FLASH_BASE
);
508 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
511 source
->address
, source
->size
,
512 write_algorithm
->address
, 0,
515 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
516 LOG_ERROR("error executing stm32l4 flash write algorithm");
518 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
520 if (error
& FLASH_WRPERR
)
521 LOG_ERROR("flash memory write protected");
524 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
525 /* Clear but report errors */
526 target_write_u32(target
, STM32_FLASH_SR
, error
);
531 target_free_working_area(target
, source
);
532 target_free_working_area(target
, write_algorithm
);
534 destroy_reg_param(®_params
[0]);
535 destroy_reg_param(®_params
[1]);
536 destroy_reg_param(®_params
[2]);
537 destroy_reg_param(®_params
[3]);
538 destroy_reg_param(®_params
[4]);
543 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
544 uint32_t offset
, uint32_t count
)
546 struct target
*target
= bank
->target
;
549 if (bank
->target
->state
!= TARGET_HALTED
) {
550 LOG_ERROR("Target not halted");
551 return ERROR_TARGET_NOT_HALTED
;
555 LOG_WARNING("offset 0x%" PRIx32
" breaks required 8-byte alignment",
557 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
561 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
563 count
= (count
+ 7) & ~7;
564 /* This pads the write chunk with random bytes by overrunning the
565 * write buffer. Padding with the erased pattern 0xff is purely
566 * cosmetical, as 8-byte flash words are ECC secured and the first
567 * write will program the ECC bits. A second write would need
568 * to reprogramm these ECC bits.
569 * But this can only be done after erase!
573 retval
= stm32l4_unlock_reg(target
);
574 if (retval
!= ERROR_OK
)
577 /* Only full double words (8-byte) can be programmed*/
578 retval
= stm32l4_write_block(bank
, buffer
, offset
, count
/ 2);
579 if (retval
!= ERROR_OK
) {
580 LOG_WARNING("block write failed");
584 LOG_WARNING("block write succeeded");
585 return target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
588 static int stm32l4_probe(struct flash_bank
*bank
)
590 struct target
*target
= bank
->target
;
591 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
593 uint16_t flash_size_in_kb
= 0xffff;
594 uint16_t max_flash_size_in_kb
;
597 uint32_t base_address
= 0x08000000;
599 stm32l4_info
->probed
= 0;
601 /* read stm32 device id register */
602 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &device_id
);
603 if (retval
!= ERROR_OK
)
605 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
607 /* set max flash size depending on family */
608 switch (device_id
& 0xfff) {
610 max_flash_size_in_kb
= 2048;
614 max_flash_size_in_kb
= 1024;
617 max_flash_size_in_kb
= 512;
620 max_flash_size_in_kb
= 256;
623 LOG_WARNING("Cannot identify target as an STM32L4 family device.");
627 /* get flash size from target. */
628 retval
= target_read_u16(target
, FLASH_SIZE_REG
, &flash_size_in_kb
);
630 /* failed reading flash size or flash size invalid (early silicon),
631 * default to max target family */
632 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
633 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
634 max_flash_size_in_kb
);
635 flash_size_in_kb
= max_flash_size_in_kb
;
638 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
640 /* did we assign a flash size? */
641 assert((flash_size_in_kb
!= 0xffff) && flash_size_in_kb
);
643 /* get options for DUAL BANK. */
644 retval
= target_read_u32(target
, STM32_FLASH_OPTR
, &options
);
646 if (retval
!= ERROR_OK
)
652 switch (device_id
& 0xfff) {
654 /* L4R/S have 1M or 2M FLASH and dual/single bank mode.
655 * Page size is 4K or 8K.*/
656 if (flash_size_in_kb
== 2048) {
657 stm32l4_info
->bank2_start
= 256;
658 if (options
& OPT_DBANK_GE_2M
) {
667 if (flash_size_in_kb
== 1024) {
668 stm32l4_info
->bank2_start
= 128;
669 if (options
& OPT_DBANK_LE_1M
) {
678 /* Invalid FLASH size for this device. */
679 LOG_WARNING("Invalid flash size for STM32L4+ family device.");
683 /* These are dual-bank devices, we need to check the OPT_DBANK_LE_1M bit here */
685 num_pages
= flash_size_in_kb
/ 2;
686 /* check that calculation result makes sense */
687 assert(num_pages
> 0);
688 if ((flash_size_in_kb
== 1024) || !(options
& OPT_DBANK_LE_1M
))
689 stm32l4_info
->bank2_start
= 256;
691 stm32l4_info
->bank2_start
= num_pages
/ 2;
696 /* These are single-bank devices */
698 num_pages
= flash_size_in_kb
/ 2;
699 /* check that calculation result makes sense */
700 assert(num_pages
> 0);
701 stm32l4_info
->bank2_start
= UINT16_MAX
;
705 /* Release sector table if allocated. */
708 bank
->sectors
= NULL
;
711 /* Set bank configuration and construct sector table. */
712 bank
->base
= base_address
;
713 bank
->size
= num_pages
* page_size
;
714 bank
->num_sectors
= num_pages
;
715 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
717 return ERROR_FAIL
; /* Checkme: What better error to use?*/
719 for (i
= 0; i
< num_pages
; i
++) {
720 bank
->sectors
[i
].offset
= i
* page_size
;
721 bank
->sectors
[i
].size
= page_size
;
722 bank
->sectors
[i
].is_erased
= -1;
723 bank
->sectors
[i
].is_protected
= 1;
726 stm32l4_info
->probed
= 1;
731 static int stm32l4_auto_probe(struct flash_bank
*bank
)
733 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
734 if (stm32l4_info
->probed
)
736 return stm32l4_probe(bank
);
739 static int get_stm32l4_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
741 struct target
*target
= bank
->target
;
742 uint32_t dbgmcu_idcode
;
744 /* read stm32 device id register */
745 int retval
= target_read_u32(target
, DBGMCU_IDCODE
, &dbgmcu_idcode
);
746 if (retval
!= ERROR_OK
)
749 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
750 uint8_t rev_id
= dbgmcu_idcode
>> 28;
751 uint8_t rev_minor
= 0;
754 for (i
= 16; i
< 28; i
++) {
755 if (dbgmcu_idcode
& (1 << i
))
761 const char *device_str
;
765 device_str
= "STM32L4R/4Sxx";
769 device_str
= "STM32L496/4A6";
773 device_str
= "STM32L475/476/486";
777 device_str
= "STM32L45x/46x";
781 device_str
= "STM32L43x/44x";
785 snprintf(buf
, buf_size
, "Cannot identify target as a STM32L4\n");
789 snprintf(buf
, buf_size
, "%s - Rev: %1d.%02d",
790 device_str
, rev_id
, rev_minor
);
795 static int stm32l4_mass_erase(struct flash_bank
*bank
, uint32_t action
)
798 struct target
*target
= bank
->target
;
800 if (target
->state
!= TARGET_HALTED
) {
801 LOG_ERROR("Target not halted");
802 return ERROR_TARGET_NOT_HALTED
;
805 retval
= stm32l4_unlock_reg(target
);
806 if (retval
!= ERROR_OK
)
809 /* mass erase flash memory */
810 retval
= target_write_u32(
811 target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
), action
);
812 if (retval
!= ERROR_OK
)
814 retval
= target_write_u32(
815 target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
),
816 action
| FLASH_STRT
);
817 if (retval
!= ERROR_OK
)
820 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
821 if (retval
!= ERROR_OK
)
824 retval
= target_write_u32(
825 target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
826 if (retval
!= ERROR_OK
)
832 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
838 command_print(CMD
, "stm32l4x mass_erase <STM32L4 bank>");
839 return ERROR_COMMAND_SYNTAX_ERROR
;
842 struct flash_bank
*bank
;
843 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
844 if (ERROR_OK
!= retval
)
847 action
= FLASH_MER1
| FLASH_MER2
;
848 retval
= stm32l4_mass_erase(bank
, action
);
849 if (retval
== ERROR_OK
) {
850 /* set all sectors as erased */
851 for (i
= 0; i
< bank
->num_sectors
; i
++)
852 bank
->sectors
[i
].is_erased
= 1;
854 command_print(CMD
, "stm32l4x mass erase complete");
856 command_print(CMD
, "stm32l4x mass erase failed");
862 COMMAND_HANDLER(stm32l4_handle_option_read_command
)
865 command_print(CMD
, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
866 return ERROR_COMMAND_SYNTAX_ERROR
;
869 struct flash_bank
*bank
;
870 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
871 if (ERROR_OK
!= retval
)
874 uint32_t reg_addr
= STM32_FLASH_BASE
;
877 reg_addr
+= strtoul(CMD_ARGV
[1], NULL
, 16);
879 retval
= stm32l4_read_option(bank
, reg_addr
, &value
);
880 if (ERROR_OK
!= retval
)
883 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr
, value
);
888 COMMAND_HANDLER(stm32l4_handle_option_write_command
)
891 command_print(CMD
, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
892 return ERROR_COMMAND_SYNTAX_ERROR
;
895 struct flash_bank
*bank
;
896 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
897 if (ERROR_OK
!= retval
)
900 uint32_t reg_addr
= STM32_FLASH_BASE
;
902 uint32_t mask
= 0xFFFFFFFF;
904 reg_addr
+= strtoul(CMD_ARGV
[1], NULL
, 16);
905 value
= strtoul(CMD_ARGV
[2], NULL
, 16);
907 mask
= strtoul(CMD_ARGV
[3], NULL
, 16);
909 command_print(CMD
, "%s Option written.\n"
910 "INFO: a reset or power cycle is required "
911 "for the new settings to take effect.", bank
->driver
->name
);
913 retval
= stm32l4_write_option(bank
, reg_addr
, value
, mask
);
917 COMMAND_HANDLER(stm32l4_handle_option_load_command
)
920 return ERROR_COMMAND_SYNTAX_ERROR
;
922 struct flash_bank
*bank
;
923 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
924 if (ERROR_OK
!= retval
)
927 struct target
*target
= bank
->target
;
929 retval
= stm32l4_unlock_reg(target
);
930 if (ERROR_OK
!= retval
)
933 retval
= stm32l4_unlock_option_reg(target
);
934 if (ERROR_OK
!= retval
)
937 /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
938 retval
= target_write_u32(target
, stm32l4_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_OBLLAUNCH
);
940 command_print(CMD
, "stm32l4x option load (POR) completed.");
944 COMMAND_HANDLER(stm32l4_handle_lock_command
)
946 struct target
*target
= NULL
;
949 return ERROR_COMMAND_SYNTAX_ERROR
;
951 struct flash_bank
*bank
;
952 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
953 if (ERROR_OK
!= retval
)
956 target
= bank
->target
;
958 if (target
->state
!= TARGET_HALTED
) {
959 LOG_ERROR("Target not halted");
960 return ERROR_TARGET_NOT_HALTED
;
963 /* set readout protection level 1 by erasing the RDP option byte */
964 if (stm32l4_write_option(bank
, STM32_FLASH_OPTR
, 0, 0x000000FF) != ERROR_OK
) {
965 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
972 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
974 struct target
*target
= NULL
;
977 return ERROR_COMMAND_SYNTAX_ERROR
;
979 struct flash_bank
*bank
;
980 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
981 if (ERROR_OK
!= retval
)
984 target
= bank
->target
;
986 if (target
->state
!= TARGET_HALTED
) {
987 LOG_ERROR("Target not halted");
988 return ERROR_TARGET_NOT_HALTED
;
991 if (stm32l4_write_option(bank
, STM32_FLASH_OPTR
, RDP_LEVEL_0
, 0x000000FF) != ERROR_OK
) {
992 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
999 static const struct command_registration stm32l4_exec_command_handlers
[] = {
1002 .handler
= stm32l4_handle_lock_command
,
1003 .mode
= COMMAND_EXEC
,
1005 .help
= "Lock entire flash device.",
1009 .handler
= stm32l4_handle_unlock_command
,
1010 .mode
= COMMAND_EXEC
,
1012 .help
= "Unlock entire protected flash device.",
1015 .name
= "mass_erase",
1016 .handler
= stm32l4_handle_mass_erase_command
,
1017 .mode
= COMMAND_EXEC
,
1019 .help
= "Erase entire flash device.",
1022 .name
= "option_read",
1023 .handler
= stm32l4_handle_option_read_command
,
1024 .mode
= COMMAND_EXEC
,
1025 .usage
= "bank_id reg_offset",
1026 .help
= "Read & Display device option bytes.",
1029 .name
= "option_write",
1030 .handler
= stm32l4_handle_option_write_command
,
1031 .mode
= COMMAND_EXEC
,
1032 .usage
= "bank_id reg_offset value mask",
1033 .help
= "Write device option bit fields with provided value.",
1036 .name
= "option_load",
1037 .handler
= stm32l4_handle_option_load_command
,
1038 .mode
= COMMAND_EXEC
,
1040 .help
= "Force re-load of device options (will cause device reset).",
1042 COMMAND_REGISTRATION_DONE
1045 static const struct command_registration stm32l4_command_handlers
[] = {
1048 .mode
= COMMAND_ANY
,
1049 .help
= "stm32l4x flash command group",
1051 .chain
= stm32l4_exec_command_handlers
,
1053 COMMAND_REGISTRATION_DONE
1056 const struct flash_driver stm32l4x_flash
= {
1058 .commands
= stm32l4_command_handlers
,
1059 .flash_bank_command
= stm32l4_flash_bank_command
,
1060 .erase
= stm32l4_erase
,
1061 .protect
= stm32l4_protect
,
1062 .write
= stm32l4_write
,
1063 .read
= default_flash_read
,
1064 .probe
= stm32l4_probe
,
1065 .auto_probe
= stm32l4_auto_probe
,
1066 .erase_check
= default_flash_blank_check
,
1067 .protect_check
= stm32l4_protect_check
,
1068 .info
= get_stm32l4_info
,
1069 .free_driver_priv
= default_flash_free_driver_priv
,
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