1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2015 by Uwe Bonnes *
5 * bon@elektron.ikp.physik.tu-darmstadt.de *
7 * Copyright (C) 2019 by Tarek Bochkati for STMicroelectronics *
8 * tarek.bouchkati@gmail.com *
9 ***************************************************************************/
16 #include <helper/align.h>
17 #include <helper/binarybuffer.h>
18 #include <helper/bits.h>
19 #include <target/algorithm.h>
20 #include <target/arm_adi_v5.h>
21 #include <target/cortex_m.h>
24 /* STM32L4xxx series for reference.
26 * RM0351 (STM32L4x5/STM32L4x6)
27 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
29 * RM0394 (STM32L43x/44x/45x/46x)
30 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
32 * RM0432 (STM32L4R/4Sxx)
33 * http://www.st.com/resource/en/reference_manual/dm00310109.pdf
35 * STM32L476RG Datasheet (for erase timing)
36 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
38 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
39 * an option byte is available to map all sectors to the first bank.
40 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
43 * RM0394 devices have a single bank only.
45 * RM0432 devices have single and dual bank operating modes.
46 * - for STM32L4R/Sxx the FLASH size is 2Mbyte or 1Mbyte.
47 * - for STM32L4P/Q5x the FLASH size is 1Mbyte or 512Kbyte.
48 * Bank page (sector) size is 4Kbyte (dual mode) or 8Kbyte (single mode).
50 * Bank mode is controlled by two different bits in option bytes register.
52 * In 2M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
53 * In 1M FLASH devices bit 21 (DB1M) controls Dual Bank mode.
55 * In 1M FLASH devices bit 22 (DBANK) controls Dual Bank mode.
56 * In 512K FLASH devices bit 21 (DB512K) controls Dual Bank mode.
59 /* STM32WBxxx series for reference.
61 * RM0434 (STM32WB55/WB35x)
62 * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
64 * RM0471 (STM32WB50/WB30x)
65 * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
68 * http://www.st.com/resource/en/reference_manual/dm00649196.pdf
71 * http://www.st.com/resource/en/reference_manual/dm00689203.pdf
74 /* STM32WLxxx series for reference.
77 * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
80 * http://www.st.com/resource/en/reference_manual/dm00451556.pdf
83 /* STM32C0xxx series for reference.
86 * http://www.st.com/resource/en/reference_manual/dm00781702.pdf
89 /* STM32G0xxx series for reference.
92 * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
95 * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
98 /* STM32G4xxx series for reference.
100 * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
101 * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
103 * Cat. 2 devices have single bank only, page size is 2kByte.
105 * Cat. 3 devices have single and dual bank operating modes,
106 * Page size is 2kByte (dual mode) or 4kByte (single mode).
108 * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
109 * Both banks are treated as a single OpenOCD bank.
111 * Cat. 4 devices have single bank only, page size is 2kByte.
114 /* STM32L5xxx series for reference.
116 * RM0428 (STM32L552xx/STM32L562xx)
117 * http://www.st.com/resource/en/reference_manual/dm00346336.pdf
120 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
122 #define FLASH_ERASE_TIMEOUT 250
123 #define FLASH_WRITE_TIMEOUT 50
126 /* relevant STM32L4 flags ****************************************************/
128 /* this flag indicates if the device flash is with dual bank architecture */
129 #define F_HAS_DUAL_BANK BIT(0)
130 /* this flags is used for dual bank devices only, it indicates if the
131 * 4 WRPxx are usable if the device is configured in single-bank mode */
132 #define F_USE_ALL_WRPXX BIT(1)
133 /* this flag indicates if the device embeds a TrustZone security feature */
134 #define F_HAS_TZ BIT(2)
135 /* this flag indicates if the device has the same flash registers as STM32L5 */
136 #define F_HAS_L5_FLASH_REGS BIT(3)
137 /* this flag indicates that programming should be done in quad-word
138 * the default programming word size is double-word */
139 #define F_QUAD_WORD_PROG BIT(4)
140 /* end of STM32L4 flags ******************************************************/
143 enum stm32l4_flash_reg_index
{
144 STM32_FLASH_ACR_INDEX
,
145 STM32_FLASH_KEYR_INDEX
,
146 STM32_FLASH_OPTKEYR_INDEX
,
147 STM32_FLASH_SR_INDEX
,
148 STM32_FLASH_CR_INDEX
,
149 /* for some devices like STM32WL5x, the CPU2 have a dedicated C2CR register w/o LOCKs,
150 * so it uses the C2CR for flash operations and CR for checking locks and locking */
151 STM32_FLASH_CR_WLK_INDEX
, /* FLASH_CR_WITH_LOCK */
152 STM32_FLASH_OPTR_INDEX
,
153 STM32_FLASH_WRP1AR_INDEX
,
154 STM32_FLASH_WRP1BR_INDEX
,
155 STM32_FLASH_WRP2AR_INDEX
,
156 STM32_FLASH_WRP2BR_INDEX
,
157 STM32_FLASH_REG_INDEX_NUM
,
162 RDP_LEVEL_0_5
= 0x55, /* for devices with TrustZone enabled */
167 static const uint32_t stm32l4_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
168 [STM32_FLASH_ACR_INDEX
] = 0x000,
169 [STM32_FLASH_KEYR_INDEX
] = 0x008,
170 [STM32_FLASH_OPTKEYR_INDEX
] = 0x00C,
171 [STM32_FLASH_SR_INDEX
] = 0x010,
172 [STM32_FLASH_CR_INDEX
] = 0x014,
173 [STM32_FLASH_OPTR_INDEX
] = 0x020,
174 [STM32_FLASH_WRP1AR_INDEX
] = 0x02C,
175 [STM32_FLASH_WRP1BR_INDEX
] = 0x030,
176 [STM32_FLASH_WRP2AR_INDEX
] = 0x04C,
177 [STM32_FLASH_WRP2BR_INDEX
] = 0x050,
180 static const uint32_t stm32wl_cpu2_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
181 [STM32_FLASH_ACR_INDEX
] = 0x000,
182 [STM32_FLASH_KEYR_INDEX
] = 0x008,
183 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
184 [STM32_FLASH_SR_INDEX
] = 0x060,
185 [STM32_FLASH_CR_INDEX
] = 0x064,
186 [STM32_FLASH_CR_WLK_INDEX
] = 0x014,
187 [STM32_FLASH_OPTR_INDEX
] = 0x020,
188 [STM32_FLASH_WRP1AR_INDEX
] = 0x02C,
189 [STM32_FLASH_WRP1BR_INDEX
] = 0x030,
192 static const uint32_t stm32l5_ns_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
193 [STM32_FLASH_ACR_INDEX
] = 0x000,
194 [STM32_FLASH_KEYR_INDEX
] = 0x008, /* NSKEYR */
195 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
196 [STM32_FLASH_SR_INDEX
] = 0x020, /* NSSR */
197 [STM32_FLASH_CR_INDEX
] = 0x028, /* NSCR */
198 [STM32_FLASH_OPTR_INDEX
] = 0x040,
199 [STM32_FLASH_WRP1AR_INDEX
] = 0x058,
200 [STM32_FLASH_WRP1BR_INDEX
] = 0x05C,
201 [STM32_FLASH_WRP2AR_INDEX
] = 0x068,
202 [STM32_FLASH_WRP2BR_INDEX
] = 0x06C,
205 static const uint32_t stm32l5_s_flash_regs
[STM32_FLASH_REG_INDEX_NUM
] = {
206 [STM32_FLASH_ACR_INDEX
] = 0x000,
207 [STM32_FLASH_KEYR_INDEX
] = 0x00C, /* SECKEYR */
208 [STM32_FLASH_OPTKEYR_INDEX
] = 0x010,
209 [STM32_FLASH_SR_INDEX
] = 0x024, /* SECSR */
210 [STM32_FLASH_CR_INDEX
] = 0x02C, /* SECCR */
211 [STM32_FLASH_OPTR_INDEX
] = 0x040,
212 [STM32_FLASH_WRP1AR_INDEX
] = 0x058,
213 [STM32_FLASH_WRP1BR_INDEX
] = 0x05C,
214 [STM32_FLASH_WRP2AR_INDEX
] = 0x068,
215 [STM32_FLASH_WRP2BR_INDEX
] = 0x06C,
223 struct stm32l4_part_info
{
225 const char *device_str
;
226 const struct stm32l4_rev
*revs
;
227 const size_t num_revs
;
228 const uint16_t max_flash_size_kb
;
229 const uint32_t flags
; /* one bit per feature, see STM32L4 flags: macros F_XXX */
230 const uint32_t flash_regs_base
;
231 const uint32_t fsize_addr
;
232 const uint32_t otp_base
;
233 const uint32_t otp_size
;
236 struct stm32l4_flash_bank
{
239 unsigned int bank1_sectors
;
242 uint32_t user_bank_size
;
244 uint32_t cr_bker_mask
;
245 uint32_t sr_bsy_mask
;
246 uint32_t wrpxxr_mask
;
247 const struct stm32l4_part_info
*part_info
;
248 uint32_t flash_regs_base
;
249 const uint32_t *flash_regs
;
251 enum stm32l4_rdp rdp
;
263 enum stm32l4_flash_reg_index reg_idx
;
271 /* human readable list of families this drivers supports (sorted alphabetically) */
272 static const char *device_families
= "STM32C0/G0/G4/L4/L4+/L5/U5/WB/WL";
274 static const struct stm32l4_rev stm32l47_l48xx_revs
[] = {
275 { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
278 static const struct stm32l4_rev stm32l43_l44xx_revs
[] = {
279 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
283 static const struct stm32l4_rev stm32c01xx_revs
[] = {
284 { 0x1000, "A" }, { 0x1001, "Z" },
287 static const struct stm32l4_rev stm32c03xx_revs
[] = {
288 { 0x1000, "A" }, { 0x1001, "Z" },
291 static const struct stm32l4_rev stm32g05_g06xx_revs
[] = {
295 static const struct stm32l4_rev stm32_g07_g08xx_revs
[] = {
296 { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
299 static const struct stm32l4_rev stm32l49_l4axx_revs
[] = {
300 { 0x1000, "A" }, { 0x2000, "B" },
303 static const struct stm32l4_rev stm32l45_l46xx_revs
[] = {
304 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
307 static const struct stm32l4_rev stm32l41_l42xx_revs
[] = {
308 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
311 static const struct stm32l4_rev stm32g03_g04xx_revs
[] = {
312 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
315 static const struct stm32l4_rev stm32g0b_g0cxx_revs
[] = {
319 static const struct stm32l4_rev stm32g43_g44xx_revs
[] = {
320 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
323 static const struct stm32l4_rev stm32g47_g48xx_revs
[] = {
324 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
327 static const struct stm32l4_rev stm32l4r_l4sxx_revs
[] = {
328 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x100F, "W" },
332 static const struct stm32l4_rev stm32l4p_l4qxx_revs
[] = {
336 static const struct stm32l4_rev stm32l55_l56xx_revs
[] = {
337 { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
340 static const struct stm32l4_rev stm32g49_g4axx_revs
[] = {
344 static const struct stm32l4_rev stm32u57_u58xx_revs
[] = {
345 { 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2000, "B" },
346 { 0x2001, "X" }, { 0x3000, "C" },
349 static const struct stm32l4_rev stm32wb1xx_revs
[] = {
350 { 0x1000, "A" }, { 0x2000, "B" },
353 static const struct stm32l4_rev stm32wb5xx_revs
[] = {
357 static const struct stm32l4_rev stm32wb3xx_revs
[] = {
361 static const struct stm32l4_rev stm32wle_wl5xx_revs
[] = {
365 static const struct stm32l4_part_info stm32l4_parts
[] = {
367 .id
= DEVID_STM32L47_L48XX
,
368 .revs
= stm32l47_l48xx_revs
,
369 .num_revs
= ARRAY_SIZE(stm32l47_l48xx_revs
),
370 .device_str
= "STM32L47/L48xx",
371 .max_flash_size_kb
= 1024,
372 .flags
= F_HAS_DUAL_BANK
,
373 .flash_regs_base
= 0x40022000,
374 .fsize_addr
= 0x1FFF75E0,
375 .otp_base
= 0x1FFF7000,
379 .id
= DEVID_STM32L43_L44XX
,
380 .revs
= stm32l43_l44xx_revs
,
381 .num_revs
= ARRAY_SIZE(stm32l43_l44xx_revs
),
382 .device_str
= "STM32L43/L44xx",
383 .max_flash_size_kb
= 256,
385 .flash_regs_base
= 0x40022000,
386 .fsize_addr
= 0x1FFF75E0,
387 .otp_base
= 0x1FFF7000,
391 .id
= DEVID_STM32C01XX
,
392 .revs
= stm32c01xx_revs
,
393 .num_revs
= ARRAY_SIZE(stm32c01xx_revs
),
394 .device_str
= "STM32C01xx",
395 .max_flash_size_kb
= 32,
397 .flash_regs_base
= 0x40022000,
398 .fsize_addr
= 0x1FFF75A0,
399 .otp_base
= 0x1FFF7000,
403 .id
= DEVID_STM32C03XX
,
404 .revs
= stm32c03xx_revs
,
405 .num_revs
= ARRAY_SIZE(stm32c03xx_revs
),
406 .device_str
= "STM32C03xx",
407 .max_flash_size_kb
= 32,
409 .flash_regs_base
= 0x40022000,
410 .fsize_addr
= 0x1FFF75A0,
411 .otp_base
= 0x1FFF7000,
415 .id
= DEVID_STM32G05_G06XX
,
416 .revs
= stm32g05_g06xx_revs
,
417 .num_revs
= ARRAY_SIZE(stm32g05_g06xx_revs
),
418 .device_str
= "STM32G05/G06xx",
419 .max_flash_size_kb
= 64,
421 .flash_regs_base
= 0x40022000,
422 .fsize_addr
= 0x1FFF75E0,
423 .otp_base
= 0x1FFF7000,
427 .id
= DEVID_STM32G07_G08XX
,
428 .revs
= stm32_g07_g08xx_revs
,
429 .num_revs
= ARRAY_SIZE(stm32_g07_g08xx_revs
),
430 .device_str
= "STM32G07/G08xx",
431 .max_flash_size_kb
= 128,
433 .flash_regs_base
= 0x40022000,
434 .fsize_addr
= 0x1FFF75E0,
435 .otp_base
= 0x1FFF7000,
439 .id
= DEVID_STM32L49_L4AXX
,
440 .revs
= stm32l49_l4axx_revs
,
441 .num_revs
= ARRAY_SIZE(stm32l49_l4axx_revs
),
442 .device_str
= "STM32L49/L4Axx",
443 .max_flash_size_kb
= 1024,
444 .flags
= F_HAS_DUAL_BANK
,
445 .flash_regs_base
= 0x40022000,
446 .fsize_addr
= 0x1FFF75E0,
447 .otp_base
= 0x1FFF7000,
451 .id
= DEVID_STM32L45_L46XX
,
452 .revs
= stm32l45_l46xx_revs
,
453 .num_revs
= ARRAY_SIZE(stm32l45_l46xx_revs
),
454 .device_str
= "STM32L45/L46xx",
455 .max_flash_size_kb
= 512,
457 .flash_regs_base
= 0x40022000,
458 .fsize_addr
= 0x1FFF75E0,
459 .otp_base
= 0x1FFF7000,
463 .id
= DEVID_STM32L41_L42XX
,
464 .revs
= stm32l41_l42xx_revs
,
465 .num_revs
= ARRAY_SIZE(stm32l41_l42xx_revs
),
466 .device_str
= "STM32L41/L42xx",
467 .max_flash_size_kb
= 128,
469 .flash_regs_base
= 0x40022000,
470 .fsize_addr
= 0x1FFF75E0,
471 .otp_base
= 0x1FFF7000,
475 .id
= DEVID_STM32G03_G04XX
,
476 .revs
= stm32g03_g04xx_revs
,
477 .num_revs
= ARRAY_SIZE(stm32g03_g04xx_revs
),
478 .device_str
= "STM32G03x/G04xx",
479 .max_flash_size_kb
= 64,
481 .flash_regs_base
= 0x40022000,
482 .fsize_addr
= 0x1FFF75E0,
483 .otp_base
= 0x1FFF7000,
487 .id
= DEVID_STM32G0B_G0CXX
,
488 .revs
= stm32g0b_g0cxx_revs
,
489 .num_revs
= ARRAY_SIZE(stm32g0b_g0cxx_revs
),
490 .device_str
= "STM32G0B/G0Cx",
491 .max_flash_size_kb
= 512,
492 .flags
= F_HAS_DUAL_BANK
,
493 .flash_regs_base
= 0x40022000,
494 .fsize_addr
= 0x1FFF75E0,
495 .otp_base
= 0x1FFF7000,
499 .id
= DEVID_STM32G43_G44XX
,
500 .revs
= stm32g43_g44xx_revs
,
501 .num_revs
= ARRAY_SIZE(stm32g43_g44xx_revs
),
502 .device_str
= "STM32G43/G44xx",
503 .max_flash_size_kb
= 128,
505 .flash_regs_base
= 0x40022000,
506 .fsize_addr
= 0x1FFF75E0,
507 .otp_base
= 0x1FFF7000,
511 .id
= DEVID_STM32G47_G48XX
,
512 .revs
= stm32g47_g48xx_revs
,
513 .num_revs
= ARRAY_SIZE(stm32g47_g48xx_revs
),
514 .device_str
= "STM32G47/G48xx",
515 .max_flash_size_kb
= 512,
516 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
517 .flash_regs_base
= 0x40022000,
518 .fsize_addr
= 0x1FFF75E0,
519 .otp_base
= 0x1FFF7000,
523 .id
= DEVID_STM32L4R_L4SXX
,
524 .revs
= stm32l4r_l4sxx_revs
,
525 .num_revs
= ARRAY_SIZE(stm32l4r_l4sxx_revs
),
526 .device_str
= "STM32L4R/L4Sxx",
527 .max_flash_size_kb
= 2048,
528 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
529 .flash_regs_base
= 0x40022000,
530 .fsize_addr
= 0x1FFF75E0,
531 .otp_base
= 0x1FFF7000,
535 .id
= DEVID_STM32L4P_L4QXX
,
536 .revs
= stm32l4p_l4qxx_revs
,
537 .num_revs
= ARRAY_SIZE(stm32l4p_l4qxx_revs
),
538 .device_str
= "STM32L4P/L4Qxx",
539 .max_flash_size_kb
= 1024,
540 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
,
541 .flash_regs_base
= 0x40022000,
542 .fsize_addr
= 0x1FFF75E0,
543 .otp_base
= 0x1FFF7000,
547 .id
= DEVID_STM32L55_L56XX
,
548 .revs
= stm32l55_l56xx_revs
,
549 .num_revs
= ARRAY_SIZE(stm32l55_l56xx_revs
),
550 .device_str
= "STM32L55/L56xx",
551 .max_flash_size_kb
= 512,
552 .flags
= F_HAS_DUAL_BANK
| F_USE_ALL_WRPXX
| F_HAS_TZ
| F_HAS_L5_FLASH_REGS
,
553 .flash_regs_base
= 0x40022000,
554 .fsize_addr
= 0x0BFA05E0,
555 .otp_base
= 0x0BFA0000,
559 .id
= DEVID_STM32G49_G4AXX
,
560 .revs
= stm32g49_g4axx_revs
,
561 .num_revs
= ARRAY_SIZE(stm32g49_g4axx_revs
),
562 .device_str
= "STM32G49/G4Axx",
563 .max_flash_size_kb
= 512,
565 .flash_regs_base
= 0x40022000,
566 .fsize_addr
= 0x1FFF75E0,
567 .otp_base
= 0x1FFF7000,
571 .id
= DEVID_STM32U57_U58XX
,
572 .revs
= stm32u57_u58xx_revs
,
573 .num_revs
= ARRAY_SIZE(stm32u57_u58xx_revs
),
574 .device_str
= "STM32U57/U58xx",
575 .max_flash_size_kb
= 2048,
576 .flags
= F_HAS_DUAL_BANK
| F_QUAD_WORD_PROG
| F_HAS_TZ
| F_HAS_L5_FLASH_REGS
,
577 .flash_regs_base
= 0x40022000,
578 .fsize_addr
= 0x0BFA07A0,
579 .otp_base
= 0x0BFA0000,
583 .id
= DEVID_STM32WB1XX
,
584 .revs
= stm32wb1xx_revs
,
585 .num_revs
= ARRAY_SIZE(stm32wb1xx_revs
),
586 .device_str
= "STM32WB1x",
587 .max_flash_size_kb
= 320,
589 .flash_regs_base
= 0x58004000,
590 .fsize_addr
= 0x1FFF75E0,
591 .otp_base
= 0x1FFF7000,
595 .id
= DEVID_STM32WB5XX
,
596 .revs
= stm32wb5xx_revs
,
597 .num_revs
= ARRAY_SIZE(stm32wb5xx_revs
),
598 .device_str
= "STM32WB5x",
599 .max_flash_size_kb
= 1024,
601 .flash_regs_base
= 0x58004000,
602 .fsize_addr
= 0x1FFF75E0,
603 .otp_base
= 0x1FFF7000,
607 .id
= DEVID_STM32WB3XX
,
608 .revs
= stm32wb3xx_revs
,
609 .num_revs
= ARRAY_SIZE(stm32wb3xx_revs
),
610 .device_str
= "STM32WB3x",
611 .max_flash_size_kb
= 512,
613 .flash_regs_base
= 0x58004000,
614 .fsize_addr
= 0x1FFF75E0,
615 .otp_base
= 0x1FFF7000,
619 .id
= DEVID_STM32WLE_WL5XX
,
620 .revs
= stm32wle_wl5xx_revs
,
621 .num_revs
= ARRAY_SIZE(stm32wle_wl5xx_revs
),
622 .device_str
= "STM32WLE/WL5x",
623 .max_flash_size_kb
= 256,
625 .flash_regs_base
= 0x58004000,
626 .fsize_addr
= 0x1FFF75E0,
627 .otp_base
= 0x1FFF7000,
632 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
633 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command
)
635 struct stm32l4_flash_bank
*stm32l4_info
;
638 return ERROR_COMMAND_SYNTAX_ERROR
;
640 /* fix-up bank base address: 0 is used for normal flash memory */
642 bank
->base
= STM32_FLASH_BANK_BASE
;
644 stm32l4_info
= calloc(1, sizeof(struct stm32l4_flash_bank
));
646 return ERROR_FAIL
; /* Checkme: What better error to use?*/
647 bank
->driver_priv
= stm32l4_info
;
649 stm32l4_info
->probed
= false;
650 stm32l4_info
->otp_enabled
= false;
651 stm32l4_info
->user_bank_size
= bank
->size
;
656 /* bitmap helper extension */
662 static void bitmap_to_ranges(unsigned long *bitmap
, unsigned int nbits
,
663 struct range
*ranges
, unsigned int *ranges_count
) {
665 bool last_bit
= 0, cur_bit
;
666 for (unsigned int i
= 0; i
< nbits
; i
++) {
667 cur_bit
= test_bit(i
, bitmap
);
669 if (cur_bit
&& !last_bit
) {
671 ranges
[*ranges_count
- 1].start
= i
;
672 ranges
[*ranges_count
- 1].end
= i
;
673 } else if (cur_bit
&& last_bit
) {
674 /* update (increment) the end this range */
675 ranges
[*ranges_count
- 1].end
= i
;
682 static inline int range_print_one(struct range
*range
, char *str
)
684 if (range
->start
== range
->end
)
685 return sprintf(str
, "[%d]", range
->start
);
687 return sprintf(str
, "[%d,%d]", range
->start
, range
->end
);
690 static char *range_print_alloc(struct range
*ranges
, unsigned int ranges_count
)
692 /* each range will be printed like the following: [start,end]
693 * start and end, both are unsigned int, an unsigned int takes 10 characters max
694 * plus 3 characters for '[', ',' and ']'
695 * thus means each range can take maximum 23 character
696 * after each range we add a ' ' as separator and finally we need the '\0'
697 * if the ranges_count is zero we reserve one char for '\0' to return an empty string */
698 char *str
= calloc(1, ranges_count
* (24 * sizeof(char)) + 1);
701 for (unsigned int i
= 0; i
< ranges_count
; i
++) {
702 ptr
+= range_print_one(&(ranges
[i
]), ptr
);
704 if (i
< ranges_count
- 1)
711 /* end of bitmap helper extension */
713 static inline bool stm32l4_is_otp(struct flash_bank
*bank
)
715 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
716 return bank
->base
== stm32l4_info
->part_info
->otp_base
;
719 static int stm32l4_otp_enable(struct flash_bank
*bank
, bool enable
)
721 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
723 if (!stm32l4_is_otp(bank
))
726 char *op_str
= enable
? "enabled" : "disabled";
728 LOG_INFO("OTP memory (bank #%d) is %s%s for write commands",
730 stm32l4_info
->otp_enabled
== enable
? "already " : "",
733 stm32l4_info
->otp_enabled
= enable
;
738 static inline bool stm32l4_otp_is_enabled(struct flash_bank
*bank
)
740 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
741 return stm32l4_info
->otp_enabled
;
744 static void stm32l4_sync_rdp_tzen(struct flash_bank
*bank
)
746 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
750 if (stm32l4_info
->part_info
->flags
& F_HAS_TZ
)
751 tzen
= (stm32l4_info
->optr
& FLASH_TZEN
) != 0;
753 uint32_t rdp
= stm32l4_info
->optr
& FLASH_RDP_MASK
;
755 /* for devices without TrustZone:
756 * RDP level 0 and 2 values are to 0xAA and 0xCC
757 * Any other value corresponds to RDP level 1
758 * for devices with TrusZone:
759 * RDP level 0 and 2 values are 0xAA and 0xCC
760 * RDP level 0.5 value is 0x55 only if TZEN = 1
761 * Any other value corresponds to RDP level 1, including 0x55 if TZEN = 0
764 if (rdp
!= RDP_LEVEL_0
&& rdp
!= RDP_LEVEL_2
) {
765 if (!tzen
|| (tzen
&& rdp
!= RDP_LEVEL_0_5
))
769 stm32l4_info
->tzen
= tzen
;
770 stm32l4_info
->rdp
= rdp
;
773 static inline uint32_t stm32l4_get_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
)
775 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
776 return stm32l4_info
->flash_regs_base
+ reg_offset
;
779 static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank
*bank
,
780 enum stm32l4_flash_reg_index reg_index
)
782 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
783 return stm32l4_get_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
]);
786 static inline int stm32l4_read_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t *value
)
788 return target_read_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
791 static inline int stm32l4_read_flash_reg_by_index(struct flash_bank
*bank
,
792 enum stm32l4_flash_reg_index reg_index
, uint32_t *value
)
794 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
795 return stm32l4_read_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
], value
);
798 static inline int stm32l4_write_flash_reg(struct flash_bank
*bank
, uint32_t reg_offset
, uint32_t value
)
800 return target_write_u32(bank
->target
, stm32l4_get_flash_reg(bank
, reg_offset
), value
);
803 static inline int stm32l4_write_flash_reg_by_index(struct flash_bank
*bank
,
804 enum stm32l4_flash_reg_index reg_index
, uint32_t value
)
806 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
807 return stm32l4_write_flash_reg(bank
, stm32l4_info
->flash_regs
[reg_index
], value
);
810 static int stm32l4_wait_status_busy(struct flash_bank
*bank
, int timeout
)
812 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
814 int retval
= ERROR_OK
;
816 /* wait for busy to clear */
818 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, &status
);
819 if (retval
!= ERROR_OK
)
821 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
822 if ((status
& stm32l4_info
->sr_bsy_mask
) == 0)
824 if (timeout
-- <= 0) {
825 LOG_ERROR("timed out waiting for flash");
831 if (status
& FLASH_WRPERR
) {
832 LOG_ERROR("stm32x device protected");
836 /* Clear but report errors */
837 if (status
& FLASH_ERROR
) {
838 if (retval
== ERROR_OK
)
840 /* If this operation fails, we ignore it and report the original
843 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, status
& FLASH_ERROR
);
849 /** set all FLASH_SECBB registers to the same value */
850 static int stm32l4_set_secbb(struct flash_bank
*bank
, uint32_t value
)
852 /* This function should be used only with device with TrustZone, do just a security check */
853 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
854 assert(stm32l4_info
->part_info
->flags
& F_HAS_TZ
);
856 /* based on RM0438 Rev6 for STM32L5x devices:
857 * to modify a page block-based security attribution, it is recommended to
858 * 1- check that no flash operation is ongoing on the related page
859 * 2- add ISB instruction after modifying the page security attribute in SECBBxRy
860 * this step is not need in case of JTAG direct access
862 int retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
863 if (retval
!= ERROR_OK
)
866 /* write SECBBxRy registers */
867 LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value
);
869 const uint8_t secbb_regs
[] = {
870 FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
871 FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
875 unsigned int num_secbb_regs
= ARRAY_SIZE(secbb_regs
);
877 /* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
878 * then consider only the first half of secbb_regs
880 if (!stm32l4_info
->dual_bank_mode
)
883 for (unsigned int i
= 0; i
< num_secbb_regs
; i
++) {
884 retval
= stm32l4_write_flash_reg(bank
, secbb_regs
[i
], value
);
885 if (retval
!= ERROR_OK
)
892 static inline int stm32l4_get_flash_cr_with_lock_index(struct flash_bank
*bank
)
894 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
895 return (stm32l4_info
->flash_regs
[STM32_FLASH_CR_WLK_INDEX
]) ?
896 STM32_FLASH_CR_WLK_INDEX
: STM32_FLASH_CR_INDEX
;
899 static int stm32l4_unlock_reg(struct flash_bank
*bank
)
901 const uint32_t flash_cr_index
= stm32l4_get_flash_cr_with_lock_index(bank
);
904 /* first check if not already unlocked
905 * otherwise writing on STM32_FLASH_KEYR will fail
907 int retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
908 if (retval
!= ERROR_OK
)
911 if ((ctrl
& FLASH_LOCK
) == 0)
914 /* unlock flash registers */
915 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_KEYR_INDEX
, KEY1
);
916 if (retval
!= ERROR_OK
)
919 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_KEYR_INDEX
, KEY2
);
920 if (retval
!= ERROR_OK
)
923 retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
924 if (retval
!= ERROR_OK
)
927 if (ctrl
& FLASH_LOCK
) {
928 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
929 return ERROR_TARGET_FAILURE
;
935 static int stm32l4_unlock_option_reg(struct flash_bank
*bank
)
937 const uint32_t flash_cr_index
= stm32l4_get_flash_cr_with_lock_index(bank
);
940 int retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
941 if (retval
!= ERROR_OK
)
944 if ((ctrl
& FLASH_OPTLOCK
) == 0)
947 /* unlock option registers */
948 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_OPTKEYR_INDEX
, OPTKEY1
);
949 if (retval
!= ERROR_OK
)
952 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_OPTKEYR_INDEX
, OPTKEY2
);
953 if (retval
!= ERROR_OK
)
956 retval
= stm32l4_read_flash_reg_by_index(bank
, flash_cr_index
, &ctrl
);
957 if (retval
!= ERROR_OK
)
960 if (ctrl
& FLASH_OPTLOCK
) {
961 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
962 return ERROR_TARGET_FAILURE
;
968 static int stm32l4_perform_obl_launch(struct flash_bank
*bank
)
972 retval
= stm32l4_unlock_reg(bank
);
973 if (retval
!= ERROR_OK
)
976 retval
= stm32l4_unlock_option_reg(bank
);
977 if (retval
!= ERROR_OK
)
980 /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
981 * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
982 * "Note: If the read protection is set while the debugger is still
983 * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
986 /* "Setting OBL_LAUNCH generates a reset so the option byte loading is performed under system reset" */
987 /* Due to this reset ST-Link reports an SWD_DP_ERROR, despite the write was successful,
988 * then just ignore the returned value */
989 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_OBL_LAUNCH
);
991 /* Need to re-probe after change */
992 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
993 stm32l4_info
->probed
= false;
996 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
),
997 FLASH_LOCK
| FLASH_OPTLOCK
);
999 if (retval
!= ERROR_OK
)
1005 static int stm32l4_write_option(struct flash_bank
*bank
, uint32_t reg_offset
,
1006 uint32_t value
, uint32_t mask
)
1008 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1009 uint32_t optiondata
;
1010 int retval
, retval2
;
1012 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &optiondata
);
1013 if (retval
!= ERROR_OK
)
1016 /* for STM32L5 and similar devices, use always non-secure
1017 * registers for option bytes programming */
1018 const uint32_t *saved_flash_regs
= stm32l4_info
->flash_regs
;
1019 if (stm32l4_info
->part_info
->flags
& F_HAS_L5_FLASH_REGS
)
1020 stm32l4_info
->flash_regs
= stm32l5_ns_flash_regs
;
1022 retval
= stm32l4_unlock_reg(bank
);
1023 if (retval
!= ERROR_OK
)
1026 retval
= stm32l4_unlock_option_reg(bank
);
1027 if (retval
!= ERROR_OK
)
1030 optiondata
= (optiondata
& ~mask
) | (value
& mask
);
1032 retval
= stm32l4_write_flash_reg(bank
, reg_offset
, optiondata
);
1033 if (retval
!= ERROR_OK
)
1036 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_OPTSTRT
);
1037 if (retval
!= ERROR_OK
)
1040 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1043 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
),
1044 FLASH_LOCK
| FLASH_OPTLOCK
);
1045 stm32l4_info
->flash_regs
= saved_flash_regs
;
1047 if (retval
!= ERROR_OK
)
1053 static int stm32l4_get_one_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
,
1054 enum stm32l4_flash_reg_index reg_idx
, int offset
)
1056 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1059 wrpxy
->reg_idx
= reg_idx
;
1060 wrpxy
->offset
= offset
;
1062 ret
= stm32l4_read_flash_reg_by_index(bank
, wrpxy
->reg_idx
, &wrpxy
->value
);
1063 if (ret
!= ERROR_OK
)
1066 wrpxy
->first
= (wrpxy
->value
& stm32l4_info
->wrpxxr_mask
) + wrpxy
->offset
;
1067 wrpxy
->last
= ((wrpxy
->value
>> 16) & stm32l4_info
->wrpxxr_mask
) + wrpxy
->offset
;
1068 wrpxy
->used
= wrpxy
->first
<= wrpxy
->last
;
1073 static int stm32l4_get_all_wrpxy(struct flash_bank
*bank
, enum stm32_bank_id dev_bank_id
,
1074 struct stm32l4_wrp
*wrpxy
, unsigned int *n_wrp
)
1076 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1081 /* for single bank devices there is 2 WRP regions.
1082 * for dual bank devices there is 2 WRP regions per bank,
1083 * if configured as single bank only 2 WRP are usable
1084 * except for STM32L4R/S/P/Q, G4 cat3, L5 ... all 4 WRP are usable
1085 * note: this should be revised, if a device will have the SWAP banks option
1088 int wrp2y_sectors_offset
= -1; /* -1 : unused */
1090 /* if bank_id is BANK1 or ALL_BANKS */
1091 if (dev_bank_id
!= STM32_BANK2
) {
1092 /* get FLASH_WRP1AR */
1093 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP1AR_INDEX
, 0);
1094 if (ret
!= ERROR_OK
)
1098 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP1BR_INDEX
, 0);
1099 if (ret
!= ERROR_OK
)
1102 /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
1103 if ((stm32l4_info
->part_info
->flags
& F_USE_ALL_WRPXX
) && !stm32l4_info
->dual_bank_mode
)
1104 wrp2y_sectors_offset
= 0;
1107 /* if bank_id is BANK2 or ALL_BANKS */
1108 if (dev_bank_id
!= STM32_BANK1
&& stm32l4_info
->dual_bank_mode
)
1109 wrp2y_sectors_offset
= stm32l4_info
->bank1_sectors
;
1111 if (wrp2y_sectors_offset
>= 0) {
1113 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP2AR_INDEX
, wrp2y_sectors_offset
);
1114 if (ret
!= ERROR_OK
)
1118 ret
= stm32l4_get_one_wrpxy(bank
, &wrpxy
[(*n_wrp
)++], STM32_FLASH_WRP2BR_INDEX
, wrp2y_sectors_offset
);
1119 if (ret
!= ERROR_OK
)
1126 static int stm32l4_write_one_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
)
1128 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1130 int wrp_start
= wrpxy
->first
- wrpxy
->offset
;
1131 int wrp_end
= wrpxy
->last
- wrpxy
->offset
;
1133 uint32_t wrp_value
= (wrp_start
& stm32l4_info
->wrpxxr_mask
) | ((wrp_end
& stm32l4_info
->wrpxxr_mask
) << 16);
1135 return stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[wrpxy
->reg_idx
], wrp_value
, 0xffffffff);
1138 static int stm32l4_write_all_wrpxy(struct flash_bank
*bank
, struct stm32l4_wrp
*wrpxy
, unsigned int n_wrp
)
1142 for (unsigned int i
= 0; i
< n_wrp
; i
++) {
1143 ret
= stm32l4_write_one_wrpxy(bank
, &wrpxy
[i
]);
1144 if (ret
!= ERROR_OK
)
1151 static int stm32l4_protect_check(struct flash_bank
*bank
)
1154 struct stm32l4_wrp wrpxy
[4];
1156 int ret
= stm32l4_get_all_wrpxy(bank
, STM32_ALL_BANKS
, wrpxy
, &n_wrp
);
1157 if (ret
!= ERROR_OK
)
1160 /* initialize all sectors as unprotected */
1161 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
1162 bank
->sectors
[i
].is_protected
= 0;
1164 /* now check WRPxy and mark the protected sectors */
1165 for (unsigned int i
= 0; i
< n_wrp
; i
++) {
1166 if (wrpxy
[i
].used
) {
1167 for (int s
= wrpxy
[i
].first
; s
<= wrpxy
[i
].last
; s
++)
1168 bank
->sectors
[s
].is_protected
= 1;
1175 static int stm32l4_erase(struct flash_bank
*bank
, unsigned int first
,
1178 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1179 int retval
, retval2
;
1181 assert((first
<= last
) && (last
< bank
->num_sectors
));
1183 if (stm32l4_is_otp(bank
)) {
1184 LOG_ERROR("cannot erase OTP memory");
1185 return ERROR_FLASH_OPER_UNSUPPORTED
;
1188 if (bank
->target
->state
!= TARGET_HALTED
) {
1189 LOG_ERROR("Target not halted");
1190 return ERROR_TARGET_NOT_HALTED
;
1193 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1194 /* set all FLASH pages as secure */
1195 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
1196 if (retval
!= ERROR_OK
) {
1197 /* restore all FLASH pages as non-secure */
1198 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
1203 retval
= stm32l4_unlock_reg(bank
);
1204 if (retval
!= ERROR_OK
)
1209 To erase a sector, follow the procedure below:
1210 1. Check that no Flash memory operation is ongoing by
1211 checking the BSY bit in the FLASH_SR register
1212 2. Set the PER bit and select the page and bank
1213 you wish to erase in the FLASH_CR register
1214 3. Set the STRT bit in the FLASH_CR register
1215 4. Wait for the BSY bit to be cleared
1218 for (unsigned int i
= first
; i
<= last
; i
++) {
1219 uint32_t erase_flags
;
1220 erase_flags
= FLASH_PER
| FLASH_STRT
;
1222 if (i
>= stm32l4_info
->bank1_sectors
) {
1224 snb
= i
- stm32l4_info
->bank1_sectors
;
1225 erase_flags
|= snb
<< FLASH_PAGE_SHIFT
| stm32l4_info
->cr_bker_mask
;
1227 erase_flags
|= i
<< FLASH_PAGE_SHIFT
;
1228 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, erase_flags
);
1229 if (retval
!= ERROR_OK
)
1232 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1233 if (retval
!= ERROR_OK
)
1238 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
), FLASH_LOCK
);
1240 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1241 /* restore all FLASH pages as non-secure */
1242 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
1243 if (retval3
!= ERROR_OK
)
1247 if (retval
!= ERROR_OK
)
1253 static int stm32l4_protect_same_bank(struct flash_bank
*bank
, enum stm32_bank_id bank_id
, int set
,
1254 unsigned int first
, unsigned int last
)
1258 /* check if the desired protection is already configured */
1259 for (i
= first
; i
<= last
; i
++) {
1260 if (bank
->sectors
[i
].is_protected
!= set
)
1262 else if (i
== last
) {
1263 LOG_INFO("The specified sectors are already %s", set
? "protected" : "unprotected");
1268 /* all sectors from first to last (or part of them) could have different
1269 * protection other than the requested */
1271 struct stm32l4_wrp wrpxy
[4];
1273 int ret
= stm32l4_get_all_wrpxy(bank
, bank_id
, wrpxy
, &n_wrp
);
1274 if (ret
!= ERROR_OK
)
1277 /* use bitmap and range helpers to optimize the WRP usage */
1278 DECLARE_BITMAP(pages
, bank
->num_sectors
);
1279 bitmap_zero(pages
, bank
->num_sectors
);
1281 for (i
= 0; i
< n_wrp
; i
++) {
1282 if (wrpxy
[i
].used
) {
1283 for (int p
= wrpxy
[i
].first
; p
<= wrpxy
[i
].last
; p
++)
1288 /* we have at most 'n_wrp' WRP areas
1289 * add one range if the user is trying to protect a fifth range */
1290 struct range ranges
[n_wrp
+ 1];
1291 unsigned int ranges_count
= 0;
1293 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1295 /* pretty-print the currently protected ranges */
1296 if (ranges_count
> 0) {
1297 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1298 LOG_DEBUG("current protected areas: %s", ranges_str
);
1301 LOG_DEBUG("current protected areas: none");
1303 if (set
) { /* flash protect */
1304 for (i
= first
; i
<= last
; i
++)
1306 } else { /* flash unprotect */
1307 for (i
= first
; i
<= last
; i
++)
1308 clear_bit(i
, pages
);
1311 /* check the ranges_count after the user request */
1312 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
1314 /* pretty-print the requested areas for protection */
1315 if (ranges_count
> 0) {
1316 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
1317 LOG_DEBUG("requested areas for protection: %s", ranges_str
);
1320 LOG_DEBUG("requested areas for protection: none");
1322 if (ranges_count
> n_wrp
) {
1323 LOG_ERROR("cannot set the requested protection "
1324 "(only %u write protection areas are available)" , n_wrp
);
1328 /* re-init all WRPxy as disabled (first > last)*/
1329 for (i
= 0; i
< n_wrp
; i
++) {
1330 wrpxy
[i
].first
= wrpxy
[i
].offset
+ 1;
1331 wrpxy
[i
].last
= wrpxy
[i
].offset
;
1334 /* then configure WRPxy areas */
1335 for (i
= 0; i
< ranges_count
; i
++) {
1336 wrpxy
[i
].first
= ranges
[i
].start
;
1337 wrpxy
[i
].last
= ranges
[i
].end
;
1340 /* finally write WRPxy registers */
1341 return stm32l4_write_all_wrpxy(bank
, wrpxy
, n_wrp
);
1344 static int stm32l4_protect(struct flash_bank
*bank
, int set
, unsigned int first
, unsigned int last
)
1346 struct target
*target
= bank
->target
;
1347 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1349 if (stm32l4_is_otp(bank
)) {
1350 LOG_ERROR("cannot protect/unprotect OTP memory");
1351 return ERROR_FLASH_OPER_UNSUPPORTED
;
1354 if (target
->state
!= TARGET_HALTED
) {
1355 LOG_ERROR("Target not halted");
1356 return ERROR_TARGET_NOT_HALTED
;
1359 /* refresh the sectors' protection */
1360 int ret
= stm32l4_protect_check(bank
);
1361 if (ret
!= ERROR_OK
)
1364 /* the requested sectors could be located into bank1 and/or bank2 */
1365 if (last
< stm32l4_info
->bank1_sectors
) {
1366 return stm32l4_protect_same_bank(bank
, STM32_BANK1
, set
, first
, last
);
1367 } else if (first
>= stm32l4_info
->bank1_sectors
) {
1368 return stm32l4_protect_same_bank(bank
, STM32_BANK2
, set
, first
, last
);
1370 ret
= stm32l4_protect_same_bank(bank
, STM32_BANK1
, set
, first
, stm32l4_info
->bank1_sectors
- 1);
1371 if (ret
!= ERROR_OK
)
1374 return stm32l4_protect_same_bank(bank
, STM32_BANK2
, set
, stm32l4_info
->bank1_sectors
, last
);
1378 /* count is the size divided by stm32l4_info->data_width */
1379 static int stm32l4_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
1380 uint32_t offset
, uint32_t count
)
1382 struct target
*target
= bank
->target
;
1383 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1384 struct working_area
*write_algorithm
;
1385 struct working_area
*source
;
1386 uint32_t address
= bank
->base
+ offset
;
1387 struct reg_param reg_params
[5];
1388 struct armv7m_algorithm armv7m_info
;
1389 int retval
= ERROR_OK
;
1391 static const uint8_t stm32l4_flash_write_code
[] = {
1392 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
1395 if (target_alloc_working_area(target
, sizeof(stm32l4_flash_write_code
),
1396 &write_algorithm
) != ERROR_OK
) {
1397 LOG_WARNING("no working area available, can't do block memory writes");
1398 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1401 retval
= target_write_buffer(target
, write_algorithm
->address
,
1402 sizeof(stm32l4_flash_write_code
),
1403 stm32l4_flash_write_code
);
1404 if (retval
!= ERROR_OK
) {
1405 target_free_working_area(target
, write_algorithm
);
1409 /* data_width should be multiple of double-word */
1410 assert(stm32l4_info
->data_width
% 8 == 0);
1411 const size_t extra_size
= sizeof(struct stm32l4_work_area
);
1412 uint32_t buffer_size
= target_get_working_area_avail(target
) - extra_size
;
1413 /* buffer_size should be multiple of stm32l4_info->data_width */
1414 buffer_size
&= ~(stm32l4_info
->data_width
- 1);
1416 if (buffer_size
< 256) {
1417 LOG_WARNING("large enough working area not available, can't do block memory writes");
1418 target_free_working_area(target
, write_algorithm
);
1419 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1420 } else if (buffer_size
> 16384) {
1421 /* probably won't benefit from more than 16k ... */
1422 buffer_size
= 16384;
1425 if (target_alloc_working_area_try(target
, buffer_size
+ extra_size
, &source
) != ERROR_OK
) {
1426 LOG_ERROR("allocating working area failed");
1427 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1430 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
1431 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
1433 /* contrib/loaders/flash/stm32/stm32l4x.c:write() arguments */
1434 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* stm32l4_work_area ptr , status (out) */
1435 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
1436 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
1437 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (of stm32l4_info->data_width) */
1439 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1440 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
1441 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
1442 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
1444 /* write algo stack pointer */
1445 init_reg_param(®_params
[4], "sp", 32, PARAM_OUT
);
1446 buf_set_u32(reg_params
[4].value
, 0, 32, source
->address
+
1447 offsetof(struct stm32l4_work_area
, stack
) + LDR_STACK_SIZE
);
1449 struct stm32l4_loader_params loader_extra_params
;
1451 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_sr_addr
,
1452 stm32l4_get_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
));
1453 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_cr_addr
,
1454 stm32l4_get_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
));
1455 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_word_size
,
1456 stm32l4_info
->data_width
);
1457 target_buffer_set_u32(target
, (uint8_t *) &loader_extra_params
.flash_sr_bsy_mask
,
1458 stm32l4_info
->sr_bsy_mask
);
1460 retval
= target_write_buffer(target
, source
->address
, sizeof(loader_extra_params
),
1461 (uint8_t *) &loader_extra_params
);
1462 if (retval
!= ERROR_OK
)
1465 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, stm32l4_info
->data_width
,
1467 ARRAY_SIZE(reg_params
), reg_params
,
1468 source
->address
+ offsetof(struct stm32l4_work_area
, fifo
),
1469 source
->size
- offsetof(struct stm32l4_work_area
, fifo
),
1470 write_algorithm
->address
, 0,
1473 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
1474 LOG_ERROR("error executing stm32l4 flash write algorithm");
1477 stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, &error
);
1478 error
&= FLASH_ERROR
;
1480 if (error
& FLASH_WRPERR
)
1481 LOG_ERROR("flash memory write protected");
1484 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
1485 /* Clear but report errors */
1486 stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_SR_INDEX
, error
);
1487 retval
= ERROR_FAIL
;
1491 target_free_working_area(target
, source
);
1492 target_free_working_area(target
, write_algorithm
);
1494 destroy_reg_param(®_params
[0]);
1495 destroy_reg_param(®_params
[1]);
1496 destroy_reg_param(®_params
[2]);
1497 destroy_reg_param(®_params
[3]);
1498 destroy_reg_param(®_params
[4]);
1503 /* count is the size divided by stm32l4_info->data_width */
1504 static int stm32l4_write_block_without_loader(struct flash_bank
*bank
, const uint8_t *buffer
,
1505 uint32_t offset
, uint32_t count
)
1507 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1508 struct target
*target
= bank
->target
;
1509 uint32_t address
= bank
->base
+ offset
;
1510 int retval
= ERROR_OK
;
1512 /* wait for BSY bit */
1513 retval
= stm32l4_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
1514 if (retval
!= ERROR_OK
)
1517 /* set PG in FLASH_CR */
1518 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, FLASH_PG
);
1519 if (retval
!= ERROR_OK
)
1523 /* write directly to flash memory */
1524 const uint8_t *src
= buffer
;
1525 const uint32_t data_width_in_words
= stm32l4_info
->data_width
/ 4;
1527 retval
= target_write_memory(target
, address
, 4, data_width_in_words
, src
);
1528 if (retval
!= ERROR_OK
)
1531 /* wait for BSY bit */
1532 retval
= stm32l4_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
1533 if (retval
!= ERROR_OK
)
1536 src
+= stm32l4_info
->data_width
;
1537 address
+= stm32l4_info
->data_width
;
1540 /* reset PG in FLASH_CR */
1541 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, 0);
1542 if (retval
!= ERROR_OK
)
1548 static int stm32l4_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1549 uint32_t offset
, uint32_t count
)
1551 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1552 int retval
= ERROR_OK
, retval2
;
1554 if (stm32l4_is_otp(bank
) && !stm32l4_otp_is_enabled(bank
)) {
1555 LOG_ERROR("OTP memory is disabled for write commands");
1559 if (bank
->target
->state
!= TARGET_HALTED
) {
1560 LOG_ERROR("Target not halted");
1561 return ERROR_TARGET_NOT_HALTED
;
1564 /* ensure that stm32l4_info->data_width is 'at least' a multiple of dword */
1565 assert(stm32l4_info
->data_width
% 8 == 0);
1567 /* The flash write must be aligned to the 'stm32l4_info->data_width' boundary.
1568 * The flash infrastructure ensures it, do just a security check */
1569 assert(offset
% stm32l4_info
->data_width
== 0);
1570 assert(count
% stm32l4_info
->data_width
== 0);
1572 /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
1573 * data to be written does not go into a gap:
1574 * suppose buffer is fully contained in bank from sector 0 to sector
1575 * num->sectors - 1 and sectors are ordered according to offset
1577 struct flash_sector
*head
= &bank
->sectors
[0];
1578 struct flash_sector
*tail
= &bank
->sectors
[bank
->num_sectors
- 1];
1580 while ((head
< tail
) && (offset
>= (head
+ 1)->offset
)) {
1581 /* buffer does not intersect head nor gap behind head */
1585 while ((head
< tail
) && (offset
+ count
<= (tail
- 1)->offset
+ (tail
- 1)->size
)) {
1586 /* buffer does not intersect tail nor gap before tail */
1590 LOG_DEBUG("data: 0x%08" PRIx32
" - 0x%08" PRIx32
", sectors: 0x%08" PRIx32
" - 0x%08" PRIx32
,
1591 offset
, offset
+ count
- 1, head
->offset
, tail
->offset
+ tail
->size
- 1);
1593 /* Now check that there is no gap from head to tail, this should work
1594 * even for multiple or non-symmetric gaps
1596 while (head
< tail
) {
1597 if (head
->offset
+ head
->size
!= (head
+ 1)->offset
) {
1598 LOG_ERROR("write into gap from " TARGET_ADDR_FMT
" to " TARGET_ADDR_FMT
,
1599 bank
->base
+ head
->offset
+ head
->size
,
1600 bank
->base
+ (head
+ 1)->offset
- 1);
1601 retval
= ERROR_FLASH_DST_OUT_OF_BANK
;
1606 if (retval
!= ERROR_OK
)
1609 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1610 /* set all FLASH pages as secure */
1611 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
1612 if (retval
!= ERROR_OK
) {
1613 /* restore all FLASH pages as non-secure */
1614 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
1619 retval
= stm32l4_unlock_reg(bank
);
1620 if (retval
!= ERROR_OK
)
1624 /* For TrustZone enabled devices, when TZEN is set and RDP level is 0.5,
1625 * the debug is possible only in non-secure state.
1626 * Thus means the flashloader will run in non-secure mode,
1627 * and the workarea need to be in non-secure RAM */
1628 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0_5
))
1629 LOG_WARNING("RDP = 0x55, the work-area should be in non-secure RAM (check SAU partitioning)");
1631 /* first try to write using the loader, for better performance */
1632 retval
= stm32l4_write_block(bank
, buffer
, offset
,
1633 count
/ stm32l4_info
->data_width
);
1635 /* if resources are not available write without a loader */
1636 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
1637 LOG_WARNING("falling back to programming without a flash loader (slower)");
1638 retval
= stm32l4_write_block_without_loader(bank
, buffer
, offset
,
1639 count
/ stm32l4_info
->data_width
);
1643 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
), FLASH_LOCK
);
1645 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1646 /* restore all FLASH pages as non-secure */
1647 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
1648 if (retval3
!= ERROR_OK
)
1652 if (retval
!= ERROR_OK
) {
1653 LOG_ERROR("block write failed");
1659 static int stm32l4_read_idcode(struct flash_bank
*bank
, uint32_t *id
)
1661 int retval
= ERROR_OK
;
1662 struct target
*target
= bank
->target
;
1664 /* try reading possible IDCODE registers, in the following order */
1665 uint32_t dbgmcu_idcode
[] = {DBGMCU_IDCODE_L4_G4
, DBGMCU_IDCODE_G0
, DBGMCU_IDCODE_L5
};
1667 for (unsigned int i
= 0; i
< ARRAY_SIZE(dbgmcu_idcode
); i
++) {
1668 retval
= target_read_u32(target
, dbgmcu_idcode
[i
], id
);
1669 if ((retval
== ERROR_OK
) && ((*id
& 0xfff) != 0) && ((*id
& 0xfff) != 0xfff))
1673 /* Workaround for STM32WL5x devices:
1674 * DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
1675 * to solve this read the UID64 (IEEE 64-bit unique device ID register) */
1677 struct armv7m_common
*armv7m
= target_to_armv7m_safe(target
);
1679 LOG_ERROR("Flash requires Cortex-M target");
1680 return ERROR_TARGET_INVALID
;
1683 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
1684 * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
1685 if (cortex_m_get_impl_part(target
) == CORTEX_M0P_PARTNO
&&
1686 armv7m
->debug_ap
&& armv7m
->debug_ap
->ap_num
== 1) {
1689 /* UID64 is contains
1690 * - Bits 63:32 : DEVNUM (unique device number, different for each individual device)
1691 * - Bits 31:08 : STID (company ID) = 0x0080E1
1692 * - Bits 07:00 : DEVID (device ID) = 0x15
1694 * read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
1696 retval
= target_read_u32(target
, UID64_IDS
, &uid64_ids
);
1697 if (retval
== ERROR_OK
&& uid64_ids
== UID64_IDS_STM32WL
) {
1698 /* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
1699 *id
= DEVID_STM32WLE_WL5XX
;
1704 LOG_ERROR("can't get the device id");
1705 return (retval
== ERROR_OK
) ? ERROR_FAIL
: retval
;
1708 static const char *get_stm32l4_rev_str(struct flash_bank
*bank
)
1710 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1711 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
1714 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1715 for (unsigned int i
= 0; i
< part_info
->num_revs
; i
++) {
1716 if (rev_id
== part_info
->revs
[i
].rev
)
1717 return part_info
->revs
[i
].str
;
1722 static const char *get_stm32l4_bank_type_str(struct flash_bank
*bank
)
1724 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1725 assert(stm32l4_info
->part_info
);
1726 return stm32l4_is_otp(bank
) ? "OTP" :
1727 stm32l4_info
->dual_bank_mode
? "Flash dual" :
1731 static int stm32l4_probe(struct flash_bank
*bank
)
1733 struct target
*target
= bank
->target
;
1734 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
1735 const struct stm32l4_part_info
*part_info
;
1736 uint16_t flash_size_kb
= 0xffff;
1738 if (!target_was_examined(target
)) {
1739 LOG_ERROR("Target not examined yet");
1740 return ERROR_TARGET_NOT_EXAMINED
;
1743 struct armv7m_common
*armv7m
= target_to_armv7m_safe(target
);
1745 LOG_ERROR("Flash requires Cortex-M target");
1746 return ERROR_TARGET_INVALID
;
1749 stm32l4_info
->probed
= false;
1751 /* read stm32 device id registers */
1752 int retval
= stm32l4_read_idcode(bank
, &stm32l4_info
->idcode
);
1753 if (retval
!= ERROR_OK
)
1756 const uint32_t device_id
= stm32l4_info
->idcode
& 0xFFF;
1758 for (unsigned int n
= 0; n
< ARRAY_SIZE(stm32l4_parts
); n
++) {
1759 if (device_id
== stm32l4_parts
[n
].id
) {
1760 stm32l4_info
->part_info
= &stm32l4_parts
[n
];
1765 if (!stm32l4_info
->part_info
) {
1766 LOG_WARNING("Cannot identify target as an %s family device.", device_families
);
1770 part_info
= stm32l4_info
->part_info
;
1771 const char *rev_str
= get_stm32l4_rev_str(bank
);
1772 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
1774 LOG_INFO("device idcode = 0x%08" PRIx32
" (%s - Rev %s : 0x%04x)",
1775 stm32l4_info
->idcode
, part_info
->device_str
, rev_str
, rev_id
);
1777 stm32l4_info
->flash_regs_base
= stm32l4_info
->part_info
->flash_regs_base
;
1778 stm32l4_info
->data_width
= (part_info
->flags
& F_QUAD_WORD_PROG
) ? 16 : 8;
1779 stm32l4_info
->cr_bker_mask
= FLASH_BKER
;
1780 stm32l4_info
->sr_bsy_mask
= FLASH_BSY
;
1782 /* Set flash write alignment boundaries.
1783 * Ask the flash infrastructure to ensure required alignment */
1784 bank
->write_start_alignment
= stm32l4_info
->data_width
;
1785 bank
->write_end_alignment
= stm32l4_info
->data_width
;
1787 /* Initialize the flash registers layout */
1788 if (part_info
->flags
& F_HAS_L5_FLASH_REGS
)
1789 stm32l4_info
->flash_regs
= stm32l5_ns_flash_regs
;
1791 stm32l4_info
->flash_regs
= stm32l4_flash_regs
;
1793 /* read flash option register */
1794 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &stm32l4_info
->optr
);
1795 if (retval
!= ERROR_OK
)
1798 stm32l4_sync_rdp_tzen(bank
);
1800 /* for devices with TrustZone, use flash secure registers when TZEN=1 and RDP is LEVEL_0 */
1801 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
1802 if (part_info
->flags
& F_HAS_L5_FLASH_REGS
) {
1803 stm32l4_info
->flash_regs_base
|= STM32L5_REGS_SEC_OFFSET
;
1804 stm32l4_info
->flash_regs
= stm32l5_s_flash_regs
;
1806 LOG_ERROR("BUG: device supported incomplete");
1807 return ERROR_NOT_IMPLEMENTED
;
1811 if (part_info
->flags
& F_HAS_TZ
)
1812 LOG_INFO("TZEN = %d : TrustZone %s by option bytes",
1814 stm32l4_info
->tzen
? "enabled" : "disabled");
1816 LOG_INFO("RDP level %s (0x%02X)",
1817 stm32l4_info
->rdp
== RDP_LEVEL_0
? "0" : stm32l4_info
->rdp
== RDP_LEVEL_0_5
? "0.5" : "1",
1820 if (stm32l4_is_otp(bank
)) {
1821 bank
->size
= part_info
->otp_size
;
1823 LOG_INFO("OTP size is %d bytes, base address is " TARGET_ADDR_FMT
, bank
->size
, bank
->base
);
1825 /* OTP memory is considered as one sector */
1826 free(bank
->sectors
);
1827 bank
->num_sectors
= 1;
1828 bank
->sectors
= alloc_block_array(0, part_info
->otp_size
, 1);
1830 if (!bank
->sectors
) {
1831 LOG_ERROR("failed to allocate bank sectors");
1835 stm32l4_info
->probed
= true;
1837 } else if (bank
->base
!= STM32_FLASH_BANK_BASE
&& bank
->base
!= STM32_FLASH_S_BANK_BASE
) {
1838 LOG_ERROR("invalid bank base address");
1842 /* get flash size from target. */
1843 retval
= target_read_u16(target
, part_info
->fsize_addr
, &flash_size_kb
);
1845 /* failed reading flash size or flash size invalid (early silicon),
1846 * default to max target family */
1847 if (retval
!= ERROR_OK
|| flash_size_kb
== 0xffff || flash_size_kb
== 0
1848 || flash_size_kb
> part_info
->max_flash_size_kb
) {
1849 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1850 part_info
->max_flash_size_kb
);
1851 flash_size_kb
= part_info
->max_flash_size_kb
;
1854 /* if the user sets the size manually then ignore the probed value
1855 * this allows us to work around devices that have a invalid flash size register value */
1856 if (stm32l4_info
->user_bank_size
) {
1857 LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
1858 flash_size_kb
= stm32l4_info
->user_bank_size
/ 1024;
1861 LOG_INFO("flash size = %d KiB", flash_size_kb
);
1863 /* did we assign a flash size? */
1864 assert((flash_size_kb
!= 0xffff) && flash_size_kb
);
1866 const bool is_max_flash_size
= flash_size_kb
== stm32l4_info
->part_info
->max_flash_size_kb
;
1868 stm32l4_info
->bank1_sectors
= 0;
1869 stm32l4_info
->hole_sectors
= 0;
1872 int page_size_kb
= 0;
1874 stm32l4_info
->dual_bank_mode
= false;
1876 switch (device_id
) {
1877 case DEVID_STM32L47_L48XX
:
1878 case DEVID_STM32L49_L4AXX
:
1879 /* if flash size is max (1M) the device is always dual bank
1880 * STM32L47/L48xx: has variants with 512K
1881 * STM32L49/L4Axx: has variants with 512 and 256
1882 * for these variants:
1883 * if DUAL_BANK = 0 -> single bank
1884 * else -> dual bank without gap
1885 * note: the page size is invariant
1888 num_pages
= flash_size_kb
/ page_size_kb
;
1889 stm32l4_info
->bank1_sectors
= num_pages
;
1891 /* check DUAL_BANK option bit if the flash is less than 1M */
1892 if (is_max_flash_size
|| (stm32l4_info
->optr
& FLASH_L4_DUAL_BANK
)) {
1893 stm32l4_info
->dual_bank_mode
= true;
1894 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1897 case DEVID_STM32L43_L44XX
:
1898 case DEVID_STM32C01XX
:
1899 case DEVID_STM32C03XX
:
1900 case DEVID_STM32G05_G06XX
:
1901 case DEVID_STM32G07_G08XX
:
1902 case DEVID_STM32L45_L46XX
:
1903 case DEVID_STM32L41_L42XX
:
1904 case DEVID_STM32G03_G04XX
:
1905 case DEVID_STM32G43_G44XX
:
1906 case DEVID_STM32G49_G4AXX
:
1907 case DEVID_STM32WB1XX
:
1908 /* single bank flash */
1910 num_pages
= flash_size_kb
/ page_size_kb
;
1911 stm32l4_info
->bank1_sectors
= num_pages
;
1913 case DEVID_STM32G0B_G0CXX
:
1914 /* single/dual bank depending on DUAL_BANK option bit */
1916 num_pages
= flash_size_kb
/ page_size_kb
;
1917 stm32l4_info
->bank1_sectors
= num_pages
;
1918 stm32l4_info
->cr_bker_mask
= FLASH_BKER_G0
;
1920 /* check DUAL_BANK bit */
1921 if (stm32l4_info
->optr
& FLASH_G0_DUAL_BANK
) {
1922 stm32l4_info
->sr_bsy_mask
= FLASH_BSY
| FLASH_BSY2
;
1923 stm32l4_info
->dual_bank_mode
= true;
1924 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1927 case DEVID_STM32G47_G48XX
:
1928 /* STM32G47/8 can be single/dual bank:
1929 * if DUAL_BANK = 0 -> single bank
1930 * else -> dual bank WITH gap
1933 num_pages
= flash_size_kb
/ page_size_kb
;
1934 stm32l4_info
->bank1_sectors
= num_pages
;
1935 if (stm32l4_info
->optr
& FLASH_G4_DUAL_BANK
) {
1936 stm32l4_info
->dual_bank_mode
= true;
1938 num_pages
= flash_size_kb
/ page_size_kb
;
1939 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1941 /* for devices with trimmed flash, there is a gap between both banks */
1942 stm32l4_info
->hole_sectors
=
1943 (part_info
->max_flash_size_kb
- flash_size_kb
) / (2 * page_size_kb
);
1946 case DEVID_STM32L4R_L4SXX
:
1947 case DEVID_STM32L4P_L4QXX
:
1948 /* STM32L4R/S can be single/dual bank:
1949 * if size = 2M check DBANK bit
1950 * if size = 1M check DB1M bit
1951 * STM32L4P/Q can be single/dual bank
1952 * if size = 1M check DBANK bit
1953 * if size = 512K check DB512K bit (same as DB1M bit)
1956 num_pages
= flash_size_kb
/ page_size_kb
;
1957 stm32l4_info
->bank1_sectors
= num_pages
;
1958 if ((is_max_flash_size
&& (stm32l4_info
->optr
& FLASH_L4R_DBANK
)) ||
1959 (!is_max_flash_size
&& (stm32l4_info
->optr
& FLASH_LRR_DB1M
))) {
1960 stm32l4_info
->dual_bank_mode
= true;
1962 num_pages
= flash_size_kb
/ page_size_kb
;
1963 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1966 case DEVID_STM32L55_L56XX
:
1967 /* STM32L55/L56xx can be single/dual bank:
1968 * if size = 512K check DBANK bit
1969 * if size = 256K check DB256K bit
1971 * default page size is 4kb, if DBANK = 1, the page size is 2kb.
1974 page_size_kb
= (stm32l4_info
->optr
& FLASH_L5_DBANK
) ? 2 : 4;
1975 num_pages
= flash_size_kb
/ page_size_kb
;
1976 stm32l4_info
->bank1_sectors
= num_pages
;
1978 if ((is_max_flash_size
&& (stm32l4_info
->optr
& FLASH_L5_DBANK
)) ||
1979 (!is_max_flash_size
&& (stm32l4_info
->optr
& FLASH_L5_DB256
))) {
1980 stm32l4_info
->dual_bank_mode
= true;
1981 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1984 case DEVID_STM32U57_U58XX
:
1985 /* if flash size is max (2M) the device is always dual bank
1986 * otherwise check DUALBANK
1989 num_pages
= flash_size_kb
/ page_size_kb
;
1990 stm32l4_info
->bank1_sectors
= num_pages
;
1991 if (is_max_flash_size
|| (stm32l4_info
->optr
& FLASH_U5_DUALBANK
)) {
1992 stm32l4_info
->dual_bank_mode
= true;
1993 stm32l4_info
->bank1_sectors
= num_pages
/ 2;
1996 case DEVID_STM32WB5XX
:
1997 case DEVID_STM32WB3XX
:
1998 /* single bank flash */
2000 num_pages
= flash_size_kb
/ page_size_kb
;
2001 stm32l4_info
->bank1_sectors
= num_pages
;
2003 case DEVID_STM32WLE_WL5XX
:
2004 /* single bank flash */
2006 num_pages
= flash_size_kb
/ page_size_kb
;
2007 stm32l4_info
->bank1_sectors
= num_pages
;
2009 /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
2010 * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
2011 if (armv7m
->debug_ap
&& armv7m
->debug_ap
->ap_num
== 1)
2012 stm32l4_info
->flash_regs
= stm32wl_cpu2_flash_regs
;
2015 LOG_ERROR("unsupported device");
2019 /* ensure that at least there is 1 flash sector / page */
2020 if (num_pages
== 0) {
2021 if (stm32l4_info
->user_bank_size
)
2022 LOG_ERROR("The specified flash size is less than page size");
2024 LOG_ERROR("Flash pages count cannot be zero");
2028 LOG_INFO("flash mode : %s-bank", stm32l4_info
->dual_bank_mode
? "dual" : "single");
2030 const int gap_size_kb
= stm32l4_info
->hole_sectors
* page_size_kb
;
2032 if (gap_size_kb
!= 0) {
2033 LOG_INFO("gap detected from 0x%08x to 0x%08x",
2034 STM32_FLASH_BANK_BASE
+ stm32l4_info
->bank1_sectors
2035 * page_size_kb
* 1024,
2036 STM32_FLASH_BANK_BASE
+ (stm32l4_info
->bank1_sectors
2037 * page_size_kb
+ gap_size_kb
) * 1024 - 1);
2040 /* number of significant bits in WRPxxR differs per device,
2041 * always right adjusted, on some devices non-implemented
2042 * bits read as '0', on others as '1' ...
2043 * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
2046 /* use *max_flash_size* instead of actual size as the trimmed versions
2047 * certainly use the same number of bits
2049 uint32_t max_pages
= stm32l4_info
->part_info
->max_flash_size_kb
/ page_size_kb
;
2051 /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
2052 stm32l4_info
->wrpxxr_mask
= ((max_pages
>> (stm32l4_info
->dual_bank_mode
? 1 : 0)) - 1);
2053 assert((stm32l4_info
->wrpxxr_mask
& 0xFFFF0000) == 0);
2054 LOG_DEBUG("WRPxxR mask 0x%04" PRIx16
, (uint16_t)stm32l4_info
->wrpxxr_mask
);
2056 free(bank
->sectors
);
2058 bank
->size
= (flash_size_kb
+ gap_size_kb
) * 1024;
2059 bank
->num_sectors
= num_pages
;
2060 bank
->sectors
= malloc(sizeof(struct flash_sector
) * bank
->num_sectors
);
2061 if (!bank
->sectors
) {
2062 LOG_ERROR("failed to allocate bank sectors");
2066 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
2067 bank
->sectors
[i
].offset
= i
* page_size_kb
* 1024;
2068 /* in dual bank configuration, if there is a gap between banks
2069 * we fix up the sector offset to consider this gap */
2070 if (i
>= stm32l4_info
->bank1_sectors
&& stm32l4_info
->hole_sectors
)
2071 bank
->sectors
[i
].offset
+= gap_size_kb
* 1024;
2072 bank
->sectors
[i
].size
= page_size_kb
* 1024;
2073 bank
->sectors
[i
].is_erased
= -1;
2074 bank
->sectors
[i
].is_protected
= 1;
2077 stm32l4_info
->probed
= true;
2081 static int stm32l4_auto_probe(struct flash_bank
*bank
)
2083 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2084 if (stm32l4_info
->probed
) {
2087 /* save flash_regs_base */
2088 uint32_t saved_flash_regs_base
= stm32l4_info
->flash_regs_base
;
2090 /* for devices with TrustZone, use NS flash registers to read OPTR */
2091 if (stm32l4_info
->part_info
->flags
& F_HAS_L5_FLASH_REGS
)
2092 stm32l4_info
->flash_regs_base
&= ~STM32L5_REGS_SEC_OFFSET
;
2094 /* read flash option register and re-probe if optr value is changed */
2095 int retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &optr_cur
);
2097 /* restore saved flash_regs_base */
2098 stm32l4_info
->flash_regs_base
= saved_flash_regs_base
;
2100 if (retval
!= ERROR_OK
)
2103 if (stm32l4_info
->optr
== optr_cur
)
2107 return stm32l4_probe(bank
);
2110 static int get_stm32l4_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
2112 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2113 const struct stm32l4_part_info
*part_info
= stm32l4_info
->part_info
;
2116 const uint16_t rev_id
= stm32l4_info
->idcode
>> 16;
2117 command_print_sameline(cmd
, "%s - Rev %s : 0x%04x", part_info
->device_str
,
2118 get_stm32l4_rev_str(bank
), rev_id
);
2119 if (stm32l4_info
->probed
)
2120 command_print_sameline(cmd
, " - %s-bank", get_stm32l4_bank_type_str(bank
));
2122 command_print_sameline(cmd
, "Cannot identify target as an %s device", device_families
);
2128 static int stm32l4_mass_erase(struct flash_bank
*bank
)
2130 int retval
, retval2
;
2131 struct target
*target
= bank
->target
;
2132 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2134 if (stm32l4_is_otp(bank
)) {
2135 LOG_ERROR("cannot erase OTP memory");
2136 return ERROR_FLASH_OPER_UNSUPPORTED
;
2139 uint32_t action
= FLASH_MER1
;
2141 if (stm32l4_info
->part_info
->flags
& F_HAS_DUAL_BANK
)
2142 action
|= FLASH_MER2
;
2144 if (target
->state
!= TARGET_HALTED
) {
2145 LOG_ERROR("Target not halted");
2146 return ERROR_TARGET_NOT_HALTED
;
2149 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
2150 /* set all FLASH pages as secure */
2151 retval
= stm32l4_set_secbb(bank
, FLASH_SECBB_SECURE
);
2152 if (retval
!= ERROR_OK
) {
2153 /* restore all FLASH pages as non-secure */
2154 stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
); /* ignore the return value */
2159 retval
= stm32l4_unlock_reg(bank
);
2160 if (retval
!= ERROR_OK
)
2163 /* mass erase flash memory */
2164 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
/ 10);
2165 if (retval
!= ERROR_OK
)
2168 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, action
);
2169 if (retval
!= ERROR_OK
)
2172 retval
= stm32l4_write_flash_reg_by_index(bank
, STM32_FLASH_CR_INDEX
, action
| FLASH_STRT
);
2173 if (retval
!= ERROR_OK
)
2176 retval
= stm32l4_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
2179 retval2
= stm32l4_write_flash_reg_by_index(bank
, stm32l4_get_flash_cr_with_lock_index(bank
), FLASH_LOCK
);
2181 if (stm32l4_info
->tzen
&& (stm32l4_info
->rdp
== RDP_LEVEL_0
)) {
2182 /* restore all FLASH pages as non-secure */
2183 int retval3
= stm32l4_set_secbb(bank
, FLASH_SECBB_NON_SECURE
);
2184 if (retval3
!= ERROR_OK
)
2188 if (retval
!= ERROR_OK
)
2194 COMMAND_HANDLER(stm32l4_handle_mass_erase_command
)
2197 command_print(CMD
, "stm32l4x mass_erase <STM32L4 bank>");
2198 return ERROR_COMMAND_SYNTAX_ERROR
;
2201 struct flash_bank
*bank
;
2202 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2203 if (retval
!= ERROR_OK
)
2206 retval
= stm32l4_mass_erase(bank
);
2207 if (retval
== ERROR_OK
)
2208 command_print(CMD
, "stm32l4x mass erase complete");
2210 command_print(CMD
, "stm32l4x mass erase failed");
2215 COMMAND_HANDLER(stm32l4_handle_option_read_command
)
2218 command_print(CMD
, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
2219 return ERROR_COMMAND_SYNTAX_ERROR
;
2222 struct flash_bank
*bank
;
2223 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2224 if (retval
!= ERROR_OK
)
2227 uint32_t reg_offset
, reg_addr
;
2230 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
2231 reg_addr
= stm32l4_get_flash_reg(bank
, reg_offset
);
2233 retval
= stm32l4_read_flash_reg(bank
, reg_offset
, &value
);
2234 if (retval
!= ERROR_OK
)
2237 command_print(CMD
, "Option Register: <0x%" PRIx32
"> = 0x%" PRIx32
"", reg_addr
, value
);
2242 COMMAND_HANDLER(stm32l4_handle_option_write_command
)
2245 command_print(CMD
, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
2246 return ERROR_COMMAND_SYNTAX_ERROR
;
2249 struct flash_bank
*bank
;
2250 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2251 if (retval
!= ERROR_OK
)
2254 uint32_t reg_offset
;
2256 uint32_t mask
= 0xFFFFFFFF;
2258 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], reg_offset
);
2259 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
2262 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[3], mask
);
2264 command_print(CMD
, "%s Option written.\n"
2265 "INFO: a reset or power cycle is required "
2266 "for the new settings to take effect.", bank
->driver
->name
);
2268 retval
= stm32l4_write_option(bank
, reg_offset
, value
, mask
);
2272 COMMAND_HANDLER(stm32l4_handle_trustzone_command
)
2274 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2275 return ERROR_COMMAND_SYNTAX_ERROR
;
2277 struct flash_bank
*bank
;
2278 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2279 if (retval
!= ERROR_OK
)
2282 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2283 if (!(stm32l4_info
->part_info
->flags
& F_HAS_TZ
)) {
2284 LOG_ERROR("This device does not have a TrustZone");
2288 retval
= stm32l4_read_flash_reg_by_index(bank
, STM32_FLASH_OPTR_INDEX
, &stm32l4_info
->optr
);
2289 if (retval
!= ERROR_OK
)
2292 stm32l4_sync_rdp_tzen(bank
);
2294 if (CMD_ARGC
== 1) {
2295 /* only display the TZEN value */
2296 LOG_INFO("Global TrustZone Security is %s", stm32l4_info
->tzen
? "enabled" : "disabled");
2301 COMMAND_PARSE_ENABLE(CMD_ARGV
[1], new_tzen
);
2303 if (new_tzen
== stm32l4_info
->tzen
) {
2304 LOG_INFO("The requested TZEN is already programmed");
2309 if (stm32l4_info
->rdp
!= RDP_LEVEL_0
) {
2310 LOG_ERROR("TZEN can be set only when RDP level is 0");
2313 retval
= stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2314 FLASH_TZEN
, FLASH_TZEN
);
2316 /* Deactivation of TZEN (from 1 to 0) is only possible when the RDP is
2317 * changing to level 0 (from level 1 to level 0 or from level 0.5 to level 0). */
2318 if (stm32l4_info
->rdp
!= RDP_LEVEL_1
&& stm32l4_info
->rdp
!= RDP_LEVEL_0_5
) {
2319 LOG_ERROR("Deactivation of TZEN is only possible when the RDP is changing to level 0");
2323 retval
= stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2324 RDP_LEVEL_0
, FLASH_RDP_MASK
| FLASH_TZEN
);
2327 if (retval
!= ERROR_OK
)
2330 return stm32l4_perform_obl_launch(bank
);
2333 COMMAND_HANDLER(stm32l4_handle_option_load_command
)
2336 return ERROR_COMMAND_SYNTAX_ERROR
;
2338 struct flash_bank
*bank
;
2339 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2340 if (retval
!= ERROR_OK
)
2343 retval
= stm32l4_perform_obl_launch(bank
);
2344 if (retval
!= ERROR_OK
) {
2345 command_print(CMD
, "stm32l4x option load failed");
2350 command_print(CMD
, "stm32l4x option load completed. Power-on reset might be required");
2355 COMMAND_HANDLER(stm32l4_handle_lock_command
)
2357 struct target
*target
= NULL
;
2360 return ERROR_COMMAND_SYNTAX_ERROR
;
2362 struct flash_bank
*bank
;
2363 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2364 if (retval
!= ERROR_OK
)
2367 if (stm32l4_is_otp(bank
)) {
2368 LOG_ERROR("cannot lock/unlock OTP memory");
2369 return ERROR_FLASH_OPER_UNSUPPORTED
;
2372 target
= bank
->target
;
2374 if (target
->state
!= TARGET_HALTED
) {
2375 LOG_ERROR("Target not halted");
2376 return ERROR_TARGET_NOT_HALTED
;
2379 /* set readout protection level 1 by erasing the RDP option byte */
2380 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2381 if (stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2382 RDP_LEVEL_1
, FLASH_RDP_MASK
) != ERROR_OK
) {
2383 command_print(CMD
, "%s failed to lock device", bank
->driver
->name
);
2390 COMMAND_HANDLER(stm32l4_handle_unlock_command
)
2392 struct target
*target
= NULL
;
2395 return ERROR_COMMAND_SYNTAX_ERROR
;
2397 struct flash_bank
*bank
;
2398 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2399 if (retval
!= ERROR_OK
)
2402 if (stm32l4_is_otp(bank
)) {
2403 LOG_ERROR("cannot lock/unlock OTP memory");
2404 return ERROR_FLASH_OPER_UNSUPPORTED
;
2407 target
= bank
->target
;
2409 if (target
->state
!= TARGET_HALTED
) {
2410 LOG_ERROR("Target not halted");
2411 return ERROR_TARGET_NOT_HALTED
;
2414 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2415 if (stm32l4_write_option(bank
, stm32l4_info
->flash_regs
[STM32_FLASH_OPTR_INDEX
],
2416 RDP_LEVEL_0
, FLASH_RDP_MASK
) != ERROR_OK
) {
2417 command_print(CMD
, "%s failed to unlock device", bank
->driver
->name
);
2424 COMMAND_HANDLER(stm32l4_handle_wrp_info_command
)
2426 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
2427 return ERROR_COMMAND_SYNTAX_ERROR
;
2429 struct flash_bank
*bank
;
2430 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2431 if (retval
!= ERROR_OK
)
2434 if (stm32l4_is_otp(bank
)) {
2435 LOG_ERROR("OTP memory does not have write protection areas");
2436 return ERROR_FLASH_OPER_UNSUPPORTED
;
2439 struct stm32l4_flash_bank
*stm32l4_info
= bank
->driver_priv
;
2440 enum stm32_bank_id dev_bank_id
= STM32_ALL_BANKS
;
2441 if (CMD_ARGC
== 2) {
2442 if (strcmp(CMD_ARGV
[1], "bank1") == 0)
2443 dev_bank_id
= STM32_BANK1
;
2444 else if (strcmp(CMD_ARGV
[1], "bank2") == 0)
2445 dev_bank_id
= STM32_BANK2
;
2447 return ERROR_COMMAND_ARGUMENT_INVALID
;
2450 if (dev_bank_id
== STM32_BANK2
) {
2451 if (!(stm32l4_info
->part_info
->flags
& F_HAS_DUAL_BANK
)) {
2452 LOG_ERROR("this device has no second bank");
2454 } else if (!stm32l4_info
->dual_bank_mode
) {
2455 LOG_ERROR("this device is configured in single bank mode");
2461 unsigned int n_wrp
, i
;
2462 struct stm32l4_wrp wrpxy
[4];
2464 ret
= stm32l4_get_all_wrpxy(bank
, dev_bank_id
, wrpxy
, &n_wrp
);
2465 if (ret
!= ERROR_OK
)
2468 /* use bitmap and range helpers to better describe protected areas */
2469 DECLARE_BITMAP(pages
, bank
->num_sectors
);
2470 bitmap_zero(pages
, bank
->num_sectors
);
2472 for (i
= 0; i
< n_wrp
; i
++) {
2473 if (wrpxy
[i
].used
) {
2474 for (int p
= wrpxy
[i
].first
; p
<= wrpxy
[i
].last
; p
++)
2479 /* we have at most 'n_wrp' WRP areas */
2480 struct range ranges
[n_wrp
];
2481 unsigned int ranges_count
= 0;
2483 bitmap_to_ranges(pages
, bank
->num_sectors
, ranges
, &ranges_count
);
2485 if (ranges_count
> 0) {
2486 /* pretty-print the protected ranges */
2487 char *ranges_str
= range_print_alloc(ranges
, ranges_count
);
2488 command_print(CMD
, "protected areas: %s", ranges_str
);
2491 command_print(CMD
, "no protected areas");
2496 COMMAND_HANDLER(stm32l4_handle_otp_command
)
2499 return ERROR_COMMAND_SYNTAX_ERROR
;
2501 struct flash_bank
*bank
;
2502 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
2503 if (retval
!= ERROR_OK
)
2506 if (!stm32l4_is_otp(bank
)) {
2507 command_print(CMD
, "the specified bank is not an OTP memory");
2510 if (strcmp(CMD_ARGV
[1], "enable") == 0)
2511 stm32l4_otp_enable(bank
, true);
2512 else if (strcmp(CMD_ARGV
[1], "disable") == 0)
2513 stm32l4_otp_enable(bank
, false);
2514 else if (strcmp(CMD_ARGV
[1], "show") == 0)
2515 command_print(CMD
, "OTP memory bank #%d is %s for write commands.",
2516 bank
->bank_number
, stm32l4_otp_is_enabled(bank
) ? "enabled" : "disabled");
2518 return ERROR_COMMAND_SYNTAX_ERROR
;
2523 static const struct command_registration stm32l4_exec_command_handlers
[] = {
2526 .handler
= stm32l4_handle_lock_command
,
2527 .mode
= COMMAND_EXEC
,
2529 .help
= "Lock entire flash device.",
2533 .handler
= stm32l4_handle_unlock_command
,
2534 .mode
= COMMAND_EXEC
,
2536 .help
= "Unlock entire protected flash device.",
2539 .name
= "mass_erase",
2540 .handler
= stm32l4_handle_mass_erase_command
,
2541 .mode
= COMMAND_EXEC
,
2543 .help
= "Erase entire flash device.",
2546 .name
= "option_read",
2547 .handler
= stm32l4_handle_option_read_command
,
2548 .mode
= COMMAND_EXEC
,
2549 .usage
= "bank_id reg_offset",
2550 .help
= "Read & Display device option bytes.",
2553 .name
= "option_write",
2554 .handler
= stm32l4_handle_option_write_command
,
2555 .mode
= COMMAND_EXEC
,
2556 .usage
= "bank_id reg_offset value mask",
2557 .help
= "Write device option bit fields with provided value.",
2560 .name
= "trustzone",
2561 .handler
= stm32l4_handle_trustzone_command
,
2562 .mode
= COMMAND_EXEC
,
2563 .usage
= "<bank_id> [enable|disable]",
2564 .help
= "Configure TrustZone security",
2568 .handler
= stm32l4_handle_wrp_info_command
,
2569 .mode
= COMMAND_EXEC
,
2570 .usage
= "bank_id [bank1|bank2]",
2571 .help
= "list the protected areas using WRP",
2574 .name
= "option_load",
2575 .handler
= stm32l4_handle_option_load_command
,
2576 .mode
= COMMAND_EXEC
,
2578 .help
= "Force re-load of device options (will cause device reset).",
2582 .handler
= stm32l4_handle_otp_command
,
2583 .mode
= COMMAND_EXEC
,
2584 .usage
= "<bank_id> <enable|disable|show>",
2585 .help
= "OTP (One Time Programmable) memory write enable/disable",
2587 COMMAND_REGISTRATION_DONE
2590 static const struct command_registration stm32l4_command_handlers
[] = {
2593 .mode
= COMMAND_ANY
,
2594 .help
= "stm32l4x flash command group",
2596 .chain
= stm32l4_exec_command_handlers
,
2598 COMMAND_REGISTRATION_DONE
2601 const struct flash_driver stm32l4x_flash
= {
2603 .commands
= stm32l4_command_handlers
,
2604 .flash_bank_command
= stm32l4_flash_bank_command
,
2605 .erase
= stm32l4_erase
,
2606 .protect
= stm32l4_protect
,
2607 .write
= stm32l4_write
,
2608 .read
= default_flash_read
,
2609 .probe
= stm32l4_probe
,
2610 .auto_probe
= stm32l4_auto_probe
,
2611 .erase_check
= default_flash_blank_check
,
2612 .protect_check
= stm32l4_protect_check
,
2613 .info
= get_stm32l4_info
,
2614 .free_driver_priv
= default_flash_free_driver_priv
,