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[openocd.git] / src / flash / nor / stm32f2x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/cortex_m.h>
33
34 /* Regarding performance:
35 *
36 * Short story - it might be best to leave the performance at
37 * current levels.
38 *
39 * You may see a jump in speed if you change to using
40 * 32bit words for the block programming.
41 *
42 * Its a shame you cannot use the double word as its
43 * even faster - but you require external VPP for that mode.
44 *
45 * Having said all that 16bit writes give us the widest vdd
46 * operating range, so may be worth adding a note to that effect.
47 *
48 */
49
50 /* Danger!!!! The STM32F1x and STM32F2x series actually have
51 * quite different flash controllers.
52 *
53 * What's more scary is that the names of the registers and their
54 * addresses are the same, but the actual bits and what they do are
55 * can be very different.
56 *
57 * To reduce testing complexity and dangers of regressions,
58 * a separate file is used for stm32fx2x.
59 *
60 * Sector sizes in kiBytes:
61 * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
62 * 1.5 MiByte part with 4 x 16, 1 x 64, 11 x 128.
63 * 2 MiByte part with 4 x 16, 1 x 64, 7 x 128, 4 x 16, 1 x 64, 7 x 128.
64 * 1 MiByte STM32F42x/43x part with DB1M Option set:
65 * 4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
66 *
67 * STM32F7[2|3]
68 * 512 kiByte part with 4 x 16, 1 x 64, 3 x 128.
69 *
70 * STM32F7[4|5]
71 * 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
72 *
73 * STM32F7[6|7]
74 * 1 MiByte part in single bank mode with 4 x 32, 1 x 128, 3 x 256.
75 * 1 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 3 x 128 each.
76 * 2 MiByte part in single-bank mode with 4 x 32, 1 x 128, 7 x 256.
77 * 2 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 7 x 128 each.
78 *
79 * Protection size is sector size.
80 *
81 * Tested with STM3220F-EVAL board.
82 *
83 * STM32F4xx series for reference.
84 *
85 * RM0090
86 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031020.pdf
87 *
88 * PM0059
89 * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/
90 * PROGRAMMING_MANUAL/CD00233952.pdf
91 *
92 * STM32F7xx series for reference.
93 *
94 * RM0385
95 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00124865.pdf
96 *
97 * RM0410
98 * http://www.st.com/resource/en/reference_manual/dm00224583.pdf
99 *
100 * RM0430
101 * http://www.st.com/resource/en/reference_manual/dm00305666.pdf
102 *
103 * RM0431
104 * http://www.st.com/resource/en/reference_manual/dm00305990.pdf
105 *
106 * STM32F1x series - notice that this code was copy, pasted and knocked
107 * into a stm32f2x driver, so in case something has been converted or
108 * bugs haven't been fixed, here are the original manuals:
109 *
110 * RM0008 - Reference manual
111 *
112 * RM0042, the Flash programming manual for low-, medium- high-density and
113 * connectivity line STM32F10x devices
114 *
115 * PM0068, the Flash programming manual for XL-density STM32F10x devices.
116 *
117 */
118
119 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
120 #define FLASH_ERASE_TIMEOUT 10000
121 #define FLASH_WRITE_TIMEOUT 5
122
123 /* Mass erase time can be as high as 32 s in x8 mode. */
124 #define FLASH_MASS_ERASE_TIMEOUT 33000
125
126 #define FLASH_BANK_BASE 0x80000000
127
128 #define STM32F2_OTP_SIZE 512
129 #define STM32F2_OTP_SECTOR_SIZE 32
130 #define STM32F2_OTP_BANK_BASE 0x1fff7800
131 #define STM32F2_OTP_LOCK_BASE ((STM32F2_OTP_BANK_BASE) + (STM32F2_OTP_SIZE))
132
133 /* see RM0410 section 3.6 "One-time programmable bytes" */
134 #define STM32F7_OTP_SECTOR_SIZE 64
135 #define STM32F7_OTP_SIZE 1024
136 #define STM32F7_OTP_BANK_BASE 0x1ff0f000
137 #define STM32F7_OTP_LOCK_BASE ((STM32F7_OTP_BANK_BASE) + (STM32F7_OTP_SIZE))
138
139 #define STM32_FLASH_BASE 0x40023c00
140 #define STM32_FLASH_ACR 0x40023c00
141 #define STM32_FLASH_KEYR 0x40023c04
142 #define STM32_FLASH_OPTKEYR 0x40023c08
143 #define STM32_FLASH_SR 0x40023c0C
144 #define STM32_FLASH_CR 0x40023c10
145 #define STM32_FLASH_OPTCR 0x40023c14
146 #define STM32_FLASH_OPTCR1 0x40023c18
147 #define STM32_FLASH_OPTCR2 0x40023c1c
148
149 /* FLASH_CR register bits */
150 #define FLASH_PG (1 << 0)
151 #define FLASH_SER (1 << 1)
152 #define FLASH_MER (1 << 2) /* MER/MER1 for f76x/77x */
153 #define FLASH_MER1 (1 << 15) /* MER2 for f76x/77x, confusing ... */
154 #define FLASH_STRT (1 << 16)
155 #define FLASH_PSIZE_8 (0 << 8)
156 #define FLASH_PSIZE_16 (1 << 8)
157 #define FLASH_PSIZE_32 (2 << 8)
158 #define FLASH_PSIZE_64 (3 << 8)
159 /* The sector number encoding is not straight binary for dual bank flash. */
160 #define FLASH_SNB(a) ((a) << 3)
161 #define FLASH_LOCK (1 << 31)
162
163 /* FLASH_SR register bits */
164 #define FLASH_BSY (1 << 16)
165 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
166 #define FLASH_PGPERR (1 << 6) /* Programming parallelism error */
167 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
168 #define FLASH_WRPERR (1 << 4) /* Write protection error */
169 #define FLASH_OPERR (1 << 1) /* Operation error */
170
171 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
172
173 /* STM32_FLASH_OPTCR register bits */
174 #define OPTCR_LOCK (1 << 0)
175 #define OPTCR_START (1 << 1)
176 #define OPTCR_NDBANK (1 << 29) /* not dual bank mode */
177 #define OPTCR_DB1M (1 << 30) /* 1 MiB devices dual flash bank option */
178 #define OPTCR_SPRMOD (1 << 31) /* switches PCROPi/nWPRi interpretation */
179
180 /* STM32_FLASH_OPTCR2 register bits */
181 #define OPTCR2_PCROP_RDP (1 << 31) /* erase PCROP zone when decreasing RDP */
182
183 /* register unlock keys */
184 #define KEY1 0x45670123
185 #define KEY2 0xCDEF89AB
186
187 /* option register unlock key */
188 #define OPTKEY1 0x08192A3B
189 #define OPTKEY2 0x4C5D6E7F
190
191 struct stm32x_options {
192 uint8_t RDP;
193 uint16_t user_options; /* bit 0-7 usual options, bit 8-11 extra options */
194 uint32_t protection;
195 uint32_t boot_addr;
196 uint32_t optcr2_pcrop;
197 };
198
199 struct stm32x_flash_bank {
200 struct stm32x_options option_bytes;
201 bool probed;
202 bool otp_unlocked;
203 bool has_large_mem; /* F42x/43x/469/479/7xx in dual bank mode */
204 bool has_extra_options; /* F42x/43x/469/479/7xx */
205 bool has_boot_addr; /* F7xx */
206 bool has_optcr2_pcrop; /* F72x/73x */
207 unsigned int protection_bits; /* F413/423 */
208 uint32_t user_bank_size;
209 };
210
211 static bool stm32x_is_otp(struct flash_bank *bank)
212 {
213 return bank->base == STM32F2_OTP_BANK_BASE ||
214 bank->base == STM32F7_OTP_BANK_BASE;
215 }
216
217 static bool stm32x_otp_is_f7(struct flash_bank *bank)
218 {
219 return bank->base == STM32F7_OTP_BANK_BASE;
220 }
221
222 static int stm32x_is_otp_unlocked(struct flash_bank *bank)
223 {
224 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
225
226 return stm32x_info->otp_unlocked;
227 }
228
229 static int stm32x_otp_disable(struct flash_bank *bank)
230 {
231 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
232
233 LOG_INFO("OTP memory bank #%u is disabled for write commands.",
234 bank->bank_number);
235 stm32x_info->otp_unlocked = false;
236 return ERROR_OK;
237 }
238
239 static int stm32x_otp_enable(struct flash_bank *bank)
240 {
241 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
242
243 if (!stm32x_info->otp_unlocked) {
244 LOG_INFO("OTP memory bank #%u is is enabled for write commands.",
245 bank->bank_number);
246 stm32x_info->otp_unlocked = true;
247 } else {
248 LOG_WARNING("OTP memory bank #%u is is already enabled for write commands.",
249 bank->bank_number);
250 }
251 return ERROR_OK;
252 }
253
254 /* flash bank stm32x <base> <size> 0 0 <target#>
255 */
256 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
257 {
258 struct stm32x_flash_bank *stm32x_info;
259
260 if (CMD_ARGC < 6)
261 return ERROR_COMMAND_SYNTAX_ERROR;
262
263 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
264 bank->driver_priv = stm32x_info;
265
266 stm32x_info->probed = false;
267 stm32x_info->otp_unlocked = false;
268 stm32x_info->user_bank_size = bank->size;
269
270 return ERROR_OK;
271 }
272
273 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
274 {
275 return reg;
276 }
277
278 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
279 {
280 struct target *target = bank->target;
281 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
282 }
283
284 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
285 {
286 struct target *target = bank->target;
287 uint32_t status;
288 int retval = ERROR_OK;
289
290 /* wait for busy to clear */
291 for (;;) {
292 retval = stm32x_get_flash_status(bank, &status);
293 if (retval != ERROR_OK)
294 return retval;
295 LOG_DEBUG("status: 0x%" PRIx32, status);
296 if ((status & FLASH_BSY) == 0)
297 break;
298 if (timeout-- <= 0) {
299 LOG_ERROR("timed out waiting for flash");
300 return ERROR_FAIL;
301 }
302 alive_sleep(1);
303 }
304
305
306 if (status & FLASH_WRPERR) {
307 LOG_ERROR("stm32x device protected");
308 retval = ERROR_FAIL;
309 }
310
311 /* Clear but report errors */
312 if (status & FLASH_ERROR) {
313 if (retval == ERROR_OK)
314 retval = ERROR_FAIL;
315 /* If this operation fails, we ignore it and report the original
316 * retval
317 */
318 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
319 status & FLASH_ERROR);
320 }
321 return retval;
322 }
323
324 static int stm32x_unlock_reg(struct target *target)
325 {
326 uint32_t ctrl;
327
328 /* first check if not already unlocked
329 * otherwise writing on STM32_FLASH_KEYR will fail
330 */
331 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
332 if (retval != ERROR_OK)
333 return retval;
334
335 if ((ctrl & FLASH_LOCK) == 0)
336 return ERROR_OK;
337
338 /* unlock flash registers */
339 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
340 if (retval != ERROR_OK)
341 return retval;
342
343 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
344 if (retval != ERROR_OK)
345 return retval;
346
347 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
348 if (retval != ERROR_OK)
349 return retval;
350
351 if (ctrl & FLASH_LOCK) {
352 LOG_ERROR("flash not unlocked STM32_FLASH_CR: 0x%" PRIx32, ctrl);
353 return ERROR_TARGET_FAILURE;
354 }
355
356 return ERROR_OK;
357 }
358
359 static int stm32x_unlock_option_reg(struct target *target)
360 {
361 uint32_t ctrl;
362
363 int retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
364 if (retval != ERROR_OK)
365 return retval;
366
367 if ((ctrl & OPTCR_LOCK) == 0)
368 return ERROR_OK;
369
370 /* unlock option registers */
371 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
372 if (retval != ERROR_OK)
373 return retval;
374
375 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
376 if (retval != ERROR_OK)
377 return retval;
378
379 retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
380 if (retval != ERROR_OK)
381 return retval;
382
383 if (ctrl & OPTCR_LOCK) {
384 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32, ctrl);
385 return ERROR_TARGET_FAILURE;
386 }
387
388 return ERROR_OK;
389 }
390
391 static int stm32x_read_options(struct flash_bank *bank)
392 {
393 uint32_t optiondata;
394 struct stm32x_flash_bank *stm32x_info = NULL;
395 struct target *target = bank->target;
396
397 stm32x_info = bank->driver_priv;
398
399 /* read current option bytes */
400 int retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
401 if (retval != ERROR_OK)
402 return retval;
403
404 /* caution: F2 implements 5 bits (WDG_SW only)
405 * whereas F7 6 bits (IWDG_SW and WWDG_SW) in user_options */
406 stm32x_info->option_bytes.user_options = optiondata & 0xfc;
407 stm32x_info->option_bytes.RDP = (optiondata >> 8) & 0xff;
408 stm32x_info->option_bytes.protection =
409 (optiondata >> 16) & (~(0xffff << stm32x_info->protection_bits) & 0xffff);
410
411 if (stm32x_info->has_extra_options) {
412 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
413 stm32x_info->option_bytes.user_options |= (optiondata >> 20) &
414 ((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00);
415 }
416
417 if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
418 retval = target_read_u32(target, STM32_FLASH_OPTCR1, &optiondata);
419 if (retval != ERROR_OK)
420 return retval;
421
422 /* FLASH_OPTCR1 has quite different meanings ... */
423 if (stm32x_info->has_boot_addr) {
424 /* for F7xx it contains boot0 and boot1 */
425 stm32x_info->option_bytes.boot_addr = optiondata;
426 } else {
427 /* for F42x/43x/469/479 it contains 12 additional protection bits */
428 stm32x_info->option_bytes.protection |= (optiondata >> 4) & 0x00fff000;
429 }
430 }
431
432 if (stm32x_info->has_optcr2_pcrop) {
433 retval = target_read_u32(target, STM32_FLASH_OPTCR2, &optiondata);
434 if (retval != ERROR_OK)
435 return retval;
436
437 stm32x_info->option_bytes.optcr2_pcrop = optiondata;
438 if (stm32x_info->has_optcr2_pcrop &&
439 (stm32x_info->option_bytes.optcr2_pcrop & ~OPTCR2_PCROP_RDP)) {
440 LOG_INFO("PCROP Engaged");
441 }
442 } else {
443 stm32x_info->option_bytes.optcr2_pcrop = 0x0;
444 }
445
446 if (stm32x_info->option_bytes.RDP != 0xAA)
447 LOG_INFO("Device Security Bit Set");
448
449 return ERROR_OK;
450 }
451
452 static int stm32x_write_options(struct flash_bank *bank)
453 {
454 struct stm32x_flash_bank *stm32x_info = NULL;
455 struct target *target = bank->target;
456 uint32_t optiondata, optiondata2;
457
458 stm32x_info = bank->driver_priv;
459
460 int retval = stm32x_unlock_option_reg(target);
461 if (retval != ERROR_OK)
462 return retval;
463
464 /* rebuild option data */
465 optiondata = stm32x_info->option_bytes.user_options & 0xfc;
466 optiondata |= stm32x_info->option_bytes.RDP << 8;
467 optiondata |= (stm32x_info->option_bytes.protection &
468 (~(0xffff << stm32x_info->protection_bits))) << 16;
469
470 if (stm32x_info->has_extra_options) {
471 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
472 optiondata |= (stm32x_info->option_bytes.user_options &
473 ((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00)) << 20;
474 }
475
476 if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
477 if (stm32x_info->has_boot_addr) {
478 /* F7xx uses FLASH_OPTCR1 for boot0 and boot1 ... */
479 optiondata2 = stm32x_info->option_bytes.boot_addr;
480 } else {
481 /* F42x/43x/469/479 uses FLASH_OPTCR1 for additional protection bits */
482 optiondata2 = (stm32x_info->option_bytes.protection & 0x00fff000) << 4;
483 }
484
485 retval = target_write_u32(target, STM32_FLASH_OPTCR1, optiondata2);
486 if (retval != ERROR_OK)
487 return retval;
488 }
489
490 /* program extra pcrop register */
491 if (stm32x_info->has_optcr2_pcrop) {
492 retval = target_write_u32(target, STM32_FLASH_OPTCR2,
493 stm32x_info->option_bytes.optcr2_pcrop);
494 if (retval != ERROR_OK)
495 return retval;
496 }
497
498 /* program options */
499 retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata);
500 if (retval != ERROR_OK)
501 return retval;
502
503 /* start programming cycle */
504 retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_START);
505 if (retval != ERROR_OK)
506 return retval;
507
508 /* wait for completion, this might trigger a security erase and take a while */
509 retval = stm32x_wait_status_busy(bank, FLASH_MASS_ERASE_TIMEOUT);
510 if (retval != ERROR_OK)
511 return retval;
512
513 /* relock registers */
514 retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_LOCK);
515 if (retval != ERROR_OK)
516 return retval;
517
518 return ERROR_OK;
519 }
520
521 static int stm32x_otp_read_protect(struct flash_bank *bank)
522 {
523 struct target *target = bank->target;
524 uint32_t lock_base;
525 int retval;
526 uint8_t lock;
527
528 lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
529 : STM32F2_OTP_LOCK_BASE;
530
531 for (unsigned int i = 0; i < bank->num_sectors; i++) {
532 retval = target_read_u8(target, lock_base + i, &lock);
533 if (retval != ERROR_OK)
534 return retval;
535 bank->sectors[i].is_protected = !lock;
536 }
537
538 return ERROR_OK;
539 }
540
541 static int stm32x_otp_protect(struct flash_bank *bank, unsigned int first,
542 unsigned int last)
543 {
544 struct target *target = bank->target;
545 uint32_t lock_base;
546 int i, retval;
547 uint8_t lock;
548
549 assert((first <= last) && (last < bank->num_sectors));
550
551 lock_base = stm32x_otp_is_f7(bank) ? STM32F7_OTP_LOCK_BASE
552 : STM32F2_OTP_LOCK_BASE;
553
554 for (i = first; first <= last; i++) {
555 retval = target_read_u8(target, lock_base + i, &lock);
556 if (retval != ERROR_OK)
557 return retval;
558 if (lock)
559 continue;
560
561 lock = 0xff;
562 retval = target_write_u8(target, lock_base + i, lock);
563 if (retval != ERROR_OK)
564 return retval;
565 }
566
567 return ERROR_OK;
568 }
569
570 static int stm32x_protect_check(struct flash_bank *bank)
571 {
572 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
573 struct flash_sector *prot_blocks;
574 unsigned int num_prot_blocks;
575 int retval;
576
577 /* if it's the OTP bank, look at the lock bits there */
578 if (stm32x_is_otp(bank))
579 return stm32x_otp_read_protect(bank);
580
581 /* read write protection settings */
582 retval = stm32x_read_options(bank);
583 if (retval != ERROR_OK) {
584 LOG_DEBUG("unable to read option bytes");
585 return retval;
586 }
587
588 if (bank->prot_blocks) {
589 num_prot_blocks = bank->num_prot_blocks;
590 prot_blocks = bank->prot_blocks;
591 } else {
592 num_prot_blocks = bank->num_sectors;
593 prot_blocks = bank->sectors;
594 }
595
596 for (unsigned int i = 0; i < num_prot_blocks; i++)
597 prot_blocks[i].is_protected =
598 ~(stm32x_info->option_bytes.protection >> i) & 1;
599
600 return ERROR_OK;
601 }
602
603 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
604 unsigned int last)
605 {
606 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
607 struct target *target = bank->target;
608
609 if (stm32x_is_otp(bank)) {
610 LOG_ERROR("Cannot erase OTP memory");
611 return ERROR_FAIL;
612 }
613
614 assert((first <= last) && (last < bank->num_sectors));
615
616 if (bank->target->state != TARGET_HALTED) {
617 LOG_ERROR("Target not halted");
618 return ERROR_TARGET_NOT_HALTED;
619 }
620
621 int retval;
622 retval = stm32x_unlock_reg(target);
623 if (retval != ERROR_OK)
624 return retval;
625
626 /*
627 Sector Erase
628 To erase a sector, follow the procedure below:
629 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
630 FLASH_SR register
631 2. Set the SER bit and select the sector
632 you wish to erase (SNB) in the FLASH_CR register
633 3. Set the STRT bit in the FLASH_CR register
634 4. Wait for the BSY bit to be cleared
635 */
636
637 for (unsigned int i = first; i <= last; i++) {
638 unsigned int snb;
639 if (stm32x_info->has_large_mem && i >= (bank->num_sectors / 2))
640 snb = (i - (bank->num_sectors / 2)) | 0x10;
641 else
642 snb = i;
643
644 retval = target_write_u32(target,
645 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(snb) | FLASH_STRT);
646 if (retval != ERROR_OK)
647 return retval;
648
649 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
650 if (retval != ERROR_OK)
651 return retval;
652 }
653
654 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
655 if (retval != ERROR_OK)
656 return retval;
657
658 return ERROR_OK;
659 }
660
661 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
662 unsigned int last)
663 {
664 struct target *target = bank->target;
665 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
666
667 if (target->state != TARGET_HALTED) {
668 LOG_ERROR("Target not halted");
669 return ERROR_TARGET_NOT_HALTED;
670 }
671
672 if (stm32x_is_otp(bank)) {
673 if (!set)
674 return ERROR_COMMAND_ARGUMENT_INVALID;
675
676 return stm32x_otp_protect(bank, first, last);
677 }
678
679 /* read protection settings */
680 int retval = stm32x_read_options(bank);
681 if (retval != ERROR_OK) {
682 LOG_DEBUG("unable to read option bytes");
683 return retval;
684 }
685
686 for (unsigned int i = first; i <= last; i++) {
687 if (set)
688 stm32x_info->option_bytes.protection &= ~(1 << i);
689 else
690 stm32x_info->option_bytes.protection |= (1 << i);
691 }
692
693 retval = stm32x_write_options(bank);
694 if (retval != ERROR_OK)
695 return retval;
696
697 return ERROR_OK;
698 }
699
700 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
701 uint32_t offset, uint32_t count)
702 {
703 struct target *target = bank->target;
704 uint32_t buffer_size = 16384;
705 struct working_area *write_algorithm;
706 struct working_area *source;
707 uint32_t address = bank->base + offset;
708 struct reg_param reg_params[5];
709 struct armv7m_algorithm armv7m_info;
710 int retval = ERROR_OK;
711
712 static const uint8_t stm32x_flash_write_code[] = {
713 #include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
714 };
715
716 if (stm32x_is_otp(bank) && !stm32x_is_otp_unlocked(bank)) {
717 LOG_ERROR("OTP memory bank is disabled for write commands.");
718 return ERROR_FAIL;
719 }
720
721 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
722 &write_algorithm) != ERROR_OK) {
723 LOG_WARNING("no working area available, can't do block memory writes");
724 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
725 }
726
727 retval = target_write_buffer(target, write_algorithm->address,
728 sizeof(stm32x_flash_write_code),
729 stm32x_flash_write_code);
730 if (retval != ERROR_OK) {
731 target_free_working_area(target, write_algorithm);
732 return retval;
733 }
734
735 /* memory buffer */
736 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
737 buffer_size /= 2;
738 if (buffer_size <= 256) {
739 /* we already allocated the writing code, but failed to get a
740 * buffer, free the algorithm */
741 target_free_working_area(target, write_algorithm);
742
743 LOG_WARNING("no large enough working area available, can't do block memory writes");
744 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
745 }
746 }
747
748 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
749 armv7m_info.core_mode = ARM_MODE_THREAD;
750
751 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
752 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
753 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
754 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (halfword-16bit) */
755 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash base */
756
757 buf_set_u32(reg_params[0].value, 0, 32, source->address);
758 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
759 buf_set_u32(reg_params[2].value, 0, 32, address);
760 buf_set_u32(reg_params[3].value, 0, 32, count);
761 buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
762
763 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
764 0, NULL,
765 5, reg_params,
766 source->address, source->size,
767 write_algorithm->address, 0,
768 &armv7m_info);
769
770 if (retval == ERROR_FLASH_OPERATION_FAILED) {
771 LOG_ERROR("error executing stm32x flash write algorithm");
772
773 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
774
775 if (error & FLASH_WRPERR)
776 LOG_ERROR("flash memory write protected");
777
778 if (error != 0) {
779 LOG_ERROR("flash write failed = 0x%08" PRIx32, error);
780 /* Clear but report errors */
781 target_write_u32(target, STM32_FLASH_SR, error);
782 retval = ERROR_FAIL;
783 }
784 }
785
786 target_free_working_area(target, source);
787 target_free_working_area(target, write_algorithm);
788
789 destroy_reg_param(&reg_params[0]);
790 destroy_reg_param(&reg_params[1]);
791 destroy_reg_param(&reg_params[2]);
792 destroy_reg_param(&reg_params[3]);
793 destroy_reg_param(&reg_params[4]);
794
795 return retval;
796 }
797
798 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
799 uint32_t offset, uint32_t count)
800 {
801 struct target *target = bank->target;
802 uint32_t words_remaining = (count / 2);
803 uint32_t bytes_remaining = (count & 0x00000001);
804 uint32_t address = bank->base + offset;
805 uint32_t bytes_written = 0;
806 int retval;
807
808 if (bank->target->state != TARGET_HALTED) {
809 LOG_ERROR("Target not halted");
810 return ERROR_TARGET_NOT_HALTED;
811 }
812
813 if (offset & 0x1) {
814 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
815 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
816 }
817
818 retval = stm32x_unlock_reg(target);
819 if (retval != ERROR_OK)
820 return retval;
821
822 /* multiple half words (2-byte) to be programmed? */
823 if (words_remaining > 0) {
824 /* try using a block write */
825 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
826 if (retval != ERROR_OK) {
827 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
828 /* if block write failed (no sufficient working area),
829 * we use normal (slow) single dword accesses */
830 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
831 }
832 } else {
833 buffer += words_remaining * 2;
834 address += words_remaining * 2;
835 words_remaining = 0;
836 }
837 }
838
839 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
840 return retval;
841
842 /*
843 Standard programming
844 The Flash memory programming sequence is as follows:
845 1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
846 FLASH_SR register.
847 2. Set the PG bit in the FLASH_CR register
848 3. Perform the data write operation(s) to the desired memory address (inside main
849 memory block or OTP area):
850 – – Half-word access in case of x16 parallelism
851 – Word access in case of x32 parallelism
852 –
853 4.
854 Byte access in case of x8 parallelism
855 Double word access in case of x64 parallelism
856 Wait for the BSY bit to be cleared
857 */
858 while (words_remaining > 0) {
859 uint16_t value;
860 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
861
862 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
863 FLASH_PG | FLASH_PSIZE_16);
864 if (retval != ERROR_OK)
865 return retval;
866
867 retval = target_write_u16(target, address, value);
868 if (retval != ERROR_OK)
869 return retval;
870
871 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
872 if (retval != ERROR_OK)
873 return retval;
874
875 bytes_written += 2;
876 words_remaining--;
877 address += 2;
878 }
879
880 if (bytes_remaining) {
881 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
882 FLASH_PG | FLASH_PSIZE_8);
883 if (retval != ERROR_OK)
884 return retval;
885 retval = target_write_u8(target, address, buffer[bytes_written]);
886 if (retval != ERROR_OK)
887 return retval;
888
889 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
890 if (retval != ERROR_OK)
891 return retval;
892 }
893
894 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
895 }
896
897 static void setup_sector(struct flash_bank *bank, unsigned int i,
898 unsigned int size)
899 {
900 assert(i < bank->num_sectors);
901 bank->sectors[i].offset = bank->size;
902 bank->sectors[i].size = size;
903 bank->size += bank->sectors[i].size;
904 LOG_DEBUG("sector %u: %ukBytes", i, size >> 10);
905 }
906
907 static uint16_t sector_size_in_kb(unsigned int i, uint16_t max_sector_size_in_kb)
908 {
909 if (i < 4)
910 return max_sector_size_in_kb / 8;
911 if (i == 4)
912 return max_sector_size_in_kb / 2;
913 return max_sector_size_in_kb;
914 }
915
916 static unsigned int calculate_number_of_sectors(struct flash_bank *bank,
917 uint16_t flash_size_in_kb,
918 uint16_t max_sector_size_in_kb)
919 {
920 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
921 uint16_t remaining_flash_size_in_kb = flash_size_in_kb;
922 unsigned int nr_sectors;
923
924 /* Dual Bank Flash has two identically-arranged banks of sectors. */
925 if (stm32x_info->has_large_mem)
926 remaining_flash_size_in_kb /= 2;
927
928 for (nr_sectors = 0; remaining_flash_size_in_kb > 0; nr_sectors++) {
929 uint16_t size_in_kb = sector_size_in_kb(nr_sectors, max_sector_size_in_kb);
930 if (size_in_kb > remaining_flash_size_in_kb) {
931 LOG_INFO("%s Bank %" PRIu16 " kiB final sector clipped to %" PRIu16 " kiB",
932 stm32x_info->has_large_mem ? "Dual" : "Single",
933 flash_size_in_kb, remaining_flash_size_in_kb);
934 remaining_flash_size_in_kb = 0;
935 } else {
936 remaining_flash_size_in_kb -= size_in_kb;
937 }
938 }
939
940 return stm32x_info->has_large_mem ? nr_sectors*2 : nr_sectors;
941 }
942
943 static void setup_bank(struct flash_bank *bank, unsigned int start,
944 uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
945 {
946 uint16_t remaining_flash_size_in_kb = flash_size_in_kb;
947 unsigned int sector_index = 0;
948 while (remaining_flash_size_in_kb > 0) {
949 uint16_t size_in_kb = sector_size_in_kb(sector_index, max_sector_size_in_kb);
950 if (size_in_kb > remaining_flash_size_in_kb) {
951 /* Clip last sector. Already warned in
952 * calculate_number_of_sectors. */
953 size_in_kb = remaining_flash_size_in_kb;
954 }
955 setup_sector(bank, start + sector_index, size_in_kb * 1024);
956 remaining_flash_size_in_kb -= size_in_kb;
957 sector_index++;
958 }
959 }
960
961 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
962 {
963 /* this checks for a stm32f4x errata issue where a
964 * stm32f2x DBGMCU_IDCODE is incorrectly returned.
965 * If the issue is detected target is forced to stm32f4x Rev A.
966 * Only effects Rev A silicon */
967
968 struct target *target = bank->target;
969
970 /* read stm32 device id register */
971 int retval = target_read_u32(target, 0xE0042000, device_id);
972 if (retval != ERROR_OK)
973 return retval;
974
975 if ((*device_id & 0xfff) == 0x411
976 && cortex_m_get_partno_safe(target) == CORTEX_M4_PARTNO) {
977 *device_id &= ~((0xFFFF << 16) | 0xfff);
978 *device_id |= (0x1000 << 16) | 0x413;
979 LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
980 }
981 return retval;
982 }
983
984 static int stm32x_probe(struct flash_bank *bank)
985 {
986 struct target *target = bank->target;
987 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
988 unsigned int num_prot_blocks, num_sectors;
989 uint16_t flash_size_in_kb;
990 uint16_t otp_size_in_b;
991 uint16_t otp_sector_size;
992 uint32_t flash_size_reg = 0x1FFF7A22;
993 uint16_t max_sector_size_in_kb = 128;
994 uint16_t max_flash_size_in_kb;
995 uint32_t device_id;
996 uint32_t base_address = 0x08000000;
997
998 stm32x_info->probed = false;
999 stm32x_info->has_large_mem = false;
1000 stm32x_info->has_boot_addr = false;
1001 stm32x_info->has_extra_options = false;
1002 stm32x_info->has_optcr2_pcrop = false;
1003 stm32x_info->protection_bits = 12; /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
1004 num_prot_blocks = 0;
1005
1006 free(bank->sectors);
1007 bank->num_sectors = 0;
1008 bank->sectors = NULL;
1009
1010 free(bank->prot_blocks);
1011 bank->num_prot_blocks = 0;
1012 bank->prot_blocks = NULL;
1013
1014 if (!target_was_examined(target)) {
1015 LOG_ERROR("Target not examined yet");
1016 return ERROR_TARGET_NOT_EXAMINED;
1017 }
1018
1019 /* if explicitly called out as OTP bank, short circuit probe */
1020 if (stm32x_is_otp(bank)) {
1021 if (stm32x_otp_is_f7(bank)) {
1022 otp_size_in_b = STM32F7_OTP_SIZE;
1023 otp_sector_size = STM32F7_OTP_SECTOR_SIZE;
1024 } else {
1025 otp_size_in_b = STM32F2_OTP_SIZE;
1026 otp_sector_size = STM32F2_OTP_SECTOR_SIZE;
1027 }
1028
1029 num_sectors = otp_size_in_b / otp_sector_size;
1030 LOG_INFO("flash size = %" PRIu16 " bytes", otp_size_in_b);
1031
1032 assert(num_sectors > 0);
1033
1034 bank->num_sectors = num_sectors;
1035 bank->sectors = calloc(sizeof(struct flash_sector), num_sectors);
1036
1037 if (stm32x_otp_is_f7(bank))
1038 bank->size = STM32F7_OTP_SIZE;
1039 else
1040 bank->size = STM32F2_OTP_SIZE;
1041
1042 for (unsigned int i = 0; i < num_sectors; i++) {
1043 bank->sectors[i].offset = i * otp_sector_size;
1044 bank->sectors[i].size = otp_sector_size;
1045 bank->sectors[i].is_erased = 1;
1046 bank->sectors[i].is_protected = 0;
1047 }
1048
1049 stm32x_info->probed = true;
1050 return ERROR_OK;
1051 }
1052
1053 /* read stm32 device id register */
1054 int retval = stm32x_get_device_id(bank, &device_id);
1055 if (retval != ERROR_OK)
1056 return retval;
1057 LOG_INFO("device id = 0x%08" PRIx32, device_id);
1058 device_id &= 0xfff; /* only bits 0-11 are used further on */
1059
1060 /* set max flash size depending on family, id taken from AN2606 */
1061 switch (device_id) {
1062 case 0x411: /* F20x/21x */
1063 case 0x413: /* F40x/41x */
1064 max_flash_size_in_kb = 1024;
1065 break;
1066
1067 case 0x419: /* F42x/43x */
1068 case 0x434: /* F469/479 */
1069 stm32x_info->has_extra_options = true;
1070 max_flash_size_in_kb = 2048;
1071 break;
1072
1073 case 0x423: /* F401xB/C */
1074 max_flash_size_in_kb = 256;
1075 break;
1076
1077 case 0x421: /* F446 */
1078 case 0x431: /* F411 */
1079 case 0x433: /* F401xD/E */
1080 case 0x441: /* F412 */
1081 max_flash_size_in_kb = 512;
1082 break;
1083
1084 case 0x458: /* F410 */
1085 max_flash_size_in_kb = 128;
1086 break;
1087
1088 case 0x449: /* F74x/75x */
1089 max_flash_size_in_kb = 1024;
1090 max_sector_size_in_kb = 256;
1091 flash_size_reg = 0x1FF0F442;
1092 stm32x_info->has_extra_options = true;
1093 stm32x_info->has_boot_addr = true;
1094 break;
1095
1096 case 0x451: /* F76x/77x */
1097 max_flash_size_in_kb = 2048;
1098 max_sector_size_in_kb = 256;
1099 flash_size_reg = 0x1FF0F442;
1100 stm32x_info->has_extra_options = true;
1101 stm32x_info->has_boot_addr = true;
1102 break;
1103
1104 case 0x452: /* F72x/73x */
1105 max_flash_size_in_kb = 512;
1106 flash_size_reg = 0x1FF07A22; /* yes, 0x1FF*0*7A22, not 0x1FF*F*7A22 */
1107 stm32x_info->has_extra_options = true;
1108 stm32x_info->has_boot_addr = true;
1109 stm32x_info->has_optcr2_pcrop = true;
1110 break;
1111
1112 case 0x463: /* F413x/423x */
1113 max_flash_size_in_kb = 1536;
1114 stm32x_info->has_extra_options = true;
1115 stm32x_info->protection_bits = 15;
1116 num_prot_blocks = 15;
1117 break;
1118
1119 default:
1120 LOG_WARNING("Cannot identify target as a STM32 family.");
1121 return ERROR_FAIL;
1122 }
1123
1124 /* get flash size from target. */
1125 retval = target_read_u16(target, flash_size_reg, &flash_size_in_kb);
1126
1127 /* failed reading flash size or flash size invalid (early silicon),
1128 * default to max target family */
1129 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
1130 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %" PRIu16 "k flash",
1131 max_flash_size_in_kb);
1132 flash_size_in_kb = max_flash_size_in_kb;
1133 }
1134
1135 /* if the user sets the size manually then ignore the probed value
1136 * this allows us to work around devices that have a invalid flash size register value */
1137 if (stm32x_info->user_bank_size) {
1138 LOG_INFO("ignoring flash probed value, using configured bank size");
1139 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
1140 }
1141
1142 LOG_INFO("flash size = %" PRIu16 " kbytes", flash_size_in_kb);
1143
1144 /* did we assign flash size? */
1145 assert(flash_size_in_kb != 0xffff);
1146
1147 /* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
1148 if ((device_id == 0x419) || (device_id == 0x434)) {
1149 uint32_t optiondata;
1150 retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
1151 if (retval != ERROR_OK) {
1152 LOG_DEBUG("unable to read option bytes");
1153 return retval;
1154 }
1155 if ((flash_size_in_kb > 1024) || (optiondata & OPTCR_DB1M)) {
1156 stm32x_info->has_large_mem = true;
1157 LOG_INFO("Dual Bank %" PRIu16 " kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
1158 } else {
1159 stm32x_info->has_large_mem = false;
1160 LOG_INFO("Single Bank %" PRIu16 " kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
1161 }
1162 }
1163
1164 /* F76x/77x devices have a dual bank option */
1165 if (device_id == 0x451) {
1166 uint32_t optiondata;
1167 retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
1168 if (retval != ERROR_OK) {
1169 LOG_DEBUG("unable to read option bytes");
1170 return retval;
1171 }
1172 if (optiondata & OPTCR_NDBANK) {
1173 stm32x_info->has_large_mem = false;
1174 LOG_INFO("Single Bank %" PRIu16 " kiB STM32F76x/77x found", flash_size_in_kb);
1175 } else {
1176 stm32x_info->has_large_mem = true;
1177 max_sector_size_in_kb >>= 1; /* sector size divided by 2 in dual-bank mode */
1178 LOG_INFO("Dual Bank %" PRIu16 " kiB STM32F76x/77x found", flash_size_in_kb);
1179 }
1180 }
1181
1182 /* calculate numbers of pages */
1183 unsigned int num_pages = calculate_number_of_sectors(
1184 bank, flash_size_in_kb, max_sector_size_in_kb);
1185
1186 bank->base = base_address;
1187 bank->num_sectors = num_pages;
1188 bank->sectors = calloc(num_pages, sizeof(struct flash_sector));
1189 for (unsigned int i = 0; i < num_pages; i++) {
1190 bank->sectors[i].is_erased = -1;
1191 bank->sectors[i].is_protected = 0;
1192 }
1193 bank->size = 0;
1194 LOG_DEBUG("allocated %u sectors", num_pages);
1195
1196 /* F76x/77x in dual bank mode */
1197 if ((device_id == 0x451) && stm32x_info->has_large_mem)
1198 num_prot_blocks = num_pages >> 1;
1199
1200 if (num_prot_blocks) {
1201 bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks);
1202 for (unsigned int i = 0; i < num_prot_blocks; i++)
1203 bank->prot_blocks[i].is_protected = 0;
1204 LOG_DEBUG("allocated %u prot blocks", num_prot_blocks);
1205 }
1206
1207 if (stm32x_info->has_large_mem) {
1208 /* dual-bank */
1209 setup_bank(bank, 0, flash_size_in_kb >> 1, max_sector_size_in_kb);
1210 setup_bank(bank, num_pages >> 1, flash_size_in_kb >> 1,
1211 max_sector_size_in_kb);
1212
1213 /* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
1214 if (device_id == 0x451) {
1215 for (unsigned int i = 0; i < num_prot_blocks; i++) {
1216 bank->prot_blocks[i].offset = bank->sectors[i << 1].offset;
1217 bank->prot_blocks[i].size = bank->sectors[i << 1].size
1218 + bank->sectors[(i << 1) + 1].size;
1219 }
1220 }
1221 } else {
1222 /* single-bank */
1223 setup_bank(bank, 0, flash_size_in_kb, max_sector_size_in_kb);
1224
1225 /* F413/F423, sectors 14 and 15 share one common protection bit */
1226 if (device_id == 0x463) {
1227 for (unsigned int i = 0; i < num_prot_blocks; i++) {
1228 bank->prot_blocks[i].offset = bank->sectors[i].offset;
1229 bank->prot_blocks[i].size = bank->sectors[i].size;
1230 }
1231 bank->prot_blocks[num_prot_blocks - 1].size <<= 1;
1232 }
1233 }
1234 bank->num_prot_blocks = num_prot_blocks;
1235 assert((bank->size >> 10) == flash_size_in_kb);
1236
1237 stm32x_info->probed = true;
1238 return ERROR_OK;
1239 }
1240
1241 static int stm32x_auto_probe(struct flash_bank *bank)
1242 {
1243 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1244 if (stm32x_info->probed)
1245 return ERROR_OK;
1246 return stm32x_probe(bank);
1247 }
1248
1249 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
1250 {
1251 uint32_t dbgmcu_idcode;
1252
1253 /* read stm32 device id register */
1254 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1255 if (retval != ERROR_OK)
1256 return retval;
1257
1258 uint16_t device_id = dbgmcu_idcode & 0xfff;
1259 uint16_t rev_id = dbgmcu_idcode >> 16;
1260 const char *device_str;
1261 const char *rev_str = NULL;
1262
1263 switch (device_id) {
1264 case 0x411:
1265 device_str = "STM32F2xx";
1266
1267 switch (rev_id) {
1268 case 0x1000:
1269 rev_str = "A";
1270 break;
1271
1272 case 0x2000:
1273 rev_str = "B";
1274 break;
1275
1276 case 0x1001:
1277 rev_str = "Z";
1278 break;
1279
1280 case 0x2001:
1281 rev_str = "Y";
1282 break;
1283
1284 case 0x2003:
1285 rev_str = "X";
1286 break;
1287
1288 case 0x2007:
1289 rev_str = "1";
1290 break;
1291
1292 case 0x200F:
1293 rev_str = "V";
1294 break;
1295
1296 case 0x201F:
1297 rev_str = "2";
1298 break;
1299 }
1300 break;
1301
1302 case 0x413:
1303 case 0x419:
1304 case 0x434:
1305 device_str = "STM32F4xx";
1306
1307 switch (rev_id) {
1308 case 0x1000:
1309 rev_str = "A";
1310 break;
1311
1312 case 0x1001:
1313 rev_str = "Z";
1314 break;
1315
1316 case 0x1003:
1317 rev_str = "Y";
1318 break;
1319
1320 case 0x1007:
1321 rev_str = "1";
1322 break;
1323
1324 case 0x2001:
1325 rev_str = "3";
1326 break;
1327 }
1328 break;
1329
1330 case 0x421:
1331 device_str = "STM32F446";
1332
1333 switch (rev_id) {
1334 case 0x1000:
1335 rev_str = "A";
1336 break;
1337 }
1338 break;
1339
1340 case 0x423:
1341 case 0x431:
1342 case 0x433:
1343 case 0x458:
1344 case 0x441:
1345 device_str = "STM32F4xx (Low Power)";
1346
1347 switch (rev_id) {
1348 case 0x1000:
1349 rev_str = "A";
1350 break;
1351
1352 case 0x1001:
1353 rev_str = "Z";
1354 break;
1355
1356 case 0x2000:
1357 rev_str = "B";
1358 break;
1359
1360 case 0x3000:
1361 rev_str = "C";
1362 break;
1363 }
1364 break;
1365
1366 case 0x449:
1367 device_str = "STM32F7[4|5]x";
1368
1369 switch (rev_id) {
1370 case 0x1000:
1371 rev_str = "A";
1372 break;
1373
1374 case 0x1001:
1375 rev_str = "Z";
1376 break;
1377 }
1378 break;
1379
1380 case 0x451:
1381 device_str = "STM32F7[6|7]x";
1382
1383 switch (rev_id) {
1384 case 0x1000:
1385 rev_str = "A";
1386 break;
1387 case 0x1001:
1388 rev_str = "Z";
1389 break;
1390 }
1391 break;
1392
1393 case 0x452:
1394 device_str = "STM32F7[2|3]x";
1395
1396 switch (rev_id) {
1397 case 0x1000:
1398 rev_str = "A";
1399 break;
1400 }
1401 break;
1402
1403 case 0x463:
1404 device_str = "STM32F4[1|2]3";
1405
1406 switch (rev_id) {
1407 case 0x1000:
1408 rev_str = "A";
1409 break;
1410 }
1411 break;
1412
1413 default:
1414 command_print_sameline(cmd, "Cannot identify target as a STM32F2/4/7\n");
1415 return ERROR_FAIL;
1416 }
1417
1418 if (rev_str)
1419 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1420 else
1421 command_print_sameline(cmd, "%s - Rev: unknown (0x%04" PRIx16 ")", device_str, rev_id);
1422
1423 return ERROR_OK;
1424 }
1425
1426 COMMAND_HANDLER(stm32x_handle_lock_command)
1427 {
1428 struct target *target = NULL;
1429 struct stm32x_flash_bank *stm32x_info = NULL;
1430
1431 if (CMD_ARGC < 1)
1432 return ERROR_COMMAND_SYNTAX_ERROR;
1433
1434 struct flash_bank *bank;
1435 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1436 if (retval != ERROR_OK)
1437 return retval;
1438
1439 stm32x_info = bank->driver_priv;
1440 target = bank->target;
1441
1442 if (target->state != TARGET_HALTED) {
1443 LOG_INFO("Target not halted");
1444 /* return ERROR_TARGET_NOT_HALTED; */
1445 }
1446
1447 if (stm32x_read_options(bank) != ERROR_OK) {
1448 command_print(CMD, "%s failed to read options", bank->driver->name);
1449 return ERROR_OK;
1450 }
1451
1452 /* set readout protection */
1453 stm32x_info->option_bytes.RDP = 0;
1454
1455 if (stm32x_write_options(bank) != ERROR_OK) {
1456 command_print(CMD, "%s failed to lock device", bank->driver->name);
1457 return ERROR_OK;
1458 }
1459
1460 command_print(CMD, "%s locked", bank->driver->name);
1461
1462 return ERROR_OK;
1463 }
1464
1465 COMMAND_HANDLER(stm32x_handle_unlock_command)
1466 {
1467 struct target *target = NULL;
1468 struct stm32x_flash_bank *stm32x_info = NULL;
1469
1470 if (CMD_ARGC < 1)
1471 return ERROR_COMMAND_SYNTAX_ERROR;
1472
1473 struct flash_bank *bank;
1474 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1475 if (retval != ERROR_OK)
1476 return retval;
1477
1478 stm32x_info = bank->driver_priv;
1479 target = bank->target;
1480
1481 if (target->state != TARGET_HALTED) {
1482 LOG_INFO("Target not halted");
1483 /* return ERROR_TARGET_NOT_HALTED; */
1484 }
1485
1486 if (stm32x_read_options(bank) != ERROR_OK) {
1487 command_print(CMD, "%s failed to read options", bank->driver->name);
1488 return ERROR_OK;
1489 }
1490
1491 /* clear readout protection and complementary option bytes
1492 * this will also force a device unlock if set */
1493 stm32x_info->option_bytes.RDP = 0xAA;
1494 if (stm32x_info->has_optcr2_pcrop) {
1495 stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1U << bank->num_sectors);
1496 }
1497
1498 if (stm32x_write_options(bank) != ERROR_OK) {
1499 command_print(CMD, "%s failed to unlock device", bank->driver->name);
1500 return ERROR_OK;
1501 }
1502
1503 command_print(CMD, "%s unlocked.\n"
1504 "INFO: a reset or power cycle is required "
1505 "for the new settings to take effect.", bank->driver->name);
1506
1507 return ERROR_OK;
1508 }
1509
1510 static int stm32x_mass_erase(struct flash_bank *bank)
1511 {
1512 int retval;
1513 uint32_t flash_mer;
1514 struct target *target = bank->target;
1515 struct stm32x_flash_bank *stm32x_info = NULL;
1516
1517 if (target->state != TARGET_HALTED) {
1518 LOG_ERROR("Target not halted");
1519 return ERROR_TARGET_NOT_HALTED;
1520 }
1521
1522 stm32x_info = bank->driver_priv;
1523
1524 retval = stm32x_unlock_reg(target);
1525 if (retval != ERROR_OK)
1526 return retval;
1527
1528 /* mass erase flash memory */
1529 if (stm32x_info->has_large_mem)
1530 flash_mer = FLASH_MER | FLASH_MER1;
1531 else
1532 flash_mer = FLASH_MER;
1533
1534 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), flash_mer);
1535 if (retval != ERROR_OK)
1536 return retval;
1537 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1538 flash_mer | FLASH_STRT);
1539 if (retval != ERROR_OK)
1540 return retval;
1541
1542 retval = stm32x_wait_status_busy(bank, FLASH_MASS_ERASE_TIMEOUT);
1543 if (retval != ERROR_OK)
1544 return retval;
1545
1546 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1547 if (retval != ERROR_OK)
1548 return retval;
1549
1550 return ERROR_OK;
1551 }
1552
1553 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1554 {
1555 if (CMD_ARGC < 1) {
1556 command_print(CMD, "stm32x mass_erase <bank>");
1557 return ERROR_COMMAND_SYNTAX_ERROR;
1558 }
1559
1560 struct flash_bank *bank;
1561 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1562 if (retval != ERROR_OK)
1563 return retval;
1564
1565 retval = stm32x_mass_erase(bank);
1566 if (retval == ERROR_OK) {
1567 command_print(CMD, "stm32x mass erase complete");
1568 } else {
1569 command_print(CMD, "stm32x mass erase failed");
1570 }
1571
1572 return retval;
1573 }
1574
1575 COMMAND_HANDLER(stm32f2x_handle_options_read_command)
1576 {
1577 int retval;
1578 struct flash_bank *bank;
1579 struct stm32x_flash_bank *stm32x_info = NULL;
1580
1581 if (CMD_ARGC != 1) {
1582 command_print(CMD, "stm32f2x options_read <bank>");
1583 return ERROR_COMMAND_SYNTAX_ERROR;
1584 }
1585
1586 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1587 if (retval != ERROR_OK)
1588 return retval;
1589
1590 retval = stm32x_read_options(bank);
1591 if (retval != ERROR_OK)
1592 return retval;
1593
1594 stm32x_info = bank->driver_priv;
1595 if (stm32x_info->has_extra_options) {
1596 if (stm32x_info->has_boot_addr) {
1597 uint32_t boot_addr = stm32x_info->option_bytes.boot_addr;
1598
1599 command_print(CMD, "stm32f2x user_options 0x%03" PRIX16 ","
1600 " boot_add0 0x%04" PRIX32 ", boot_add1 0x%04" PRIX32,
1601 stm32x_info->option_bytes.user_options,
1602 boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16);
1603 if (stm32x_info->has_optcr2_pcrop) {
1604 command_print(CMD, "stm32f2x optcr2_pcrop 0x%08" PRIX32,
1605 stm32x_info->option_bytes.optcr2_pcrop);
1606 }
1607 } else {
1608 command_print(CMD, "stm32f2x user_options 0x%03" PRIX16,
1609 stm32x_info->option_bytes.user_options);
1610 }
1611 } else {
1612 command_print(CMD, "stm32f2x user_options 0x%02" PRIX16,
1613 stm32x_info->option_bytes.user_options);
1614
1615 }
1616
1617 return retval;
1618 }
1619
1620 COMMAND_HANDLER(stm32f2x_handle_options_write_command)
1621 {
1622 int retval;
1623 struct flash_bank *bank;
1624 struct stm32x_flash_bank *stm32x_info = NULL;
1625 uint16_t user_options, boot_addr0, boot_addr1, options_mask;
1626
1627 if (CMD_ARGC < 1) {
1628 command_print(CMD, "stm32f2x options_write <bank> ...");
1629 return ERROR_COMMAND_SYNTAX_ERROR;
1630 }
1631
1632 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1633 if (retval != ERROR_OK)
1634 return retval;
1635
1636 retval = stm32x_read_options(bank);
1637 if (retval != ERROR_OK)
1638 return retval;
1639
1640 stm32x_info = bank->driver_priv;
1641 if (stm32x_info->has_boot_addr) {
1642 if (CMD_ARGC != 4) {
1643 command_print(CMD, "stm32f2x options_write <bank> <user_options>"
1644 " <boot_addr0> <boot_addr1>");
1645 return ERROR_COMMAND_SYNTAX_ERROR;
1646 }
1647 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[2], boot_addr0);
1648 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], boot_addr1);
1649 stm32x_info->option_bytes.boot_addr = boot_addr0 | (((uint32_t) boot_addr1) << 16);
1650 } else {
1651 if (CMD_ARGC != 2) {
1652 command_print(CMD, "stm32f2x options_write <bank> <user_options>");
1653 return ERROR_COMMAND_SYNTAX_ERROR;
1654 }
1655 }
1656
1657 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], user_options);
1658 options_mask = !stm32x_info->has_extra_options ? ~0xfc :
1659 ~(((0xf00 << (stm32x_info->protection_bits - 12)) | 0xff) & 0xffc);
1660 if (user_options & options_mask) {
1661 command_print(CMD, "stm32f2x invalid user_options");
1662 return ERROR_COMMAND_ARGUMENT_INVALID;
1663 }
1664
1665 stm32x_info->option_bytes.user_options = user_options;
1666
1667 if (stm32x_write_options(bank) != ERROR_OK) {
1668 command_print(CMD, "stm32f2x failed to write options");
1669 return ERROR_OK;
1670 }
1671
1672 /* switching between single- and dual-bank modes requires re-probe */
1673 /* ... and reprogramming of whole flash */
1674 stm32x_info->probed = false;
1675
1676 command_print(CMD, "stm32f2x write options complete.\n"
1677 "INFO: a reset or power cycle is required "
1678 "for the new settings to take effect.");
1679 return retval;
1680 }
1681
1682 COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command)
1683 {
1684 int retval;
1685 struct flash_bank *bank;
1686 struct stm32x_flash_bank *stm32x_info = NULL;
1687 uint32_t optcr2_pcrop;
1688
1689 if (CMD_ARGC != 2) {
1690 command_print(CMD, "stm32f2x optcr2_write <bank> <optcr2_value>");
1691 return ERROR_COMMAND_SYNTAX_ERROR;
1692 }
1693
1694 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1695 if (retval != ERROR_OK)
1696 return retval;
1697
1698 stm32x_info = bank->driver_priv;
1699 if (!stm32x_info->has_optcr2_pcrop) {
1700 command_print(CMD, "no optcr2 register");
1701 return ERROR_COMMAND_ARGUMENT_INVALID;
1702 }
1703
1704 command_print(CMD, "INFO: To disable PCROP, set PCROP_RDP"
1705 " with PCROPi bits STILL SET, then\nlock device and"
1706 " finally unlock it. Clears PCROP and mass erases flash.");
1707
1708 retval = stm32x_read_options(bank);
1709 if (retval != ERROR_OK)
1710 return retval;
1711
1712 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], optcr2_pcrop);
1713 stm32x_info->option_bytes.optcr2_pcrop = optcr2_pcrop;
1714
1715 if (stm32x_write_options(bank) != ERROR_OK) {
1716 command_print(CMD, "stm32f2x failed to write options");
1717 return ERROR_OK;
1718 }
1719
1720 command_print(CMD, "stm32f2x optcr2_write complete.");
1721 return retval;
1722 }
1723
1724 COMMAND_HANDLER(stm32x_handle_otp_command)
1725 {
1726 if (CMD_ARGC < 2) {
1727 command_print(CMD, "stm32x otp <bank> (enable|disable|show)");
1728 return ERROR_COMMAND_SYNTAX_ERROR;
1729 }
1730
1731 struct flash_bank *bank;
1732 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1733 if (retval != ERROR_OK)
1734 return retval;
1735 if (stm32x_is_otp(bank)) {
1736 if (strcmp(CMD_ARGV[1], "enable") == 0) {
1737 stm32x_otp_enable(bank);
1738 } else if (strcmp(CMD_ARGV[1], "disable") == 0) {
1739 stm32x_otp_disable(bank);
1740 } else if (strcmp(CMD_ARGV[1], "show") == 0) {
1741 command_print(CMD,
1742 "OTP memory bank #%u is %s for write commands.",
1743 bank->bank_number,
1744 stm32x_is_otp_unlocked(bank) ? "enabled" : "disabled");
1745 } else {
1746 return ERROR_COMMAND_SYNTAX_ERROR;
1747 }
1748 } else {
1749 command_print(CMD, "Failed: not an OTP bank.");
1750 }
1751
1752 return retval;
1753 }
1754
1755 static const struct command_registration stm32f2x_exec_command_handlers[] = {
1756 {
1757 .name = "lock",
1758 .handler = stm32x_handle_lock_command,
1759 .mode = COMMAND_EXEC,
1760 .usage = "bank_id",
1761 .help = "Lock entire flash device.",
1762 },
1763 {
1764 .name = "unlock",
1765 .handler = stm32x_handle_unlock_command,
1766 .mode = COMMAND_EXEC,
1767 .usage = "bank_id",
1768 .help = "Unlock entire protected flash device.",
1769 },
1770 {
1771 .name = "mass_erase",
1772 .handler = stm32x_handle_mass_erase_command,
1773 .mode = COMMAND_EXEC,
1774 .usage = "bank_id",
1775 .help = "Erase entire flash device.",
1776 },
1777 {
1778 .name = "options_read",
1779 .handler = stm32f2x_handle_options_read_command,
1780 .mode = COMMAND_EXEC,
1781 .usage = "bank_id",
1782 .help = "Read and display device option bytes.",
1783 },
1784 {
1785 .name = "options_write",
1786 .handler = stm32f2x_handle_options_write_command,
1787 .mode = COMMAND_EXEC,
1788 .usage = "bank_id user_options [ boot_add0 boot_add1 ]",
1789 .help = "Write option bytes",
1790 },
1791 {
1792 .name = "optcr2_write",
1793 .handler = stm32f2x_handle_optcr2_write_command,
1794 .mode = COMMAND_EXEC,
1795 .usage = "bank_id optcr2",
1796 .help = "Write optcr2 word",
1797 },
1798 {
1799 .name = "otp",
1800 .handler = stm32x_handle_otp_command,
1801 .mode = COMMAND_EXEC,
1802 .usage = "bank_id",
1803 .help = "OTP (One Time Programmable) memory write enable/disable.",
1804 },
1805 COMMAND_REGISTRATION_DONE
1806 };
1807
1808 static const struct command_registration stm32f2x_command_handlers[] = {
1809 {
1810 .name = "stm32f2x",
1811 .mode = COMMAND_ANY,
1812 .help = "stm32f2x flash command group",
1813 .usage = "",
1814 .chain = stm32f2x_exec_command_handlers,
1815 },
1816 COMMAND_REGISTRATION_DONE
1817 };
1818
1819 const struct flash_driver stm32f2x_flash = {
1820 .name = "stm32f2x",
1821 .commands = stm32f2x_command_handlers,
1822 .flash_bank_command = stm32x_flash_bank_command,
1823 .erase = stm32x_erase,
1824 .protect = stm32x_protect,
1825 .write = stm32x_write,
1826 .read = default_flash_read,
1827 .probe = stm32x_probe,
1828 .auto_probe = stm32x_auto_probe,
1829 .erase_check = default_flash_blank_check,
1830 .protect_check = stm32x_protect_check,
1831 .info = get_stm32x_info,
1832 .free_driver_priv = default_flash_free_driver_priv,
1833 };
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