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flash/stm32f1x: add support for RISC-V GigaDevice GD32VF103
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include <string.h>
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/cortex_m.h>
35
36 /* stm32x register locations */
37
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
40
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
49
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
61
62 /* option byte location */
63
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
72
73 /* FLASH_CR register bits */
74
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
83 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
84
85 /* FLASH_SR register bits */
86
87 #define FLASH_BSY (1 << 0)
88 #define FLASH_PGERR (1 << 2)
89 #define FLASH_WRPRTERR (1 << 4)
90 #define FLASH_EOP (1 << 5)
91
92 /* STM32_FLASH_OBR bit definitions (reading) */
93
94 #define OPT_ERROR 0
95 #define OPT_READOUT 1
96 #define OPT_RDWDGSW 2
97 #define OPT_RDRSTSTOP 3
98 #define OPT_RDRSTSTDBY 4
99 #define OPT_BFB2 5 /* dual flash bank only */
100
101 /* register unlock keys */
102
103 #define KEY1 0x45670123
104 #define KEY2 0xCDEF89AB
105
106 /* timeout values */
107
108 #define FLASH_WRITE_TIMEOUT 10
109 #define FLASH_ERASE_TIMEOUT 100
110
111 struct stm32x_options {
112 uint8_t rdp;
113 uint8_t user;
114 uint16_t data;
115 uint32_t protection;
116 };
117
118 struct stm32x_flash_bank {
119 struct stm32x_options option_bytes;
120 int ppage_size;
121 bool probed;
122
123 bool has_dual_banks;
124 /* used to access dual flash bank stm32xl */
125 bool can_load_options;
126 uint32_t register_base;
127 uint8_t default_rdp;
128 int user_data_offset;
129 int option_offset;
130 uint32_t user_bank_size;
131 };
132
133 static int stm32x_mass_erase(struct flash_bank *bank);
134 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
135 uint32_t address, uint32_t hwords_count);
136
137 /* flash bank stm32x <base> <size> 0 0 <target#>
138 */
139 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
140 {
141 struct stm32x_flash_bank *stm32x_info;
142
143 if (CMD_ARGC < 6)
144 return ERROR_COMMAND_SYNTAX_ERROR;
145
146 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
147
148 bank->driver_priv = stm32x_info;
149 stm32x_info->probed = false;
150 stm32x_info->has_dual_banks = false;
151 stm32x_info->can_load_options = false;
152 stm32x_info->register_base = FLASH_REG_BASE_B0;
153 stm32x_info->user_bank_size = bank->size;
154
155 /* The flash write must be aligned to a halfword boundary */
156 bank->write_start_alignment = bank->write_end_alignment = 2;
157
158 return ERROR_OK;
159 }
160
161 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
162 {
163 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
164 return reg + stm32x_info->register_base;
165 }
166
167 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
168 {
169 struct target *target = bank->target;
170 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
171 }
172
173 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
174 {
175 struct target *target = bank->target;
176 uint32_t status;
177 int retval = ERROR_OK;
178
179 /* wait for busy to clear */
180 for (;;) {
181 retval = stm32x_get_flash_status(bank, &status);
182 if (retval != ERROR_OK)
183 return retval;
184 LOG_DEBUG("status: 0x%" PRIx32 "", status);
185 if ((status & FLASH_BSY) == 0)
186 break;
187 if (timeout-- <= 0) {
188 LOG_ERROR("timed out waiting for flash");
189 return ERROR_FLASH_BUSY;
190 }
191 alive_sleep(1);
192 }
193
194 if (status & FLASH_WRPRTERR) {
195 LOG_ERROR("stm32x device protected");
196 retval = ERROR_FLASH_PROTECTED;
197 }
198
199 if (status & FLASH_PGERR) {
200 LOG_ERROR("stm32x device programming failed / flash not erased");
201 retval = ERROR_FLASH_OPERATION_FAILED;
202 }
203
204 /* Clear but report errors */
205 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
206 /* If this operation fails, we ignore it and report the original
207 * retval
208 */
209 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
210 FLASH_WRPRTERR | FLASH_PGERR);
211 }
212 return retval;
213 }
214
215 static int stm32x_check_operation_supported(struct flash_bank *bank)
216 {
217 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
218
219 /* if we have a dual flash bank device then
220 * we need to perform option byte stuff on bank0 only */
221 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
222 LOG_ERROR("Option byte operations must use bank 0");
223 return ERROR_FLASH_OPERATION_FAILED;
224 }
225
226 return ERROR_OK;
227 }
228
229 static int stm32x_read_options(struct flash_bank *bank)
230 {
231 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
232 struct target *target = bank->target;
233 uint32_t option_bytes;
234 int retval;
235
236 /* read user and read protection option bytes, user data option bytes */
237 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
238 if (retval != ERROR_OK)
239 return retval;
240
241 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
242 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
243 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
244
245 /* read write protection option bytes */
246 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
247 if (retval != ERROR_OK)
248 return retval;
249
250 return ERROR_OK;
251 }
252
253 static int stm32x_erase_options(struct flash_bank *bank)
254 {
255 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
256 struct target *target = bank->target;
257
258 /* read current options */
259 stm32x_read_options(bank);
260
261 /* unlock flash registers */
262 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
263 if (retval != ERROR_OK)
264 return retval;
265 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
266 if (retval != ERROR_OK)
267 goto flash_lock;
268
269 /* unlock option flash registers */
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
271 if (retval != ERROR_OK)
272 goto flash_lock;
273 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
274 if (retval != ERROR_OK)
275 goto flash_lock;
276
277 /* erase option bytes */
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 goto flash_lock;
281 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
282 if (retval != ERROR_OK)
283 goto flash_lock;
284
285 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
286 if (retval != ERROR_OK)
287 goto flash_lock;
288
289 /* clear read protection option byte
290 * this will also force a device unlock if set */
291 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
292
293 return ERROR_OK;
294
295 flash_lock:
296 target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
297 return retval;
298 }
299
300 static int stm32x_write_options(struct flash_bank *bank)
301 {
302 struct stm32x_flash_bank *stm32x_info = NULL;
303 struct target *target = bank->target;
304
305 stm32x_info = bank->driver_priv;
306
307 /* unlock flash registers */
308 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
309 if (retval != ERROR_OK)
310 return retval;
311 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
312 if (retval != ERROR_OK)
313 goto flash_lock;
314
315 /* unlock option flash registers */
316 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
317 if (retval != ERROR_OK)
318 goto flash_lock;
319 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
320 if (retval != ERROR_OK)
321 goto flash_lock;
322
323 /* program option bytes */
324 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
325 if (retval != ERROR_OK)
326 goto flash_lock;
327
328 uint8_t opt_bytes[16];
329
330 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
331 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
332 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
333 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
334 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
335 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
336 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
337 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
338
339 /* Block write is preferred in favour of operation with ancient ST-Link
340 * firmwares without 16-bit memory access. See
341 * 480: flash: stm32f1x: write option bytes using the loader
342 * https://review.openocd.org/c/openocd/+/480
343 */
344 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
345
346 flash_lock:
347 {
348 int retval2 = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
349 if (retval == ERROR_OK)
350 retval = retval2;
351 }
352 return retval;
353 }
354
355 static int stm32x_protect_check(struct flash_bank *bank)
356 {
357 struct target *target = bank->target;
358 uint32_t protection;
359
360 int retval = stm32x_check_operation_supported(bank);
361 if (retval != ERROR_OK)
362 return retval;
363
364 /* medium density - each bit refers to a 4 sector protection block
365 * high density - each bit refers to a 2 sector protection block
366 * bit 31 refers to all remaining sectors in a bank */
367 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
368 if (retval != ERROR_OK)
369 return retval;
370
371 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
372 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
373
374 return ERROR_OK;
375 }
376
377 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
378 unsigned int last)
379 {
380 struct target *target = bank->target;
381
382 if (bank->target->state != TARGET_HALTED) {
383 LOG_ERROR("Target not halted");
384 return ERROR_TARGET_NOT_HALTED;
385 }
386
387 if ((first == 0) && (last == (bank->num_sectors - 1)))
388 return stm32x_mass_erase(bank);
389
390 /* unlock flash registers */
391 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
392 if (retval != ERROR_OK)
393 return retval;
394 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
395 if (retval != ERROR_OK)
396 goto flash_lock;
397
398 for (unsigned int i = first; i <= last; i++) {
399 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
400 if (retval != ERROR_OK)
401 goto flash_lock;
402 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
403 bank->base + bank->sectors[i].offset);
404 if (retval != ERROR_OK)
405 goto flash_lock;
406 retval = target_write_u32(target,
407 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
408 if (retval != ERROR_OK)
409 goto flash_lock;
410
411 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
412 if (retval != ERROR_OK)
413 goto flash_lock;
414 }
415
416 flash_lock:
417 {
418 int retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
419 if (retval == ERROR_OK)
420 retval = retval2;
421 }
422 return retval;
423 }
424
425 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
426 unsigned int last)
427 {
428 struct target *target = bank->target;
429 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
430
431 if (target->state != TARGET_HALTED) {
432 LOG_ERROR("Target not halted");
433 return ERROR_TARGET_NOT_HALTED;
434 }
435
436 int retval = stm32x_check_operation_supported(bank);
437 if (retval != ERROR_OK)
438 return retval;
439
440 retval = stm32x_erase_options(bank);
441 if (retval != ERROR_OK) {
442 LOG_ERROR("stm32x failed to erase options");
443 return retval;
444 }
445
446 for (unsigned int i = first; i <= last; i++) {
447 if (set)
448 stm32x_info->option_bytes.protection &= ~(1 << i);
449 else
450 stm32x_info->option_bytes.protection |= (1 << i);
451 }
452
453 return stm32x_write_options(bank);
454 }
455
456 static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buffer,
457 uint32_t address, uint32_t hwords_count)
458 {
459 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
460 struct target *target = bank->target;
461 uint32_t buffer_size;
462 struct working_area *write_algorithm;
463 struct working_area *source;
464 struct armv7m_algorithm armv7m_info;
465 int retval;
466
467 static const uint8_t stm32x_flash_write_code[] = {
468 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
469 };
470
471 /* flash write code */
472 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
473 &write_algorithm) != ERROR_OK) {
474 LOG_WARNING("no working area available, can't do block memory writes");
475 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
476 }
477
478 retval = target_write_buffer(target, write_algorithm->address,
479 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
480 if (retval != ERROR_OK) {
481 target_free_working_area(target, write_algorithm);
482 return retval;
483 }
484
485 /* memory buffer */
486 buffer_size = target_get_working_area_avail(target);
487 buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
488 /* Normally we allocate all available working area.
489 * MIN shrinks buffer_size if the size of the written block is smaller.
490 * MAX prevents using async algo if the available working area is smaller
491 * than 256, the following allocation fails with
492 * ERROR_TARGET_RESOURCE_NOT_AVAILABLE and slow flashing takes place.
493 */
494
495 retval = target_alloc_working_area(target, buffer_size, &source);
496 /* Allocated size is always 32-bit word aligned */
497 if (retval != ERROR_OK) {
498 target_free_working_area(target, write_algorithm);
499 LOG_WARNING("no large enough working area available, can't do block memory writes");
500 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
501 * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
502 */
503 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
504 }
505
506 struct reg_param reg_params[5];
507
508 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
509 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
510 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
511 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
512 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
513
514 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
515 buf_set_u32(reg_params[1].value, 0, 32, hwords_count);
516 buf_set_u32(reg_params[2].value, 0, 32, source->address);
517 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
518 buf_set_u32(reg_params[4].value, 0, 32, address);
519
520 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
521 armv7m_info.core_mode = ARM_MODE_THREAD;
522
523 retval = target_run_flash_async_algorithm(target, buffer, hwords_count, 2,
524 0, NULL,
525 ARRAY_SIZE(reg_params), reg_params,
526 source->address, source->size,
527 write_algorithm->address, 0,
528 &armv7m_info);
529
530 if (retval == ERROR_FLASH_OPERATION_FAILED) {
531 /* Actually we just need to check for programming errors
532 * stm32x_wait_status_busy also reports error and clears status bits.
533 *
534 * Target algo returns flash status in r0 only if properly finished.
535 * It is safer to re-read status register.
536 */
537 int retval2 = stm32x_wait_status_busy(bank, 5);
538 if (retval2 != ERROR_OK)
539 retval = retval2;
540
541 LOG_ERROR("flash write failed just before address 0x%"PRIx32,
542 buf_get_u32(reg_params[4].value, 0, 32));
543 }
544
545 for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
546 destroy_reg_param(&reg_params[i]);
547
548 target_free_working_area(target, source);
549 target_free_working_area(target, write_algorithm);
550
551 return retval;
552 }
553
554 static int stm32x_write_block_riscv(struct flash_bank *bank, const uint8_t *buffer,
555 uint32_t address, uint32_t hwords_count)
556 {
557 struct target *target = bank->target;
558 uint32_t buffer_size;
559 struct working_area *write_algorithm;
560 struct working_area *source;
561 static const uint8_t gd32vf103_flash_write_code[] = {
562 #include "../../../contrib/loaders/flash/gd32vf103/gd32vf103.inc"
563 };
564
565 /* flash write code */
566 if (target_alloc_working_area(target, sizeof(gd32vf103_flash_write_code),
567 &write_algorithm) != ERROR_OK) {
568 LOG_WARNING("no working area available, can't do block memory writes");
569 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
570 }
571
572 int retval = target_write_buffer(target, write_algorithm->address,
573 sizeof(gd32vf103_flash_write_code), gd32vf103_flash_write_code);
574 if (retval != ERROR_OK) {
575 target_free_working_area(target, write_algorithm);
576 return retval;
577 }
578
579 /* memory buffer */
580 buffer_size = target_get_working_area_avail(target);
581 buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
582
583 retval = target_alloc_working_area(target, buffer_size, &source);
584 /* Allocated size is always word aligned */
585 if (retval != ERROR_OK) {
586 target_free_working_area(target, write_algorithm);
587 LOG_WARNING("no large enough working area available, can't do block memory writes");
588 /* target_alloc_working_area() may return ERROR_FAIL if area backup fails:
589 * convert any error to ERROR_TARGET_RESOURCE_NOT_AVAILABLE
590 */
591 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
592 }
593
594 struct reg_param reg_params[4];
595
596 init_reg_param(&reg_params[0], "a0", 32, PARAM_OUT); /* poiner to FLASH_SR */
597 init_reg_param(&reg_params[1], "a1", 32, PARAM_OUT); /* count (halfword-16bit) */
598 init_reg_param(&reg_params[2], "a2", 32, PARAM_OUT); /* buffer start */
599 init_reg_param(&reg_params[3], "a3", 32, PARAM_IN_OUT); /* target address */
600
601 while (hwords_count > 0) {
602 uint32_t thisrun_hwords = source->size / 2;
603
604 /* Limit to the amount of data we actually want to write */
605 if (thisrun_hwords > hwords_count)
606 thisrun_hwords = hwords_count;
607
608 /* Write data to buffer */
609 retval = target_write_buffer(target, source->address,
610 thisrun_hwords * 2, buffer);
611 if (retval != ERROR_OK)
612 break;
613
614 buf_set_u32(reg_params[0].value, 0, 32, stm32x_get_flash_reg(bank, STM32_FLASH_SR));
615 buf_set_u32(reg_params[1].value, 0, 32, thisrun_hwords);
616 buf_set_u32(reg_params[2].value, 0, 32, source->address);
617 buf_set_u32(reg_params[3].value, 0, 32, address);
618
619 retval = target_run_algorithm(target,
620 0, NULL,
621 ARRAY_SIZE(reg_params), reg_params,
622 write_algorithm->address,
623 write_algorithm->address + sizeof(gd32vf103_flash_write_code) - 4,
624 10000, NULL);
625
626 if (retval != ERROR_OK) {
627 LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d",
628 write_algorithm->address, retval);
629 break;
630 }
631
632 /* Actually we just need to check for programming errors
633 * stm32x_wait_status_busy also reports error and clears status bits
634 */
635 retval = stm32x_wait_status_busy(bank, 5);
636 if (retval != ERROR_OK) {
637 LOG_ERROR("flash write failed at address 0x%"PRIx32,
638 buf_get_u32(reg_params[3].value, 0, 32));
639 break;
640 }
641
642 /* Update counters */
643 buffer += thisrun_hwords * 2;
644 address += thisrun_hwords * 2;
645 hwords_count -= thisrun_hwords;
646 }
647
648 for (unsigned int i = 0; i < ARRAY_SIZE(reg_params); i++)
649 destroy_reg_param(&reg_params[i]);
650
651 target_free_working_area(target, source);
652 target_free_working_area(target, write_algorithm);
653
654 return retval;
655 }
656
657 /** Writes a block to flash either using target algorithm
658 * or use fallback, host controlled halfword-by-halfword access.
659 * Flash controller must be unlocked before this call.
660 */
661 static int stm32x_write_block(struct flash_bank *bank,
662 const uint8_t *buffer, uint32_t address, uint32_t hwords_count)
663 {
664 struct target *target = bank->target;
665
666 /* The flash write must be aligned to a halfword boundary.
667 * The flash infrastructure ensures it, do just a security check
668 */
669 assert(address % 2 == 0);
670
671 int retval;
672 struct arm *arm = target_to_arm(target);
673 if (is_arm(arm)) {
674 /* try using a block write - on ARM architecture or... */
675 retval = stm32x_write_block_async(bank, buffer, address, hwords_count);
676 } else {
677 /* ... RISC-V architecture */
678 retval = stm32x_write_block_riscv(bank, buffer, address, hwords_count);
679 }
680
681 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
682 /* if block write failed (no sufficient working area),
683 * we use normal (slow) single halfword accesses */
684 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
685
686 while (hwords_count > 0) {
687 retval = target_write_memory(target, address, 2, 1, buffer);
688 if (retval != ERROR_OK)
689 return retval;
690
691 retval = stm32x_wait_status_busy(bank, 5);
692 if (retval != ERROR_OK)
693 return retval;
694
695 hwords_count--;
696 buffer += 2;
697 address += 2;
698 }
699 }
700 return retval;
701 }
702
703 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
704 uint32_t offset, uint32_t count)
705 {
706 struct target *target = bank->target;
707
708 if (bank->target->state != TARGET_HALTED) {
709 LOG_ERROR("Target not halted");
710 return ERROR_TARGET_NOT_HALTED;
711 }
712
713 /* The flash write must be aligned to a halfword boundary.
714 * The flash infrastructure ensures it, do just a security check
715 */
716 assert(offset % 2 == 0);
717 assert(count % 2 == 0);
718
719 int retval, retval2;
720
721 /* unlock flash registers */
722 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
723 if (retval != ERROR_OK)
724 return retval;
725 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
726 if (retval != ERROR_OK)
727 goto reset_pg_and_lock;
728
729 /* enable flash programming */
730 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
731 if (retval != ERROR_OK)
732 goto reset_pg_and_lock;
733
734 /* write to flash */
735 retval = stm32x_write_block(bank, buffer, bank->base + offset, count / 2);
736
737 reset_pg_and_lock:
738 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
739 if (retval == ERROR_OK)
740 retval = retval2;
741
742 return retval;
743 }
744
745 struct stm32x_property_addr {
746 uint32_t device_id;
747 uint32_t flash_size;
748 };
749
750 static int stm32x_get_property_addr(struct target *target, struct stm32x_property_addr *addr)
751 {
752 if (!target_was_examined(target)) {
753 LOG_ERROR("Target not examined yet");
754 return ERROR_TARGET_NOT_EXAMINED;
755 }
756
757 switch (cortex_m_get_partno_safe(target)) {
758 case CORTEX_M0_PARTNO: /* STM32F0x devices */
759 addr->device_id = 0x40015800;
760 addr->flash_size = 0x1FFFF7CC;
761 return ERROR_OK;
762 case CORTEX_M3_PARTNO: /* STM32F1x devices */
763 addr->device_id = 0xE0042000;
764 addr->flash_size = 0x1FFFF7E0;
765 return ERROR_OK;
766 case CORTEX_M4_PARTNO: /* STM32F3x devices */
767 addr->device_id = 0xE0042000;
768 addr->flash_size = 0x1FFFF7CC;
769 return ERROR_OK;
770 case CORTEX_M23_PARTNO: /* GD32E23x devices */
771 addr->device_id = 0x40015800;
772 addr->flash_size = 0x1FFFF7E0;
773 return ERROR_OK;
774 case CORTEX_M_PARTNO_INVALID:
775 /* Check for GD32VF103 with RISC-V CPU */
776 if (strcmp(target_type_name(target), "riscv") == 0
777 && target_address_bits(target) == 32) {
778 /* There is nothing like arm common_magic in riscv_info_t
779 * check text name of target and if target is 32-bit
780 */
781 addr->device_id = 0xE0042000;
782 addr->flash_size = 0x1FFFF7E0;
783 return ERROR_OK;
784 }
785 /* fallthrough */
786 default:
787 LOG_ERROR("Cannot identify target as a stm32x");
788 return ERROR_FAIL;
789 }
790 }
791
792 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
793 {
794 struct target *target = bank->target;
795 struct stm32x_property_addr addr;
796
797 int retval = stm32x_get_property_addr(target, &addr);
798 if (retval != ERROR_OK)
799 return retval;
800
801 return target_read_u32(target, addr.device_id, device_id);
802 }
803
804 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
805 {
806 struct target *target = bank->target;
807 struct stm32x_property_addr addr;
808
809 int retval = stm32x_get_property_addr(target, &addr);
810 if (retval != ERROR_OK)
811 return retval;
812
813 return target_read_u16(target, addr.flash_size, flash_size_in_kb);
814 }
815
816 static int stm32x_probe(struct flash_bank *bank)
817 {
818 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
819 uint16_t flash_size_in_kb;
820 uint16_t max_flash_size_in_kb;
821 uint32_t dbgmcu_idcode;
822 int page_size;
823 uint32_t base_address = 0x08000000;
824
825 stm32x_info->probed = false;
826 stm32x_info->register_base = FLASH_REG_BASE_B0;
827 stm32x_info->user_data_offset = 10;
828 stm32x_info->option_offset = 0;
829
830 /* default factory read protection level 0 */
831 stm32x_info->default_rdp = 0xA5;
832
833 /* read stm32 device id register */
834 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
835 if (retval != ERROR_OK)
836 return retval;
837
838 LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
839
840 uint16_t device_id = dbgmcu_idcode & 0xfff;
841 uint16_t rev_id = dbgmcu_idcode >> 16;
842
843 /* set page size, protection granularity and max flash size depending on family */
844 switch (device_id) {
845 case 0x440: /* stm32f05x */
846 page_size = 1024;
847 stm32x_info->ppage_size = 4;
848 max_flash_size_in_kb = 64;
849 stm32x_info->user_data_offset = 16;
850 stm32x_info->option_offset = 6;
851 stm32x_info->default_rdp = 0xAA;
852 stm32x_info->can_load_options = true;
853 break;
854 case 0x444: /* stm32f03x */
855 case 0x445: /* stm32f04x */
856 page_size = 1024;
857 stm32x_info->ppage_size = 4;
858 max_flash_size_in_kb = 32;
859 stm32x_info->user_data_offset = 16;
860 stm32x_info->option_offset = 6;
861 stm32x_info->default_rdp = 0xAA;
862 stm32x_info->can_load_options = true;
863 break;
864 case 0x448: /* stm32f07x */
865 page_size = 2048;
866 stm32x_info->ppage_size = 4;
867 max_flash_size_in_kb = 128;
868 stm32x_info->user_data_offset = 16;
869 stm32x_info->option_offset = 6;
870 stm32x_info->default_rdp = 0xAA;
871 stm32x_info->can_load_options = true;
872 break;
873 case 0x442: /* stm32f09x */
874 page_size = 2048;
875 stm32x_info->ppage_size = 4;
876 max_flash_size_in_kb = 256;
877 stm32x_info->user_data_offset = 16;
878 stm32x_info->option_offset = 6;
879 stm32x_info->default_rdp = 0xAA;
880 stm32x_info->can_load_options = true;
881 break;
882 case 0x410: /* stm32f1x medium-density */
883 page_size = 1024;
884 stm32x_info->ppage_size = 4;
885 max_flash_size_in_kb = 128;
886 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
887 share DEV_ID with STM32F101/2/3 medium-density line,
888 however they use a REV_ID different from any STM32 device.
889 The main difference is another offset of user option bits
890 (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
891 (FLASH_OBR/FMC_OBSTAT 0x4002201C).
892 This caused problems e.g. during flash block programming
893 because of unexpected active hardware watchog. */
894 switch (rev_id) {
895 case 0x1303: /* gd32f1x0 */
896 stm32x_info->user_data_offset = 16;
897 stm32x_info->option_offset = 6;
898 max_flash_size_in_kb = 64;
899 break;
900 case 0x1704: /* gd32f3x0 */
901 stm32x_info->user_data_offset = 16;
902 stm32x_info->option_offset = 6;
903 break;
904 case 0x1906: /* gd32vf103 */
905 break;
906 case 0x1909: /* gd32e23x */
907 stm32x_info->user_data_offset = 16;
908 stm32x_info->option_offset = 6;
909 max_flash_size_in_kb = 64;
910 break;
911 }
912 break;
913 case 0x412: /* stm32f1x low-density */
914 page_size = 1024;
915 stm32x_info->ppage_size = 4;
916 max_flash_size_in_kb = 32;
917 break;
918 case 0x414: /* stm32f1x high-density */
919 page_size = 2048;
920 stm32x_info->ppage_size = 2;
921 max_flash_size_in_kb = 512;
922 break;
923 case 0x418: /* stm32f1x connectivity */
924 page_size = 2048;
925 stm32x_info->ppage_size = 2;
926 max_flash_size_in_kb = 256;
927 break;
928 case 0x430: /* stm32f1 XL-density (dual flash banks) */
929 page_size = 2048;
930 stm32x_info->ppage_size = 2;
931 max_flash_size_in_kb = 1024;
932 stm32x_info->has_dual_banks = true;
933 break;
934 case 0x420: /* stm32f100xx low- and medium-density value line */
935 page_size = 1024;
936 stm32x_info->ppage_size = 4;
937 max_flash_size_in_kb = 128;
938 break;
939 case 0x428: /* stm32f100xx high-density value line */
940 page_size = 2048;
941 stm32x_info->ppage_size = 4;
942 max_flash_size_in_kb = 512;
943 break;
944 case 0x422: /* stm32f302/3xb/c */
945 page_size = 2048;
946 stm32x_info->ppage_size = 2;
947 max_flash_size_in_kb = 256;
948 stm32x_info->user_data_offset = 16;
949 stm32x_info->option_offset = 6;
950 stm32x_info->default_rdp = 0xAA;
951 stm32x_info->can_load_options = true;
952 break;
953 case 0x446: /* stm32f303xD/E */
954 page_size = 2048;
955 stm32x_info->ppage_size = 2;
956 max_flash_size_in_kb = 512;
957 stm32x_info->user_data_offset = 16;
958 stm32x_info->option_offset = 6;
959 stm32x_info->default_rdp = 0xAA;
960 stm32x_info->can_load_options = true;
961 break;
962 case 0x432: /* stm32f37x */
963 page_size = 2048;
964 stm32x_info->ppage_size = 2;
965 max_flash_size_in_kb = 256;
966 stm32x_info->user_data_offset = 16;
967 stm32x_info->option_offset = 6;
968 stm32x_info->default_rdp = 0xAA;
969 stm32x_info->can_load_options = true;
970 break;
971 case 0x438: /* stm32f33x */
972 case 0x439: /* stm32f302x6/8 */
973 page_size = 2048;
974 stm32x_info->ppage_size = 2;
975 max_flash_size_in_kb = 64;
976 stm32x_info->user_data_offset = 16;
977 stm32x_info->option_offset = 6;
978 stm32x_info->default_rdp = 0xAA;
979 stm32x_info->can_load_options = true;
980 break;
981 default:
982 LOG_WARNING("Cannot identify target as a STM32 family.");
983 return ERROR_FAIL;
984 }
985
986 /* get flash size from target. */
987 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
988
989 /* failed reading flash size or flash size invalid (early silicon),
990 * default to max target family */
991 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
992 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
993 max_flash_size_in_kb);
994 flash_size_in_kb = max_flash_size_in_kb;
995 }
996
997 if (stm32x_info->has_dual_banks) {
998 /* split reported size into matching bank */
999 if (bank->base != 0x08080000) {
1000 /* bank 0 will be fixed 512k */
1001 flash_size_in_kb = 512;
1002 } else {
1003 flash_size_in_kb -= 512;
1004 /* bank1 also uses a register offset */
1005 stm32x_info->register_base = FLASH_REG_BASE_B1;
1006 base_address = 0x08080000;
1007 }
1008 }
1009
1010 /* if the user sets the size manually then ignore the probed value
1011 * this allows us to work around devices that have a invalid flash size register value */
1012 if (stm32x_info->user_bank_size) {
1013 LOG_INFO("ignoring flash probed value, using configured bank size");
1014 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
1015 }
1016
1017 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
1018
1019 /* did we assign flash size? */
1020 assert(flash_size_in_kb != 0xffff);
1021
1022 /* calculate numbers of pages */
1023 int num_pages = flash_size_in_kb * 1024 / page_size;
1024
1025 /* check that calculation result makes sense */
1026 assert(num_pages > 0);
1027
1028 free(bank->sectors);
1029 bank->sectors = NULL;
1030
1031 free(bank->prot_blocks);
1032 bank->prot_blocks = NULL;
1033
1034 bank->base = base_address;
1035 bank->size = (num_pages * page_size);
1036
1037 bank->num_sectors = num_pages;
1038 bank->sectors = alloc_block_array(0, page_size, num_pages);
1039 if (!bank->sectors)
1040 return ERROR_FAIL;
1041
1042 /* calculate number of write protection blocks */
1043 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
1044 if (num_prot_blocks > 32)
1045 num_prot_blocks = 32;
1046
1047 bank->num_prot_blocks = num_prot_blocks;
1048 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
1049 if (!bank->prot_blocks)
1050 return ERROR_FAIL;
1051
1052 if (num_prot_blocks == 32)
1053 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
1054
1055 stm32x_info->probed = true;
1056
1057 return ERROR_OK;
1058 }
1059
1060 static int stm32x_auto_probe(struct flash_bank *bank)
1061 {
1062 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1063 if (stm32x_info->probed)
1064 return ERROR_OK;
1065 return stm32x_probe(bank);
1066 }
1067
1068 #if 0
1069 COMMAND_HANDLER(stm32x_handle_part_id_command)
1070 {
1071 return ERROR_OK;
1072 }
1073 #endif
1074
1075 static const char *get_stm32f0_revision(uint16_t rev_id)
1076 {
1077 const char *rev_str = NULL;
1078
1079 switch (rev_id) {
1080 case 0x1000:
1081 rev_str = "1.0";
1082 break;
1083 case 0x2000:
1084 rev_str = "2.0";
1085 break;
1086 }
1087 return rev_str;
1088 }
1089
1090 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
1091 {
1092 uint32_t dbgmcu_idcode;
1093
1094 /* read stm32 device id register */
1095 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1096 if (retval != ERROR_OK)
1097 return retval;
1098
1099 uint16_t device_id = dbgmcu_idcode & 0xfff;
1100 uint16_t rev_id = dbgmcu_idcode >> 16;
1101 const char *device_str;
1102 const char *rev_str = NULL;
1103
1104 switch (device_id) {
1105 case 0x410:
1106 device_str = "STM32F10x (Medium Density)";
1107
1108 switch (rev_id) {
1109 case 0x0000:
1110 rev_str = "A";
1111 break;
1112
1113 case 0x1303: /* gd32f1x0 */
1114 device_str = "GD32F1x0";
1115 break;
1116
1117 case 0x1704: /* gd32f3x0 */
1118 device_str = "GD32F3x0";
1119 break;
1120
1121 case 0x1906:
1122 device_str = "GD32VF103";
1123 break;
1124
1125 case 0x1909: /* gd32e23x */
1126 device_str = "GD32E23x";
1127 break;
1128
1129 case 0x2000:
1130 rev_str = "B";
1131 break;
1132
1133 case 0x2001:
1134 rev_str = "Z";
1135 break;
1136
1137 case 0x2003:
1138 rev_str = "Y";
1139 break;
1140 }
1141 break;
1142
1143 case 0x412:
1144 device_str = "STM32F10x (Low Density)";
1145
1146 switch (rev_id) {
1147 case 0x1000:
1148 rev_str = "A";
1149 break;
1150 }
1151 break;
1152
1153 case 0x414:
1154 device_str = "STM32F10x (High Density)";
1155
1156 switch (rev_id) {
1157 case 0x1000:
1158 rev_str = "A";
1159 break;
1160
1161 case 0x1001:
1162 rev_str = "Z";
1163 break;
1164
1165 case 0x1003:
1166 rev_str = "Y";
1167 break;
1168 }
1169 break;
1170
1171 case 0x418:
1172 device_str = "STM32F10x (Connectivity)";
1173
1174 switch (rev_id) {
1175 case 0x1000:
1176 rev_str = "A";
1177 break;
1178
1179 case 0x1001:
1180 rev_str = "Z";
1181 break;
1182 }
1183 break;
1184
1185 case 0x420:
1186 device_str = "STM32F100 (Low/Medium Density)";
1187
1188 switch (rev_id) {
1189 case 0x1000:
1190 rev_str = "A";
1191 break;
1192
1193 case 0x1001:
1194 rev_str = "Z";
1195 break;
1196 }
1197 break;
1198
1199 case 0x422:
1200 device_str = "STM32F302xB/C";
1201
1202 switch (rev_id) {
1203 case 0x1000:
1204 rev_str = "A";
1205 break;
1206
1207 case 0x1001:
1208 rev_str = "Z";
1209 break;
1210
1211 case 0x1003:
1212 rev_str = "Y";
1213 break;
1214
1215 case 0x2000:
1216 rev_str = "B";
1217 break;
1218 }
1219 break;
1220
1221 case 0x428:
1222 device_str = "STM32F100 (High Density)";
1223
1224 switch (rev_id) {
1225 case 0x1000:
1226 rev_str = "A";
1227 break;
1228
1229 case 0x1001:
1230 rev_str = "Z";
1231 break;
1232 }
1233 break;
1234
1235 case 0x430:
1236 device_str = "STM32F10x (XL Density)";
1237
1238 switch (rev_id) {
1239 case 0x1000:
1240 rev_str = "A";
1241 break;
1242 }
1243 break;
1244
1245 case 0x432:
1246 device_str = "STM32F37x";
1247
1248 switch (rev_id) {
1249 case 0x1000:
1250 rev_str = "A";
1251 break;
1252
1253 case 0x2000:
1254 rev_str = "B";
1255 break;
1256 }
1257 break;
1258
1259 case 0x438:
1260 device_str = "STM32F33x";
1261
1262 switch (rev_id) {
1263 case 0x1000:
1264 rev_str = "A";
1265 break;
1266 }
1267 break;
1268
1269 case 0x439:
1270 device_str = "STM32F302x6/8";
1271
1272 switch (rev_id) {
1273 case 0x1000:
1274 rev_str = "A";
1275 break;
1276
1277 case 0x1001:
1278 rev_str = "Z";
1279 break;
1280 }
1281 break;
1282
1283 case 0x444:
1284 device_str = "STM32F03x";
1285 rev_str = get_stm32f0_revision(rev_id);
1286 break;
1287
1288 case 0x440:
1289 device_str = "STM32F05x";
1290 rev_str = get_stm32f0_revision(rev_id);
1291 break;
1292
1293 case 0x445:
1294 device_str = "STM32F04x";
1295 rev_str = get_stm32f0_revision(rev_id);
1296 break;
1297
1298 case 0x446:
1299 device_str = "STM32F303xD/E";
1300 switch (rev_id) {
1301 case 0x1000:
1302 rev_str = "A";
1303 break;
1304 }
1305 break;
1306
1307 case 0x448:
1308 device_str = "STM32F07x";
1309 rev_str = get_stm32f0_revision(rev_id);
1310 break;
1311
1312 case 0x442:
1313 device_str = "STM32F09x";
1314 rev_str = get_stm32f0_revision(rev_id);
1315 break;
1316
1317 default:
1318 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1319 return ERROR_FAIL;
1320 }
1321
1322 if (rev_str)
1323 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1324 else
1325 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1326
1327 return ERROR_OK;
1328 }
1329
1330 COMMAND_HANDLER(stm32x_handle_lock_command)
1331 {
1332 struct target *target = NULL;
1333 struct stm32x_flash_bank *stm32x_info = NULL;
1334
1335 if (CMD_ARGC < 1)
1336 return ERROR_COMMAND_SYNTAX_ERROR;
1337
1338 struct flash_bank *bank;
1339 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1340 if (retval != ERROR_OK)
1341 return retval;
1342
1343 stm32x_info = bank->driver_priv;
1344
1345 target = bank->target;
1346
1347 if (target->state != TARGET_HALTED) {
1348 LOG_ERROR("Target not halted");
1349 return ERROR_TARGET_NOT_HALTED;
1350 }
1351
1352 retval = stm32x_check_operation_supported(bank);
1353 if (retval != ERROR_OK)
1354 return retval;
1355
1356 if (stm32x_erase_options(bank) != ERROR_OK) {
1357 command_print(CMD, "stm32x failed to erase options");
1358 return ERROR_OK;
1359 }
1360
1361 /* set readout protection */
1362 stm32x_info->option_bytes.rdp = 0;
1363
1364 if (stm32x_write_options(bank) != ERROR_OK) {
1365 command_print(CMD, "stm32x failed to lock device");
1366 return ERROR_OK;
1367 }
1368
1369 command_print(CMD, "stm32x locked");
1370
1371 return ERROR_OK;
1372 }
1373
1374 COMMAND_HANDLER(stm32x_handle_unlock_command)
1375 {
1376 struct target *target = NULL;
1377
1378 if (CMD_ARGC < 1)
1379 return ERROR_COMMAND_SYNTAX_ERROR;
1380
1381 struct flash_bank *bank;
1382 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1383 if (retval != ERROR_OK)
1384 return retval;
1385
1386 target = bank->target;
1387
1388 if (target->state != TARGET_HALTED) {
1389 LOG_ERROR("Target not halted");
1390 return ERROR_TARGET_NOT_HALTED;
1391 }
1392
1393 retval = stm32x_check_operation_supported(bank);
1394 if (retval != ERROR_OK)
1395 return retval;
1396
1397 if (stm32x_erase_options(bank) != ERROR_OK) {
1398 command_print(CMD, "stm32x failed to erase options");
1399 return ERROR_OK;
1400 }
1401
1402 if (stm32x_write_options(bank) != ERROR_OK) {
1403 command_print(CMD, "stm32x failed to unlock device");
1404 return ERROR_OK;
1405 }
1406
1407 command_print(CMD, "stm32x unlocked.\n"
1408 "INFO: a reset or power cycle is required "
1409 "for the new settings to take effect.");
1410
1411 return ERROR_OK;
1412 }
1413
1414 COMMAND_HANDLER(stm32x_handle_options_read_command)
1415 {
1416 uint32_t optionbyte, protection;
1417 struct target *target = NULL;
1418 struct stm32x_flash_bank *stm32x_info = NULL;
1419
1420 if (CMD_ARGC < 1)
1421 return ERROR_COMMAND_SYNTAX_ERROR;
1422
1423 struct flash_bank *bank;
1424 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1425 if (retval != ERROR_OK)
1426 return retval;
1427
1428 stm32x_info = bank->driver_priv;
1429
1430 target = bank->target;
1431
1432 if (target->state != TARGET_HALTED) {
1433 LOG_ERROR("Target not halted");
1434 return ERROR_TARGET_NOT_HALTED;
1435 }
1436
1437 retval = stm32x_check_operation_supported(bank);
1438 if (retval != ERROR_OK)
1439 return retval;
1440
1441 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1442 if (retval != ERROR_OK)
1443 return retval;
1444
1445 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1446
1447 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1448 if (retval != ERROR_OK)
1449 return retval;
1450
1451 if (optionbyte & (1 << OPT_ERROR))
1452 command_print(CMD, "option byte complement error");
1453
1454 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1455 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1456
1457 command_print(CMD, "read protection: %s",
1458 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1459
1460 /* user option bytes are offset depending on variant */
1461 optionbyte >>= stm32x_info->option_offset;
1462
1463 command_print(CMD, "watchdog: %sware",
1464 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1465
1466 command_print(CMD, "stop mode: %sreset generated upon entry",
1467 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1468
1469 command_print(CMD, "standby mode: %sreset generated upon entry",
1470 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1471
1472 if (stm32x_info->has_dual_banks)
1473 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1474
1475 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1476
1477 return ERROR_OK;
1478 }
1479
1480 COMMAND_HANDLER(stm32x_handle_options_write_command)
1481 {
1482 struct target *target = NULL;
1483 struct stm32x_flash_bank *stm32x_info = NULL;
1484 uint8_t optionbyte;
1485 uint16_t useropt;
1486
1487 if (CMD_ARGC < 2)
1488 return ERROR_COMMAND_SYNTAX_ERROR;
1489
1490 struct flash_bank *bank;
1491 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1492 if (retval != ERROR_OK)
1493 return retval;
1494
1495 stm32x_info = bank->driver_priv;
1496
1497 target = bank->target;
1498
1499 if (target->state != TARGET_HALTED) {
1500 LOG_ERROR("Target not halted");
1501 return ERROR_TARGET_NOT_HALTED;
1502 }
1503
1504 retval = stm32x_check_operation_supported(bank);
1505 if (retval != ERROR_OK)
1506 return retval;
1507
1508 retval = stm32x_read_options(bank);
1509 if (retval != ERROR_OK)
1510 return retval;
1511
1512 /* start with current options */
1513 optionbyte = stm32x_info->option_bytes.user;
1514 useropt = stm32x_info->option_bytes.data;
1515
1516 /* skip over flash bank */
1517 CMD_ARGC--;
1518 CMD_ARGV++;
1519
1520 while (CMD_ARGC) {
1521 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1522 optionbyte |= (1 << 0);
1523 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1524 optionbyte &= ~(1 << 0);
1525 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1526 optionbyte |= (1 << 1);
1527 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1528 optionbyte &= ~(1 << 1);
1529 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1530 optionbyte |= (1 << 2);
1531 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1532 optionbyte &= ~(1 << 2);
1533 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1534 if (CMD_ARGC < 2)
1535 return ERROR_COMMAND_SYNTAX_ERROR;
1536 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1537 CMD_ARGC--;
1538 CMD_ARGV++;
1539 } else if (stm32x_info->has_dual_banks) {
1540 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1541 optionbyte |= (1 << 3);
1542 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1543 optionbyte &= ~(1 << 3);
1544 else
1545 return ERROR_COMMAND_SYNTAX_ERROR;
1546 } else
1547 return ERROR_COMMAND_SYNTAX_ERROR;
1548 CMD_ARGC--;
1549 CMD_ARGV++;
1550 }
1551
1552 if (stm32x_erase_options(bank) != ERROR_OK) {
1553 command_print(CMD, "stm32x failed to erase options");
1554 return ERROR_OK;
1555 }
1556
1557 stm32x_info->option_bytes.user = optionbyte;
1558 stm32x_info->option_bytes.data = useropt;
1559
1560 if (stm32x_write_options(bank) != ERROR_OK) {
1561 command_print(CMD, "stm32x failed to write options");
1562 return ERROR_OK;
1563 }
1564
1565 command_print(CMD, "stm32x write options complete.\n"
1566 "INFO: %spower cycle is required "
1567 "for the new settings to take effect.",
1568 stm32x_info->can_load_options
1569 ? "'stm32f1x options_load' command or " : "");
1570
1571 return ERROR_OK;
1572 }
1573
1574 COMMAND_HANDLER(stm32x_handle_options_load_command)
1575 {
1576 if (CMD_ARGC < 1)
1577 return ERROR_COMMAND_SYNTAX_ERROR;
1578
1579 struct flash_bank *bank;
1580 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1581 if (retval != ERROR_OK)
1582 return retval;
1583
1584 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1585
1586 if (!stm32x_info->can_load_options) {
1587 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1588 "required instead.");
1589 return ERROR_FAIL;
1590 }
1591
1592 struct target *target = bank->target;
1593
1594 if (target->state != TARGET_HALTED) {
1595 LOG_ERROR("Target not halted");
1596 return ERROR_TARGET_NOT_HALTED;
1597 }
1598
1599 retval = stm32x_check_operation_supported(bank);
1600 if (retval != ERROR_OK)
1601 return retval;
1602
1603 /* unlock option flash registers */
1604 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1605 if (retval != ERROR_OK)
1606 return retval;
1607 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1608 if (retval != ERROR_OK) {
1609 (void)target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1610 return retval;
1611 }
1612
1613 /* force re-load of option bytes - generates software reset */
1614 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1615 if (retval != ERROR_OK)
1616 return retval;
1617
1618 return ERROR_OK;
1619 }
1620
1621 static int stm32x_mass_erase(struct flash_bank *bank)
1622 {
1623 struct target *target = bank->target;
1624
1625 if (target->state != TARGET_HALTED) {
1626 LOG_ERROR("Target not halted");
1627 return ERROR_TARGET_NOT_HALTED;
1628 }
1629
1630 /* unlock option flash registers */
1631 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1632 if (retval != ERROR_OK)
1633 return retval;
1634 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1635 if (retval != ERROR_OK)
1636 goto flash_lock;
1637
1638 /* mass erase flash memory */
1639 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1640 if (retval != ERROR_OK)
1641 goto flash_lock;
1642 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1643 FLASH_MER | FLASH_STRT);
1644 if (retval != ERROR_OK)
1645 goto flash_lock;
1646
1647 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1648
1649 flash_lock:
1650 {
1651 int retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1652 if (retval == ERROR_OK)
1653 retval = retval2;
1654 }
1655 return retval;
1656 }
1657
1658 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1659 {
1660 if (CMD_ARGC < 1)
1661 return ERROR_COMMAND_SYNTAX_ERROR;
1662
1663 struct flash_bank *bank;
1664 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1665 if (retval != ERROR_OK)
1666 return retval;
1667
1668 retval = stm32x_mass_erase(bank);
1669 if (retval == ERROR_OK)
1670 command_print(CMD, "stm32x mass erase complete");
1671 else
1672 command_print(CMD, "stm32x mass erase failed");
1673
1674 return retval;
1675 }
1676
1677 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1678 {
1679 .name = "lock",
1680 .handler = stm32x_handle_lock_command,
1681 .mode = COMMAND_EXEC,
1682 .usage = "bank_id",
1683 .help = "Lock entire flash device.",
1684 },
1685 {
1686 .name = "unlock",
1687 .handler = stm32x_handle_unlock_command,
1688 .mode = COMMAND_EXEC,
1689 .usage = "bank_id",
1690 .help = "Unlock entire protected flash device.",
1691 },
1692 {
1693 .name = "mass_erase",
1694 .handler = stm32x_handle_mass_erase_command,
1695 .mode = COMMAND_EXEC,
1696 .usage = "bank_id",
1697 .help = "Erase entire flash device.",
1698 },
1699 {
1700 .name = "options_read",
1701 .handler = stm32x_handle_options_read_command,
1702 .mode = COMMAND_EXEC,
1703 .usage = "bank_id",
1704 .help = "Read and display device option bytes.",
1705 },
1706 {
1707 .name = "options_write",
1708 .handler = stm32x_handle_options_write_command,
1709 .mode = COMMAND_EXEC,
1710 .usage = "bank_id ('SWWDG'|'HWWDG') "
1711 "('RSTSTNDBY'|'NORSTSTNDBY') "
1712 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1713 .help = "Replace bits in device option bytes.",
1714 },
1715 {
1716 .name = "options_load",
1717 .handler = stm32x_handle_options_load_command,
1718 .mode = COMMAND_EXEC,
1719 .usage = "bank_id",
1720 .help = "Force re-load of device option bytes.",
1721 },
1722 COMMAND_REGISTRATION_DONE
1723 };
1724
1725 static const struct command_registration stm32f1x_command_handlers[] = {
1726 {
1727 .name = "stm32f1x",
1728 .mode = COMMAND_ANY,
1729 .help = "stm32f1x flash command group",
1730 .usage = "",
1731 .chain = stm32f1x_exec_command_handlers,
1732 },
1733 COMMAND_REGISTRATION_DONE
1734 };
1735
1736 const struct flash_driver stm32f1x_flash = {
1737 .name = "stm32f1x",
1738 .commands = stm32f1x_command_handlers,
1739 .flash_bank_command = stm32x_flash_bank_command,
1740 .erase = stm32x_erase,
1741 .protect = stm32x_protect,
1742 .write = stm32x_write,
1743 .read = default_flash_read,
1744 .probe = stm32x_probe,
1745 .auto_probe = stm32x_auto_probe,
1746 .erase_check = default_flash_blank_check,
1747 .protect_check = stm32x_protect_check,
1748 .info = get_stm32x_info,
1749 .free_driver_priv = default_flash_free_driver_priv,
1750 };
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