1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
36 /* stm32x register locations */
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
62 /* option byte location */
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
73 /* FLASH_CR register bits */
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
84 /* FLASH_SR register bits */
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
91 /* STM32_FLASH_OBR bit definitions (reading) */
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
100 /* register unlock keys */
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
105 struct stm32x_options
{
107 uint16_t user_options
;
108 uint16_t protection
[4];
111 struct stm32x_flash_bank
{
112 struct stm32x_options option_bytes
;
113 struct working_area
*write_algorithm
;
118 /* used to access dual flash bank stm32xl */
119 uint32_t register_base
;
122 static int stm32x_mass_erase(struct flash_bank
*bank
);
123 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
);
125 /* flash bank stm32x <base> <size> 0 0 <target#>
127 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
129 struct stm32x_flash_bank
*stm32x_info
;
132 return ERROR_COMMAND_SYNTAX_ERROR
;
134 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
136 bank
->driver_priv
= stm32x_info
;
137 stm32x_info
->write_algorithm
= NULL
;
138 stm32x_info
->probed
= 0;
139 stm32x_info
->has_dual_banks
= false;
140 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
145 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
147 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
148 return reg
+ stm32x_info
->register_base
;
151 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
153 struct target
*target
= bank
->target
;
154 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
157 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
159 struct target
*target
= bank
->target
;
161 int retval
= ERROR_OK
;
163 /* wait for busy to clear */
165 retval
= stm32x_get_flash_status(bank
, &status
);
166 if (retval
!= ERROR_OK
)
168 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
169 if ((status
& FLASH_BSY
) == 0)
171 if (timeout
-- <= 0) {
172 LOG_ERROR("timed out waiting for flash");
178 if (status
& FLASH_WRPRTERR
) {
179 LOG_ERROR("stm32x device protected");
183 if (status
& FLASH_PGERR
) {
184 LOG_ERROR("stm32x device programming failed");
188 /* Clear but report errors */
189 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
)) {
190 /* If this operation fails, we ignore it and report the original
193 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
194 FLASH_WRPRTERR
| FLASH_PGERR
);
199 int stm32x_check_operation_supported(struct flash_bank
*bank
)
201 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
203 /* if we have a dual flash bank device then
204 * we need to perform option byte stuff on bank0 only */
205 if (stm32x_info
->register_base
!= FLASH_REG_BASE_B0
) {
206 LOG_ERROR("Option Byte Operation's must use bank0");
207 return ERROR_FLASH_OPERATION_FAILED
;
213 static int stm32x_read_options(struct flash_bank
*bank
)
216 struct stm32x_flash_bank
*stm32x_info
= NULL
;
217 struct target
*target
= bank
->target
;
219 stm32x_info
= bank
->driver_priv
;
221 /* read current option bytes */
222 int retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optiondata
);
223 if (retval
!= ERROR_OK
)
226 stm32x_info
->option_bytes
.user_options
= (uint16_t)0xFFF8 | ((optiondata
>> 2) & 0x07);
227 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
229 if (optiondata
& (1 << OPT_READOUT
))
230 LOG_INFO("Device Security Bit Set");
232 /* each bit refers to a 4bank protection */
233 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &optiondata
);
234 if (retval
!= ERROR_OK
)
237 stm32x_info
->option_bytes
.protection
[0] = (uint16_t)optiondata
;
238 stm32x_info
->option_bytes
.protection
[1] = (uint16_t)(optiondata
>> 8);
239 stm32x_info
->option_bytes
.protection
[2] = (uint16_t)(optiondata
>> 16);
240 stm32x_info
->option_bytes
.protection
[3] = (uint16_t)(optiondata
>> 24);
245 static int stm32x_erase_options(struct flash_bank
*bank
)
247 struct stm32x_flash_bank
*stm32x_info
= NULL
;
248 struct target
*target
= bank
->target
;
250 stm32x_info
= bank
->driver_priv
;
252 /* read current options */
253 stm32x_read_options(bank
);
255 /* unlock flash registers */
256 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
257 if (retval
!= ERROR_OK
)
260 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
261 if (retval
!= ERROR_OK
)
264 /* unlock option flash registers */
265 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
266 if (retval
!= ERROR_OK
)
268 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
269 if (retval
!= ERROR_OK
)
272 /* erase option bytes */
273 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_OPTWRE
);
274 if (retval
!= ERROR_OK
)
276 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
277 if (retval
!= ERROR_OK
)
280 retval
= stm32x_wait_status_busy(bank
, 10);
281 if (retval
!= ERROR_OK
)
284 /* clear readout protection and complementary option bytes
285 * this will also force a device unlock if set */
286 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
291 static int stm32x_write_options(struct flash_bank
*bank
)
293 struct stm32x_flash_bank
*stm32x_info
= NULL
;
294 struct target
*target
= bank
->target
;
296 stm32x_info
= bank
->driver_priv
;
298 /* unlock flash registers */
299 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
300 if (retval
!= ERROR_OK
)
302 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
303 if (retval
!= ERROR_OK
)
306 /* unlock option flash registers */
307 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
308 if (retval
!= ERROR_OK
)
310 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
311 if (retval
!= ERROR_OK
)
314 /* program option bytes */
315 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTPG
| FLASH_OPTWRE
);
316 if (retval
!= ERROR_OK
)
319 /* write user option byte */
320 retval
= target_write_u16(target
, STM32_OB_USER
, stm32x_info
->option_bytes
.user_options
);
321 if (retval
!= ERROR_OK
)
324 retval
= stm32x_wait_status_busy(bank
, 10);
325 if (retval
!= ERROR_OK
)
328 /* write protection byte 1 */
329 retval
= target_write_u16(target
, STM32_OB_WRP0
, stm32x_info
->option_bytes
.protection
[0]);
330 if (retval
!= ERROR_OK
)
333 retval
= stm32x_wait_status_busy(bank
, 10);
334 if (retval
!= ERROR_OK
)
337 /* write protection byte 2 */
338 retval
= target_write_u16(target
, STM32_OB_WRP1
, stm32x_info
->option_bytes
.protection
[1]);
339 if (retval
!= ERROR_OK
)
342 retval
= stm32x_wait_status_busy(bank
, 10);
343 if (retval
!= ERROR_OK
)
346 /* write protection byte 3 */
347 retval
= target_write_u16(target
, STM32_OB_WRP2
, stm32x_info
->option_bytes
.protection
[2]);
348 if (retval
!= ERROR_OK
)
351 retval
= stm32x_wait_status_busy(bank
, 10);
352 if (retval
!= ERROR_OK
)
355 /* write protection byte 4 */
356 retval
= target_write_u16(target
, STM32_OB_WRP3
, stm32x_info
->option_bytes
.protection
[3]);
357 if (retval
!= ERROR_OK
)
360 retval
= stm32x_wait_status_busy(bank
, 10);
361 if (retval
!= ERROR_OK
)
364 /* write readout protection bit */
365 retval
= target_write_u16(target
, STM32_OB_RDP
, stm32x_info
->option_bytes
.RDP
);
366 if (retval
!= ERROR_OK
)
369 retval
= stm32x_wait_status_busy(bank
, 10);
370 if (retval
!= ERROR_OK
)
373 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_LOCK
);
374 if (retval
!= ERROR_OK
)
380 static int stm32x_protect_check(struct flash_bank
*bank
)
382 struct target
*target
= bank
->target
;
383 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
390 if (target
->state
!= TARGET_HALTED
) {
391 LOG_ERROR("Target not halted");
392 return ERROR_TARGET_NOT_HALTED
;
395 int retval
= stm32x_check_operation_supported(bank
);
396 if (ERROR_OK
!= retval
)
399 /* medium density - each bit refers to a 4bank protection
400 * high density - each bit refers to a 2bank protection */
401 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
402 if (retval
!= ERROR_OK
)
405 /* medium density - each protection bit is for 4 * 1K pages
406 * high density - each protection bit is for 2 * 2K pages */
407 num_bits
= (bank
->num_sectors
/ stm32x_info
->ppage_size
);
409 if (stm32x_info
->ppage_size
== 2) {
410 /* high density flash/connectivity line protection */
414 if (protection
& (1 << 31))
417 /* bit 31 controls sector 62 - 255 protection for high density
418 * bit 31 controls sector 62 - 127 protection for connectivity line */
419 for (s
= 62; s
< bank
->num_sectors
; s
++)
420 bank
->sectors
[s
].is_protected
= set
;
422 if (bank
->num_sectors
> 61)
425 for (i
= 0; i
< num_bits
; i
++) {
428 if (protection
& (1 << i
))
431 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
432 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
435 /* low/medium density flash protection */
436 for (i
= 0; i
< num_bits
; i
++) {
439 if (protection
& (1 << i
))
442 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
443 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
450 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
452 struct target
*target
= bank
->target
;
455 if (bank
->target
->state
!= TARGET_HALTED
) {
456 LOG_ERROR("Target not halted");
457 return ERROR_TARGET_NOT_HALTED
;
460 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
461 return stm32x_mass_erase(bank
);
463 /* unlock flash registers */
464 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
465 if (retval
!= ERROR_OK
)
467 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
468 if (retval
!= ERROR_OK
)
471 for (i
= first
; i
<= last
; i
++) {
472 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
);
473 if (retval
!= ERROR_OK
)
475 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_AR
),
476 bank
->base
+ bank
->sectors
[i
].offset
);
477 if (retval
!= ERROR_OK
)
479 retval
= target_write_u32(target
,
480 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
| FLASH_STRT
);
481 if (retval
!= ERROR_OK
)
484 retval
= stm32x_wait_status_busy(bank
, 100);
485 if (retval
!= ERROR_OK
)
488 bank
->sectors
[i
].is_erased
= 1;
491 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
492 if (retval
!= ERROR_OK
)
498 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
500 struct stm32x_flash_bank
*stm32x_info
= NULL
;
501 struct target
*target
= bank
->target
;
502 uint16_t prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
507 stm32x_info
= bank
->driver_priv
;
509 if (target
->state
!= TARGET_HALTED
) {
510 LOG_ERROR("Target not halted");
511 return ERROR_TARGET_NOT_HALTED
;
514 int retval
= stm32x_check_operation_supported(bank
);
515 if (ERROR_OK
!= retval
)
518 if ((first
% stm32x_info
->ppage_size
) != 0) {
519 LOG_WARNING("aligned start protect sector to a %d sector boundary",
520 stm32x_info
->ppage_size
);
521 first
= first
- (first
% stm32x_info
->ppage_size
);
523 if (((last
+ 1) % stm32x_info
->ppage_size
) != 0) {
524 LOG_WARNING("aligned end protect sector to a %d sector boundary",
525 stm32x_info
->ppage_size
);
527 last
= last
- (last
% stm32x_info
->ppage_size
);
531 /* medium density - each bit refers to a 4bank protection
532 * high density - each bit refers to a 2bank protection */
533 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
534 if (retval
!= ERROR_OK
)
537 prot_reg
[0] = (uint16_t)protection
;
538 prot_reg
[1] = (uint16_t)(protection
>> 8);
539 prot_reg
[2] = (uint16_t)(protection
>> 16);
540 prot_reg
[3] = (uint16_t)(protection
>> 24);
542 if (stm32x_info
->ppage_size
== 2) {
543 /* high density flash */
545 /* bit 7 controls sector 62 - 255 protection */
548 prot_reg
[3] &= ~(1 << 7);
550 prot_reg
[3] |= (1 << 7);
558 for (i
= first
; i
<= last
; i
++) {
559 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
560 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
563 prot_reg
[reg
] &= ~(1 << bit
);
565 prot_reg
[reg
] |= (1 << bit
);
568 /* medium density flash */
569 for (i
= first
; i
<= last
; i
++) {
570 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
571 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
574 prot_reg
[reg
] &= ~(1 << bit
);
576 prot_reg
[reg
] |= (1 << bit
);
580 status
= stm32x_erase_options(bank
);
581 if (status
!= ERROR_OK
)
584 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
585 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
586 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
587 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
589 return stm32x_write_options(bank
);
592 static int stm32x_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
593 uint32_t offset
, uint32_t count
)
595 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
596 struct target
*target
= bank
->target
;
597 uint32_t buffer_size
= 16384;
598 struct working_area
*source
;
599 uint32_t address
= bank
->base
+ offset
;
600 struct reg_param reg_params
[5];
601 struct armv7m_algorithm armv7m_info
;
602 int retval
= ERROR_OK
;
604 /* see contrib/loaders/flash/stm32f1x.S for src */
606 static const uint8_t stm32x_flash_write_code
[] = {
607 /* #define STM32_FLASH_SR_OFFSET 0x0C */
609 0x16, 0x68, /* ldr r6, [r2, #0] */
610 0x00, 0x2e, /* cmp r6, #0 */
611 0x18, 0xd0, /* beq exit */
612 0x55, 0x68, /* ldr r5, [r2, #4] */
613 0xb5, 0x42, /* cmp r5, r6 */
614 0xf9, 0xd0, /* beq wait_fifo */
615 0x2e, 0x88, /* ldrh r6, [r5, #0] */
616 0x26, 0x80, /* strh r6, [r4, #0] */
617 0x02, 0x35, /* adds r5, #2 */
618 0x02, 0x34, /* adds r4, #2 */
620 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
621 0x01, 0x27, /* movs r7, #1 */
622 0x3e, 0x42, /* tst r6, r7 */
623 0xfb, 0xd1, /* bne busy */
624 0x14, 0x27, /* movs r7, #0x14 */
625 0x3e, 0x42, /* tst r6, r7 */
626 0x08, 0xd1, /* bne error */
627 0x9d, 0x42, /* cmp r5, r3 */
628 0x01, 0xd3, /* bcc no_wrap */
629 0x15, 0x46, /* mov r5, r2 */
630 0x08, 0x35, /* adds r5, #8 */
632 0x55, 0x60, /* str r5, [r2, #4] */
633 0x01, 0x39, /* subs r1, r1, #1 */
634 0x00, 0x29, /* cmp r1, #0 */
635 0x02, 0xd0, /* beq exit */
636 0xe5, 0xe7, /* b wait_fifo */
638 0x00, 0x20, /* movs r0, #0 */
639 0x50, 0x60, /* str r0, [r2, #4] */
641 0x30, 0x46, /* mov r0, r6 */
642 0x00, 0xbe, /* bkpt #0 */
645 /* flash write code */
646 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
647 &stm32x_info
->write_algorithm
) != ERROR_OK
) {
648 LOG_WARNING("no working area available, can't do block memory writes");
649 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
652 retval
= target_write_buffer(target
, stm32x_info
->write_algorithm
->address
,
653 sizeof(stm32x_flash_write_code
), (uint8_t *)stm32x_flash_write_code
);
654 if (retval
!= ERROR_OK
)
658 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
660 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
661 if (buffer_size
<= 256) {
662 /* if we already allocated the writing code, but failed to get a
663 * buffer, free the algorithm */
664 if (stm32x_info
->write_algorithm
)
665 target_free_working_area(target
, stm32x_info
->write_algorithm
);
667 LOG_WARNING("no large enough working area available, can't do block memory writes");
668 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
672 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* flash base (in), status (out) */
673 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* count (halfword-16bit) */
674 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer start */
675 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* buffer end */
676 init_reg_param(®_params
[4], "r4", 32, PARAM_IN_OUT
); /* target address */
678 buf_set_u32(reg_params
[0].value
, 0, 32, stm32x_info
->register_base
);
679 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
680 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
681 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
682 buf_set_u32(reg_params
[4].value
, 0, 32, address
);
684 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
685 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
687 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
690 source
->address
, source
->size
,
691 stm32x_info
->write_algorithm
->address
, 0,
694 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
695 LOG_ERROR("flash write failed at address 0x%"PRIx32
,
696 buf_get_u32(reg_params
[4].value
, 0, 32));
698 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_PGERR
) {
699 LOG_ERROR("flash memory not erased before writing");
700 /* Clear but report errors */
701 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_PGERR
);
704 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_WRPRTERR
) {
705 LOG_ERROR("flash memory write protected");
706 /* Clear but report errors */
707 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_WRPRTERR
);
711 target_free_working_area(target
, source
);
712 target_free_working_area(target
, stm32x_info
->write_algorithm
);
714 destroy_reg_param(®_params
[0]);
715 destroy_reg_param(®_params
[1]);
716 destroy_reg_param(®_params
[2]);
717 destroy_reg_param(®_params
[3]);
718 destroy_reg_param(®_params
[4]);
723 static int stm32x_write(struct flash_bank
*bank
, uint8_t *buffer
,
724 uint32_t offset
, uint32_t count
)
726 struct target
*target
= bank
->target
;
727 uint8_t *new_buffer
= NULL
;
729 if (bank
->target
->state
!= TARGET_HALTED
) {
730 LOG_ERROR("Target not halted");
731 return ERROR_TARGET_NOT_HALTED
;
735 LOG_ERROR("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
736 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
739 /* If there's an odd number of bytes, the data has to be padded. Duplicate
740 * the buffer and use the normal code path with a single block write since
741 * it's probably cheaper than to special case the last odd write using
742 * discrete accesses. */
744 new_buffer
= malloc(count
+ 1);
745 if (new_buffer
== NULL
) {
746 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
749 LOG_INFO("odd number of bytes to write, padding with 0xff");
750 buffer
= memcpy(new_buffer
, buffer
, count
);
751 buffer
[count
++] = 0xff;
754 uint32_t words_remaining
= count
/ 2;
757 /* unlock flash registers */
758 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
759 if (retval
!= ERROR_OK
)
761 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
762 if (retval
!= ERROR_OK
)
765 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
766 if (retval
!= ERROR_OK
)
769 /* try using a block write */
770 retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
);
772 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
773 /* if block write failed (no sufficient working area),
774 * we use normal (slow) single halfword accesses */
775 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
777 while (words_remaining
> 0) {
779 memcpy(&value
, buffer
, sizeof(uint16_t));
781 retval
= target_write_u16(target
, bank
->base
+ offset
, value
);
782 if (retval
!= ERROR_OK
)
783 goto reset_pg_and_lock
;
785 retval
= stm32x_wait_status_busy(bank
, 5);
786 if (retval
!= ERROR_OK
)
787 goto reset_pg_and_lock
;
796 retval2
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
797 if (retval
== ERROR_OK
)
807 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
809 /* This check the device CPUID core register to detect
810 * the M0 from the M3 devices. */
812 struct target
*target
= bank
->target
;
813 uint32_t cpuid
, device_id_register
= 0;
815 /* Get the CPUID from the ARM Core
816 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
817 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
818 if (retval
!= ERROR_OK
)
821 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
822 /* 0xC20 is M0 devices */
823 device_id_register
= 0x40015800;
824 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
825 /* 0xC23 is M3 devices */
826 device_id_register
= 0xE0042000;
827 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
828 /* 0xC24 is M4 devices */
829 device_id_register
= 0xE0042000;
831 LOG_ERROR("Cannot identify target as a stm32x");
835 /* read stm32 device id register */
836 retval
= target_read_u32(target
, device_id_register
, device_id
);
837 if (retval
!= ERROR_OK
)
843 static int stm32x_get_flash_size(struct flash_bank
*bank
, uint16_t *flash_size_in_kb
)
845 struct target
*target
= bank
->target
;
846 uint32_t cpuid
, flash_size_reg
;
848 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
849 if (retval
!= ERROR_OK
)
852 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
853 /* 0xC20 is M0 devices */
854 flash_size_reg
= 0x1FFFF7CC;
855 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
856 /* 0xC23 is M3 devices */
857 flash_size_reg
= 0x1FFFF7E0;
858 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
859 /* 0xC24 is M4 devices */
860 flash_size_reg
= 0x1FFFF7CC;
862 LOG_ERROR("Cannot identify target as a stm32x");
866 retval
= target_read_u16(target
, flash_size_reg
, flash_size_in_kb
);
867 if (retval
!= ERROR_OK
)
873 static int stm32x_probe(struct flash_bank
*bank
)
875 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
877 uint16_t flash_size_in_kb
;
878 uint16_t max_flash_size_in_kb
;
881 uint32_t base_address
= 0x08000000;
883 stm32x_info
->probed
= 0;
884 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
886 /* read stm32 device id register */
887 int retval
= stm32x_get_device_id(bank
, &device_id
);
888 if (retval
!= ERROR_OK
)
891 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
893 /* set page size, protection granularity and max flash size depending on family */
894 switch (device_id
& 0xfff) {
895 case 0x410: /* medium density */
897 stm32x_info
->ppage_size
= 4;
898 max_flash_size_in_kb
= 128;
900 case 0x412: /* low density */
902 stm32x_info
->ppage_size
= 4;
903 max_flash_size_in_kb
= 32;
905 case 0x414: /* high density */
907 stm32x_info
->ppage_size
= 2;
908 max_flash_size_in_kb
= 512;
910 case 0x418: /* connectivity line density */
912 stm32x_info
->ppage_size
= 2;
913 max_flash_size_in_kb
= 256;
915 case 0x420: /* value line density */
917 stm32x_info
->ppage_size
= 4;
918 max_flash_size_in_kb
= 128;
920 case 0x422: /* stm32f30x */
922 stm32x_info
->ppage_size
= 2;
923 max_flash_size_in_kb
= 256;
925 case 0x428: /* value line High density */
927 stm32x_info
->ppage_size
= 4;
928 max_flash_size_in_kb
= 128;
930 case 0x430: /* xl line density (dual flash banks) */
932 stm32x_info
->ppage_size
= 2;
933 max_flash_size_in_kb
= 1024;
934 stm32x_info
->has_dual_banks
= true;
936 case 0x432: /* stm32f37x */
938 stm32x_info
->ppage_size
= 2;
939 max_flash_size_in_kb
= 256;
941 case 0x440: /* stm32f0x */
943 stm32x_info
->ppage_size
= 4;
944 max_flash_size_in_kb
= 64;
947 LOG_WARNING("Cannot identify target as a STM32 family.");
951 /* get flash size from target. */
952 retval
= stm32x_get_flash_size(bank
, &flash_size_in_kb
);
954 /* failed reading flash size or flash size invalid (early silicon),
955 * default to max target family */
956 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
957 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
958 max_flash_size_in_kb
);
959 flash_size_in_kb
= max_flash_size_in_kb
;
962 if (stm32x_info
->has_dual_banks
) {
963 /* split reported size into matching bank */
964 if (bank
->base
!= 0x08080000) {
965 /* bank 0 will be fixed 512k */
966 flash_size_in_kb
= 512;
968 flash_size_in_kb
-= 512;
969 /* bank1 also uses a register offset */
970 stm32x_info
->register_base
= FLASH_REG_BASE_B1
;
971 base_address
= 0x08080000;
975 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
977 /* did we assign flash size? */
978 assert(flash_size_in_kb
!= 0xffff);
980 /* calculate numbers of pages */
981 int num_pages
= flash_size_in_kb
* 1024 / page_size
;
983 /* check that calculation result makes sense */
984 assert(num_pages
> 0);
988 bank
->sectors
= NULL
;
991 bank
->base
= base_address
;
992 bank
->size
= (num_pages
* page_size
);
993 bank
->num_sectors
= num_pages
;
994 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
996 for (i
= 0; i
< num_pages
; i
++) {
997 bank
->sectors
[i
].offset
= i
* page_size
;
998 bank
->sectors
[i
].size
= page_size
;
999 bank
->sectors
[i
].is_erased
= -1;
1000 bank
->sectors
[i
].is_protected
= 1;
1003 stm32x_info
->probed
= 1;
1008 static int stm32x_auto_probe(struct flash_bank
*bank
)
1010 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1011 if (stm32x_info
->probed
)
1013 return stm32x_probe(bank
);
1017 COMMAND_HANDLER(stm32x_handle_part_id_command
)
1023 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1028 /* read stm32 device id register */
1029 int retval
= stm32x_get_device_id(bank
, &device_id
);
1030 if (retval
!= ERROR_OK
)
1033 if ((device_id
& 0xfff) == 0x410) {
1034 printed
= snprintf(buf
, buf_size
, "stm32x (Medium Density) - Rev: ");
1036 buf_size
-= printed
;
1038 switch (device_id
>> 16) {
1040 snprintf(buf
, buf_size
, "A");
1044 snprintf(buf
, buf_size
, "B");
1048 snprintf(buf
, buf_size
, "Z");
1052 snprintf(buf
, buf_size
, "Y");
1056 snprintf(buf
, buf_size
, "unknown");
1059 } else if ((device_id
& 0xfff) == 0x412) {
1060 printed
= snprintf(buf
, buf_size
, "stm32x (Low Density) - Rev: ");
1062 buf_size
-= printed
;
1064 switch (device_id
>> 16) {
1066 snprintf(buf
, buf_size
, "A");
1070 snprintf(buf
, buf_size
, "unknown");
1073 } else if ((device_id
& 0xfff) == 0x414) {
1074 printed
= snprintf(buf
, buf_size
, "stm32x (High Density) - Rev: ");
1076 buf_size
-= printed
;
1078 switch (device_id
>> 16) {
1080 snprintf(buf
, buf_size
, "A");
1084 snprintf(buf
, buf_size
, "Z");
1088 snprintf(buf
, buf_size
, "unknown");
1091 } else if ((device_id
& 0xfff) == 0x418) {
1092 printed
= snprintf(buf
, buf_size
, "stm32x (Connectivity) - Rev: ");
1094 buf_size
-= printed
;
1096 switch (device_id
>> 16) {
1098 snprintf(buf
, buf_size
, "A");
1102 snprintf(buf
, buf_size
, "Z");
1106 snprintf(buf
, buf_size
, "unknown");
1109 } else if ((device_id
& 0xfff) == 0x420) {
1110 printed
= snprintf(buf
, buf_size
, "stm32x (Value) - Rev: ");
1112 buf_size
-= printed
;
1114 switch (device_id
>> 16) {
1116 snprintf(buf
, buf_size
, "A");
1120 snprintf(buf
, buf_size
, "Z");
1124 snprintf(buf
, buf_size
, "unknown");
1127 } else if ((device_id
& 0xfff) == 0x422) {
1128 printed
= snprintf(buf
, buf_size
, "stm32f30x - Rev: ");
1130 buf_size
-= printed
;
1132 switch (device_id
>> 16) {
1134 snprintf(buf
, buf_size
, "1.0");
1138 snprintf(buf
, buf_size
, "unknown");
1141 } else if ((device_id
& 0xfff) == 0x428) {
1142 printed
= snprintf(buf
, buf_size
, "stm32x (Value HD) - Rev: ");
1144 buf_size
-= printed
;
1146 switch (device_id
>> 16) {
1148 snprintf(buf
, buf_size
, "A");
1152 snprintf(buf
, buf_size
, "Z");
1156 snprintf(buf
, buf_size
, "unknown");
1159 } else if ((device_id
& 0xfff) == 0x430) {
1160 printed
= snprintf(buf
, buf_size
, "stm32x (XL) - Rev: ");
1162 buf_size
-= printed
;
1164 switch (device_id
>> 16) {
1166 snprintf(buf
, buf_size
, "A");
1170 snprintf(buf
, buf_size
, "unknown");
1173 } else if ((device_id
& 0xfff) == 0x432) {
1174 printed
= snprintf(buf
, buf_size
, "stm32f37x - Rev: ");
1176 buf_size
-= printed
;
1178 switch (device_id
>> 16) {
1180 snprintf(buf
, buf_size
, "1.0");
1184 snprintf(buf
, buf_size
, "unknown");
1187 } else if ((device_id
& 0xfff) == 0x440) {
1188 printed
= snprintf(buf
, buf_size
, "stm32f0x - Rev: ");
1190 buf_size
-= printed
;
1192 switch (device_id
>> 16) {
1194 snprintf(buf
, buf_size
, "1.0");
1198 snprintf(buf
, buf_size
, "2.0");
1202 snprintf(buf
, buf_size
, "unknown");
1206 snprintf(buf
, buf_size
, "Cannot identify target as a stm32x\n");
1213 COMMAND_HANDLER(stm32x_handle_lock_command
)
1215 struct target
*target
= NULL
;
1216 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1219 return ERROR_COMMAND_SYNTAX_ERROR
;
1221 struct flash_bank
*bank
;
1222 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1223 if (ERROR_OK
!= retval
)
1226 stm32x_info
= bank
->driver_priv
;
1228 target
= bank
->target
;
1230 if (target
->state
!= TARGET_HALTED
) {
1231 LOG_ERROR("Target not halted");
1232 return ERROR_TARGET_NOT_HALTED
;
1235 retval
= stm32x_check_operation_supported(bank
);
1236 if (ERROR_OK
!= retval
)
1239 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1240 command_print(CMD_CTX
, "stm32x failed to erase options");
1244 /* set readout protection */
1245 stm32x_info
->option_bytes
.RDP
= 0;
1247 if (stm32x_write_options(bank
) != ERROR_OK
) {
1248 command_print(CMD_CTX
, "stm32x failed to lock device");
1252 command_print(CMD_CTX
, "stm32x locked");
1257 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1259 struct target
*target
= NULL
;
1262 return ERROR_COMMAND_SYNTAX_ERROR
;
1264 struct flash_bank
*bank
;
1265 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1266 if (ERROR_OK
!= retval
)
1269 target
= bank
->target
;
1271 if (target
->state
!= TARGET_HALTED
) {
1272 LOG_ERROR("Target not halted");
1273 return ERROR_TARGET_NOT_HALTED
;
1276 retval
= stm32x_check_operation_supported(bank
);
1277 if (ERROR_OK
!= retval
)
1280 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1281 command_print(CMD_CTX
, "stm32x failed to unlock device");
1285 if (stm32x_write_options(bank
) != ERROR_OK
) {
1286 command_print(CMD_CTX
, "stm32x failed to lock device");
1290 command_print(CMD_CTX
, "stm32x unlocked.\n"
1291 "INFO: a reset or power cycle is required "
1292 "for the new settings to take effect.");
1297 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1299 uint32_t optionbyte
;
1300 struct target
*target
= NULL
;
1301 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1304 return ERROR_COMMAND_SYNTAX_ERROR
;
1306 struct flash_bank
*bank
;
1307 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1308 if (ERROR_OK
!= retval
)
1311 stm32x_info
= bank
->driver_priv
;
1313 target
= bank
->target
;
1315 if (target
->state
!= TARGET_HALTED
) {
1316 LOG_ERROR("Target not halted");
1317 return ERROR_TARGET_NOT_HALTED
;
1320 retval
= stm32x_check_operation_supported(bank
);
1321 if (ERROR_OK
!= retval
)
1324 retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optionbyte
);
1325 if (retval
!= ERROR_OK
)
1327 command_print(CMD_CTX
, "Option Byte: 0x%" PRIx32
"", optionbyte
);
1329 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_ERROR
, 1))
1330 command_print(CMD_CTX
, "Option Byte Complement Error");
1332 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_READOUT
, 1))
1333 command_print(CMD_CTX
, "Readout Protection On");
1335 command_print(CMD_CTX
, "Readout Protection Off");
1337 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDWDGSW
, 1))
1338 command_print(CMD_CTX
, "Software Watchdog");
1340 command_print(CMD_CTX
, "Hardware Watchdog");
1342 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDRSTSTOP
, 1))
1343 command_print(CMD_CTX
, "Stop: No reset generated");
1345 command_print(CMD_CTX
, "Stop: Reset generated");
1347 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDRSTSTDBY
, 1))
1348 command_print(CMD_CTX
, "Standby: No reset generated");
1350 command_print(CMD_CTX
, "Standby: Reset generated");
1352 if (stm32x_info
->has_dual_banks
) {
1353 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_BFB2
, 1))
1354 command_print(CMD_CTX
, "Boot: Bank 0");
1356 command_print(CMD_CTX
, "Boot: Bank 1");
1362 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1364 struct target
*target
= NULL
;
1365 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1366 uint16_t optionbyte
= 0xF8;
1369 return ERROR_COMMAND_SYNTAX_ERROR
;
1371 struct flash_bank
*bank
;
1372 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1373 if (ERROR_OK
!= retval
)
1376 stm32x_info
= bank
->driver_priv
;
1378 target
= bank
->target
;
1380 if (target
->state
!= TARGET_HALTED
) {
1381 LOG_ERROR("Target not halted");
1382 return ERROR_TARGET_NOT_HALTED
;
1385 retval
= stm32x_check_operation_supported(bank
);
1386 if (ERROR_OK
!= retval
)
1389 /* REVISIT: ignores some options which we will display...
1390 * and doesn't insist on the specified syntax.
1394 if (strcmp(CMD_ARGV
[1], "SWWDG") == 0)
1395 optionbyte
|= (1 << 0);
1396 else /* REVISIT must be "HWWDG" then ... */
1397 optionbyte
&= ~(1 << 0);
1400 if (strcmp(CMD_ARGV
[2], "NORSTSTOP") == 0)
1401 optionbyte
|= (1 << 1);
1402 else /* REVISIT must be "RSTSTNDBY" then ... */
1403 optionbyte
&= ~(1 << 1);
1405 /* OPT_RDRSTSTDBY */
1406 if (strcmp(CMD_ARGV
[3], "NORSTSTNDBY") == 0)
1407 optionbyte
|= (1 << 2);
1408 else /* REVISIT must be "RSTSTOP" then ... */
1409 optionbyte
&= ~(1 << 2);
1411 if (CMD_ARGC
> 4 && stm32x_info
->has_dual_banks
) {
1413 if (strcmp(CMD_ARGV
[4], "BOOT0") == 0)
1414 optionbyte
|= (1 << 3);
1416 optionbyte
&= ~(1 << 3);
1419 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1420 command_print(CMD_CTX
, "stm32x failed to erase options");
1424 stm32x_info
->option_bytes
.user_options
= optionbyte
;
1426 if (stm32x_write_options(bank
) != ERROR_OK
) {
1427 command_print(CMD_CTX
, "stm32x failed to write options");
1431 command_print(CMD_CTX
, "stm32x write options complete.\n"
1432 "INFO: a reset or power cycle is required "
1433 "for the new settings to take effect.");
1438 static int stm32x_mass_erase(struct flash_bank
*bank
)
1440 struct target
*target
= bank
->target
;
1442 if (target
->state
!= TARGET_HALTED
) {
1443 LOG_ERROR("Target not halted");
1444 return ERROR_TARGET_NOT_HALTED
;
1447 /* unlock option flash registers */
1448 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1449 if (retval
!= ERROR_OK
)
1451 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1452 if (retval
!= ERROR_OK
)
1455 /* mass erase flash memory */
1456 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_MER
);
1457 if (retval
!= ERROR_OK
)
1459 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1460 FLASH_MER
| FLASH_STRT
);
1461 if (retval
!= ERROR_OK
)
1464 retval
= stm32x_wait_status_busy(bank
, 100);
1465 if (retval
!= ERROR_OK
)
1468 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1469 if (retval
!= ERROR_OK
)
1475 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1480 return ERROR_COMMAND_SYNTAX_ERROR
;
1482 struct flash_bank
*bank
;
1483 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1484 if (ERROR_OK
!= retval
)
1487 retval
= stm32x_mass_erase(bank
);
1488 if (retval
== ERROR_OK
) {
1489 /* set all sectors as erased */
1490 for (i
= 0; i
< bank
->num_sectors
; i
++)
1491 bank
->sectors
[i
].is_erased
= 1;
1493 command_print(CMD_CTX
, "stm32x mass erase complete");
1495 command_print(CMD_CTX
, "stm32x mass erase failed");
1500 static const struct command_registration stm32x_exec_command_handlers
[] = {
1503 .handler
= stm32x_handle_lock_command
,
1504 .mode
= COMMAND_EXEC
,
1506 .help
= "Lock entire flash device.",
1510 .handler
= stm32x_handle_unlock_command
,
1511 .mode
= COMMAND_EXEC
,
1513 .help
= "Unlock entire protected flash device.",
1516 .name
= "mass_erase",
1517 .handler
= stm32x_handle_mass_erase_command
,
1518 .mode
= COMMAND_EXEC
,
1520 .help
= "Erase entire flash device.",
1523 .name
= "options_read",
1524 .handler
= stm32x_handle_options_read_command
,
1525 .mode
= COMMAND_EXEC
,
1527 .help
= "Read and display device option byte.",
1530 .name
= "options_write",
1531 .handler
= stm32x_handle_options_write_command
,
1532 .mode
= COMMAND_EXEC
,
1533 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1534 "('RSTSTNDBY'|'NORSTSTNDBY') "
1535 "('RSTSTOP'|'NORSTSTOP')",
1536 .help
= "Replace bits in device option byte.",
1538 COMMAND_REGISTRATION_DONE
1541 static const struct command_registration stm32x_command_handlers
[] = {
1544 .mode
= COMMAND_ANY
,
1545 .help
= "stm32f1x flash command group",
1547 .chain
= stm32x_exec_command_handlers
,
1549 COMMAND_REGISTRATION_DONE
1552 struct flash_driver stm32f1x_flash
= {
1554 .commands
= stm32x_command_handlers
,
1555 .flash_bank_command
= stm32x_flash_bank_command
,
1556 .erase
= stm32x_erase
,
1557 .protect
= stm32x_protect
,
1558 .write
= stm32x_write
,
1559 .read
= default_flash_read
,
1560 .probe
= stm32x_probe
,
1561 .auto_probe
= stm32x_auto_probe
,
1562 .erase_check
= default_flash_blank_check
,
1563 .protect_check
= stm32x_protect_check
,
1564 .info
= get_stm32x_info
,
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