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[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 bool probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 return ERROR_OK;
155 }
156
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
158 {
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
161 }
162
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
164 {
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
167 }
168
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
170 {
171 struct target *target = bank->target;
172 uint32_t status;
173 int retval = ERROR_OK;
174
175 /* wait for busy to clear */
176 for (;;) {
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
179 return retval;
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
182 break;
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
185 return ERROR_FAIL;
186 }
187 alive_sleep(1);
188 }
189
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
192 retval = ERROR_FAIL;
193 }
194
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
197 retval = ERROR_FAIL;
198 }
199
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
203 * retval
204 */
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
207 }
208 return retval;
209 }
210
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
212 {
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
214
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int stm32x_read_options(struct flash_bank *bank)
226 {
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
230 int retval;
231
232 /* read user and read protection option bytes, user data option bytes */
233 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
238 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
239 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
240
241 /* read write protection option bytes */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
243 if (retval != ERROR_OK)
244 return retval;
245
246 return ERROR_OK;
247 }
248
249 static int stm32x_erase_options(struct flash_bank *bank)
250 {
251 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
252 struct target *target = bank->target;
253
254 /* read current options */
255 stm32x_read_options(bank);
256
257 /* unlock flash registers */
258 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
259 if (retval != ERROR_OK)
260 return retval;
261
262 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
263 if (retval != ERROR_OK)
264 return retval;
265
266 /* unlock option flash registers */
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
268 if (retval != ERROR_OK)
269 return retval;
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* erase option bytes */
275 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
276 if (retval != ERROR_OK)
277 return retval;
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 return retval;
281
282 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
283 if (retval != ERROR_OK)
284 return retval;
285
286 /* clear read protection option byte
287 * this will also force a device unlock if set */
288 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
289
290 return ERROR_OK;
291 }
292
293 static int stm32x_write_options(struct flash_bank *bank)
294 {
295 struct stm32x_flash_bank *stm32x_info = NULL;
296 struct target *target = bank->target;
297
298 stm32x_info = bank->driver_priv;
299
300 /* unlock flash registers */
301 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
302 if (retval != ERROR_OK)
303 return retval;
304 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
305 if (retval != ERROR_OK)
306 return retval;
307
308 /* unlock option flash registers */
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
310 if (retval != ERROR_OK)
311 return retval;
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
313 if (retval != ERROR_OK)
314 return retval;
315
316 /* program option bytes */
317 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
318 if (retval != ERROR_OK)
319 return retval;
320
321 uint8_t opt_bytes[16];
322
323 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
324 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
325 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
326 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
327 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
328 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
331
332 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
333 if (retval != ERROR_OK) {
334 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
335 LOG_ERROR("working area required to erase options bytes");
336 return retval;
337 }
338
339 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
340 if (retval != ERROR_OK)
341 return retval;
342
343 return ERROR_OK;
344 }
345
346 static int stm32x_protect_check(struct flash_bank *bank)
347 {
348 struct target *target = bank->target;
349 uint32_t protection;
350
351 int retval = stm32x_check_operation_supported(bank);
352 if (ERROR_OK != retval)
353 return retval;
354
355 /* medium density - each bit refers to a 4 sector protection block
356 * high density - each bit refers to a 2 sector protection block
357 * bit 31 refers to all remaining sectors in a bank */
358 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
359 if (retval != ERROR_OK)
360 return retval;
361
362 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
363 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
364
365 return ERROR_OK;
366 }
367
368 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
369 unsigned int last)
370 {
371 struct target *target = bank->target;
372
373 if (bank->target->state != TARGET_HALTED) {
374 LOG_ERROR("Target not halted");
375 return ERROR_TARGET_NOT_HALTED;
376 }
377
378 if ((first == 0) && (last == (bank->num_sectors - 1)))
379 return stm32x_mass_erase(bank);
380
381 /* unlock flash registers */
382 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
383 if (retval != ERROR_OK)
384 return retval;
385 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
386 if (retval != ERROR_OK)
387 return retval;
388
389 for (unsigned int i = first; i <= last; i++) {
390 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
391 if (retval != ERROR_OK)
392 return retval;
393 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
394 bank->base + bank->sectors[i].offset);
395 if (retval != ERROR_OK)
396 return retval;
397 retval = target_write_u32(target,
398 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
399 if (retval != ERROR_OK)
400 return retval;
401
402 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
403 if (retval != ERROR_OK)
404 return retval;
405
406 bank->sectors[i].is_erased = 1;
407 }
408
409 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
410 if (retval != ERROR_OK)
411 return retval;
412
413 return ERROR_OK;
414 }
415
416 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
417 unsigned int last)
418 {
419 struct target *target = bank->target;
420 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
421
422 if (target->state != TARGET_HALTED) {
423 LOG_ERROR("Target not halted");
424 return ERROR_TARGET_NOT_HALTED;
425 }
426
427 int retval = stm32x_check_operation_supported(bank);
428 if (retval != ERROR_OK)
429 return retval;
430
431 retval = stm32x_erase_options(bank);
432 if (retval != ERROR_OK) {
433 LOG_ERROR("stm32x failed to erase options");
434 return retval;
435 }
436
437 for (unsigned int i = first; i <= last; i++) {
438 if (set)
439 stm32x_info->option_bytes.protection &= ~(1 << i);
440 else
441 stm32x_info->option_bytes.protection |= (1 << i);
442 }
443
444 return stm32x_write_options(bank);
445 }
446
447 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
448 uint32_t address, uint32_t count)
449 {
450 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
451 struct target *target = bank->target;
452 uint32_t buffer_size = 16384;
453 struct working_area *write_algorithm;
454 struct working_area *source;
455 struct reg_param reg_params[5];
456 struct armv7m_algorithm armv7m_info;
457 int retval = ERROR_OK;
458
459 static const uint8_t stm32x_flash_write_code[] = {
460 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
461 };
462
463 /* flash write code */
464 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
465 &write_algorithm) != ERROR_OK) {
466 LOG_WARNING("no working area available, can't do block memory writes");
467 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
468 }
469
470 retval = target_write_buffer(target, write_algorithm->address,
471 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
472 if (retval != ERROR_OK) {
473 target_free_working_area(target, write_algorithm);
474 return retval;
475 }
476
477 /* memory buffer */
478 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
479 buffer_size /= 2;
480 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
481 if (buffer_size <= 256) {
482 /* we already allocated the writing code, but failed to get a
483 * buffer, free the algorithm */
484 target_free_working_area(target, write_algorithm);
485
486 LOG_WARNING("no large enough working area available, can't do block memory writes");
487 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
488 }
489 }
490
491 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
492 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
493 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
494 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
495 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
496
497 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
498 buf_set_u32(reg_params[1].value, 0, 32, count);
499 buf_set_u32(reg_params[2].value, 0, 32, source->address);
500 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
501 buf_set_u32(reg_params[4].value, 0, 32, address);
502
503 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
504 armv7m_info.core_mode = ARM_MODE_THREAD;
505
506 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
507 0, NULL,
508 5, reg_params,
509 source->address, source->size,
510 write_algorithm->address, 0,
511 &armv7m_info);
512
513 if (retval == ERROR_FLASH_OPERATION_FAILED) {
514 LOG_ERROR("flash write failed at address 0x%"PRIx32,
515 buf_get_u32(reg_params[4].value, 0, 32));
516
517 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
518 LOG_ERROR("flash memory not erased before writing");
519 /* Clear but report errors */
520 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
521 }
522
523 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
524 LOG_ERROR("flash memory write protected");
525 /* Clear but report errors */
526 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
527 }
528 }
529
530 target_free_working_area(target, source);
531 target_free_working_area(target, write_algorithm);
532
533 destroy_reg_param(&reg_params[0]);
534 destroy_reg_param(&reg_params[1]);
535 destroy_reg_param(&reg_params[2]);
536 destroy_reg_param(&reg_params[3]);
537 destroy_reg_param(&reg_params[4]);
538
539 return retval;
540 }
541
542 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
543 uint32_t offset, uint32_t count)
544 {
545 struct target *target = bank->target;
546 uint8_t *new_buffer = NULL;
547
548 if (bank->target->state != TARGET_HALTED) {
549 LOG_ERROR("Target not halted");
550 return ERROR_TARGET_NOT_HALTED;
551 }
552
553 if (offset & 0x1) {
554 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
555 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
556 }
557
558 /* If there's an odd number of bytes, the data has to be padded. Duplicate
559 * the buffer and use the normal code path with a single block write since
560 * it's probably cheaper than to special case the last odd write using
561 * discrete accesses. */
562 if (count & 1) {
563 new_buffer = malloc(count + 1);
564 if (new_buffer == NULL) {
565 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
566 return ERROR_FAIL;
567 }
568 LOG_INFO("odd number of bytes to write, padding with 0xff");
569 buffer = memcpy(new_buffer, buffer, count);
570 new_buffer[count++] = 0xff;
571 }
572
573 uint32_t words_remaining = count / 2;
574 int retval, retval2;
575
576 /* unlock flash registers */
577 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
578 if (retval != ERROR_OK)
579 goto cleanup;
580 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
581 if (retval != ERROR_OK)
582 goto cleanup;
583
584 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
585 if (retval != ERROR_OK)
586 goto cleanup;
587
588 /* try using a block write */
589 retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
590
591 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
592 /* if block write failed (no sufficient working area),
593 * we use normal (slow) single halfword accesses */
594 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
595
596 while (words_remaining > 0) {
597 uint16_t value;
598 memcpy(&value, buffer, sizeof(uint16_t));
599
600 retval = target_write_u16(target, bank->base + offset, value);
601 if (retval != ERROR_OK)
602 goto reset_pg_and_lock;
603
604 retval = stm32x_wait_status_busy(bank, 5);
605 if (retval != ERROR_OK)
606 goto reset_pg_and_lock;
607
608 words_remaining--;
609 buffer += 2;
610 offset += 2;
611 }
612 }
613
614 reset_pg_and_lock:
615 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
616 if (retval == ERROR_OK)
617 retval = retval2;
618
619 cleanup:
620 if (new_buffer)
621 free(new_buffer);
622
623 return retval;
624 }
625
626 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
627 {
628 /* This check the device CPUID core register to detect
629 * the M0 from the M3 devices. */
630
631 struct target *target = bank->target;
632 uint32_t cpuid, device_id_register = 0;
633
634 /* Get the CPUID from the ARM Core
635 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
636 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
637 if (retval != ERROR_OK)
638 return retval;
639
640 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
641 /* 0xC20 is M0 devices */
642 device_id_register = 0x40015800;
643 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
644 /* 0xC23 is M3 devices */
645 device_id_register = 0xE0042000;
646 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
647 /* 0xC24 is M4 devices */
648 device_id_register = 0xE0042000;
649 } else {
650 LOG_ERROR("Cannot identify target as a stm32x");
651 return ERROR_FAIL;
652 }
653
654 /* read stm32 device id register */
655 retval = target_read_u32(target, device_id_register, device_id);
656 if (retval != ERROR_OK)
657 return retval;
658
659 return retval;
660 }
661
662 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
663 {
664 struct target *target = bank->target;
665 uint32_t cpuid, flash_size_reg;
666
667 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
668 if (retval != ERROR_OK)
669 return retval;
670
671 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
672 /* 0xC20 is M0 devices */
673 flash_size_reg = 0x1FFFF7CC;
674 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
675 /* 0xC23 is M3 devices */
676 flash_size_reg = 0x1FFFF7E0;
677 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
678 /* 0xC24 is M4 devices */
679 flash_size_reg = 0x1FFFF7CC;
680 } else {
681 LOG_ERROR("Cannot identify target as a stm32x");
682 return ERROR_FAIL;
683 }
684
685 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
686 if (retval != ERROR_OK)
687 return retval;
688
689 return retval;
690 }
691
692 static int stm32x_probe(struct flash_bank *bank)
693 {
694 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
695 uint16_t flash_size_in_kb;
696 uint16_t max_flash_size_in_kb;
697 uint32_t device_id;
698 int page_size;
699 uint32_t base_address = 0x08000000;
700
701 stm32x_info->probed = false;
702 stm32x_info->register_base = FLASH_REG_BASE_B0;
703 stm32x_info->user_data_offset = 10;
704 stm32x_info->option_offset = 0;
705
706 /* default factory read protection level 0 */
707 stm32x_info->default_rdp = 0xA5;
708
709 /* read stm32 device id register */
710 int retval = stm32x_get_device_id(bank, &device_id);
711 if (retval != ERROR_OK)
712 return retval;
713
714 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
715
716 /* set page size, protection granularity and max flash size depending on family */
717 switch (device_id & 0xfff) {
718 case 0x440: /* stm32f05x */
719 page_size = 1024;
720 stm32x_info->ppage_size = 4;
721 max_flash_size_in_kb = 64;
722 stm32x_info->user_data_offset = 16;
723 stm32x_info->option_offset = 6;
724 stm32x_info->default_rdp = 0xAA;
725 stm32x_info->can_load_options = true;
726 break;
727 case 0x444: /* stm32f03x */
728 case 0x445: /* stm32f04x */
729 page_size = 1024;
730 stm32x_info->ppage_size = 4;
731 max_flash_size_in_kb = 32;
732 stm32x_info->user_data_offset = 16;
733 stm32x_info->option_offset = 6;
734 stm32x_info->default_rdp = 0xAA;
735 stm32x_info->can_load_options = true;
736 break;
737 case 0x448: /* stm32f07x */
738 page_size = 2048;
739 stm32x_info->ppage_size = 4;
740 max_flash_size_in_kb = 128;
741 stm32x_info->user_data_offset = 16;
742 stm32x_info->option_offset = 6;
743 stm32x_info->default_rdp = 0xAA;
744 stm32x_info->can_load_options = true;
745 break;
746 case 0x442: /* stm32f09x */
747 page_size = 2048;
748 stm32x_info->ppage_size = 4;
749 max_flash_size_in_kb = 256;
750 stm32x_info->user_data_offset = 16;
751 stm32x_info->option_offset = 6;
752 stm32x_info->default_rdp = 0xAA;
753 stm32x_info->can_load_options = true;
754 break;
755 case 0x410: /* stm32f1x medium-density */
756 page_size = 1024;
757 stm32x_info->ppage_size = 4;
758 max_flash_size_in_kb = 128;
759 break;
760 case 0x412: /* stm32f1x low-density */
761 page_size = 1024;
762 stm32x_info->ppage_size = 4;
763 max_flash_size_in_kb = 32;
764 break;
765 case 0x414: /* stm32f1x high-density */
766 page_size = 2048;
767 stm32x_info->ppage_size = 2;
768 max_flash_size_in_kb = 512;
769 break;
770 case 0x418: /* stm32f1x connectivity */
771 page_size = 2048;
772 stm32x_info->ppage_size = 2;
773 max_flash_size_in_kb = 256;
774 break;
775 case 0x430: /* stm32f1 XL-density (dual flash banks) */
776 page_size = 2048;
777 stm32x_info->ppage_size = 2;
778 max_flash_size_in_kb = 1024;
779 stm32x_info->has_dual_banks = true;
780 break;
781 case 0x420: /* stm32f100xx low- and medium-density value line */
782 page_size = 1024;
783 stm32x_info->ppage_size = 4;
784 max_flash_size_in_kb = 128;
785 break;
786 case 0x428: /* stm32f100xx high-density value line */
787 page_size = 2048;
788 stm32x_info->ppage_size = 4;
789 max_flash_size_in_kb = 512;
790 break;
791 case 0x422: /* stm32f302/3xb/c */
792 page_size = 2048;
793 stm32x_info->ppage_size = 2;
794 max_flash_size_in_kb = 256;
795 stm32x_info->user_data_offset = 16;
796 stm32x_info->option_offset = 6;
797 stm32x_info->default_rdp = 0xAA;
798 stm32x_info->can_load_options = true;
799 break;
800 case 0x446: /* stm32f303xD/E */
801 page_size = 2048;
802 stm32x_info->ppage_size = 2;
803 max_flash_size_in_kb = 512;
804 stm32x_info->user_data_offset = 16;
805 stm32x_info->option_offset = 6;
806 stm32x_info->default_rdp = 0xAA;
807 stm32x_info->can_load_options = true;
808 break;
809 case 0x432: /* stm32f37x */
810 page_size = 2048;
811 stm32x_info->ppage_size = 2;
812 max_flash_size_in_kb = 256;
813 stm32x_info->user_data_offset = 16;
814 stm32x_info->option_offset = 6;
815 stm32x_info->default_rdp = 0xAA;
816 stm32x_info->can_load_options = true;
817 break;
818 case 0x438: /* stm32f33x */
819 case 0x439: /* stm32f302x6/8 */
820 page_size = 2048;
821 stm32x_info->ppage_size = 2;
822 max_flash_size_in_kb = 64;
823 stm32x_info->user_data_offset = 16;
824 stm32x_info->option_offset = 6;
825 stm32x_info->default_rdp = 0xAA;
826 stm32x_info->can_load_options = true;
827 break;
828 default:
829 LOG_WARNING("Cannot identify target as a STM32 family.");
830 return ERROR_FAIL;
831 }
832
833 /* get flash size from target. */
834 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
835
836 /* failed reading flash size or flash size invalid (early silicon),
837 * default to max target family */
838 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
839 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
840 max_flash_size_in_kb);
841 flash_size_in_kb = max_flash_size_in_kb;
842 }
843
844 if (stm32x_info->has_dual_banks) {
845 /* split reported size into matching bank */
846 if (bank->base != 0x08080000) {
847 /* bank 0 will be fixed 512k */
848 flash_size_in_kb = 512;
849 } else {
850 flash_size_in_kb -= 512;
851 /* bank1 also uses a register offset */
852 stm32x_info->register_base = FLASH_REG_BASE_B1;
853 base_address = 0x08080000;
854 }
855 }
856
857 /* if the user sets the size manually then ignore the probed value
858 * this allows us to work around devices that have a invalid flash size register value */
859 if (stm32x_info->user_bank_size) {
860 LOG_INFO("ignoring flash probed value, using configured bank size");
861 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
862 }
863
864 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
865
866 /* did we assign flash size? */
867 assert(flash_size_in_kb != 0xffff);
868
869 /* calculate numbers of pages */
870 int num_pages = flash_size_in_kb * 1024 / page_size;
871
872 /* check that calculation result makes sense */
873 assert(num_pages > 0);
874
875 if (bank->sectors) {
876 free(bank->sectors);
877 bank->sectors = NULL;
878 }
879
880 if (bank->prot_blocks) {
881 free(bank->prot_blocks);
882 bank->prot_blocks = NULL;
883 }
884
885 bank->base = base_address;
886 bank->size = (num_pages * page_size);
887
888 bank->num_sectors = num_pages;
889 bank->sectors = alloc_block_array(0, page_size, num_pages);
890 if (!bank->sectors)
891 return ERROR_FAIL;
892
893 /* calculate number of write protection blocks */
894 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
895 if (num_prot_blocks > 32)
896 num_prot_blocks = 32;
897
898 bank->num_prot_blocks = num_prot_blocks;
899 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
900 if (!bank->prot_blocks)
901 return ERROR_FAIL;
902
903 if (num_prot_blocks == 32)
904 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
905
906 stm32x_info->probed = true;
907
908 return ERROR_OK;
909 }
910
911 static int stm32x_auto_probe(struct flash_bank *bank)
912 {
913 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
914 if (stm32x_info->probed)
915 return ERROR_OK;
916 return stm32x_probe(bank);
917 }
918
919 #if 0
920 COMMAND_HANDLER(stm32x_handle_part_id_command)
921 {
922 return ERROR_OK;
923 }
924 #endif
925
926 static const char *get_stm32f0_revision(uint16_t rev_id)
927 {
928 const char *rev_str = NULL;
929
930 switch (rev_id) {
931 case 0x1000:
932 rev_str = "1.0";
933 break;
934 case 0x2000:
935 rev_str = "2.0";
936 break;
937 }
938 return rev_str;
939 }
940
941 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
942 {
943 uint32_t dbgmcu_idcode;
944
945 /* read stm32 device id register */
946 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
947 if (retval != ERROR_OK)
948 return retval;
949
950 uint16_t device_id = dbgmcu_idcode & 0xfff;
951 uint16_t rev_id = dbgmcu_idcode >> 16;
952 const char *device_str;
953 const char *rev_str = NULL;
954
955 switch (device_id) {
956 case 0x410:
957 device_str = "STM32F10x (Medium Density)";
958
959 switch (rev_id) {
960 case 0x0000:
961 rev_str = "A";
962 break;
963
964 case 0x2000:
965 rev_str = "B";
966 break;
967
968 case 0x2001:
969 rev_str = "Z";
970 break;
971
972 case 0x2003:
973 rev_str = "Y";
974 break;
975 }
976 break;
977
978 case 0x412:
979 device_str = "STM32F10x (Low Density)";
980
981 switch (rev_id) {
982 case 0x1000:
983 rev_str = "A";
984 break;
985 }
986 break;
987
988 case 0x414:
989 device_str = "STM32F10x (High Density)";
990
991 switch (rev_id) {
992 case 0x1000:
993 rev_str = "A";
994 break;
995
996 case 0x1001:
997 rev_str = "Z";
998 break;
999
1000 case 0x1003:
1001 rev_str = "Y";
1002 break;
1003 }
1004 break;
1005
1006 case 0x418:
1007 device_str = "STM32F10x (Connectivity)";
1008
1009 switch (rev_id) {
1010 case 0x1000:
1011 rev_str = "A";
1012 break;
1013
1014 case 0x1001:
1015 rev_str = "Z";
1016 break;
1017 }
1018 break;
1019
1020 case 0x420:
1021 device_str = "STM32F100 (Low/Medium Density)";
1022
1023 switch (rev_id) {
1024 case 0x1000:
1025 rev_str = "A";
1026 break;
1027
1028 case 0x1001:
1029 rev_str = "Z";
1030 break;
1031 }
1032 break;
1033
1034 case 0x422:
1035 device_str = "STM32F302xB/C";
1036
1037 switch (rev_id) {
1038 case 0x1000:
1039 rev_str = "A";
1040 break;
1041
1042 case 0x1001:
1043 rev_str = "Z";
1044 break;
1045
1046 case 0x1003:
1047 rev_str = "Y";
1048 break;
1049
1050 case 0x2000:
1051 rev_str = "B";
1052 break;
1053 }
1054 break;
1055
1056 case 0x428:
1057 device_str = "STM32F100 (High Density)";
1058
1059 switch (rev_id) {
1060 case 0x1000:
1061 rev_str = "A";
1062 break;
1063
1064 case 0x1001:
1065 rev_str = "Z";
1066 break;
1067 }
1068 break;
1069
1070 case 0x430:
1071 device_str = "STM32F10x (XL Density)";
1072
1073 switch (rev_id) {
1074 case 0x1000:
1075 rev_str = "A";
1076 break;
1077 }
1078 break;
1079
1080 case 0x432:
1081 device_str = "STM32F37x";
1082
1083 switch (rev_id) {
1084 case 0x1000:
1085 rev_str = "A";
1086 break;
1087
1088 case 0x2000:
1089 rev_str = "B";
1090 break;
1091 }
1092 break;
1093
1094 case 0x438:
1095 device_str = "STM32F33x";
1096
1097 switch (rev_id) {
1098 case 0x1000:
1099 rev_str = "A";
1100 break;
1101 }
1102 break;
1103
1104 case 0x439:
1105 device_str = "STM32F302x6/8";
1106
1107 switch (rev_id) {
1108 case 0x1000:
1109 rev_str = "A";
1110 break;
1111
1112 case 0x1001:
1113 rev_str = "Z";
1114 break;
1115 }
1116 break;
1117
1118 case 0x444:
1119 device_str = "STM32F03x";
1120 rev_str = get_stm32f0_revision(rev_id);
1121 break;
1122
1123 case 0x440:
1124 device_str = "STM32F05x";
1125 rev_str = get_stm32f0_revision(rev_id);
1126 break;
1127
1128 case 0x445:
1129 device_str = "STM32F04x";
1130 rev_str = get_stm32f0_revision(rev_id);
1131 break;
1132
1133 case 0x446:
1134 device_str = "STM32F303xD/E";
1135 switch (rev_id) {
1136 case 0x1000:
1137 rev_str = "A";
1138 break;
1139 }
1140 break;
1141
1142 case 0x448:
1143 device_str = "STM32F07x";
1144 rev_str = get_stm32f0_revision(rev_id);
1145 break;
1146
1147 case 0x442:
1148 device_str = "STM32F09x";
1149 rev_str = get_stm32f0_revision(rev_id);
1150 break;
1151
1152 default:
1153 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1154 return ERROR_FAIL;
1155 }
1156
1157 if (rev_str != NULL)
1158 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1159 else
1160 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1161
1162 return ERROR_OK;
1163 }
1164
1165 COMMAND_HANDLER(stm32x_handle_lock_command)
1166 {
1167 struct target *target = NULL;
1168 struct stm32x_flash_bank *stm32x_info = NULL;
1169
1170 if (CMD_ARGC < 1)
1171 return ERROR_COMMAND_SYNTAX_ERROR;
1172
1173 struct flash_bank *bank;
1174 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1175 if (ERROR_OK != retval)
1176 return retval;
1177
1178 stm32x_info = bank->driver_priv;
1179
1180 target = bank->target;
1181
1182 if (target->state != TARGET_HALTED) {
1183 LOG_ERROR("Target not halted");
1184 return ERROR_TARGET_NOT_HALTED;
1185 }
1186
1187 retval = stm32x_check_operation_supported(bank);
1188 if (ERROR_OK != retval)
1189 return retval;
1190
1191 if (stm32x_erase_options(bank) != ERROR_OK) {
1192 command_print(CMD, "stm32x failed to erase options");
1193 return ERROR_OK;
1194 }
1195
1196 /* set readout protection */
1197 stm32x_info->option_bytes.rdp = 0;
1198
1199 if (stm32x_write_options(bank) != ERROR_OK) {
1200 command_print(CMD, "stm32x failed to lock device");
1201 return ERROR_OK;
1202 }
1203
1204 command_print(CMD, "stm32x locked");
1205
1206 return ERROR_OK;
1207 }
1208
1209 COMMAND_HANDLER(stm32x_handle_unlock_command)
1210 {
1211 struct target *target = NULL;
1212
1213 if (CMD_ARGC < 1)
1214 return ERROR_COMMAND_SYNTAX_ERROR;
1215
1216 struct flash_bank *bank;
1217 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1218 if (ERROR_OK != retval)
1219 return retval;
1220
1221 target = bank->target;
1222
1223 if (target->state != TARGET_HALTED) {
1224 LOG_ERROR("Target not halted");
1225 return ERROR_TARGET_NOT_HALTED;
1226 }
1227
1228 retval = stm32x_check_operation_supported(bank);
1229 if (ERROR_OK != retval)
1230 return retval;
1231
1232 if (stm32x_erase_options(bank) != ERROR_OK) {
1233 command_print(CMD, "stm32x failed to erase options");
1234 return ERROR_OK;
1235 }
1236
1237 if (stm32x_write_options(bank) != ERROR_OK) {
1238 command_print(CMD, "stm32x failed to unlock device");
1239 return ERROR_OK;
1240 }
1241
1242 command_print(CMD, "stm32x unlocked.\n"
1243 "INFO: a reset or power cycle is required "
1244 "for the new settings to take effect.");
1245
1246 return ERROR_OK;
1247 }
1248
1249 COMMAND_HANDLER(stm32x_handle_options_read_command)
1250 {
1251 uint32_t optionbyte, protection;
1252 struct target *target = NULL;
1253 struct stm32x_flash_bank *stm32x_info = NULL;
1254
1255 if (CMD_ARGC < 1)
1256 return ERROR_COMMAND_SYNTAX_ERROR;
1257
1258 struct flash_bank *bank;
1259 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1260 if (ERROR_OK != retval)
1261 return retval;
1262
1263 stm32x_info = bank->driver_priv;
1264
1265 target = bank->target;
1266
1267 if (target->state != TARGET_HALTED) {
1268 LOG_ERROR("Target not halted");
1269 return ERROR_TARGET_NOT_HALTED;
1270 }
1271
1272 retval = stm32x_check_operation_supported(bank);
1273 if (ERROR_OK != retval)
1274 return retval;
1275
1276 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1277 if (retval != ERROR_OK)
1278 return retval;
1279
1280 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1281
1282 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1283 if (retval != ERROR_OK)
1284 return retval;
1285
1286 if (optionbyte & (1 << OPT_ERROR))
1287 command_print(CMD, "option byte complement error");
1288
1289 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1290 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1291
1292 command_print(CMD, "read protection: %s",
1293 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1294
1295 /* user option bytes are offset depending on variant */
1296 optionbyte >>= stm32x_info->option_offset;
1297
1298 command_print(CMD, "watchdog: %sware",
1299 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1300
1301 command_print(CMD, "stop mode: %sreset generated upon entry",
1302 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1303
1304 command_print(CMD, "standby mode: %sreset generated upon entry",
1305 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1306
1307 if (stm32x_info->has_dual_banks)
1308 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1309
1310 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1311
1312 return ERROR_OK;
1313 }
1314
1315 COMMAND_HANDLER(stm32x_handle_options_write_command)
1316 {
1317 struct target *target = NULL;
1318 struct stm32x_flash_bank *stm32x_info = NULL;
1319 uint8_t optionbyte;
1320 uint16_t useropt;
1321
1322 if (CMD_ARGC < 2)
1323 return ERROR_COMMAND_SYNTAX_ERROR;
1324
1325 struct flash_bank *bank;
1326 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1327 if (ERROR_OK != retval)
1328 return retval;
1329
1330 stm32x_info = bank->driver_priv;
1331
1332 target = bank->target;
1333
1334 if (target->state != TARGET_HALTED) {
1335 LOG_ERROR("Target not halted");
1336 return ERROR_TARGET_NOT_HALTED;
1337 }
1338
1339 retval = stm32x_check_operation_supported(bank);
1340 if (ERROR_OK != retval)
1341 return retval;
1342
1343 retval = stm32x_read_options(bank);
1344 if (ERROR_OK != retval)
1345 return retval;
1346
1347 /* start with current options */
1348 optionbyte = stm32x_info->option_bytes.user;
1349 useropt = stm32x_info->option_bytes.data;
1350
1351 /* skip over flash bank */
1352 CMD_ARGC--;
1353 CMD_ARGV++;
1354
1355 while (CMD_ARGC) {
1356 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1357 optionbyte |= (1 << 0);
1358 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1359 optionbyte &= ~(1 << 0);
1360 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1361 optionbyte |= (1 << 1);
1362 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1363 optionbyte &= ~(1 << 1);
1364 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1365 optionbyte |= (1 << 2);
1366 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1367 optionbyte &= ~(1 << 2);
1368 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1369 if (CMD_ARGC < 2)
1370 return ERROR_COMMAND_SYNTAX_ERROR;
1371 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1372 CMD_ARGC--;
1373 CMD_ARGV++;
1374 } else if (stm32x_info->has_dual_banks) {
1375 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1376 optionbyte |= (1 << 3);
1377 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1378 optionbyte &= ~(1 << 3);
1379 else
1380 return ERROR_COMMAND_SYNTAX_ERROR;
1381 } else
1382 return ERROR_COMMAND_SYNTAX_ERROR;
1383 CMD_ARGC--;
1384 CMD_ARGV++;
1385 }
1386
1387 if (stm32x_erase_options(bank) != ERROR_OK) {
1388 command_print(CMD, "stm32x failed to erase options");
1389 return ERROR_OK;
1390 }
1391
1392 stm32x_info->option_bytes.user = optionbyte;
1393 stm32x_info->option_bytes.data = useropt;
1394
1395 if (stm32x_write_options(bank) != ERROR_OK) {
1396 command_print(CMD, "stm32x failed to write options");
1397 return ERROR_OK;
1398 }
1399
1400 command_print(CMD, "stm32x write options complete.\n"
1401 "INFO: %spower cycle is required "
1402 "for the new settings to take effect.",
1403 stm32x_info->can_load_options
1404 ? "'stm32f1x options_load' command or " : "");
1405
1406 return ERROR_OK;
1407 }
1408
1409 COMMAND_HANDLER(stm32x_handle_options_load_command)
1410 {
1411 if (CMD_ARGC < 1)
1412 return ERROR_COMMAND_SYNTAX_ERROR;
1413
1414 struct flash_bank *bank;
1415 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1416 if (ERROR_OK != retval)
1417 return retval;
1418
1419 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1420
1421 if (!stm32x_info->can_load_options) {
1422 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1423 "required instead.");
1424 return ERROR_FAIL;
1425 }
1426
1427 struct target *target = bank->target;
1428
1429 if (target->state != TARGET_HALTED) {
1430 LOG_ERROR("Target not halted");
1431 return ERROR_TARGET_NOT_HALTED;
1432 }
1433
1434 retval = stm32x_check_operation_supported(bank);
1435 if (ERROR_OK != retval)
1436 return retval;
1437
1438 /* unlock option flash registers */
1439 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1440 if (retval != ERROR_OK)
1441 return retval;
1442 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1443 if (retval != ERROR_OK)
1444 return retval;
1445
1446 /* force re-load of option bytes - generates software reset */
1447 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1448 if (retval != ERROR_OK)
1449 return retval;
1450
1451 return ERROR_OK;
1452 }
1453
1454 static int stm32x_mass_erase(struct flash_bank *bank)
1455 {
1456 struct target *target = bank->target;
1457
1458 if (target->state != TARGET_HALTED) {
1459 LOG_ERROR("Target not halted");
1460 return ERROR_TARGET_NOT_HALTED;
1461 }
1462
1463 /* unlock option flash registers */
1464 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1465 if (retval != ERROR_OK)
1466 return retval;
1467 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1468 if (retval != ERROR_OK)
1469 return retval;
1470
1471 /* mass erase flash memory */
1472 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1473 if (retval != ERROR_OK)
1474 return retval;
1475 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1476 FLASH_MER | FLASH_STRT);
1477 if (retval != ERROR_OK)
1478 return retval;
1479
1480 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1481 if (retval != ERROR_OK)
1482 return retval;
1483
1484 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1485 if (retval != ERROR_OK)
1486 return retval;
1487
1488 return ERROR_OK;
1489 }
1490
1491 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1492 {
1493 if (CMD_ARGC < 1)
1494 return ERROR_COMMAND_SYNTAX_ERROR;
1495
1496 struct flash_bank *bank;
1497 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1498 if (ERROR_OK != retval)
1499 return retval;
1500
1501 retval = stm32x_mass_erase(bank);
1502 if (retval == ERROR_OK) {
1503 /* set all sectors as erased */
1504 for (unsigned int i = 0; i < bank->num_sectors; i++)
1505 bank->sectors[i].is_erased = 1;
1506
1507 command_print(CMD, "stm32x mass erase complete");
1508 } else
1509 command_print(CMD, "stm32x mass erase failed");
1510
1511 return retval;
1512 }
1513
1514 static const struct command_registration stm32x_exec_command_handlers[] = {
1515 {
1516 .name = "lock",
1517 .handler = stm32x_handle_lock_command,
1518 .mode = COMMAND_EXEC,
1519 .usage = "bank_id",
1520 .help = "Lock entire flash device.",
1521 },
1522 {
1523 .name = "unlock",
1524 .handler = stm32x_handle_unlock_command,
1525 .mode = COMMAND_EXEC,
1526 .usage = "bank_id",
1527 .help = "Unlock entire protected flash device.",
1528 },
1529 {
1530 .name = "mass_erase",
1531 .handler = stm32x_handle_mass_erase_command,
1532 .mode = COMMAND_EXEC,
1533 .usage = "bank_id",
1534 .help = "Erase entire flash device.",
1535 },
1536 {
1537 .name = "options_read",
1538 .handler = stm32x_handle_options_read_command,
1539 .mode = COMMAND_EXEC,
1540 .usage = "bank_id",
1541 .help = "Read and display device option bytes.",
1542 },
1543 {
1544 .name = "options_write",
1545 .handler = stm32x_handle_options_write_command,
1546 .mode = COMMAND_EXEC,
1547 .usage = "bank_id ('SWWDG'|'HWWDG') "
1548 "('RSTSTNDBY'|'NORSTSTNDBY') "
1549 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1550 .help = "Replace bits in device option bytes.",
1551 },
1552 {
1553 .name = "options_load",
1554 .handler = stm32x_handle_options_load_command,
1555 .mode = COMMAND_EXEC,
1556 .usage = "bank_id",
1557 .help = "Force re-load of device option bytes.",
1558 },
1559 COMMAND_REGISTRATION_DONE
1560 };
1561
1562 static const struct command_registration stm32x_command_handlers[] = {
1563 {
1564 .name = "stm32f1x",
1565 .mode = COMMAND_ANY,
1566 .help = "stm32f1x flash command group",
1567 .usage = "",
1568 .chain = stm32x_exec_command_handlers,
1569 },
1570 COMMAND_REGISTRATION_DONE
1571 };
1572
1573 const struct flash_driver stm32f1x_flash = {
1574 .name = "stm32f1x",
1575 .commands = stm32x_command_handlers,
1576 .flash_bank_command = stm32x_flash_bank_command,
1577 .erase = stm32x_erase,
1578 .protect = stm32x_protect,
1579 .write = stm32x_write,
1580 .read = default_flash_read,
1581 .probe = stm32x_probe,
1582 .auto_probe = stm32x_auto_probe,
1583 .erase_check = default_flash_blank_check,
1584 .protect_check = stm32x_protect_check,
1585 .info = get_stm32x_info,
1586 .free_driver_priv = default_flash_free_driver_priv,
1587 };
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