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flash/nor/nrf5: unify size of HWID
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 bool probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 return ERROR_OK;
155 }
156
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
158 {
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
161 }
162
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
164 {
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
167 }
168
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
170 {
171 struct target *target = bank->target;
172 uint32_t status;
173 int retval = ERROR_OK;
174
175 /* wait for busy to clear */
176 for (;;) {
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
179 return retval;
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
182 break;
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
185 return ERROR_FAIL;
186 }
187 alive_sleep(1);
188 }
189
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
192 retval = ERROR_FAIL;
193 }
194
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
197 retval = ERROR_FAIL;
198 }
199
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
203 * retval
204 */
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
207 }
208 return retval;
209 }
210
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
212 {
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
214
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int stm32x_read_options(struct flash_bank *bank)
226 {
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
230 int retval;
231
232 /* read user and read protection option bytes, user data option bytes */
233 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
238 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
239 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
240
241 /* read write protection option bytes */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
243 if (retval != ERROR_OK)
244 return retval;
245
246 return ERROR_OK;
247 }
248
249 static int stm32x_erase_options(struct flash_bank *bank)
250 {
251 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
252 struct target *target = bank->target;
253
254 /* read current options */
255 stm32x_read_options(bank);
256
257 /* unlock flash registers */
258 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
259 if (retval != ERROR_OK)
260 return retval;
261
262 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
263 if (retval != ERROR_OK)
264 return retval;
265
266 /* unlock option flash registers */
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
268 if (retval != ERROR_OK)
269 return retval;
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* erase option bytes */
275 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
276 if (retval != ERROR_OK)
277 return retval;
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 return retval;
281
282 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
283 if (retval != ERROR_OK)
284 return retval;
285
286 /* clear read protection option byte
287 * this will also force a device unlock if set */
288 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
289
290 return ERROR_OK;
291 }
292
293 static int stm32x_write_options(struct flash_bank *bank)
294 {
295 struct stm32x_flash_bank *stm32x_info = NULL;
296 struct target *target = bank->target;
297
298 stm32x_info = bank->driver_priv;
299
300 /* unlock flash registers */
301 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
302 if (retval != ERROR_OK)
303 return retval;
304 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
305 if (retval != ERROR_OK)
306 return retval;
307
308 /* unlock option flash registers */
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
310 if (retval != ERROR_OK)
311 return retval;
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
313 if (retval != ERROR_OK)
314 return retval;
315
316 /* program option bytes */
317 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
318 if (retval != ERROR_OK)
319 return retval;
320
321 uint8_t opt_bytes[16];
322
323 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
324 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
325 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
326 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
327 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
328 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
331
332 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
333 if (retval != ERROR_OK) {
334 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
335 LOG_ERROR("working area required to erase options bytes");
336 return retval;
337 }
338
339 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
340 if (retval != ERROR_OK)
341 return retval;
342
343 return ERROR_OK;
344 }
345
346 static int stm32x_protect_check(struct flash_bank *bank)
347 {
348 struct target *target = bank->target;
349 uint32_t protection;
350
351 int retval = stm32x_check_operation_supported(bank);
352 if (ERROR_OK != retval)
353 return retval;
354
355 /* medium density - each bit refers to a 4 sector protection block
356 * high density - each bit refers to a 2 sector protection block
357 * bit 31 refers to all remaining sectors in a bank */
358 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
359 if (retval != ERROR_OK)
360 return retval;
361
362 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
363 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
364
365 return ERROR_OK;
366 }
367
368 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
369 unsigned int last)
370 {
371 struct target *target = bank->target;
372
373 if (bank->target->state != TARGET_HALTED) {
374 LOG_ERROR("Target not halted");
375 return ERROR_TARGET_NOT_HALTED;
376 }
377
378 if ((first == 0) && (last == (bank->num_sectors - 1)))
379 return stm32x_mass_erase(bank);
380
381 /* unlock flash registers */
382 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
383 if (retval != ERROR_OK)
384 return retval;
385 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
386 if (retval != ERROR_OK)
387 return retval;
388
389 for (unsigned int i = first; i <= last; i++) {
390 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
391 if (retval != ERROR_OK)
392 return retval;
393 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
394 bank->base + bank->sectors[i].offset);
395 if (retval != ERROR_OK)
396 return retval;
397 retval = target_write_u32(target,
398 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
399 if (retval != ERROR_OK)
400 return retval;
401
402 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
403 if (retval != ERROR_OK)
404 return retval;
405
406 bank->sectors[i].is_erased = 1;
407 }
408
409 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
410 if (retval != ERROR_OK)
411 return retval;
412
413 return ERROR_OK;
414 }
415
416 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
417 unsigned int last)
418 {
419 struct target *target = bank->target;
420 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
421
422 if (target->state != TARGET_HALTED) {
423 LOG_ERROR("Target not halted");
424 return ERROR_TARGET_NOT_HALTED;
425 }
426
427 int retval = stm32x_check_operation_supported(bank);
428 if (retval != ERROR_OK)
429 return retval;
430
431 retval = stm32x_erase_options(bank);
432 if (retval != ERROR_OK) {
433 LOG_ERROR("stm32x failed to erase options");
434 return retval;
435 }
436
437 for (unsigned int i = first; i <= last; i++) {
438 if (set)
439 stm32x_info->option_bytes.protection &= ~(1 << i);
440 else
441 stm32x_info->option_bytes.protection |= (1 << i);
442 }
443
444 return stm32x_write_options(bank);
445 }
446
447 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
448 uint32_t address, uint32_t count)
449 {
450 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
451 struct target *target = bank->target;
452 uint32_t buffer_size = 16384;
453 struct working_area *write_algorithm;
454 struct working_area *source;
455 struct reg_param reg_params[5];
456 struct armv7m_algorithm armv7m_info;
457 int retval = ERROR_OK;
458
459 static const uint8_t stm32x_flash_write_code[] = {
460 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
461 };
462
463 /* flash write code */
464 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
465 &write_algorithm) != ERROR_OK) {
466 LOG_WARNING("no working area available, can't do block memory writes");
467 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
468 }
469
470 retval = target_write_buffer(target, write_algorithm->address,
471 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
472 if (retval != ERROR_OK) {
473 target_free_working_area(target, write_algorithm);
474 return retval;
475 }
476
477 /* memory buffer */
478 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
479 buffer_size /= 2;
480 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
481 if (buffer_size <= 256) {
482 /* we already allocated the writing code, but failed to get a
483 * buffer, free the algorithm */
484 target_free_working_area(target, write_algorithm);
485
486 LOG_WARNING("no large enough working area available, can't do block memory writes");
487 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
488 }
489 }
490
491 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
492 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
493 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
494 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
495 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
496
497 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
498 buf_set_u32(reg_params[1].value, 0, 32, count);
499 buf_set_u32(reg_params[2].value, 0, 32, source->address);
500 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
501 buf_set_u32(reg_params[4].value, 0, 32, address);
502
503 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
504 armv7m_info.core_mode = ARM_MODE_THREAD;
505
506 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
507 0, NULL,
508 5, reg_params,
509 source->address, source->size,
510 write_algorithm->address, 0,
511 &armv7m_info);
512
513 if (retval == ERROR_FLASH_OPERATION_FAILED) {
514 LOG_ERROR("flash write failed at address 0x%"PRIx32,
515 buf_get_u32(reg_params[4].value, 0, 32));
516
517 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
518 LOG_ERROR("flash memory not erased before writing");
519 /* Clear but report errors */
520 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
521 }
522
523 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
524 LOG_ERROR("flash memory write protected");
525 /* Clear but report errors */
526 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
527 }
528 }
529
530 target_free_working_area(target, source);
531 target_free_working_area(target, write_algorithm);
532
533 destroy_reg_param(&reg_params[0]);
534 destroy_reg_param(&reg_params[1]);
535 destroy_reg_param(&reg_params[2]);
536 destroy_reg_param(&reg_params[3]);
537 destroy_reg_param(&reg_params[4]);
538
539 return retval;
540 }
541
542 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
543 uint32_t offset, uint32_t count)
544 {
545 struct target *target = bank->target;
546 uint8_t *new_buffer = NULL;
547
548 if (bank->target->state != TARGET_HALTED) {
549 LOG_ERROR("Target not halted");
550 return ERROR_TARGET_NOT_HALTED;
551 }
552
553 if (offset & 0x1) {
554 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
555 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
556 }
557
558 /* If there's an odd number of bytes, the data has to be padded. Duplicate
559 * the buffer and use the normal code path with a single block write since
560 * it's probably cheaper than to special case the last odd write using
561 * discrete accesses. */
562 if (count & 1) {
563 new_buffer = malloc(count + 1);
564 if (new_buffer == NULL) {
565 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
566 return ERROR_FAIL;
567 }
568 LOG_INFO("odd number of bytes to write, padding with 0xff");
569 buffer = memcpy(new_buffer, buffer, count);
570 new_buffer[count++] = 0xff;
571 }
572
573 uint32_t words_remaining = count / 2;
574 int retval, retval2;
575
576 /* unlock flash registers */
577 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
578 if (retval != ERROR_OK)
579 goto cleanup;
580 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
581 if (retval != ERROR_OK)
582 goto cleanup;
583
584 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
585 if (retval != ERROR_OK)
586 goto cleanup;
587
588 /* try using a block write */
589 retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
590
591 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
592 /* if block write failed (no sufficient working area),
593 * we use normal (slow) single halfword accesses */
594 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
595
596 while (words_remaining > 0) {
597 uint16_t value;
598 memcpy(&value, buffer, sizeof(uint16_t));
599
600 retval = target_write_u16(target, bank->base + offset, value);
601 if (retval != ERROR_OK)
602 goto reset_pg_and_lock;
603
604 retval = stm32x_wait_status_busy(bank, 5);
605 if (retval != ERROR_OK)
606 goto reset_pg_and_lock;
607
608 words_remaining--;
609 buffer += 2;
610 offset += 2;
611 }
612 }
613
614 reset_pg_and_lock:
615 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
616 if (retval == ERROR_OK)
617 retval = retval2;
618
619 cleanup:
620 free(new_buffer);
621 return retval;
622 }
623
624 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
625 {
626 /* This check the device CPUID core register to detect
627 * the M0 from the M3 devices. */
628
629 struct target *target = bank->target;
630 uint32_t cpuid, device_id_register = 0;
631
632 /* Get the CPUID from the ARM Core
633 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
634 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
635 if (retval != ERROR_OK)
636 return retval;
637
638 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
639 /* 0xC20 is M0 devices */
640 device_id_register = 0x40015800;
641 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
642 /* 0xC23 is M3 devices */
643 device_id_register = 0xE0042000;
644 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
645 /* 0xC24 is M4 devices */
646 device_id_register = 0xE0042000;
647 } else {
648 LOG_ERROR("Cannot identify target as a stm32x");
649 return ERROR_FAIL;
650 }
651
652 /* read stm32 device id register */
653 retval = target_read_u32(target, device_id_register, device_id);
654 if (retval != ERROR_OK)
655 return retval;
656
657 return retval;
658 }
659
660 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
661 {
662 struct target *target = bank->target;
663 uint32_t cpuid, flash_size_reg;
664
665 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
666 if (retval != ERROR_OK)
667 return retval;
668
669 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
670 /* 0xC20 is M0 devices */
671 flash_size_reg = 0x1FFFF7CC;
672 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
673 /* 0xC23 is M3 devices */
674 flash_size_reg = 0x1FFFF7E0;
675 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
676 /* 0xC24 is M4 devices */
677 flash_size_reg = 0x1FFFF7CC;
678 } else {
679 LOG_ERROR("Cannot identify target as a stm32x");
680 return ERROR_FAIL;
681 }
682
683 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
684 if (retval != ERROR_OK)
685 return retval;
686
687 return retval;
688 }
689
690 static int stm32x_probe(struct flash_bank *bank)
691 {
692 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
693 uint16_t flash_size_in_kb;
694 uint16_t max_flash_size_in_kb;
695 uint32_t device_id;
696 int page_size;
697 uint32_t base_address = 0x08000000;
698
699 stm32x_info->probed = false;
700 stm32x_info->register_base = FLASH_REG_BASE_B0;
701 stm32x_info->user_data_offset = 10;
702 stm32x_info->option_offset = 0;
703
704 /* default factory read protection level 0 */
705 stm32x_info->default_rdp = 0xA5;
706
707 /* read stm32 device id register */
708 int retval = stm32x_get_device_id(bank, &device_id);
709 if (retval != ERROR_OK)
710 return retval;
711
712 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
713
714 /* set page size, protection granularity and max flash size depending on family */
715 switch (device_id & 0xfff) {
716 case 0x440: /* stm32f05x */
717 page_size = 1024;
718 stm32x_info->ppage_size = 4;
719 max_flash_size_in_kb = 64;
720 stm32x_info->user_data_offset = 16;
721 stm32x_info->option_offset = 6;
722 stm32x_info->default_rdp = 0xAA;
723 stm32x_info->can_load_options = true;
724 break;
725 case 0x444: /* stm32f03x */
726 case 0x445: /* stm32f04x */
727 page_size = 1024;
728 stm32x_info->ppage_size = 4;
729 max_flash_size_in_kb = 32;
730 stm32x_info->user_data_offset = 16;
731 stm32x_info->option_offset = 6;
732 stm32x_info->default_rdp = 0xAA;
733 stm32x_info->can_load_options = true;
734 break;
735 case 0x448: /* stm32f07x */
736 page_size = 2048;
737 stm32x_info->ppage_size = 4;
738 max_flash_size_in_kb = 128;
739 stm32x_info->user_data_offset = 16;
740 stm32x_info->option_offset = 6;
741 stm32x_info->default_rdp = 0xAA;
742 stm32x_info->can_load_options = true;
743 break;
744 case 0x442: /* stm32f09x */
745 page_size = 2048;
746 stm32x_info->ppage_size = 4;
747 max_flash_size_in_kb = 256;
748 stm32x_info->user_data_offset = 16;
749 stm32x_info->option_offset = 6;
750 stm32x_info->default_rdp = 0xAA;
751 stm32x_info->can_load_options = true;
752 break;
753 case 0x410: /* stm32f1x medium-density */
754 page_size = 1024;
755 stm32x_info->ppage_size = 4;
756 max_flash_size_in_kb = 128;
757 break;
758 case 0x412: /* stm32f1x low-density */
759 page_size = 1024;
760 stm32x_info->ppage_size = 4;
761 max_flash_size_in_kb = 32;
762 break;
763 case 0x414: /* stm32f1x high-density */
764 page_size = 2048;
765 stm32x_info->ppage_size = 2;
766 max_flash_size_in_kb = 512;
767 break;
768 case 0x418: /* stm32f1x connectivity */
769 page_size = 2048;
770 stm32x_info->ppage_size = 2;
771 max_flash_size_in_kb = 256;
772 break;
773 case 0x430: /* stm32f1 XL-density (dual flash banks) */
774 page_size = 2048;
775 stm32x_info->ppage_size = 2;
776 max_flash_size_in_kb = 1024;
777 stm32x_info->has_dual_banks = true;
778 break;
779 case 0x420: /* stm32f100xx low- and medium-density value line */
780 page_size = 1024;
781 stm32x_info->ppage_size = 4;
782 max_flash_size_in_kb = 128;
783 break;
784 case 0x428: /* stm32f100xx high-density value line */
785 page_size = 2048;
786 stm32x_info->ppage_size = 4;
787 max_flash_size_in_kb = 512;
788 break;
789 case 0x422: /* stm32f302/3xb/c */
790 page_size = 2048;
791 stm32x_info->ppage_size = 2;
792 max_flash_size_in_kb = 256;
793 stm32x_info->user_data_offset = 16;
794 stm32x_info->option_offset = 6;
795 stm32x_info->default_rdp = 0xAA;
796 stm32x_info->can_load_options = true;
797 break;
798 case 0x446: /* stm32f303xD/E */
799 page_size = 2048;
800 stm32x_info->ppage_size = 2;
801 max_flash_size_in_kb = 512;
802 stm32x_info->user_data_offset = 16;
803 stm32x_info->option_offset = 6;
804 stm32x_info->default_rdp = 0xAA;
805 stm32x_info->can_load_options = true;
806 break;
807 case 0x432: /* stm32f37x */
808 page_size = 2048;
809 stm32x_info->ppage_size = 2;
810 max_flash_size_in_kb = 256;
811 stm32x_info->user_data_offset = 16;
812 stm32x_info->option_offset = 6;
813 stm32x_info->default_rdp = 0xAA;
814 stm32x_info->can_load_options = true;
815 break;
816 case 0x438: /* stm32f33x */
817 case 0x439: /* stm32f302x6/8 */
818 page_size = 2048;
819 stm32x_info->ppage_size = 2;
820 max_flash_size_in_kb = 64;
821 stm32x_info->user_data_offset = 16;
822 stm32x_info->option_offset = 6;
823 stm32x_info->default_rdp = 0xAA;
824 stm32x_info->can_load_options = true;
825 break;
826 default:
827 LOG_WARNING("Cannot identify target as a STM32 family.");
828 return ERROR_FAIL;
829 }
830
831 /* get flash size from target. */
832 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
833
834 /* failed reading flash size or flash size invalid (early silicon),
835 * default to max target family */
836 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
837 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
838 max_flash_size_in_kb);
839 flash_size_in_kb = max_flash_size_in_kb;
840 }
841
842 if (stm32x_info->has_dual_banks) {
843 /* split reported size into matching bank */
844 if (bank->base != 0x08080000) {
845 /* bank 0 will be fixed 512k */
846 flash_size_in_kb = 512;
847 } else {
848 flash_size_in_kb -= 512;
849 /* bank1 also uses a register offset */
850 stm32x_info->register_base = FLASH_REG_BASE_B1;
851 base_address = 0x08080000;
852 }
853 }
854
855 /* if the user sets the size manually then ignore the probed value
856 * this allows us to work around devices that have a invalid flash size register value */
857 if (stm32x_info->user_bank_size) {
858 LOG_INFO("ignoring flash probed value, using configured bank size");
859 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
860 }
861
862 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
863
864 /* did we assign flash size? */
865 assert(flash_size_in_kb != 0xffff);
866
867 /* calculate numbers of pages */
868 int num_pages = flash_size_in_kb * 1024 / page_size;
869
870 /* check that calculation result makes sense */
871 assert(num_pages > 0);
872
873 free(bank->sectors);
874 bank->sectors = NULL;
875
876 free(bank->prot_blocks);
877 bank->prot_blocks = NULL;
878
879 bank->base = base_address;
880 bank->size = (num_pages * page_size);
881
882 bank->num_sectors = num_pages;
883 bank->sectors = alloc_block_array(0, page_size, num_pages);
884 if (!bank->sectors)
885 return ERROR_FAIL;
886
887 /* calculate number of write protection blocks */
888 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
889 if (num_prot_blocks > 32)
890 num_prot_blocks = 32;
891
892 bank->num_prot_blocks = num_prot_blocks;
893 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
894 if (!bank->prot_blocks)
895 return ERROR_FAIL;
896
897 if (num_prot_blocks == 32)
898 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
899
900 stm32x_info->probed = true;
901
902 return ERROR_OK;
903 }
904
905 static int stm32x_auto_probe(struct flash_bank *bank)
906 {
907 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
908 if (stm32x_info->probed)
909 return ERROR_OK;
910 return stm32x_probe(bank);
911 }
912
913 #if 0
914 COMMAND_HANDLER(stm32x_handle_part_id_command)
915 {
916 return ERROR_OK;
917 }
918 #endif
919
920 static const char *get_stm32f0_revision(uint16_t rev_id)
921 {
922 const char *rev_str = NULL;
923
924 switch (rev_id) {
925 case 0x1000:
926 rev_str = "1.0";
927 break;
928 case 0x2000:
929 rev_str = "2.0";
930 break;
931 }
932 return rev_str;
933 }
934
935 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
936 {
937 uint32_t dbgmcu_idcode;
938
939 /* read stm32 device id register */
940 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
941 if (retval != ERROR_OK)
942 return retval;
943
944 uint16_t device_id = dbgmcu_idcode & 0xfff;
945 uint16_t rev_id = dbgmcu_idcode >> 16;
946 const char *device_str;
947 const char *rev_str = NULL;
948
949 switch (device_id) {
950 case 0x410:
951 device_str = "STM32F10x (Medium Density)";
952
953 switch (rev_id) {
954 case 0x0000:
955 rev_str = "A";
956 break;
957
958 case 0x2000:
959 rev_str = "B";
960 break;
961
962 case 0x2001:
963 rev_str = "Z";
964 break;
965
966 case 0x2003:
967 rev_str = "Y";
968 break;
969 }
970 break;
971
972 case 0x412:
973 device_str = "STM32F10x (Low Density)";
974
975 switch (rev_id) {
976 case 0x1000:
977 rev_str = "A";
978 break;
979 }
980 break;
981
982 case 0x414:
983 device_str = "STM32F10x (High Density)";
984
985 switch (rev_id) {
986 case 0x1000:
987 rev_str = "A";
988 break;
989
990 case 0x1001:
991 rev_str = "Z";
992 break;
993
994 case 0x1003:
995 rev_str = "Y";
996 break;
997 }
998 break;
999
1000 case 0x418:
1001 device_str = "STM32F10x (Connectivity)";
1002
1003 switch (rev_id) {
1004 case 0x1000:
1005 rev_str = "A";
1006 break;
1007
1008 case 0x1001:
1009 rev_str = "Z";
1010 break;
1011 }
1012 break;
1013
1014 case 0x420:
1015 device_str = "STM32F100 (Low/Medium Density)";
1016
1017 switch (rev_id) {
1018 case 0x1000:
1019 rev_str = "A";
1020 break;
1021
1022 case 0x1001:
1023 rev_str = "Z";
1024 break;
1025 }
1026 break;
1027
1028 case 0x422:
1029 device_str = "STM32F302xB/C";
1030
1031 switch (rev_id) {
1032 case 0x1000:
1033 rev_str = "A";
1034 break;
1035
1036 case 0x1001:
1037 rev_str = "Z";
1038 break;
1039
1040 case 0x1003:
1041 rev_str = "Y";
1042 break;
1043
1044 case 0x2000:
1045 rev_str = "B";
1046 break;
1047 }
1048 break;
1049
1050 case 0x428:
1051 device_str = "STM32F100 (High Density)";
1052
1053 switch (rev_id) {
1054 case 0x1000:
1055 rev_str = "A";
1056 break;
1057
1058 case 0x1001:
1059 rev_str = "Z";
1060 break;
1061 }
1062 break;
1063
1064 case 0x430:
1065 device_str = "STM32F10x (XL Density)";
1066
1067 switch (rev_id) {
1068 case 0x1000:
1069 rev_str = "A";
1070 break;
1071 }
1072 break;
1073
1074 case 0x432:
1075 device_str = "STM32F37x";
1076
1077 switch (rev_id) {
1078 case 0x1000:
1079 rev_str = "A";
1080 break;
1081
1082 case 0x2000:
1083 rev_str = "B";
1084 break;
1085 }
1086 break;
1087
1088 case 0x438:
1089 device_str = "STM32F33x";
1090
1091 switch (rev_id) {
1092 case 0x1000:
1093 rev_str = "A";
1094 break;
1095 }
1096 break;
1097
1098 case 0x439:
1099 device_str = "STM32F302x6/8";
1100
1101 switch (rev_id) {
1102 case 0x1000:
1103 rev_str = "A";
1104 break;
1105
1106 case 0x1001:
1107 rev_str = "Z";
1108 break;
1109 }
1110 break;
1111
1112 case 0x444:
1113 device_str = "STM32F03x";
1114 rev_str = get_stm32f0_revision(rev_id);
1115 break;
1116
1117 case 0x440:
1118 device_str = "STM32F05x";
1119 rev_str = get_stm32f0_revision(rev_id);
1120 break;
1121
1122 case 0x445:
1123 device_str = "STM32F04x";
1124 rev_str = get_stm32f0_revision(rev_id);
1125 break;
1126
1127 case 0x446:
1128 device_str = "STM32F303xD/E";
1129 switch (rev_id) {
1130 case 0x1000:
1131 rev_str = "A";
1132 break;
1133 }
1134 break;
1135
1136 case 0x448:
1137 device_str = "STM32F07x";
1138 rev_str = get_stm32f0_revision(rev_id);
1139 break;
1140
1141 case 0x442:
1142 device_str = "STM32F09x";
1143 rev_str = get_stm32f0_revision(rev_id);
1144 break;
1145
1146 default:
1147 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1148 return ERROR_FAIL;
1149 }
1150
1151 if (rev_str != NULL)
1152 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1153 else
1154 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1155
1156 return ERROR_OK;
1157 }
1158
1159 COMMAND_HANDLER(stm32x_handle_lock_command)
1160 {
1161 struct target *target = NULL;
1162 struct stm32x_flash_bank *stm32x_info = NULL;
1163
1164 if (CMD_ARGC < 1)
1165 return ERROR_COMMAND_SYNTAX_ERROR;
1166
1167 struct flash_bank *bank;
1168 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1169 if (ERROR_OK != retval)
1170 return retval;
1171
1172 stm32x_info = bank->driver_priv;
1173
1174 target = bank->target;
1175
1176 if (target->state != TARGET_HALTED) {
1177 LOG_ERROR("Target not halted");
1178 return ERROR_TARGET_NOT_HALTED;
1179 }
1180
1181 retval = stm32x_check_operation_supported(bank);
1182 if (ERROR_OK != retval)
1183 return retval;
1184
1185 if (stm32x_erase_options(bank) != ERROR_OK) {
1186 command_print(CMD, "stm32x failed to erase options");
1187 return ERROR_OK;
1188 }
1189
1190 /* set readout protection */
1191 stm32x_info->option_bytes.rdp = 0;
1192
1193 if (stm32x_write_options(bank) != ERROR_OK) {
1194 command_print(CMD, "stm32x failed to lock device");
1195 return ERROR_OK;
1196 }
1197
1198 command_print(CMD, "stm32x locked");
1199
1200 return ERROR_OK;
1201 }
1202
1203 COMMAND_HANDLER(stm32x_handle_unlock_command)
1204 {
1205 struct target *target = NULL;
1206
1207 if (CMD_ARGC < 1)
1208 return ERROR_COMMAND_SYNTAX_ERROR;
1209
1210 struct flash_bank *bank;
1211 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1212 if (ERROR_OK != retval)
1213 return retval;
1214
1215 target = bank->target;
1216
1217 if (target->state != TARGET_HALTED) {
1218 LOG_ERROR("Target not halted");
1219 return ERROR_TARGET_NOT_HALTED;
1220 }
1221
1222 retval = stm32x_check_operation_supported(bank);
1223 if (ERROR_OK != retval)
1224 return retval;
1225
1226 if (stm32x_erase_options(bank) != ERROR_OK) {
1227 command_print(CMD, "stm32x failed to erase options");
1228 return ERROR_OK;
1229 }
1230
1231 if (stm32x_write_options(bank) != ERROR_OK) {
1232 command_print(CMD, "stm32x failed to unlock device");
1233 return ERROR_OK;
1234 }
1235
1236 command_print(CMD, "stm32x unlocked.\n"
1237 "INFO: a reset or power cycle is required "
1238 "for the new settings to take effect.");
1239
1240 return ERROR_OK;
1241 }
1242
1243 COMMAND_HANDLER(stm32x_handle_options_read_command)
1244 {
1245 uint32_t optionbyte, protection;
1246 struct target *target = NULL;
1247 struct stm32x_flash_bank *stm32x_info = NULL;
1248
1249 if (CMD_ARGC < 1)
1250 return ERROR_COMMAND_SYNTAX_ERROR;
1251
1252 struct flash_bank *bank;
1253 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1254 if (ERROR_OK != retval)
1255 return retval;
1256
1257 stm32x_info = bank->driver_priv;
1258
1259 target = bank->target;
1260
1261 if (target->state != TARGET_HALTED) {
1262 LOG_ERROR("Target not halted");
1263 return ERROR_TARGET_NOT_HALTED;
1264 }
1265
1266 retval = stm32x_check_operation_supported(bank);
1267 if (ERROR_OK != retval)
1268 return retval;
1269
1270 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1271 if (retval != ERROR_OK)
1272 return retval;
1273
1274 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1275
1276 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1277 if (retval != ERROR_OK)
1278 return retval;
1279
1280 if (optionbyte & (1 << OPT_ERROR))
1281 command_print(CMD, "option byte complement error");
1282
1283 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1284 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1285
1286 command_print(CMD, "read protection: %s",
1287 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1288
1289 /* user option bytes are offset depending on variant */
1290 optionbyte >>= stm32x_info->option_offset;
1291
1292 command_print(CMD, "watchdog: %sware",
1293 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1294
1295 command_print(CMD, "stop mode: %sreset generated upon entry",
1296 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1297
1298 command_print(CMD, "standby mode: %sreset generated upon entry",
1299 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1300
1301 if (stm32x_info->has_dual_banks)
1302 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1303
1304 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1305
1306 return ERROR_OK;
1307 }
1308
1309 COMMAND_HANDLER(stm32x_handle_options_write_command)
1310 {
1311 struct target *target = NULL;
1312 struct stm32x_flash_bank *stm32x_info = NULL;
1313 uint8_t optionbyte;
1314 uint16_t useropt;
1315
1316 if (CMD_ARGC < 2)
1317 return ERROR_COMMAND_SYNTAX_ERROR;
1318
1319 struct flash_bank *bank;
1320 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1321 if (ERROR_OK != retval)
1322 return retval;
1323
1324 stm32x_info = bank->driver_priv;
1325
1326 target = bank->target;
1327
1328 if (target->state != TARGET_HALTED) {
1329 LOG_ERROR("Target not halted");
1330 return ERROR_TARGET_NOT_HALTED;
1331 }
1332
1333 retval = stm32x_check_operation_supported(bank);
1334 if (ERROR_OK != retval)
1335 return retval;
1336
1337 retval = stm32x_read_options(bank);
1338 if (ERROR_OK != retval)
1339 return retval;
1340
1341 /* start with current options */
1342 optionbyte = stm32x_info->option_bytes.user;
1343 useropt = stm32x_info->option_bytes.data;
1344
1345 /* skip over flash bank */
1346 CMD_ARGC--;
1347 CMD_ARGV++;
1348
1349 while (CMD_ARGC) {
1350 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1351 optionbyte |= (1 << 0);
1352 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1353 optionbyte &= ~(1 << 0);
1354 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1355 optionbyte |= (1 << 1);
1356 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1357 optionbyte &= ~(1 << 1);
1358 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1359 optionbyte |= (1 << 2);
1360 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1361 optionbyte &= ~(1 << 2);
1362 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1363 if (CMD_ARGC < 2)
1364 return ERROR_COMMAND_SYNTAX_ERROR;
1365 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1366 CMD_ARGC--;
1367 CMD_ARGV++;
1368 } else if (stm32x_info->has_dual_banks) {
1369 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1370 optionbyte |= (1 << 3);
1371 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1372 optionbyte &= ~(1 << 3);
1373 else
1374 return ERROR_COMMAND_SYNTAX_ERROR;
1375 } else
1376 return ERROR_COMMAND_SYNTAX_ERROR;
1377 CMD_ARGC--;
1378 CMD_ARGV++;
1379 }
1380
1381 if (stm32x_erase_options(bank) != ERROR_OK) {
1382 command_print(CMD, "stm32x failed to erase options");
1383 return ERROR_OK;
1384 }
1385
1386 stm32x_info->option_bytes.user = optionbyte;
1387 stm32x_info->option_bytes.data = useropt;
1388
1389 if (stm32x_write_options(bank) != ERROR_OK) {
1390 command_print(CMD, "stm32x failed to write options");
1391 return ERROR_OK;
1392 }
1393
1394 command_print(CMD, "stm32x write options complete.\n"
1395 "INFO: %spower cycle is required "
1396 "for the new settings to take effect.",
1397 stm32x_info->can_load_options
1398 ? "'stm32f1x options_load' command or " : "");
1399
1400 return ERROR_OK;
1401 }
1402
1403 COMMAND_HANDLER(stm32x_handle_options_load_command)
1404 {
1405 if (CMD_ARGC < 1)
1406 return ERROR_COMMAND_SYNTAX_ERROR;
1407
1408 struct flash_bank *bank;
1409 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1410 if (ERROR_OK != retval)
1411 return retval;
1412
1413 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1414
1415 if (!stm32x_info->can_load_options) {
1416 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1417 "required instead.");
1418 return ERROR_FAIL;
1419 }
1420
1421 struct target *target = bank->target;
1422
1423 if (target->state != TARGET_HALTED) {
1424 LOG_ERROR("Target not halted");
1425 return ERROR_TARGET_NOT_HALTED;
1426 }
1427
1428 retval = stm32x_check_operation_supported(bank);
1429 if (ERROR_OK != retval)
1430 return retval;
1431
1432 /* unlock option flash registers */
1433 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1434 if (retval != ERROR_OK)
1435 return retval;
1436 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1437 if (retval != ERROR_OK)
1438 return retval;
1439
1440 /* force re-load of option bytes - generates software reset */
1441 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1442 if (retval != ERROR_OK)
1443 return retval;
1444
1445 return ERROR_OK;
1446 }
1447
1448 static int stm32x_mass_erase(struct flash_bank *bank)
1449 {
1450 struct target *target = bank->target;
1451
1452 if (target->state != TARGET_HALTED) {
1453 LOG_ERROR("Target not halted");
1454 return ERROR_TARGET_NOT_HALTED;
1455 }
1456
1457 /* unlock option flash registers */
1458 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1459 if (retval != ERROR_OK)
1460 return retval;
1461 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1462 if (retval != ERROR_OK)
1463 return retval;
1464
1465 /* mass erase flash memory */
1466 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1467 if (retval != ERROR_OK)
1468 return retval;
1469 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1470 FLASH_MER | FLASH_STRT);
1471 if (retval != ERROR_OK)
1472 return retval;
1473
1474 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1475 if (retval != ERROR_OK)
1476 return retval;
1477
1478 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1479 if (retval != ERROR_OK)
1480 return retval;
1481
1482 return ERROR_OK;
1483 }
1484
1485 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1486 {
1487 if (CMD_ARGC < 1)
1488 return ERROR_COMMAND_SYNTAX_ERROR;
1489
1490 struct flash_bank *bank;
1491 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1492 if (ERROR_OK != retval)
1493 return retval;
1494
1495 retval = stm32x_mass_erase(bank);
1496 if (retval == ERROR_OK) {
1497 /* set all sectors as erased */
1498 for (unsigned int i = 0; i < bank->num_sectors; i++)
1499 bank->sectors[i].is_erased = 1;
1500
1501 command_print(CMD, "stm32x mass erase complete");
1502 } else
1503 command_print(CMD, "stm32x mass erase failed");
1504
1505 return retval;
1506 }
1507
1508 static const struct command_registration stm32x_exec_command_handlers[] = {
1509 {
1510 .name = "lock",
1511 .handler = stm32x_handle_lock_command,
1512 .mode = COMMAND_EXEC,
1513 .usage = "bank_id",
1514 .help = "Lock entire flash device.",
1515 },
1516 {
1517 .name = "unlock",
1518 .handler = stm32x_handle_unlock_command,
1519 .mode = COMMAND_EXEC,
1520 .usage = "bank_id",
1521 .help = "Unlock entire protected flash device.",
1522 },
1523 {
1524 .name = "mass_erase",
1525 .handler = stm32x_handle_mass_erase_command,
1526 .mode = COMMAND_EXEC,
1527 .usage = "bank_id",
1528 .help = "Erase entire flash device.",
1529 },
1530 {
1531 .name = "options_read",
1532 .handler = stm32x_handle_options_read_command,
1533 .mode = COMMAND_EXEC,
1534 .usage = "bank_id",
1535 .help = "Read and display device option bytes.",
1536 },
1537 {
1538 .name = "options_write",
1539 .handler = stm32x_handle_options_write_command,
1540 .mode = COMMAND_EXEC,
1541 .usage = "bank_id ('SWWDG'|'HWWDG') "
1542 "('RSTSTNDBY'|'NORSTSTNDBY') "
1543 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1544 .help = "Replace bits in device option bytes.",
1545 },
1546 {
1547 .name = "options_load",
1548 .handler = stm32x_handle_options_load_command,
1549 .mode = COMMAND_EXEC,
1550 .usage = "bank_id",
1551 .help = "Force re-load of device option bytes.",
1552 },
1553 COMMAND_REGISTRATION_DONE
1554 };
1555
1556 static const struct command_registration stm32x_command_handlers[] = {
1557 {
1558 .name = "stm32f1x",
1559 .mode = COMMAND_ANY,
1560 .help = "stm32f1x flash command group",
1561 .usage = "",
1562 .chain = stm32x_exec_command_handlers,
1563 },
1564 COMMAND_REGISTRATION_DONE
1565 };
1566
1567 const struct flash_driver stm32f1x_flash = {
1568 .name = "stm32f1x",
1569 .commands = stm32x_command_handlers,
1570 .flash_bank_command = stm32x_flash_bank_command,
1571 .erase = stm32x_erase,
1572 .protect = stm32x_protect,
1573 .write = stm32x_write,
1574 .read = default_flash_read,
1575 .probe = stm32x_probe,
1576 .auto_probe = stm32x_auto_probe,
1577 .erase_check = default_flash_blank_check,
1578 .protect_check = stm32x_protect_check,
1579 .info = get_stm32x_info,
1580 .free_driver_priv = default_flash_free_driver_priv,
1581 };
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