Code Review / openocd.git / blob
? search:


29a3b7e06fd914b4b3a789d52074e54c699f22fc
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/cortex_m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 bool probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 return ERROR_OK;
155 }
156
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
158 {
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
161 }
162
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
164 {
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
167 }
168
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
170 {
171 struct target *target = bank->target;
172 uint32_t status;
173 int retval = ERROR_OK;
174
175 /* wait for busy to clear */
176 for (;;) {
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
179 return retval;
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
182 break;
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
185 return ERROR_FAIL;
186 }
187 alive_sleep(1);
188 }
189
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
192 retval = ERROR_FAIL;
193 }
194
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
197 retval = ERROR_FAIL;
198 }
199
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
203 * retval
204 */
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
207 }
208 return retval;
209 }
210
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
212 {
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
214
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option byte operations must use bank 0");
219 return ERROR_FLASH_OPERATION_FAILED;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int stm32x_read_options(struct flash_bank *bank)
226 {
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
230 int retval;
231
232 /* read user and read protection option bytes, user data option bytes */
233 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
238 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
239 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
240
241 /* read write protection option bytes */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
243 if (retval != ERROR_OK)
244 return retval;
245
246 return ERROR_OK;
247 }
248
249 static int stm32x_erase_options(struct flash_bank *bank)
250 {
251 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
252 struct target *target = bank->target;
253
254 /* read current options */
255 stm32x_read_options(bank);
256
257 /* unlock flash registers */
258 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
259 if (retval != ERROR_OK)
260 return retval;
261
262 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
263 if (retval != ERROR_OK)
264 return retval;
265
266 /* unlock option flash registers */
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
268 if (retval != ERROR_OK)
269 return retval;
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* erase option bytes */
275 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
276 if (retval != ERROR_OK)
277 return retval;
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 return retval;
281
282 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
283 if (retval != ERROR_OK)
284 return retval;
285
286 /* clear read protection option byte
287 * this will also force a device unlock if set */
288 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
289
290 return ERROR_OK;
291 }
292
293 static int stm32x_write_options(struct flash_bank *bank)
294 {
295 struct stm32x_flash_bank *stm32x_info = NULL;
296 struct target *target = bank->target;
297
298 stm32x_info = bank->driver_priv;
299
300 /* unlock flash registers */
301 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
302 if (retval != ERROR_OK)
303 return retval;
304 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
305 if (retval != ERROR_OK)
306 return retval;
307
308 /* unlock option flash registers */
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
310 if (retval != ERROR_OK)
311 return retval;
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
313 if (retval != ERROR_OK)
314 return retval;
315
316 /* program option bytes */
317 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
318 if (retval != ERROR_OK)
319 return retval;
320
321 uint8_t opt_bytes[16];
322
323 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
324 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
325 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
326 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
327 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
328 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
331
332 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
333 if (retval != ERROR_OK) {
334 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
335 LOG_ERROR("working area required to erase options bytes");
336 return retval;
337 }
338
339 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
340 if (retval != ERROR_OK)
341 return retval;
342
343 return ERROR_OK;
344 }
345
346 static int stm32x_protect_check(struct flash_bank *bank)
347 {
348 struct target *target = bank->target;
349 uint32_t protection;
350
351 int retval = stm32x_check_operation_supported(bank);
352 if (retval != ERROR_OK)
353 return retval;
354
355 /* medium density - each bit refers to a 4 sector protection block
356 * high density - each bit refers to a 2 sector protection block
357 * bit 31 refers to all remaining sectors in a bank */
358 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
359 if (retval != ERROR_OK)
360 return retval;
361
362 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
363 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
364
365 return ERROR_OK;
366 }
367
368 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
369 unsigned int last)
370 {
371 struct target *target = bank->target;
372
373 if (bank->target->state != TARGET_HALTED) {
374 LOG_ERROR("Target not halted");
375 return ERROR_TARGET_NOT_HALTED;
376 }
377
378 if ((first == 0) && (last == (bank->num_sectors - 1)))
379 return stm32x_mass_erase(bank);
380
381 /* unlock flash registers */
382 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
383 if (retval != ERROR_OK)
384 return retval;
385 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
386 if (retval != ERROR_OK)
387 return retval;
388
389 for (unsigned int i = first; i <= last; i++) {
390 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
391 if (retval != ERROR_OK)
392 return retval;
393 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
394 bank->base + bank->sectors[i].offset);
395 if (retval != ERROR_OK)
396 return retval;
397 retval = target_write_u32(target,
398 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
399 if (retval != ERROR_OK)
400 return retval;
401
402 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
403 if (retval != ERROR_OK)
404 return retval;
405 }
406
407 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
408 if (retval != ERROR_OK)
409 return retval;
410
411 return ERROR_OK;
412 }
413
414 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
415 unsigned int last)
416 {
417 struct target *target = bank->target;
418 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
419
420 if (target->state != TARGET_HALTED) {
421 LOG_ERROR("Target not halted");
422 return ERROR_TARGET_NOT_HALTED;
423 }
424
425 int retval = stm32x_check_operation_supported(bank);
426 if (retval != ERROR_OK)
427 return retval;
428
429 retval = stm32x_erase_options(bank);
430 if (retval != ERROR_OK) {
431 LOG_ERROR("stm32x failed to erase options");
432 return retval;
433 }
434
435 for (unsigned int i = first; i <= last; i++) {
436 if (set)
437 stm32x_info->option_bytes.protection &= ~(1 << i);
438 else
439 stm32x_info->option_bytes.protection |= (1 << i);
440 }
441
442 return stm32x_write_options(bank);
443 }
444
445 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
446 uint32_t address, uint32_t count)
447 {
448 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
449 struct target *target = bank->target;
450 uint32_t buffer_size = 16384;
451 struct working_area *write_algorithm;
452 struct working_area *source;
453 struct reg_param reg_params[5];
454 struct armv7m_algorithm armv7m_info;
455 int retval = ERROR_OK;
456
457 static const uint8_t stm32x_flash_write_code[] = {
458 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
459 };
460
461 /* flash write code */
462 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
463 &write_algorithm) != ERROR_OK) {
464 LOG_WARNING("no working area available, can't do block memory writes");
465 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
466 }
467
468 retval = target_write_buffer(target, write_algorithm->address,
469 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
470 if (retval != ERROR_OK) {
471 target_free_working_area(target, write_algorithm);
472 return retval;
473 }
474
475 /* memory buffer */
476 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
477 buffer_size /= 2;
478 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
479 if (buffer_size <= 256) {
480 /* we already allocated the writing code, but failed to get a
481 * buffer, free the algorithm */
482 target_free_working_area(target, write_algorithm);
483
484 LOG_WARNING("no large enough working area available, can't do block memory writes");
485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
486 }
487 }
488
489 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
490 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
491 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
492 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
493 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
494
495 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
496 buf_set_u32(reg_params[1].value, 0, 32, count);
497 buf_set_u32(reg_params[2].value, 0, 32, source->address);
498 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
499 buf_set_u32(reg_params[4].value, 0, 32, address);
500
501 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
502 armv7m_info.core_mode = ARM_MODE_THREAD;
503
504 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
505 0, NULL,
506 5, reg_params,
507 source->address, source->size,
508 write_algorithm->address, 0,
509 &armv7m_info);
510
511 if (retval == ERROR_FLASH_OPERATION_FAILED) {
512 LOG_ERROR("flash write failed at address 0x%"PRIx32,
513 buf_get_u32(reg_params[4].value, 0, 32));
514
515 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
516 LOG_ERROR("flash memory not erased before writing");
517 /* Clear but report errors */
518 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
519 }
520
521 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
522 LOG_ERROR("flash memory write protected");
523 /* Clear but report errors */
524 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
525 }
526 }
527
528 target_free_working_area(target, source);
529 target_free_working_area(target, write_algorithm);
530
531 destroy_reg_param(&reg_params[0]);
532 destroy_reg_param(&reg_params[1]);
533 destroy_reg_param(&reg_params[2]);
534 destroy_reg_param(&reg_params[3]);
535 destroy_reg_param(&reg_params[4]);
536
537 return retval;
538 }
539
540 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
541 uint32_t offset, uint32_t count)
542 {
543 struct target *target = bank->target;
544 uint8_t *new_buffer = NULL;
545
546 if (bank->target->state != TARGET_HALTED) {
547 LOG_ERROR("Target not halted");
548 return ERROR_TARGET_NOT_HALTED;
549 }
550
551 if (offset & 0x1) {
552 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
553 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
554 }
555
556 /* If there's an odd number of bytes, the data has to be padded. Duplicate
557 * the buffer and use the normal code path with a single block write since
558 * it's probably cheaper than to special case the last odd write using
559 * discrete accesses. */
560 if (count & 1) {
561 new_buffer = malloc(count + 1);
562 if (!new_buffer) {
563 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
564 return ERROR_FAIL;
565 }
566 LOG_INFO("odd number of bytes to write, padding with 0xff");
567 buffer = memcpy(new_buffer, buffer, count);
568 new_buffer[count++] = 0xff;
569 }
570
571 uint32_t words_remaining = count / 2;
572 int retval, retval2;
573
574 /* unlock flash registers */
575 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
576 if (retval != ERROR_OK)
577 goto cleanup;
578 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
579 if (retval != ERROR_OK)
580 goto cleanup;
581
582 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
583 if (retval != ERROR_OK)
584 goto cleanup;
585
586 /* try using a block write */
587 retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
588
589 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
590 /* if block write failed (no sufficient working area),
591 * we use normal (slow) single halfword accesses */
592 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
593
594 while (words_remaining > 0) {
595 uint16_t value;
596 memcpy(&value, buffer, sizeof(uint16_t));
597
598 retval = target_write_u16(target, bank->base + offset, value);
599 if (retval != ERROR_OK)
600 goto reset_pg_and_lock;
601
602 retval = stm32x_wait_status_busy(bank, 5);
603 if (retval != ERROR_OK)
604 goto reset_pg_and_lock;
605
606 words_remaining--;
607 buffer += 2;
608 offset += 2;
609 }
610 }
611
612 reset_pg_and_lock:
613 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
614 if (retval == ERROR_OK)
615 retval = retval2;
616
617 cleanup:
618 free(new_buffer);
619 return retval;
620 }
621
622 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
623 {
624 struct target *target = bank->target;
625 uint32_t device_id_register = 0;
626
627 if (!target_was_examined(target)) {
628 LOG_ERROR("Target not examined yet");
629 return ERROR_TARGET_NOT_EXAMINED;
630 }
631
632 switch (cortex_m_get_partno_safe(target)) {
633 case CORTEX_M0_PARTNO: /* STM32F0x devices */
634 device_id_register = 0x40015800;
635 break;
636 case CORTEX_M3_PARTNO: /* STM32F1x devices */
637 device_id_register = 0xE0042000;
638 break;
639 case CORTEX_M4_PARTNO: /* STM32F3x devices */
640 device_id_register = 0xE0042000;
641 break;
642 case CORTEX_M23_PARTNO: /* GD32E23x devices */
643 device_id_register = 0x40015800;
644 break;
645 default:
646 LOG_ERROR("Cannot identify target as a stm32x");
647 return ERROR_FAIL;
648 }
649
650 /* read stm32 device id register */
651 int retval = target_read_u32(target, device_id_register, device_id);
652 if (retval != ERROR_OK)
653 return retval;
654
655 return retval;
656 }
657
658 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
659 {
660 struct target *target = bank->target;
661 uint32_t flash_size_reg;
662
663 if (!target_was_examined(target)) {
664 LOG_ERROR("Target not examined yet");
665 return ERROR_TARGET_NOT_EXAMINED;
666 }
667
668 switch (cortex_m_get_partno_safe(target)) {
669 case CORTEX_M0_PARTNO: /* STM32F0x devices */
670 flash_size_reg = 0x1FFFF7CC;
671 break;
672 case CORTEX_M3_PARTNO: /* STM32F1x devices */
673 flash_size_reg = 0x1FFFF7E0;
674 break;
675 case CORTEX_M4_PARTNO: /* STM32F3x devices */
676 flash_size_reg = 0x1FFFF7CC;
677 break;
678 case CORTEX_M23_PARTNO: /* GD32E23x devices */
679 flash_size_reg = 0x1FFFF7E0;
680 break;
681 default:
682 LOG_ERROR("Cannot identify target as a stm32x");
683 return ERROR_FAIL;
684 }
685
686 int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
687 if (retval != ERROR_OK)
688 return retval;
689
690 return retval;
691 }
692
693 static int stm32x_probe(struct flash_bank *bank)
694 {
695 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
696 uint16_t flash_size_in_kb;
697 uint16_t max_flash_size_in_kb;
698 uint32_t dbgmcu_idcode;
699 int page_size;
700 uint32_t base_address = 0x08000000;
701
702 stm32x_info->probed = false;
703 stm32x_info->register_base = FLASH_REG_BASE_B0;
704 stm32x_info->user_data_offset = 10;
705 stm32x_info->option_offset = 0;
706
707 /* default factory read protection level 0 */
708 stm32x_info->default_rdp = 0xA5;
709
710 /* read stm32 device id register */
711 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
712 if (retval != ERROR_OK)
713 return retval;
714
715 LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
716
717 uint16_t device_id = dbgmcu_idcode & 0xfff;
718 uint16_t rev_id = dbgmcu_idcode >> 16;
719
720 /* set page size, protection granularity and max flash size depending on family */
721 switch (device_id) {
722 case 0x440: /* stm32f05x */
723 page_size = 1024;
724 stm32x_info->ppage_size = 4;
725 max_flash_size_in_kb = 64;
726 stm32x_info->user_data_offset = 16;
727 stm32x_info->option_offset = 6;
728 stm32x_info->default_rdp = 0xAA;
729 stm32x_info->can_load_options = true;
730 break;
731 case 0x444: /* stm32f03x */
732 case 0x445: /* stm32f04x */
733 page_size = 1024;
734 stm32x_info->ppage_size = 4;
735 max_flash_size_in_kb = 32;
736 stm32x_info->user_data_offset = 16;
737 stm32x_info->option_offset = 6;
738 stm32x_info->default_rdp = 0xAA;
739 stm32x_info->can_load_options = true;
740 break;
741 case 0x448: /* stm32f07x */
742 page_size = 2048;
743 stm32x_info->ppage_size = 4;
744 max_flash_size_in_kb = 128;
745 stm32x_info->user_data_offset = 16;
746 stm32x_info->option_offset = 6;
747 stm32x_info->default_rdp = 0xAA;
748 stm32x_info->can_load_options = true;
749 break;
750 case 0x442: /* stm32f09x */
751 page_size = 2048;
752 stm32x_info->ppage_size = 4;
753 max_flash_size_in_kb = 256;
754 stm32x_info->user_data_offset = 16;
755 stm32x_info->option_offset = 6;
756 stm32x_info->default_rdp = 0xAA;
757 stm32x_info->can_load_options = true;
758 break;
759 case 0x410: /* stm32f1x medium-density */
760 page_size = 1024;
761 stm32x_info->ppage_size = 4;
762 max_flash_size_in_kb = 128;
763 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
764 share DEV_ID with STM32F101/2/3 medium-density line,
765 however they use a REV_ID different from any STM32 device.
766 The main difference is another offset of user option bits
767 (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
768 (FLASH_OBR/FMC_OBSTAT 0x4002201C).
769 This caused problems e.g. during flash block programming
770 because of unexpected active hardware watchog. */
771 switch (rev_id) {
772 case 0x1303: /* gd32f1x0 */
773 stm32x_info->user_data_offset = 16;
774 stm32x_info->option_offset = 6;
775 max_flash_size_in_kb = 64;
776 break;
777 case 0x1704: /* gd32f3x0 */
778 stm32x_info->user_data_offset = 16;
779 stm32x_info->option_offset = 6;
780 break;
781 case 0x1909: /* gd32e23x */
782 stm32x_info->user_data_offset = 16;
783 stm32x_info->option_offset = 6;
784 max_flash_size_in_kb = 64;
785 break;
786 }
787 break;
788 case 0x412: /* stm32f1x low-density */
789 page_size = 1024;
790 stm32x_info->ppage_size = 4;
791 max_flash_size_in_kb = 32;
792 break;
793 case 0x414: /* stm32f1x high-density */
794 page_size = 2048;
795 stm32x_info->ppage_size = 2;
796 max_flash_size_in_kb = 512;
797 break;
798 case 0x418: /* stm32f1x connectivity */
799 page_size = 2048;
800 stm32x_info->ppage_size = 2;
801 max_flash_size_in_kb = 256;
802 break;
803 case 0x430: /* stm32f1 XL-density (dual flash banks) */
804 page_size = 2048;
805 stm32x_info->ppage_size = 2;
806 max_flash_size_in_kb = 1024;
807 stm32x_info->has_dual_banks = true;
808 break;
809 case 0x420: /* stm32f100xx low- and medium-density value line */
810 page_size = 1024;
811 stm32x_info->ppage_size = 4;
812 max_flash_size_in_kb = 128;
813 break;
814 case 0x428: /* stm32f100xx high-density value line */
815 page_size = 2048;
816 stm32x_info->ppage_size = 4;
817 max_flash_size_in_kb = 512;
818 break;
819 case 0x422: /* stm32f302/3xb/c */
820 page_size = 2048;
821 stm32x_info->ppage_size = 2;
822 max_flash_size_in_kb = 256;
823 stm32x_info->user_data_offset = 16;
824 stm32x_info->option_offset = 6;
825 stm32x_info->default_rdp = 0xAA;
826 stm32x_info->can_load_options = true;
827 break;
828 case 0x446: /* stm32f303xD/E */
829 page_size = 2048;
830 stm32x_info->ppage_size = 2;
831 max_flash_size_in_kb = 512;
832 stm32x_info->user_data_offset = 16;
833 stm32x_info->option_offset = 6;
834 stm32x_info->default_rdp = 0xAA;
835 stm32x_info->can_load_options = true;
836 break;
837 case 0x432: /* stm32f37x */
838 page_size = 2048;
839 stm32x_info->ppage_size = 2;
840 max_flash_size_in_kb = 256;
841 stm32x_info->user_data_offset = 16;
842 stm32x_info->option_offset = 6;
843 stm32x_info->default_rdp = 0xAA;
844 stm32x_info->can_load_options = true;
845 break;
846 case 0x438: /* stm32f33x */
847 case 0x439: /* stm32f302x6/8 */
848 page_size = 2048;
849 stm32x_info->ppage_size = 2;
850 max_flash_size_in_kb = 64;
851 stm32x_info->user_data_offset = 16;
852 stm32x_info->option_offset = 6;
853 stm32x_info->default_rdp = 0xAA;
854 stm32x_info->can_load_options = true;
855 break;
856 default:
857 LOG_WARNING("Cannot identify target as a STM32 family.");
858 return ERROR_FAIL;
859 }
860
861 /* get flash size from target. */
862 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
863
864 /* failed reading flash size or flash size invalid (early silicon),
865 * default to max target family */
866 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
867 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
868 max_flash_size_in_kb);
869 flash_size_in_kb = max_flash_size_in_kb;
870 }
871
872 if (stm32x_info->has_dual_banks) {
873 /* split reported size into matching bank */
874 if (bank->base != 0x08080000) {
875 /* bank 0 will be fixed 512k */
876 flash_size_in_kb = 512;
877 } else {
878 flash_size_in_kb -= 512;
879 /* bank1 also uses a register offset */
880 stm32x_info->register_base = FLASH_REG_BASE_B1;
881 base_address = 0x08080000;
882 }
883 }
884
885 /* if the user sets the size manually then ignore the probed value
886 * this allows us to work around devices that have a invalid flash size register value */
887 if (stm32x_info->user_bank_size) {
888 LOG_INFO("ignoring flash probed value, using configured bank size");
889 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
890 }
891
892 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
893
894 /* did we assign flash size? */
895 assert(flash_size_in_kb != 0xffff);
896
897 /* calculate numbers of pages */
898 int num_pages = flash_size_in_kb * 1024 / page_size;
899
900 /* check that calculation result makes sense */
901 assert(num_pages > 0);
902
903 free(bank->sectors);
904 bank->sectors = NULL;
905
906 free(bank->prot_blocks);
907 bank->prot_blocks = NULL;
908
909 bank->base = base_address;
910 bank->size = (num_pages * page_size);
911
912 bank->num_sectors = num_pages;
913 bank->sectors = alloc_block_array(0, page_size, num_pages);
914 if (!bank->sectors)
915 return ERROR_FAIL;
916
917 /* calculate number of write protection blocks */
918 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
919 if (num_prot_blocks > 32)
920 num_prot_blocks = 32;
921
922 bank->num_prot_blocks = num_prot_blocks;
923 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
924 if (!bank->prot_blocks)
925 return ERROR_FAIL;
926
927 if (num_prot_blocks == 32)
928 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
929
930 stm32x_info->probed = true;
931
932 return ERROR_OK;
933 }
934
935 static int stm32x_auto_probe(struct flash_bank *bank)
936 {
937 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
938 if (stm32x_info->probed)
939 return ERROR_OK;
940 return stm32x_probe(bank);
941 }
942
943 #if 0
944 COMMAND_HANDLER(stm32x_handle_part_id_command)
945 {
946 return ERROR_OK;
947 }
948 #endif
949
950 static const char *get_stm32f0_revision(uint16_t rev_id)
951 {
952 const char *rev_str = NULL;
953
954 switch (rev_id) {
955 case 0x1000:
956 rev_str = "1.0";
957 break;
958 case 0x2000:
959 rev_str = "2.0";
960 break;
961 }
962 return rev_str;
963 }
964
965 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
966 {
967 uint32_t dbgmcu_idcode;
968
969 /* read stm32 device id register */
970 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
971 if (retval != ERROR_OK)
972 return retval;
973
974 uint16_t device_id = dbgmcu_idcode & 0xfff;
975 uint16_t rev_id = dbgmcu_idcode >> 16;
976 const char *device_str;
977 const char *rev_str = NULL;
978
979 switch (device_id) {
980 case 0x410:
981 device_str = "STM32F10x (Medium Density)";
982
983 switch (rev_id) {
984 case 0x0000:
985 rev_str = "A";
986 break;
987
988 case 0x1303: /* gd32f1x0 */
989 device_str = "GD32F1x0";
990 break;
991
992 case 0x1704: /* gd32f3x0 */
993 device_str = "GD32F3x0";
994 break;
995
996 case 0x1909: /* gd32e23x */
997 device_str = "GD32E23x";
998 break;
999
1000 case 0x2000:
1001 rev_str = "B";
1002 break;
1003
1004 case 0x2001:
1005 rev_str = "Z";
1006 break;
1007
1008 case 0x2003:
1009 rev_str = "Y";
1010 break;
1011 }
1012 break;
1013
1014 case 0x412:
1015 device_str = "STM32F10x (Low Density)";
1016
1017 switch (rev_id) {
1018 case 0x1000:
1019 rev_str = "A";
1020 break;
1021 }
1022 break;
1023
1024 case 0x414:
1025 device_str = "STM32F10x (High Density)";
1026
1027 switch (rev_id) {
1028 case 0x1000:
1029 rev_str = "A";
1030 break;
1031
1032 case 0x1001:
1033 rev_str = "Z";
1034 break;
1035
1036 case 0x1003:
1037 rev_str = "Y";
1038 break;
1039 }
1040 break;
1041
1042 case 0x418:
1043 device_str = "STM32F10x (Connectivity)";
1044
1045 switch (rev_id) {
1046 case 0x1000:
1047 rev_str = "A";
1048 break;
1049
1050 case 0x1001:
1051 rev_str = "Z";
1052 break;
1053 }
1054 break;
1055
1056 case 0x420:
1057 device_str = "STM32F100 (Low/Medium Density)";
1058
1059 switch (rev_id) {
1060 case 0x1000:
1061 rev_str = "A";
1062 break;
1063
1064 case 0x1001:
1065 rev_str = "Z";
1066 break;
1067 }
1068 break;
1069
1070 case 0x422:
1071 device_str = "STM32F302xB/C";
1072
1073 switch (rev_id) {
1074 case 0x1000:
1075 rev_str = "A";
1076 break;
1077
1078 case 0x1001:
1079 rev_str = "Z";
1080 break;
1081
1082 case 0x1003:
1083 rev_str = "Y";
1084 break;
1085
1086 case 0x2000:
1087 rev_str = "B";
1088 break;
1089 }
1090 break;
1091
1092 case 0x428:
1093 device_str = "STM32F100 (High Density)";
1094
1095 switch (rev_id) {
1096 case 0x1000:
1097 rev_str = "A";
1098 break;
1099
1100 case 0x1001:
1101 rev_str = "Z";
1102 break;
1103 }
1104 break;
1105
1106 case 0x430:
1107 device_str = "STM32F10x (XL Density)";
1108
1109 switch (rev_id) {
1110 case 0x1000:
1111 rev_str = "A";
1112 break;
1113 }
1114 break;
1115
1116 case 0x432:
1117 device_str = "STM32F37x";
1118
1119 switch (rev_id) {
1120 case 0x1000:
1121 rev_str = "A";
1122 break;
1123
1124 case 0x2000:
1125 rev_str = "B";
1126 break;
1127 }
1128 break;
1129
1130 case 0x438:
1131 device_str = "STM32F33x";
1132
1133 switch (rev_id) {
1134 case 0x1000:
1135 rev_str = "A";
1136 break;
1137 }
1138 break;
1139
1140 case 0x439:
1141 device_str = "STM32F302x6/8";
1142
1143 switch (rev_id) {
1144 case 0x1000:
1145 rev_str = "A";
1146 break;
1147
1148 case 0x1001:
1149 rev_str = "Z";
1150 break;
1151 }
1152 break;
1153
1154 case 0x444:
1155 device_str = "STM32F03x";
1156 rev_str = get_stm32f0_revision(rev_id);
1157 break;
1158
1159 case 0x440:
1160 device_str = "STM32F05x";
1161 rev_str = get_stm32f0_revision(rev_id);
1162 break;
1163
1164 case 0x445:
1165 device_str = "STM32F04x";
1166 rev_str = get_stm32f0_revision(rev_id);
1167 break;
1168
1169 case 0x446:
1170 device_str = "STM32F303xD/E";
1171 switch (rev_id) {
1172 case 0x1000:
1173 rev_str = "A";
1174 break;
1175 }
1176 break;
1177
1178 case 0x448:
1179 device_str = "STM32F07x";
1180 rev_str = get_stm32f0_revision(rev_id);
1181 break;
1182
1183 case 0x442:
1184 device_str = "STM32F09x";
1185 rev_str = get_stm32f0_revision(rev_id);
1186 break;
1187
1188 default:
1189 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1190 return ERROR_FAIL;
1191 }
1192
1193 if (rev_str)
1194 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1195 else
1196 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1197
1198 return ERROR_OK;
1199 }
1200
1201 COMMAND_HANDLER(stm32x_handle_lock_command)
1202 {
1203 struct target *target = NULL;
1204 struct stm32x_flash_bank *stm32x_info = NULL;
1205
1206 if (CMD_ARGC < 1)
1207 return ERROR_COMMAND_SYNTAX_ERROR;
1208
1209 struct flash_bank *bank;
1210 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1211 if (retval != ERROR_OK)
1212 return retval;
1213
1214 stm32x_info = bank->driver_priv;
1215
1216 target = bank->target;
1217
1218 if (target->state != TARGET_HALTED) {
1219 LOG_ERROR("Target not halted");
1220 return ERROR_TARGET_NOT_HALTED;
1221 }
1222
1223 retval = stm32x_check_operation_supported(bank);
1224 if (retval != ERROR_OK)
1225 return retval;
1226
1227 if (stm32x_erase_options(bank) != ERROR_OK) {
1228 command_print(CMD, "stm32x failed to erase options");
1229 return ERROR_OK;
1230 }
1231
1232 /* set readout protection */
1233 stm32x_info->option_bytes.rdp = 0;
1234
1235 if (stm32x_write_options(bank) != ERROR_OK) {
1236 command_print(CMD, "stm32x failed to lock device");
1237 return ERROR_OK;
1238 }
1239
1240 command_print(CMD, "stm32x locked");
1241
1242 return ERROR_OK;
1243 }
1244
1245 COMMAND_HANDLER(stm32x_handle_unlock_command)
1246 {
1247 struct target *target = NULL;
1248
1249 if (CMD_ARGC < 1)
1250 return ERROR_COMMAND_SYNTAX_ERROR;
1251
1252 struct flash_bank *bank;
1253 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1254 if (retval != ERROR_OK)
1255 return retval;
1256
1257 target = bank->target;
1258
1259 if (target->state != TARGET_HALTED) {
1260 LOG_ERROR("Target not halted");
1261 return ERROR_TARGET_NOT_HALTED;
1262 }
1263
1264 retval = stm32x_check_operation_supported(bank);
1265 if (retval != ERROR_OK)
1266 return retval;
1267
1268 if (stm32x_erase_options(bank) != ERROR_OK) {
1269 command_print(CMD, "stm32x failed to erase options");
1270 return ERROR_OK;
1271 }
1272
1273 if (stm32x_write_options(bank) != ERROR_OK) {
1274 command_print(CMD, "stm32x failed to unlock device");
1275 return ERROR_OK;
1276 }
1277
1278 command_print(CMD, "stm32x unlocked.\n"
1279 "INFO: a reset or power cycle is required "
1280 "for the new settings to take effect.");
1281
1282 return ERROR_OK;
1283 }
1284
1285 COMMAND_HANDLER(stm32x_handle_options_read_command)
1286 {
1287 uint32_t optionbyte, protection;
1288 struct target *target = NULL;
1289 struct stm32x_flash_bank *stm32x_info = NULL;
1290
1291 if (CMD_ARGC < 1)
1292 return ERROR_COMMAND_SYNTAX_ERROR;
1293
1294 struct flash_bank *bank;
1295 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1296 if (retval != ERROR_OK)
1297 return retval;
1298
1299 stm32x_info = bank->driver_priv;
1300
1301 target = bank->target;
1302
1303 if (target->state != TARGET_HALTED) {
1304 LOG_ERROR("Target not halted");
1305 return ERROR_TARGET_NOT_HALTED;
1306 }
1307
1308 retval = stm32x_check_operation_supported(bank);
1309 if (retval != ERROR_OK)
1310 return retval;
1311
1312 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1313 if (retval != ERROR_OK)
1314 return retval;
1315
1316 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1317
1318 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1319 if (retval != ERROR_OK)
1320 return retval;
1321
1322 if (optionbyte & (1 << OPT_ERROR))
1323 command_print(CMD, "option byte complement error");
1324
1325 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1326 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1327
1328 command_print(CMD, "read protection: %s",
1329 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1330
1331 /* user option bytes are offset depending on variant */
1332 optionbyte >>= stm32x_info->option_offset;
1333
1334 command_print(CMD, "watchdog: %sware",
1335 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1336
1337 command_print(CMD, "stop mode: %sreset generated upon entry",
1338 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1339
1340 command_print(CMD, "standby mode: %sreset generated upon entry",
1341 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1342
1343 if (stm32x_info->has_dual_banks)
1344 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1345
1346 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1347
1348 return ERROR_OK;
1349 }
1350
1351 COMMAND_HANDLER(stm32x_handle_options_write_command)
1352 {
1353 struct target *target = NULL;
1354 struct stm32x_flash_bank *stm32x_info = NULL;
1355 uint8_t optionbyte;
1356 uint16_t useropt;
1357
1358 if (CMD_ARGC < 2)
1359 return ERROR_COMMAND_SYNTAX_ERROR;
1360
1361 struct flash_bank *bank;
1362 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1363 if (retval != ERROR_OK)
1364 return retval;
1365
1366 stm32x_info = bank->driver_priv;
1367
1368 target = bank->target;
1369
1370 if (target->state != TARGET_HALTED) {
1371 LOG_ERROR("Target not halted");
1372 return ERROR_TARGET_NOT_HALTED;
1373 }
1374
1375 retval = stm32x_check_operation_supported(bank);
1376 if (retval != ERROR_OK)
1377 return retval;
1378
1379 retval = stm32x_read_options(bank);
1380 if (retval != ERROR_OK)
1381 return retval;
1382
1383 /* start with current options */
1384 optionbyte = stm32x_info->option_bytes.user;
1385 useropt = stm32x_info->option_bytes.data;
1386
1387 /* skip over flash bank */
1388 CMD_ARGC--;
1389 CMD_ARGV++;
1390
1391 while (CMD_ARGC) {
1392 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1393 optionbyte |= (1 << 0);
1394 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1395 optionbyte &= ~(1 << 0);
1396 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1397 optionbyte |= (1 << 1);
1398 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1399 optionbyte &= ~(1 << 1);
1400 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1401 optionbyte |= (1 << 2);
1402 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1403 optionbyte &= ~(1 << 2);
1404 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1405 if (CMD_ARGC < 2)
1406 return ERROR_COMMAND_SYNTAX_ERROR;
1407 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1408 CMD_ARGC--;
1409 CMD_ARGV++;
1410 } else if (stm32x_info->has_dual_banks) {
1411 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1412 optionbyte |= (1 << 3);
1413 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1414 optionbyte &= ~(1 << 3);
1415 else
1416 return ERROR_COMMAND_SYNTAX_ERROR;
1417 } else
1418 return ERROR_COMMAND_SYNTAX_ERROR;
1419 CMD_ARGC--;
1420 CMD_ARGV++;
1421 }
1422
1423 if (stm32x_erase_options(bank) != ERROR_OK) {
1424 command_print(CMD, "stm32x failed to erase options");
1425 return ERROR_OK;
1426 }
1427
1428 stm32x_info->option_bytes.user = optionbyte;
1429 stm32x_info->option_bytes.data = useropt;
1430
1431 if (stm32x_write_options(bank) != ERROR_OK) {
1432 command_print(CMD, "stm32x failed to write options");
1433 return ERROR_OK;
1434 }
1435
1436 command_print(CMD, "stm32x write options complete.\n"
1437 "INFO: %spower cycle is required "
1438 "for the new settings to take effect.",
1439 stm32x_info->can_load_options
1440 ? "'stm32f1x options_load' command or " : "");
1441
1442 return ERROR_OK;
1443 }
1444
1445 COMMAND_HANDLER(stm32x_handle_options_load_command)
1446 {
1447 if (CMD_ARGC < 1)
1448 return ERROR_COMMAND_SYNTAX_ERROR;
1449
1450 struct flash_bank *bank;
1451 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1452 if (retval != ERROR_OK)
1453 return retval;
1454
1455 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1456
1457 if (!stm32x_info->can_load_options) {
1458 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1459 "required instead.");
1460 return ERROR_FAIL;
1461 }
1462
1463 struct target *target = bank->target;
1464
1465 if (target->state != TARGET_HALTED) {
1466 LOG_ERROR("Target not halted");
1467 return ERROR_TARGET_NOT_HALTED;
1468 }
1469
1470 retval = stm32x_check_operation_supported(bank);
1471 if (retval != ERROR_OK)
1472 return retval;
1473
1474 /* unlock option flash registers */
1475 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1476 if (retval != ERROR_OK)
1477 return retval;
1478 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1479 if (retval != ERROR_OK)
1480 return retval;
1481
1482 /* force re-load of option bytes - generates software reset */
1483 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1484 if (retval != ERROR_OK)
1485 return retval;
1486
1487 return ERROR_OK;
1488 }
1489
1490 static int stm32x_mass_erase(struct flash_bank *bank)
1491 {
1492 struct target *target = bank->target;
1493
1494 if (target->state != TARGET_HALTED) {
1495 LOG_ERROR("Target not halted");
1496 return ERROR_TARGET_NOT_HALTED;
1497 }
1498
1499 /* unlock option flash registers */
1500 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1501 if (retval != ERROR_OK)
1502 return retval;
1503 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1504 if (retval != ERROR_OK)
1505 return retval;
1506
1507 /* mass erase flash memory */
1508 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1509 if (retval != ERROR_OK)
1510 return retval;
1511 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1512 FLASH_MER | FLASH_STRT);
1513 if (retval != ERROR_OK)
1514 return retval;
1515
1516 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1517 if (retval != ERROR_OK)
1518 return retval;
1519
1520 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1521 if (retval != ERROR_OK)
1522 return retval;
1523
1524 return ERROR_OK;
1525 }
1526
1527 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1528 {
1529 if (CMD_ARGC < 1)
1530 return ERROR_COMMAND_SYNTAX_ERROR;
1531
1532 struct flash_bank *bank;
1533 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1534 if (retval != ERROR_OK)
1535 return retval;
1536
1537 retval = stm32x_mass_erase(bank);
1538 if (retval == ERROR_OK)
1539 command_print(CMD, "stm32x mass erase complete");
1540 else
1541 command_print(CMD, "stm32x mass erase failed");
1542
1543 return retval;
1544 }
1545
1546 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1547 {
1548 .name = "lock",
1549 .handler = stm32x_handle_lock_command,
1550 .mode = COMMAND_EXEC,
1551 .usage = "bank_id",
1552 .help = "Lock entire flash device.",
1553 },
1554 {
1555 .name = "unlock",
1556 .handler = stm32x_handle_unlock_command,
1557 .mode = COMMAND_EXEC,
1558 .usage = "bank_id",
1559 .help = "Unlock entire protected flash device.",
1560 },
1561 {
1562 .name = "mass_erase",
1563 .handler = stm32x_handle_mass_erase_command,
1564 .mode = COMMAND_EXEC,
1565 .usage = "bank_id",
1566 .help = "Erase entire flash device.",
1567 },
1568 {
1569 .name = "options_read",
1570 .handler = stm32x_handle_options_read_command,
1571 .mode = COMMAND_EXEC,
1572 .usage = "bank_id",
1573 .help = "Read and display device option bytes.",
1574 },
1575 {
1576 .name = "options_write",
1577 .handler = stm32x_handle_options_write_command,
1578 .mode = COMMAND_EXEC,
1579 .usage = "bank_id ('SWWDG'|'HWWDG') "
1580 "('RSTSTNDBY'|'NORSTSTNDBY') "
1581 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1582 .help = "Replace bits in device option bytes.",
1583 },
1584 {
1585 .name = "options_load",
1586 .handler = stm32x_handle_options_load_command,
1587 .mode = COMMAND_EXEC,
1588 .usage = "bank_id",
1589 .help = "Force re-load of device option bytes.",
1590 },
1591 COMMAND_REGISTRATION_DONE
1592 };
1593
1594 static const struct command_registration stm32f1x_command_handlers[] = {
1595 {
1596 .name = "stm32f1x",
1597 .mode = COMMAND_ANY,
1598 .help = "stm32f1x flash command group",
1599 .usage = "",
1600 .chain = stm32f1x_exec_command_handlers,
1601 },
1602 COMMAND_REGISTRATION_DONE
1603 };
1604
1605 const struct flash_driver stm32f1x_flash = {
1606 .name = "stm32f1x",
1607 .commands = stm32f1x_command_handlers,
1608 .flash_bank_command = stm32x_flash_bank_command,
1609 .erase = stm32x_erase,
1610 .protect = stm32x_protect,
1611 .write = stm32x_write,
1612 .read = default_flash_read,
1613 .probe = stm32x_probe,
1614 .auto_probe = stm32x_auto_probe,
1615 .erase_check = default_flash_blank_check,
1616 .protect_check = stm32x_protect_check,
1617 .info = get_stm32x_info,
1618 .free_driver_priv = default_flash_free_driver_priv,
1619 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)