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flash/nor/nrf5: fix protection setting on nRF51
[openocd.git] / src / flash / nor / nrf5.c
1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "imp.h"
26 #include <target/algorithm.h>
27 #include <target/armv7m.h>
28 #include <helper/types.h>
29 #include <helper/time_support.h>
30
31 /* Both those values are constant across the current spectrum ofr nRF5 devices */
32 #define WATCHDOG_REFRESH_REGISTER 0x40010600
33 #define WATCHDOG_REFRESH_VALUE 0x6e524635
34
35 enum {
36 NRF5_FLASH_BASE = 0x00000000,
37 };
38
39 enum nrf5_ficr_registers {
40 NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
41
42 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
43
44 NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
45 NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
46
47 NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028),
48 NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C),
49 NRF51_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
50 NRF51_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
51 NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
52 NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
53 NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
54
55 NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
56 NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
57 NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
58 NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
59 NRF5_FICR_ER1 = NRF5_FICR_REG(0x084),
60 NRF5_FICR_ER2 = NRF5_FICR_REG(0x088),
61 NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C),
62 NRF5_FICR_IR0 = NRF5_FICR_REG(0x090),
63 NRF5_FICR_IR1 = NRF5_FICR_REG(0x094),
64 NRF5_FICR_IR2 = NRF5_FICR_REG(0x098),
65 NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C),
66 NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
67 NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
68 NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
69
70 NRF51_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
71 NRF51_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
72 NRF51_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
73 NRF51_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
74 NRF51_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
75 NRF51_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
76 NRF51_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
77 NRF51_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
78 NRF51_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
79 NRF51_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
80 NRF51_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
81
82 /* Following registers are available on nRF52 and on nRF51 since rev 3 */
83 NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
84 NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104),
85 NRF5_FICR_INFO_PACKAGE = NRF5_FICR_REG(0x108),
86 NRF5_FICR_INFO_RAM = NRF5_FICR_REG(0x10C),
87 NRF5_FICR_INFO_FLASH = NRF5_FICR_REG(0x110),
88 };
89
90 enum nrf5_uicr_registers {
91 NRF5_UICR_BASE = 0x10001000, /* User Information
92 * Configuration Registers */
93
94 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
95
96 NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
97 NRF51_UICR_RBPCONF = NRF5_UICR_REG(0x004),
98 NRF51_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
99 NRF51_UICR_FWID = NRF5_UICR_REG(0x010),
100 };
101
102 enum nrf5_nvmc_registers {
103 NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
104 * Controller Registers */
105
106 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
107
108 NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
109 NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504),
110 NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
111 NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
112 NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
113
114 NRF5_BPROT_BASE = 0x40000000,
115 };
116
117 enum nrf5_nvmc_config_bits {
118 NRF5_NVMC_CONFIG_REN = 0x00,
119 NRF5_NVMC_CONFIG_WEN = 0x01,
120 NRF5_NVMC_CONFIG_EEN = 0x02,
121
122 };
123
124 struct nrf52_ficr_info {
125 uint32_t part;
126 uint32_t variant;
127 uint32_t package;
128 uint32_t ram;
129 uint32_t flash;
130 };
131
132 enum nrf5_features {
133 NRF5_FEATURE_SERIES_51 = 1 << 0,
134 NRF5_FEATURE_SERIES_52 = 1 << 1,
135 NRF5_FEATURE_BPROT = 1 << 2,
136 NRF5_FEATURE_ACL_PROT = 1 << 3,
137 };
138
139 struct nrf5_device_spec {
140 uint16_t hwid;
141 const char *part;
142 const char *variant;
143 const char *build_code;
144 unsigned int flash_size_kb;
145 enum nrf5_features features;
146 };
147
148 struct nrf5_info {
149 uint32_t refcount;
150
151 struct nrf5_bank {
152 struct nrf5_info *chip;
153 bool probed;
154 } bank[2];
155 struct target *target;
156
157 /* chip identification stored in nrf5_probe() for use in nrf5_info() */
158 bool ficr_info_valid;
159 struct nrf52_ficr_info ficr_info;
160 const struct nrf5_device_spec *spec;
161 uint32_t hwid;
162 enum nrf5_features features;
163 unsigned int flash_size_kb;
164 unsigned int ram_size_kb;
165 };
166
167 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
168 { \
169 .hwid = (id), \
170 .part = pt, \
171 .variant = var, \
172 .build_code = bcode, \
173 .flash_size_kb = (fsize), \
174 .features = NRF5_FEATURE_SERIES_51, \
175 }
176
177 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \
178 { \
179 .hwid = (id), \
180 .part = pt, \
181 .variant = var, \
182 .build_code = bcode, \
183 .flash_size_kb = (fsize), \
184 .features = features, \
185 }
186
187 /* The known devices table below is derived from the "nRF5x series
188 * compatibility matrix" documents, which can be found in the "DocLib" of
189 * nordic:
190 *
191 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview
192 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview
193 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview
194 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview
195 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview
196 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview
197 *
198 * Up to date with Matrix v2.0, plus some additional HWIDs.
199 *
200 * The additional HWIDs apply where the build code in the matrix is
201 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
202 * for x==0, x!=0 means different (unspecified) HWIDs.
203 */
204 static const struct nrf5_device_spec nrf5_known_devices_table[] = {
205 /* nRF51822 Devices (IC rev 1). */
206 NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
207 NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
208 NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
209 NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
210 NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
211
212 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
213 with built-in jlink seem to use engineering samples not listed
214 in the nRF51 Series Compatibility Matrix V1.0. */
215 NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
216
217 /* nRF51822 Devices (IC rev 2). */
218 NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
219 NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
220 NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
221 NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
222 NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
223 NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
224 NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
225 NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
226 NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
227
228 /* nRF51822 Devices (IC rev 3). */
229 NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
230 NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
231 NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
232 NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
233 NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
234 NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
235 NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
236 NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
237 NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
238
239 /* nRF51422 Devices (IC rev 1). */
240 NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
241 NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
242 NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
243
244 /* nRF51422 Devices (IC rev 2). */
245 NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
246 NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
247 NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
248 NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
249
250 /* nRF51422 Devices (IC rev 3). */
251 NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
252 NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
253 NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
254 NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
255 NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
256 NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
257 NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
258
259 /* The driver fully autodetects nRF52 series devices by FICR INFO,
260 * no need for nRF52xxx HWIDs in this table */
261 #if 0
262 /* nRF52810 Devices */
263 NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
264 NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
265
266 /* nRF52832 Devices */
267 NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
268 NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
269 NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
270
271 /* nRF52840 Devices */
272 NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_ACL_PROT),
273 #endif
274 };
275
276 struct nrf5_device_package {
277 uint32_t package;
278 const char *code;
279 };
280
281 /* Newer devices have FICR INFO.PACKAGE.
282 * This table converts its value to two character code */
283 static const struct nrf5_device_package nrf5_packages_table[] = {
284 { 0x2000, "QF" },
285 { 0x2001, "CH" },
286 { 0x2002, "CI" },
287 { 0x2005, "CK" },
288 };
289
290 const struct flash_driver nrf5_flash, nrf51_flash;
291
292 static int nrf5_bank_is_probed(struct flash_bank *bank)
293 {
294 struct nrf5_bank *nbank = bank->driver_priv;
295
296 assert(nbank != NULL);
297
298 return nbank->probed;
299 }
300 static int nrf5_probe(struct flash_bank *bank);
301
302 static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip)
303 {
304 if (bank->target->state != TARGET_HALTED) {
305 LOG_ERROR("Target not halted");
306 return ERROR_TARGET_NOT_HALTED;
307 }
308
309 struct nrf5_bank *nbank = bank->driver_priv;
310 *chip = nbank->chip;
311
312 int probed = nrf5_bank_is_probed(bank);
313 if (probed < 0)
314 return probed;
315 else if (!probed)
316 return nrf5_probe(bank);
317 else
318 return ERROR_OK;
319 }
320
321 static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
322 {
323 uint32_t ready;
324 int res;
325 int timeout_ms = 340;
326 int64_t ts_start = timeval_ms();
327
328 do {
329 res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
330 if (res != ERROR_OK) {
331 LOG_ERROR("Couldn't read NVMC_READY register");
332 return res;
333 }
334
335 if (ready == 0x00000001)
336 return ERROR_OK;
337
338 keep_alive();
339
340 } while ((timeval_ms()-ts_start) < timeout_ms);
341
342 LOG_DEBUG("Timed out waiting for NVMC_READY");
343 return ERROR_FLASH_BUSY;
344 }
345
346 static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
347 {
348 int res;
349 res = target_write_u32(chip->target,
350 NRF5_NVMC_CONFIG,
351 NRF5_NVMC_CONFIG_EEN);
352
353 if (res != ERROR_OK) {
354 LOG_ERROR("Failed to enable erase operation");
355 return res;
356 }
357
358 /*
359 According to NVMC examples in Nordic SDK busy status must be
360 checked after writing to NVMC_CONFIG
361 */
362 res = nrf5_wait_for_nvmc(chip);
363 if (res != ERROR_OK)
364 LOG_ERROR("Erase enable did not complete");
365
366 return res;
367 }
368
369 static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
370 {
371 int res;
372 res = target_write_u32(chip->target,
373 NRF5_NVMC_CONFIG,
374 NRF5_NVMC_CONFIG_WEN);
375
376 if (res != ERROR_OK) {
377 LOG_ERROR("Failed to enable write operation");
378 return res;
379 }
380
381 /*
382 According to NVMC examples in Nordic SDK busy status must be
383 checked after writing to NVMC_CONFIG
384 */
385 res = nrf5_wait_for_nvmc(chip);
386 if (res != ERROR_OK)
387 LOG_ERROR("Write enable did not complete");
388
389 return res;
390 }
391
392 static int nrf5_nvmc_read_only(struct nrf5_info *chip)
393 {
394 int res;
395 res = target_write_u32(chip->target,
396 NRF5_NVMC_CONFIG,
397 NRF5_NVMC_CONFIG_REN);
398
399 if (res != ERROR_OK) {
400 LOG_ERROR("Failed to enable read-only operation");
401 return res;
402 }
403 /*
404 According to NVMC examples in Nordic SDK busy status must be
405 checked after writing to NVMC_CONFIG
406 */
407 res = nrf5_wait_for_nvmc(chip);
408 if (res != ERROR_OK)
409 LOG_ERROR("Read only enable did not complete");
410
411 return res;
412 }
413
414 static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
415 uint32_t erase_register, uint32_t erase_value)
416 {
417 int res;
418
419 res = nrf5_nvmc_erase_enable(chip);
420 if (res != ERROR_OK)
421 goto error;
422
423 res = target_write_u32(chip->target,
424 erase_register,
425 erase_value);
426 if (res != ERROR_OK)
427 goto set_read_only;
428
429 res = nrf5_wait_for_nvmc(chip);
430 if (res != ERROR_OK)
431 goto set_read_only;
432
433 return nrf5_nvmc_read_only(chip);
434
435 set_read_only:
436 nrf5_nvmc_read_only(chip);
437 error:
438 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
439 erase_register, erase_value);
440 return ERROR_FAIL;
441 }
442
443 static int nrf5_protect_check_bprot(struct flash_bank *bank)
444 {
445 struct nrf5_bank *nbank = bank->driver_priv;
446 struct nrf5_info *chip = nbank->chip;
447
448 assert(chip != NULL);
449
450 static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
451 uint32_t bprot_reg = 0;
452 int res;
453
454 for (unsigned int i = 0; i < bank->num_sectors; i++) {
455 unsigned int bit = i % 32;
456 if (bit == 0) {
457 unsigned int n_reg = i / 32;
458 if (n_reg >= ARRAY_SIZE(nrf5_bprot_offsets))
459 break;
460
461 res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
462 if (res != ERROR_OK)
463 return res;
464 }
465 bank->sectors[i].is_protected = (bprot_reg & (1 << bit)) ? 1 : 0;
466 }
467 return ERROR_OK;
468 }
469
470 static int nrf5_protect_check(struct flash_bank *bank)
471 {
472 int res;
473 uint32_t clenr0;
474
475 /* UICR cannot be write protected so just return early */
476 if (bank->base == NRF5_UICR_BASE)
477 return ERROR_OK;
478
479 struct nrf5_bank *nbank = bank->driver_priv;
480 struct nrf5_info *chip = nbank->chip;
481
482 assert(chip != NULL);
483
484 if (chip->features & NRF5_FEATURE_BPROT)
485 return nrf5_protect_check_bprot(bank);
486
487 if (!(chip->features & NRF5_FEATURE_SERIES_51)) {
488 LOG_WARNING("Flash protection of this nRF device is not supported");
489 return ERROR_FLASH_OPER_UNSUPPORTED;
490 }
491
492 res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
493 &clenr0);
494 if (res != ERROR_OK) {
495 LOG_ERROR("Couldn't read code region 0 size[FICR]");
496 return res;
497 }
498
499 if (clenr0 == 0xFFFFFFFF) {
500 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
501 &clenr0);
502 if (res != ERROR_OK) {
503 LOG_ERROR("Couldn't read code region 0 size[UICR]");
504 return res;
505 }
506 }
507
508 for (unsigned int i = 0; i < bank->num_sectors; i++)
509 bank->sectors[i].is_protected =
510 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
511
512 return ERROR_OK;
513 }
514
515 static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int first,
516 unsigned int last)
517 {
518 int res;
519 uint32_t clenr0, ppfc;
520 struct nrf5_bank *nbank = bank->driver_priv;
521 struct nrf5_info *chip = nbank->chip;
522
523 if (first != 0) {
524 LOG_ERROR("Code region 0 must start at the beginning of the bank");
525 return ERROR_FAIL;
526 }
527
528 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
529 &ppfc);
530 if (res != ERROR_OK) {
531 LOG_ERROR("Couldn't read PPFC register");
532 return res;
533 }
534
535 if ((ppfc & 0xFF) == 0x00) {
536 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
537 return ERROR_FAIL;
538 }
539
540 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
541 &clenr0);
542 if (res != ERROR_OK) {
543 LOG_ERROR("Couldn't read code region 0 size from UICR");
544 return res;
545 }
546
547 if (!set || clenr0 != 0xFFFFFFFF) {
548 LOG_ERROR("You need to perform chip erase before changing the protection settings");
549 return ERROR_FAIL;
550 }
551
552 res = nrf5_nvmc_write_enable(chip);
553 if (res != ERROR_OK)
554 goto error;
555
556 clenr0 = bank->sectors[last].offset + bank->sectors[last].size;
557 res = target_write_u32(chip->target, NRF51_UICR_CLENR0, clenr0);
558
559 int res2 = nrf5_wait_for_nvmc(chip);
560
561 if (res == ERROR_OK)
562 res = res2;
563
564 if (res == ERROR_OK)
565 LOG_INFO("A reset or power cycle is required for the new protection settings to take effect.");
566 else
567 LOG_ERROR("Couldn't write code region 0 size to UICR");
568
569 error:
570 nrf5_nvmc_read_only(chip);
571
572 nrf5_protect_check(bank);
573
574 return res;
575 }
576
577 static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
578 unsigned int last)
579 {
580 int res;
581 struct nrf5_info *chip;
582
583 /* UICR cannot be write protected so just bail out early */
584 if (bank->base == NRF5_UICR_BASE) {
585 LOG_ERROR("UICR page does not support protection");
586 return ERROR_FLASH_OPER_UNSUPPORTED;
587 }
588
589 res = nrf5_get_probed_chip_if_halted(bank, &chip);
590 if (res != ERROR_OK)
591 return res;
592
593 if (chip->features & NRF5_FEATURE_SERIES_51)
594 return nrf5_protect_clenr0(bank, set, first, last);
595
596 LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
597 return ERROR_FLASH_OPER_UNSUPPORTED;
598 }
599
600 static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
601 {
602 uint8_t b[4];
603
604 h_u32_to_be(b, variant);
605 if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
606 memcpy(bf, b, 4);
607 bf[4] = 0;
608 return true;
609 }
610
611 strcpy(bf, "xxxx");
612 return false;
613 }
614
615 static const char *nrf5_decode_info_package(uint32_t package)
616 {
617 for (size_t i = 0; i < ARRAY_SIZE(nrf5_packages_table); i++) {
618 if (nrf5_packages_table[i].package == package)
619 return nrf5_packages_table[i].code;
620 }
621 return "xx";
622 }
623
624 static int nrf5_info(struct flash_bank *bank, char *buf, int buf_size)
625 {
626 struct nrf5_bank *nbank = bank->driver_priv;
627 struct nrf5_info *chip = nbank->chip;
628 int res;
629
630 if (chip->spec) {
631 res = snprintf(buf, buf_size,
632 "nRF%s-%s(build code: %s)",
633 chip->spec->part, chip->spec->variant, chip->spec->build_code);
634
635 } else if (chip->ficr_info_valid) {
636 char variant[5];
637 nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
638 res = snprintf(buf, buf_size,
639 "nRF%" PRIx32 "-%s%.2s(build code: %s)",
640 chip->ficr_info.part,
641 nrf5_decode_info_package(chip->ficr_info.package),
642 variant, &variant[2]);
643
644 } else {
645 res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%08" PRIx32 ")",
646 chip->hwid);
647 }
648 if (res <= 0)
649 return ERROR_FAIL;
650
651 snprintf(buf + res, buf_size - res, " %ukB Flash, %ukB RAM",
652 chip->flash_size_kb, chip->ram_size_kb);
653 return ERROR_OK;
654 }
655
656 static int nrf5_read_ficr_info(struct nrf5_info *chip)
657 {
658 int res;
659 struct target *target = chip->target;
660
661 chip->ficr_info_valid = false;
662
663 res = target_read_u32(target, NRF5_FICR_INFO_PART, &chip->ficr_info.part);
664 if (res != ERROR_OK) {
665 LOG_DEBUG("Couldn't read FICR INFO.PART register");
666 return res;
667 }
668
669 uint32_t series = chip->ficr_info.part & 0xfffff000;
670 switch (series) {
671 case 0x51000:
672 chip->features = NRF5_FEATURE_SERIES_51;
673 break;
674
675 case 0x52000:
676 chip->features = NRF5_FEATURE_SERIES_52;
677
678 switch (chip->ficr_info.part) {
679 case 0x52810:
680 case 0x52832:
681 chip->features |= NRF5_FEATURE_BPROT;
682 break;
683
684 case 0x52840:
685 chip->features |= NRF5_FEATURE_ACL_PROT;
686 break;
687 }
688 break;
689
690 default:
691 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
692 PRIx32, chip->ficr_info.part);
693 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
694 }
695
696 /* Now we know the device has FICR INFO filled by something relevant:
697 * Although it is not documented, the tested nRF51 rev 3 devices
698 * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
699 * VARIANT and PACKAGE coding is unknown for a nRF51 device.
700 * nRF52 devices have FICR INFO documented and always filled. */
701
702 res = target_read_u32(target, NRF5_FICR_INFO_VARIANT, &chip->ficr_info.variant);
703 if (res != ERROR_OK)
704 return res;
705
706 res = target_read_u32(target, NRF5_FICR_INFO_PACKAGE, &chip->ficr_info.package);
707 if (res != ERROR_OK)
708 return res;
709
710 res = target_read_u32(target, NRF5_FICR_INFO_RAM, &chip->ficr_info.ram);
711 if (res != ERROR_OK)
712 return res;
713
714 res = target_read_u32(target, NRF5_FICR_INFO_FLASH, &chip->ficr_info.flash);
715 if (res != ERROR_OK)
716 return res;
717
718 chip->ficr_info_valid = true;
719 return ERROR_OK;
720 }
721
722 static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
723 {
724 int res;
725
726 *ram_size = 0;
727
728 uint32_t numramblock;
729 res = target_read_u32(target, NRF51_FICR_NUMRAMBLOCK, &numramblock);
730 if (res != ERROR_OK) {
731 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
732 return res;
733 }
734
735 if (numramblock < 1 || numramblock > 4) {
736 LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
737 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
738 }
739
740 for (unsigned int i = 0; i < numramblock; i++) {
741 uint32_t sizeramblock;
742 res = target_read_u32(target, NRF51_FICR_SIZERAMBLOCK0 + sizeof(uint32_t)*i, &sizeramblock);
743 if (res != ERROR_OK) {
744 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
745 return res;
746 }
747 if (sizeramblock < 1024 || sizeramblock > 65536)
748 LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
749 else
750 *ram_size += sizeramblock;
751 }
752 return res;
753 }
754
755 static int nrf5_probe(struct flash_bank *bank)
756 {
757 int res;
758 struct nrf5_bank *nbank = bank->driver_priv;
759 struct nrf5_info *chip = nbank->chip;
760 struct target *target = chip->target;
761
762 res = target_read_u32(target, NRF5_FICR_CONFIGID, &chip->hwid);
763 if (res != ERROR_OK) {
764 LOG_ERROR("Couldn't read CONFIGID register");
765 return res;
766 }
767
768 chip->hwid &= 0xFFFF; /* HWID is stored in the lower two
769 * bytes of the CONFIGID register */
770
771 /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
772 chip->features = NRF5_FEATURE_SERIES_51;
773
774 /* Don't bail out on error for the case that some old engineering
775 * sample has FICR INFO registers unreadable. We can proceed anyway. */
776 (void)nrf5_read_ficr_info(chip);
777
778 chip->spec = NULL;
779 for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
780 if (chip->hwid == nrf5_known_devices_table[i].hwid) {
781 chip->spec = &nrf5_known_devices_table[i];
782 chip->features = chip->spec->features;
783 break;
784 }
785 }
786
787 if (chip->spec && chip->ficr_info_valid) {
788 /* check if HWID table gives the same part as FICR INFO */
789 if (chip->ficr_info.part != strtoul(chip->spec->part, NULL, 16))
790 LOG_WARNING("HWID 0x%04" PRIx32 " mismatch: FICR INFO.PART %"
791 PRIx32, chip->hwid, chip->ficr_info.part);
792 }
793
794 if (chip->ficr_info_valid) {
795 chip->ram_size_kb = chip->ficr_info.ram;
796 } else {
797 uint32_t ram_size;
798 nrf5_get_ram_size(target, &ram_size);
799 chip->ram_size_kb = ram_size / 1024;
800 }
801
802 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
803 uint32_t flash_page_size;
804 res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
805 &flash_page_size);
806 if (res != ERROR_OK) {
807 LOG_ERROR("Couldn't read code page size");
808 return res;
809 }
810
811 /* Note the register name is misleading,
812 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
813 uint32_t num_sectors;
814 res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
815 if (res != ERROR_OK) {
816 LOG_ERROR("Couldn't read code memory size");
817 return res;
818 }
819
820 chip->flash_size_kb = num_sectors * flash_page_size / 1024;
821
822 if (!chip->bank[0].probed && !chip->bank[1].probed) {
823 char buf[80];
824 nrf5_info(bank, buf, sizeof(buf));
825 if (!chip->spec && !chip->ficr_info_valid) {
826 LOG_INFO("Unknown device: %s", buf);
827 } else {
828 LOG_INFO("%s", buf);
829 }
830 }
831
832 free(bank->sectors);
833
834 if (bank->base == NRF5_FLASH_BASE) {
835 /* Sanity check */
836 if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
837 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
838 if (chip->ficr_info_valid && chip->flash_size_kb != chip->ficr_info.flash)
839 LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
840
841 bank->num_sectors = num_sectors;
842 bank->size = num_sectors * flash_page_size;
843
844 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
845 if (!bank->sectors)
846 return ERROR_FAIL;
847
848 nrf5_protect_check(bank);
849
850 chip->bank[0].probed = true;
851
852 } else {
853 bank->num_sectors = 1;
854 bank->size = flash_page_size;
855
856 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
857 if (!bank->sectors)
858 return ERROR_FAIL;
859
860 bank->sectors[0].is_protected = 0;
861
862 chip->bank[1].probed = true;
863 }
864
865 return ERROR_OK;
866 }
867
868 static int nrf5_auto_probe(struct flash_bank *bank)
869 {
870 int probed = nrf5_bank_is_probed(bank);
871
872 if (probed < 0)
873 return probed;
874 else if (probed)
875 return ERROR_OK;
876 else
877 return nrf5_probe(bank);
878 }
879
880 static int nrf5_erase_all(struct nrf5_info *chip)
881 {
882 LOG_DEBUG("Erasing all non-volatile memory");
883 return nrf5_nvmc_generic_erase(chip,
884 NRF5_NVMC_ERASEALL,
885 0x00000001);
886 }
887
888 static int nrf5_erase_page(struct flash_bank *bank,
889 struct nrf5_info *chip,
890 struct flash_sector *sector)
891 {
892 int res;
893
894 LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
895
896 if (bank->base == NRF5_UICR_BASE) {
897 if (chip->features & NRF5_FEATURE_SERIES_51) {
898 uint32_t ppfc;
899 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
900 &ppfc);
901 if (res != ERROR_OK) {
902 LOG_ERROR("Couldn't read PPFC register");
903 return res;
904 }
905
906 if ((ppfc & 0xFF) == 0xFF) {
907 /* We can't erase the UICR. Double-check to
908 see if it's already erased before complaining. */
909 default_flash_blank_check(bank);
910 if (sector->is_erased == 1)
911 return ERROR_OK;
912
913 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
914 return ERROR_FAIL;
915 }
916 }
917
918 res = nrf5_nvmc_generic_erase(chip,
919 NRF5_NVMC_ERASEUICR,
920 0x00000001);
921
922
923 } else {
924 res = nrf5_nvmc_generic_erase(chip,
925 NRF5_NVMC_ERASEPAGE,
926 sector->offset);
927 }
928
929 return res;
930 }
931
932 /* Start a low level flash write for the specified region */
933 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
934 {
935 struct target *target = chip->target;
936 uint32_t buffer_size = 8192;
937 struct working_area *write_algorithm;
938 struct working_area *source;
939 struct reg_param reg_params[6];
940 struct armv7m_algorithm armv7m_info;
941 int retval = ERROR_OK;
942
943 static const uint8_t nrf5_flash_write_code[] = {
944 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
945 };
946
947 LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
948 assert(bytes % 4 == 0);
949
950 /* allocate working area with flash programming code */
951 if (target_alloc_working_area(target, sizeof(nrf5_flash_write_code),
952 &write_algorithm) != ERROR_OK) {
953 LOG_WARNING("no working area available, falling back to slow memory writes");
954
955 for (; bytes > 0; bytes -= 4) {
956 retval = target_write_memory(target, address, 4, 1, buffer);
957 if (retval != ERROR_OK)
958 return retval;
959
960 retval = nrf5_wait_for_nvmc(chip);
961 if (retval != ERROR_OK)
962 return retval;
963
964 address += 4;
965 buffer += 4;
966 }
967
968 return ERROR_OK;
969 }
970
971 retval = target_write_buffer(target, write_algorithm->address,
972 sizeof(nrf5_flash_write_code),
973 nrf5_flash_write_code);
974 if (retval != ERROR_OK)
975 return retval;
976
977 /* memory buffer */
978 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
979 buffer_size /= 2;
980 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
981 if (buffer_size <= 256) {
982 /* free working area, write algorithm already allocated */
983 target_free_working_area(target, write_algorithm);
984
985 LOG_WARNING("No large enough working area available, can't do block memory writes");
986 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
987 }
988 }
989
990 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
991 armv7m_info.core_mode = ARM_MODE_THREAD;
992
993 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
994 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer start */
995 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer end */
996 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
997 init_reg_param(&reg_params[4], "r6", 32, PARAM_OUT); /* watchdog refresh value */
998 init_reg_param(&reg_params[5], "r7", 32, PARAM_OUT); /* watchdog refresh register address */
999
1000 buf_set_u32(reg_params[0].value, 0, 32, bytes);
1001 buf_set_u32(reg_params[1].value, 0, 32, source->address);
1002 buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
1003 buf_set_u32(reg_params[3].value, 0, 32, address);
1004 buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
1005 buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER);
1006
1007 retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
1008 0, NULL,
1009 ARRAY_SIZE(reg_params), reg_params,
1010 source->address, source->size,
1011 write_algorithm->address, 0,
1012 &armv7m_info);
1013
1014 target_free_working_area(target, source);
1015 target_free_working_area(target, write_algorithm);
1016
1017 destroy_reg_param(&reg_params[0]);
1018 destroy_reg_param(&reg_params[1]);
1019 destroy_reg_param(&reg_params[2]);
1020 destroy_reg_param(&reg_params[3]);
1021 destroy_reg_param(&reg_params[4]);
1022 destroy_reg_param(&reg_params[5]);
1023
1024 return retval;
1025 }
1026
1027 static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
1028 uint32_t offset, uint32_t count)
1029 {
1030 struct nrf5_info *chip;
1031
1032 int res = nrf5_get_probed_chip_if_halted(bank, &chip);
1033 if (res != ERROR_OK)
1034 return res;
1035
1036 assert(offset % 4 == 0);
1037 assert(count % 4 == 0);
1038
1039 res = nrf5_nvmc_write_enable(chip);
1040 if (res != ERROR_OK)
1041 goto error;
1042
1043 res = nrf5_ll_flash_write(chip, bank->base + offset, buffer, count);
1044 if (res != ERROR_OK)
1045 goto error;
1046
1047 return nrf5_nvmc_read_only(chip);
1048
1049 error:
1050 nrf5_nvmc_read_only(chip);
1051 LOG_ERROR("Failed to write to nrf5 flash");
1052 return res;
1053 }
1054
1055 static int nrf5_erase(struct flash_bank *bank, unsigned int first,
1056 unsigned int last)
1057 {
1058 int res;
1059 struct nrf5_info *chip;
1060
1061 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1062 if (res != ERROR_OK)
1063 return res;
1064
1065 /* For each sector to be erased */
1066 for (unsigned int s = first; s <= last && res == ERROR_OK; s++)
1067 res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
1068
1069 return res;
1070 }
1071
1072 static void nrf5_free_driver_priv(struct flash_bank *bank)
1073 {
1074 struct nrf5_bank *nbank = bank->driver_priv;
1075 struct nrf5_info *chip = nbank->chip;
1076 if (chip == NULL)
1077 return;
1078
1079 chip->refcount--;
1080 if (chip->refcount == 0) {
1081 free(chip);
1082 bank->driver_priv = NULL;
1083 }
1084 }
1085
1086 static struct nrf5_info *nrf5_get_chip(struct target *target)
1087 {
1088 struct flash_bank *bank_iter;
1089
1090 /* iterate over nrf5 banks of same target */
1091 for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
1092 if (bank_iter->driver != &nrf5_flash && bank_iter->driver != &nrf51_flash)
1093 continue;
1094
1095 if (bank_iter->target != target)
1096 continue;
1097
1098 struct nrf5_bank *nbank = bank_iter->driver_priv;
1099 if (!nbank)
1100 continue;
1101
1102 if (nbank->chip)
1103 return nbank->chip;
1104 }
1105 return NULL;
1106 }
1107
1108 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
1109 {
1110 struct nrf5_info *chip;
1111 struct nrf5_bank *nbank = NULL;
1112
1113 switch (bank->base) {
1114 case NRF5_FLASH_BASE:
1115 case NRF5_UICR_BASE:
1116 break;
1117 default:
1118 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
1119 return ERROR_FAIL;
1120 }
1121
1122 chip = nrf5_get_chip(bank->target);
1123 if (!chip) {
1124 /* Create a new chip */
1125 chip = calloc(1, sizeof(*chip));
1126 if (!chip)
1127 return ERROR_FAIL;
1128
1129 chip->target = bank->target;
1130 }
1131
1132 switch (bank->base) {
1133 case NRF5_FLASH_BASE:
1134 nbank = &chip->bank[0];
1135 break;
1136 case NRF5_UICR_BASE:
1137 nbank = &chip->bank[1];
1138 break;
1139 }
1140 assert(nbank != NULL);
1141
1142 chip->refcount++;
1143 nbank->chip = chip;
1144 nbank->probed = false;
1145 bank->driver_priv = nbank;
1146 bank->write_start_alignment = bank->write_end_alignment = 4;
1147
1148 return ERROR_OK;
1149 }
1150
1151 COMMAND_HANDLER(nrf5_handle_mass_erase_command)
1152 {
1153 int res;
1154 struct flash_bank *bank = NULL;
1155 struct target *target = get_current_target(CMD_CTX);
1156
1157 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1158 if (res != ERROR_OK)
1159 return res;
1160
1161 assert(bank != NULL);
1162
1163 struct nrf5_info *chip;
1164
1165 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1166 if (res != ERROR_OK)
1167 return res;
1168
1169 if (chip->features & NRF5_FEATURE_SERIES_51) {
1170 uint32_t ppfc;
1171 res = target_read_u32(target, NRF51_FICR_PPFC,
1172 &ppfc);
1173 if (res != ERROR_OK) {
1174 LOG_ERROR("Couldn't read PPFC register");
1175 return res;
1176 }
1177
1178 if ((ppfc & 0xFF) == 0x00) {
1179 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1180 "mass erase command won't work.");
1181 return ERROR_FAIL;
1182 }
1183 }
1184
1185 res = nrf5_erase_all(chip);
1186 if (res != ERROR_OK) {
1187 LOG_ERROR("Failed to erase the chip");
1188 nrf5_protect_check(bank);
1189 return res;
1190 }
1191
1192 res = nrf5_protect_check(bank);
1193 if (res != ERROR_OK) {
1194 LOG_ERROR("Failed to check chip's write protection");
1195 return res;
1196 }
1197
1198 res = get_flash_bank_by_addr(target, NRF5_UICR_BASE, true, &bank);
1199 if (res != ERROR_OK)
1200 return res;
1201
1202 return ERROR_OK;
1203 }
1204
1205 COMMAND_HANDLER(nrf5_handle_info_command)
1206 {
1207 int res;
1208 struct flash_bank *bank = NULL;
1209 struct target *target = get_current_target(CMD_CTX);
1210
1211 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1212 if (res != ERROR_OK)
1213 return res;
1214
1215 assert(bank != NULL);
1216
1217 struct nrf5_info *chip;
1218
1219 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1220 if (res != ERROR_OK)
1221 return res;
1222
1223 static struct {
1224 const uint32_t address;
1225 uint32_t value;
1226 } ficr[] = {
1227 { .address = NRF5_FICR_CODEPAGESIZE },
1228 { .address = NRF5_FICR_CODESIZE },
1229 { .address = NRF51_FICR_CLENR0 },
1230 { .address = NRF51_FICR_PPFC },
1231 { .address = NRF51_FICR_NUMRAMBLOCK },
1232 { .address = NRF51_FICR_SIZERAMBLOCK0 },
1233 { .address = NRF51_FICR_SIZERAMBLOCK1 },
1234 { .address = NRF51_FICR_SIZERAMBLOCK2 },
1235 { .address = NRF51_FICR_SIZERAMBLOCK3 },
1236 { .address = NRF5_FICR_CONFIGID },
1237 { .address = NRF5_FICR_DEVICEID0 },
1238 { .address = NRF5_FICR_DEVICEID1 },
1239 { .address = NRF5_FICR_ER0 },
1240 { .address = NRF5_FICR_ER1 },
1241 { .address = NRF5_FICR_ER2 },
1242 { .address = NRF5_FICR_ER3 },
1243 { .address = NRF5_FICR_IR0 },
1244 { .address = NRF5_FICR_IR1 },
1245 { .address = NRF5_FICR_IR2 },
1246 { .address = NRF5_FICR_IR3 },
1247 { .address = NRF5_FICR_DEVICEADDRTYPE },
1248 { .address = NRF5_FICR_DEVICEADDR0 },
1249 { .address = NRF5_FICR_DEVICEADDR1 },
1250 { .address = NRF51_FICR_OVERRIDEN },
1251 { .address = NRF51_FICR_NRF_1MBIT0 },
1252 { .address = NRF51_FICR_NRF_1MBIT1 },
1253 { .address = NRF51_FICR_NRF_1MBIT2 },
1254 { .address = NRF51_FICR_NRF_1MBIT3 },
1255 { .address = NRF51_FICR_NRF_1MBIT4 },
1256 { .address = NRF51_FICR_BLE_1MBIT0 },
1257 { .address = NRF51_FICR_BLE_1MBIT1 },
1258 { .address = NRF51_FICR_BLE_1MBIT2 },
1259 { .address = NRF51_FICR_BLE_1MBIT3 },
1260 { .address = NRF51_FICR_BLE_1MBIT4 },
1261 }, uicr[] = {
1262 { .address = NRF51_UICR_CLENR0, },
1263 { .address = NRF51_UICR_RBPCONF },
1264 { .address = NRF51_UICR_XTALFREQ },
1265 { .address = NRF51_UICR_FWID },
1266 };
1267
1268 for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1269 res = target_read_u32(chip->target, ficr[i].address,
1270 &ficr[i].value);
1271 if (res != ERROR_OK) {
1272 LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1273 return res;
1274 }
1275 }
1276
1277 for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1278 res = target_read_u32(chip->target, uicr[i].address,
1279 &uicr[i].value);
1280 if (res != ERROR_OK) {
1281 LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1282 return res;
1283 }
1284 }
1285
1286 command_print(CMD,
1287 "\n[factory information control block]\n\n"
1288 "code page size: %"PRIu32"B\n"
1289 "code memory size: %"PRIu32"kB\n"
1290 "code region 0 size: %"PRIu32"kB\n"
1291 "pre-programmed code: %s\n"
1292 "number of ram blocks: %"PRIu32"\n"
1293 "ram block 0 size: %"PRIu32"B\n"
1294 "ram block 1 size: %"PRIu32"B\n"
1295 "ram block 2 size: %"PRIu32"B\n"
1296 "ram block 3 size: %"PRIu32 "B\n"
1297 "config id: %" PRIx32 "\n"
1298 "device id: 0x%"PRIx32"%08"PRIx32"\n"
1299 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1300 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1301 "device address type: 0x%"PRIx32"\n"
1302 "device address: 0x%"PRIx32"%08"PRIx32"\n"
1303 "override enable: %"PRIx32"\n"
1304 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1305 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1306 "\n[user information control block]\n\n"
1307 "code region 0 size: %"PRIu32"kB\n"
1308 "read back protection configuration: %"PRIx32"\n"
1309 "reset value for XTALFREQ: %"PRIx32"\n"
1310 "firmware id: 0x%04"PRIx32,
1311 ficr[0].value,
1312 (ficr[1].value * ficr[0].value) / 1024,
1313 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1314 ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1315 ficr[4].value,
1316 ficr[5].value,
1317 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1318 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1319 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1320 ficr[9].value,
1321 ficr[10].value, ficr[11].value,
1322 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1323 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1324 ficr[20].value,
1325 ficr[21].value, ficr[22].value,
1326 ficr[23].value,
1327 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1328 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1329 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1330 uicr[1].value & 0xFFFF,
1331 uicr[2].value & 0xFF,
1332 uicr[3].value & 0xFFFF);
1333
1334 return ERROR_OK;
1335 }
1336
1337 static const struct command_registration nrf5_exec_command_handlers[] = {
1338 {
1339 .name = "mass_erase",
1340 .handler = nrf5_handle_mass_erase_command,
1341 .mode = COMMAND_EXEC,
1342 .help = "Erase all flash contents of the chip.",
1343 .usage = "",
1344 },
1345 {
1346 .name = "info",
1347 .handler = nrf5_handle_info_command,
1348 .mode = COMMAND_EXEC,
1349 .help = "Show FICR and UICR info.",
1350 .usage = "",
1351 },
1352 COMMAND_REGISTRATION_DONE
1353 };
1354
1355 static const struct command_registration nrf5_command_handlers[] = {
1356 {
1357 .name = "nrf5",
1358 .mode = COMMAND_ANY,
1359 .help = "nrf5 flash command group",
1360 .usage = "",
1361 .chain = nrf5_exec_command_handlers,
1362 },
1363 {
1364 .name = "nrf51",
1365 .mode = COMMAND_ANY,
1366 .help = "nrf51 flash command group",
1367 .usage = "",
1368 .chain = nrf5_exec_command_handlers,
1369 },
1370 COMMAND_REGISTRATION_DONE
1371 };
1372
1373 const struct flash_driver nrf5_flash = {
1374 .name = "nrf5",
1375 .commands = nrf5_command_handlers,
1376 .flash_bank_command = nrf5_flash_bank_command,
1377 .info = nrf5_info,
1378 .erase = nrf5_erase,
1379 .protect = nrf5_protect,
1380 .write = nrf5_write,
1381 .read = default_flash_read,
1382 .probe = nrf5_probe,
1383 .auto_probe = nrf5_auto_probe,
1384 .erase_check = default_flash_blank_check,
1385 .protect_check = nrf5_protect_check,
1386 .free_driver_priv = nrf5_free_driver_priv,
1387 };
1388
1389 /* We need to retain the flash-driver name as well as the commands
1390 * for backwards compatibility */
1391 const struct flash_driver nrf51_flash = {
1392 .name = "nrf51",
1393 .commands = nrf5_command_handlers,
1394 .flash_bank_command = nrf5_flash_bank_command,
1395 .info = nrf5_info,
1396 .erase = nrf5_erase,
1397 .protect = nrf5_protect,
1398 .write = nrf5_write,
1399 .read = default_flash_read,
1400 .probe = nrf5_probe,
1401 .auto_probe = nrf5_auto_probe,
1402 .erase_check = default_flash_blank_check,
1403 .protect_check = nrf5_protect_check,
1404 .free_driver_priv = nrf5_free_driver_priv,
1405 };
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