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flash/nor/nrf5: add missing package codes
[openocd.git] / src / flash / nor / nrf5.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2013 Synapse Product Development *
5 * Andrey Smirnov <andrew.smironv@gmail.com> *
6 * Angus Gratton <gus@projectgus.com> *
7 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
8 ***************************************************************************/
9
10 #ifdef HAVE_CONFIG_H
11 #include "config.h"
12 #endif
13
14 #include "imp.h"
15 #include <helper/binarybuffer.h>
16 #include <target/algorithm.h>
17 #include <target/armv7m.h>
18 #include <helper/types.h>
19 #include <helper/time_support.h>
20
21 /* Both those values are constant across the current spectrum ofr nRF5 devices */
22 #define WATCHDOG_REFRESH_REGISTER 0x40010600
23 #define WATCHDOG_REFRESH_VALUE 0x6e524635
24
25 enum {
26 NRF5_FLASH_BASE = 0x00000000,
27 };
28
29 enum nrf5_ficr_registers {
30 NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
31
32 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
33
34 NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
35 NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
36
37 NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028),
38 NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C),
39 NRF51_FICR_NUMRAMBLOCK = NRF5_FICR_REG(0x034),
40 NRF51_FICR_SIZERAMBLOCK0 = NRF5_FICR_REG(0x038),
41 NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
42 NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
43 NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
44
45 /* CONFIGID is documented on nRF51 series only.
46 * On nRF52 is present but not documented */
47 NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
48
49 NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
50 NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
51 NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
52 NRF5_FICR_ER1 = NRF5_FICR_REG(0x084),
53 NRF5_FICR_ER2 = NRF5_FICR_REG(0x088),
54 NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C),
55 NRF5_FICR_IR0 = NRF5_FICR_REG(0x090),
56 NRF5_FICR_IR1 = NRF5_FICR_REG(0x094),
57 NRF5_FICR_IR2 = NRF5_FICR_REG(0x098),
58 NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C),
59 NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
60 NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
61 NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
62
63 NRF51_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
64 NRF51_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
65 NRF51_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
66 NRF51_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
67 NRF51_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
68 NRF51_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
69 NRF51_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
70 NRF51_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
71 NRF51_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
72 NRF51_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
73 NRF51_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
74
75 /* Following registers are available on nRF52 and on nRF51 since rev 3 */
76 NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
77 NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104),
78 NRF5_FICR_INFO_PACKAGE = NRF5_FICR_REG(0x108),
79 NRF5_FICR_INFO_RAM = NRF5_FICR_REG(0x10C),
80 NRF5_FICR_INFO_FLASH = NRF5_FICR_REG(0x110),
81 };
82
83 enum nrf5_uicr_registers {
84 NRF5_UICR_BASE = 0x10001000, /* User Information
85 * Configuration Registers */
86
87 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
88
89 NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
90 NRF51_UICR_RBPCONF = NRF5_UICR_REG(0x004),
91 NRF51_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
92 NRF51_UICR_FWID = NRF5_UICR_REG(0x010),
93 };
94
95 enum nrf5_nvmc_registers {
96 NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
97 * Controller Registers */
98
99 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
100
101 NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
102 NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504),
103 NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
104 NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
105 NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
106
107 NRF5_BPROT_BASE = 0x40000000,
108 };
109
110 enum nrf5_nvmc_config_bits {
111 NRF5_NVMC_CONFIG_REN = 0x00,
112 NRF5_NVMC_CONFIG_WEN = 0x01,
113 NRF5_NVMC_CONFIG_EEN = 0x02,
114
115 };
116
117 struct nrf52_ficr_info {
118 uint32_t part;
119 uint32_t variant;
120 uint32_t package;
121 uint32_t ram;
122 uint32_t flash;
123 };
124
125 enum nrf5_features {
126 NRF5_FEATURE_SERIES_51 = 1 << 0,
127 NRF5_FEATURE_SERIES_52 = 1 << 1,
128 NRF5_FEATURE_BPROT = 1 << 2,
129 NRF5_FEATURE_ACL_PROT = 1 << 3,
130 };
131
132 struct nrf5_device_spec {
133 uint16_t hwid;
134 const char *part;
135 const char *variant;
136 const char *build_code;
137 unsigned int flash_size_kb;
138 enum nrf5_features features;
139 };
140
141 struct nrf5_info {
142 unsigned int refcount;
143
144 struct nrf5_bank {
145 struct nrf5_info *chip;
146 bool probed;
147 } bank[2];
148 struct target *target;
149
150 /* chip identification stored in nrf5_probe() for use in nrf5_info() */
151 bool ficr_info_valid;
152 struct nrf52_ficr_info ficr_info;
153 const struct nrf5_device_spec *spec;
154 uint16_t hwid;
155 enum nrf5_features features;
156 unsigned int flash_size_kb;
157 unsigned int ram_size_kb;
158 };
159
160 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
161 { \
162 .hwid = (id), \
163 .part = pt, \
164 .variant = var, \
165 .build_code = bcode, \
166 .flash_size_kb = (fsize), \
167 .features = NRF5_FEATURE_SERIES_51, \
168 }
169
170 /*
171 * The table maps known HWIDs to the part numbers, variant
172 * build code and some other info. For nRF51 rev 1 and 2 devices
173 * this is the only way how to get the part number and variant.
174 *
175 * All tested nRF51 rev 3 devices have FICR INFO fields
176 * but the fields are not documented in RM so we keep HWIDs in
177 * this table.
178 *
179 * nRF52 and newer devices have FICR INFO documented, the autodetection
180 * can rely on it and HWIDs table is not used.
181 *
182 * The known devices table below is derived from the "nRF5x series
183 * compatibility matrix" documents.
184 *
185 * Up to date with Matrix v2.0, plus some additional HWIDs.
186 *
187 * The additional HWIDs apply where the build code in the matrix is
188 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
189 * for x==0, x!=0 means different (unspecified) HWIDs.
190 */
191 static const struct nrf5_device_spec nrf5_known_devices_table[] = {
192 /* nRF51822 Devices (IC rev 1). */
193 NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
194 NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
195 NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
196 NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
197 NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
198
199 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
200 with built-in jlink seem to use engineering samples not listed
201 in the nRF51 Series Compatibility Matrix V1.0. */
202 NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
203
204 /* nRF51822 Devices (IC rev 2). */
205 NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
206 NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
207 NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
208 NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
209 NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
210 NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
211 NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
212 NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
213 NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
214
215 /* nRF51822 Devices (IC rev 3). */
216 NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
217 NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
218 NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
219 NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
220 NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
221 NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
222 NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
223 NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
224 NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
225
226 /* nRF51422 Devices (IC rev 1). */
227 NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
228 NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
229 NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
230
231 /* nRF51422 Devices (IC rev 2). */
232 NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
233 NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
234 NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
235 NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
236
237 /* nRF51422 Devices (IC rev 3). */
238 NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
239 NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
240 NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
241 NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
242 NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
243 NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
244 NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
245
246 /* The driver fully autodetects nRF52 series devices by FICR INFO,
247 * no need for nRF52xxx HWIDs in this table */
248 };
249
250 struct nrf5_device_package {
251 uint32_t package;
252 const char *code;
253 };
254
255 /* Newer devices have FICR INFO.PACKAGE.
256 * This table converts its value to two character code */
257 static const struct nrf5_device_package nrf52_packages_table[] = {
258 { 0x2000, "QF" },
259 { 0x2001, "CH" },
260 { 0x2002, "CI" },
261 { 0x2003, "QC" },
262 { 0x2004, "QI/CA" }, /* differs nRF52805, 810, 811: CA, nRF52833, 840: QI */
263 { 0x2005, "CK" },
264 { 0x2007, "QD" },
265 { 0x2008, "CJ" },
266 { 0x2009, "CF" },
267 };
268
269 const struct flash_driver nrf5_flash, nrf51_flash;
270
271 static bool nrf5_bank_is_probed(const struct flash_bank *bank)
272 {
273 struct nrf5_bank *nbank = bank->driver_priv;
274
275 assert(nbank);
276
277 return nbank->probed;
278 }
279 static int nrf5_probe(struct flash_bank *bank);
280
281 static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip)
282 {
283 if (bank->target->state != TARGET_HALTED) {
284 LOG_ERROR("Target not halted");
285 return ERROR_TARGET_NOT_HALTED;
286 }
287
288 struct nrf5_bank *nbank = bank->driver_priv;
289 *chip = nbank->chip;
290
291 if (nrf5_bank_is_probed(bank))
292 return ERROR_OK;
293
294 return nrf5_probe(bank);
295 }
296
297 static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
298 {
299 uint32_t ready;
300 int res;
301 int timeout_ms = 340;
302 int64_t ts_start = timeval_ms();
303
304 do {
305 res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
306 if (res != ERROR_OK) {
307 LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
308 return res;
309 }
310
311 if (ready == 0x00000001)
312 return ERROR_OK;
313
314 keep_alive();
315
316 } while ((timeval_ms()-ts_start) < timeout_ms);
317
318 LOG_DEBUG("Timed out waiting for NVMC_READY");
319 return ERROR_FLASH_BUSY;
320 }
321
322 static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
323 {
324 int res;
325 res = target_write_u32(chip->target,
326 NRF5_NVMC_CONFIG,
327 NRF5_NVMC_CONFIG_EEN);
328
329 if (res != ERROR_OK) {
330 LOG_ERROR("Failed to enable erase operation");
331 return res;
332 }
333
334 /*
335 According to NVMC examples in Nordic SDK busy status must be
336 checked after writing to NVMC_CONFIG
337 */
338 res = nrf5_wait_for_nvmc(chip);
339 if (res != ERROR_OK)
340 LOG_ERROR("Erase enable did not complete");
341
342 return res;
343 }
344
345 static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
346 {
347 int res;
348 res = target_write_u32(chip->target,
349 NRF5_NVMC_CONFIG,
350 NRF5_NVMC_CONFIG_WEN);
351
352 if (res != ERROR_OK) {
353 LOG_ERROR("Failed to enable write operation");
354 return res;
355 }
356
357 /*
358 According to NVMC examples in Nordic SDK busy status must be
359 checked after writing to NVMC_CONFIG
360 */
361 res = nrf5_wait_for_nvmc(chip);
362 if (res != ERROR_OK)
363 LOG_ERROR("Write enable did not complete");
364
365 return res;
366 }
367
368 static int nrf5_nvmc_read_only(struct nrf5_info *chip)
369 {
370 int res;
371 res = target_write_u32(chip->target,
372 NRF5_NVMC_CONFIG,
373 NRF5_NVMC_CONFIG_REN);
374
375 if (res != ERROR_OK) {
376 LOG_ERROR("Failed to enable read-only operation");
377 return res;
378 }
379 /*
380 According to NVMC examples in Nordic SDK busy status must be
381 checked after writing to NVMC_CONFIG
382 */
383 res = nrf5_wait_for_nvmc(chip);
384 if (res != ERROR_OK)
385 LOG_ERROR("Read only enable did not complete");
386
387 return res;
388 }
389
390 static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
391 uint32_t erase_register, uint32_t erase_value)
392 {
393 int res;
394
395 res = nrf5_nvmc_erase_enable(chip);
396 if (res != ERROR_OK)
397 goto error;
398
399 res = target_write_u32(chip->target,
400 erase_register,
401 erase_value);
402 if (res != ERROR_OK)
403 goto set_read_only;
404
405 res = nrf5_wait_for_nvmc(chip);
406 if (res != ERROR_OK)
407 goto set_read_only;
408
409 return nrf5_nvmc_read_only(chip);
410
411 set_read_only:
412 nrf5_nvmc_read_only(chip);
413 error:
414 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
415 erase_register, erase_value);
416 return ERROR_FAIL;
417 }
418
419 static int nrf5_protect_check_clenr0(struct flash_bank *bank)
420 {
421 int res;
422 uint32_t clenr0;
423 struct nrf5_bank *nbank = bank->driver_priv;
424 struct nrf5_info *chip = nbank->chip;
425
426 assert(chip);
427
428 res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
429 &clenr0);
430 if (res != ERROR_OK) {
431 LOG_ERROR("Couldn't read code region 0 size[FICR]");
432 return res;
433 }
434
435 if (clenr0 == 0xFFFFFFFF) {
436 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
437 &clenr0);
438 if (res != ERROR_OK) {
439 LOG_ERROR("Couldn't read code region 0 size[UICR]");
440 return res;
441 }
442 }
443
444 for (unsigned int i = 0; i < bank->num_sectors; i++)
445 bank->sectors[i].is_protected =
446 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
447
448 return ERROR_OK;
449 }
450
451 static int nrf5_protect_check_bprot(struct flash_bank *bank)
452 {
453 struct nrf5_bank *nbank = bank->driver_priv;
454 struct nrf5_info *chip = nbank->chip;
455
456 assert(chip);
457
458 static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
459 uint32_t bprot_reg = 0;
460 int res;
461
462 for (unsigned int i = 0; i < bank->num_sectors; i++) {
463 unsigned int bit = i % 32;
464 if (bit == 0) {
465 unsigned int n_reg = i / 32;
466 if (n_reg >= ARRAY_SIZE(nrf5_bprot_offsets))
467 break;
468
469 res = target_read_u32(chip->target, NRF5_BPROT_BASE + nrf5_bprot_offsets[n_reg], &bprot_reg);
470 if (res != ERROR_OK)
471 return res;
472 }
473 bank->sectors[i].is_protected = (bprot_reg & (1 << bit)) ? 1 : 0;
474 }
475 return ERROR_OK;
476 }
477
478 static int nrf5_protect_check(struct flash_bank *bank)
479 {
480 /* UICR cannot be write protected so just return early */
481 if (bank->base == NRF5_UICR_BASE)
482 return ERROR_OK;
483
484 struct nrf5_bank *nbank = bank->driver_priv;
485 struct nrf5_info *chip = nbank->chip;
486
487 assert(chip);
488
489 if (chip->features & NRF5_FEATURE_BPROT)
490 return nrf5_protect_check_bprot(bank);
491
492 if (chip->features & NRF5_FEATURE_SERIES_51)
493 return nrf5_protect_check_clenr0(bank);
494
495 LOG_WARNING("Flash protection of this nRF device is not supported");
496 return ERROR_FLASH_OPER_UNSUPPORTED;
497 }
498
499 static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int first,
500 unsigned int last)
501 {
502 int res;
503 uint32_t clenr0, ppfc;
504 struct nrf5_bank *nbank = bank->driver_priv;
505 struct nrf5_info *chip = nbank->chip;
506
507 if (first != 0) {
508 LOG_ERROR("Code region 0 must start at the beginning of the bank");
509 return ERROR_FAIL;
510 }
511
512 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
513 &ppfc);
514 if (res != ERROR_OK) {
515 LOG_ERROR("Couldn't read PPFC register");
516 return res;
517 }
518
519 if ((ppfc & 0xFF) == 0x00) {
520 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
521 return ERROR_FAIL;
522 }
523
524 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
525 &clenr0);
526 if (res != ERROR_OK) {
527 LOG_ERROR("Couldn't read code region 0 size from UICR");
528 return res;
529 }
530
531 if (!set || clenr0 != 0xFFFFFFFF) {
532 LOG_ERROR("You need to perform chip erase before changing the protection settings");
533 return ERROR_FAIL;
534 }
535
536 res = nrf5_nvmc_write_enable(chip);
537 if (res != ERROR_OK)
538 goto error;
539
540 clenr0 = bank->sectors[last].offset + bank->sectors[last].size;
541 res = target_write_u32(chip->target, NRF51_UICR_CLENR0, clenr0);
542
543 int res2 = nrf5_wait_for_nvmc(chip);
544
545 if (res == ERROR_OK)
546 res = res2;
547
548 if (res == ERROR_OK)
549 LOG_INFO("A reset or power cycle is required for the new protection settings to take effect.");
550 else
551 LOG_ERROR("Couldn't write code region 0 size to UICR");
552
553 error:
554 nrf5_nvmc_read_only(chip);
555
556 return res;
557 }
558
559 static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
560 unsigned int last)
561 {
562 int res;
563 struct nrf5_info *chip;
564
565 /* UICR cannot be write protected so just bail out early */
566 if (bank->base == NRF5_UICR_BASE) {
567 LOG_ERROR("UICR page does not support protection");
568 return ERROR_FLASH_OPER_UNSUPPORTED;
569 }
570
571 res = nrf5_get_probed_chip_if_halted(bank, &chip);
572 if (res != ERROR_OK)
573 return res;
574
575 if (chip->features & NRF5_FEATURE_SERIES_51)
576 return nrf5_protect_clenr0(bank, set, first, last);
577
578 LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
579 return ERROR_FLASH_OPER_UNSUPPORTED;
580 }
581
582 static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
583 {
584 uint8_t b[4];
585
586 h_u32_to_be(b, variant);
587 if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
588 memcpy(bf, b, 4);
589 bf[4] = 0;
590 return true;
591 }
592
593 strcpy(bf, "xxxx");
594 return false;
595 }
596
597 static const char *nrf5_decode_info_package(uint32_t package)
598 {
599 for (size_t i = 0; i < ARRAY_SIZE(nrf52_packages_table); i++) {
600 if (nrf52_packages_table[i].package == package)
601 return nrf52_packages_table[i].code;
602 }
603 return "xx";
604 }
605
606 static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
607 {
608 int res;
609 if (chip->spec) {
610 res = snprintf(buf, buf_size, "nRF%s-%s(build code: %s)",
611 chip->spec->part, chip->spec->variant, chip->spec->build_code);
612 } else if (chip->ficr_info_valid) {
613 char variant[5];
614 nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
615 res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s%.2s(build code: %s)",
616 chip->ficr_info.part,
617 nrf5_decode_info_package(chip->ficr_info.package),
618 variant, &variant[2]);
619 } else {
620 res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")", chip->hwid);
621 }
622
623 /* safety: */
624 if (res <= 0 || (unsigned int)res >= buf_size) {
625 LOG_ERROR("BUG: buffer problem in %s", __func__);
626 return ERROR_FAIL;
627 }
628 return ERROR_OK;
629 }
630
631 static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
632 {
633 struct nrf5_bank *nbank = bank->driver_priv;
634 struct nrf5_info *chip = nbank->chip;
635
636 char chip_type_str[256];
637 if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
638 return ERROR_FAIL;
639
640 command_print_sameline(cmd, "%s %ukB Flash, %ukB RAM",
641 chip_type_str, chip->flash_size_kb, chip->ram_size_kb);
642 return ERROR_OK;
643 }
644
645 static int nrf5_read_ficr_info(struct nrf5_info *chip)
646 {
647 int res;
648 struct target *target = chip->target;
649
650 chip->ficr_info_valid = false;
651
652 res = target_read_u32(target, NRF5_FICR_INFO_PART, &chip->ficr_info.part);
653 if (res != ERROR_OK) {
654 LOG_DEBUG("Couldn't read FICR INFO.PART register");
655 return res;
656 }
657
658 uint32_t series = chip->ficr_info.part & 0xfffff000;
659 switch (series) {
660 case 0x51000:
661 chip->features = NRF5_FEATURE_SERIES_51;
662 break;
663
664 case 0x52000:
665 chip->features = NRF5_FEATURE_SERIES_52;
666
667 switch (chip->ficr_info.part) {
668 case 0x52810:
669 case 0x52832:
670 chip->features |= NRF5_FEATURE_BPROT;
671 break;
672
673 case 0x52840:
674 chip->features |= NRF5_FEATURE_ACL_PROT;
675 break;
676 }
677 break;
678
679 default:
680 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
681 PRIx32, chip->ficr_info.part);
682 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
683 }
684
685 /* Now we know the device has FICR INFO filled by something relevant:
686 * Although it is not documented, the tested nRF51 rev 3 devices
687 * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
688 * VARIANT and PACKAGE coding is unknown for a nRF51 device.
689 * nRF52 devices have FICR INFO documented and always filled. */
690
691 res = target_read_u32(target, NRF5_FICR_INFO_VARIANT, &chip->ficr_info.variant);
692 if (res != ERROR_OK)
693 return res;
694
695 res = target_read_u32(target, NRF5_FICR_INFO_PACKAGE, &chip->ficr_info.package);
696 if (res != ERROR_OK)
697 return res;
698
699 res = target_read_u32(target, NRF5_FICR_INFO_RAM, &chip->ficr_info.ram);
700 if (res != ERROR_OK)
701 return res;
702
703 res = target_read_u32(target, NRF5_FICR_INFO_FLASH, &chip->ficr_info.flash);
704 if (res != ERROR_OK)
705 return res;
706
707 chip->ficr_info_valid = true;
708 return ERROR_OK;
709 }
710
711 static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
712 {
713 int res;
714
715 *ram_size = 0;
716
717 uint32_t numramblock;
718 res = target_read_u32(target, NRF51_FICR_NUMRAMBLOCK, &numramblock);
719 if (res != ERROR_OK) {
720 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
721 return res;
722 }
723
724 if (numramblock < 1 || numramblock > 4) {
725 LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32, numramblock);
726 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
727 }
728
729 for (unsigned int i = 0; i < numramblock; i++) {
730 uint32_t sizeramblock;
731 res = target_read_u32(target, NRF51_FICR_SIZERAMBLOCK0 + sizeof(uint32_t)*i, &sizeramblock);
732 if (res != ERROR_OK) {
733 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
734 return res;
735 }
736 if (sizeramblock < 1024 || sizeramblock > 65536)
737 LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32, sizeramblock);
738 else
739 *ram_size += sizeramblock;
740 }
741 return res;
742 }
743
744 static int nrf5_probe(struct flash_bank *bank)
745 {
746 int res;
747 struct nrf5_bank *nbank = bank->driver_priv;
748 struct nrf5_info *chip = nbank->chip;
749 struct target *target = chip->target;
750
751 uint32_t configid;
752 res = target_read_u32(target, NRF5_FICR_CONFIGID, &configid);
753 if (res != ERROR_OK) {
754 LOG_ERROR("Couldn't read CONFIGID register");
755 return res;
756 }
757
758 /* HWID is stored in the lower two bytes of the CONFIGID register */
759 chip->hwid = configid & 0xFFFF;
760
761 /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
762 chip->features = NRF5_FEATURE_SERIES_51;
763
764 /* Don't bail out on error for the case that some old engineering
765 * sample has FICR INFO registers unreadable. We can proceed anyway. */
766 (void)nrf5_read_ficr_info(chip);
767
768 chip->spec = NULL;
769 for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
770 if (chip->hwid == nrf5_known_devices_table[i].hwid) {
771 chip->spec = &nrf5_known_devices_table[i];
772 chip->features = chip->spec->features;
773 break;
774 }
775 }
776
777 if (chip->spec && chip->ficr_info_valid) {
778 /* check if HWID table gives the same part as FICR INFO */
779 if (chip->ficr_info.part != strtoul(chip->spec->part, NULL, 16))
780 LOG_WARNING("HWID 0x%04" PRIx32 " mismatch: FICR INFO.PART %"
781 PRIx32, chip->hwid, chip->ficr_info.part);
782 }
783
784 if (chip->ficr_info_valid) {
785 chip->ram_size_kb = chip->ficr_info.ram;
786 } else {
787 uint32_t ram_size;
788 nrf5_get_ram_size(target, &ram_size);
789 chip->ram_size_kb = ram_size / 1024;
790 }
791
792 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
793 uint32_t flash_page_size;
794 res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
795 &flash_page_size);
796 if (res != ERROR_OK) {
797 LOG_ERROR("Couldn't read code page size");
798 return res;
799 }
800
801 /* Note the register name is misleading,
802 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
803 uint32_t num_sectors;
804 res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
805 if (res != ERROR_OK) {
806 LOG_ERROR("Couldn't read code memory size");
807 return res;
808 }
809
810 chip->flash_size_kb = num_sectors * flash_page_size / 1024;
811
812 if (!chip->bank[0].probed && !chip->bank[1].probed) {
813 char chip_type_str[256];
814 if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
815 return ERROR_FAIL;
816 const bool device_is_unknown = (!chip->spec && !chip->ficr_info_valid);
817 LOG_INFO("%s%s %ukB Flash, %ukB RAM",
818 device_is_unknown ? "Unknown device: " : "",
819 chip_type_str,
820 chip->flash_size_kb,
821 chip->ram_size_kb);
822 }
823
824 free(bank->sectors);
825
826 if (bank->base == NRF5_FLASH_BASE) {
827 /* Sanity check */
828 if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
829 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
830 if (chip->ficr_info_valid && chip->flash_size_kb != chip->ficr_info.flash)
831 LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
832
833 bank->num_sectors = num_sectors;
834 bank->size = num_sectors * flash_page_size;
835
836 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
837 if (!bank->sectors)
838 return ERROR_FAIL;
839
840 chip->bank[0].probed = true;
841
842 } else {
843 bank->num_sectors = 1;
844 bank->size = flash_page_size;
845
846 bank->sectors = alloc_block_array(0, flash_page_size, num_sectors);
847 if (!bank->sectors)
848 return ERROR_FAIL;
849
850 bank->sectors[0].is_protected = 0;
851
852 chip->bank[1].probed = true;
853 }
854
855 return ERROR_OK;
856 }
857
858 static int nrf5_auto_probe(struct flash_bank *bank)
859 {
860 if (nrf5_bank_is_probed(bank))
861 return ERROR_OK;
862
863 return nrf5_probe(bank);
864 }
865
866 static int nrf5_erase_all(struct nrf5_info *chip)
867 {
868 LOG_DEBUG("Erasing all non-volatile memory");
869 return nrf5_nvmc_generic_erase(chip,
870 NRF5_NVMC_ERASEALL,
871 0x00000001);
872 }
873
874 static int nrf5_erase_page(struct flash_bank *bank,
875 struct nrf5_info *chip,
876 struct flash_sector *sector)
877 {
878 int res;
879
880 LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
881
882 if (bank->base == NRF5_UICR_BASE) {
883 if (chip->features & NRF5_FEATURE_SERIES_51) {
884 uint32_t ppfc;
885 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
886 &ppfc);
887 if (res != ERROR_OK) {
888 LOG_ERROR("Couldn't read PPFC register");
889 return res;
890 }
891
892 if ((ppfc & 0xFF) == 0xFF) {
893 /* We can't erase the UICR. Double-check to
894 see if it's already erased before complaining. */
895 default_flash_blank_check(bank);
896 if (sector->is_erased == 1)
897 return ERROR_OK;
898
899 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
900 return ERROR_FAIL;
901 }
902 }
903
904 res = nrf5_nvmc_generic_erase(chip,
905 NRF5_NVMC_ERASEUICR,
906 0x00000001);
907
908
909 } else {
910 res = nrf5_nvmc_generic_erase(chip,
911 NRF5_NVMC_ERASEPAGE,
912 sector->offset);
913 }
914
915 return res;
916 }
917
918 /* Start a low level flash write for the specified region */
919 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
920 {
921 struct target *target = chip->target;
922 uint32_t buffer_size = 8192;
923 struct working_area *write_algorithm;
924 struct working_area *source;
925 struct reg_param reg_params[6];
926 struct armv7m_algorithm armv7m_info;
927 int retval = ERROR_OK;
928
929 static const uint8_t nrf5_flash_write_code[] = {
930 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
931 };
932
933 LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
934 assert(bytes % 4 == 0);
935
936 /* allocate working area with flash programming code */
937 if (target_alloc_working_area(target, sizeof(nrf5_flash_write_code),
938 &write_algorithm) != ERROR_OK) {
939 LOG_WARNING("no working area available, falling back to slow memory writes");
940
941 for (; bytes > 0; bytes -= 4) {
942 retval = target_write_memory(target, address, 4, 1, buffer);
943 if (retval != ERROR_OK)
944 return retval;
945
946 retval = nrf5_wait_for_nvmc(chip);
947 if (retval != ERROR_OK)
948 return retval;
949
950 address += 4;
951 buffer += 4;
952 }
953
954 return ERROR_OK;
955 }
956
957 retval = target_write_buffer(target, write_algorithm->address,
958 sizeof(nrf5_flash_write_code),
959 nrf5_flash_write_code);
960 if (retval != ERROR_OK)
961 return retval;
962
963 /* memory buffer */
964 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
965 buffer_size /= 2;
966 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
967 if (buffer_size <= 256) {
968 /* free working area, write algorithm already allocated */
969 target_free_working_area(target, write_algorithm);
970
971 LOG_WARNING("No large enough working area available, can't do block memory writes");
972 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
973 }
974 }
975
976 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
977 armv7m_info.core_mode = ARM_MODE_THREAD;
978
979 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* byte count */
980 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer start */
981 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer end */
982 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT); /* target address */
983 init_reg_param(&reg_params[4], "r6", 32, PARAM_OUT); /* watchdog refresh value */
984 init_reg_param(&reg_params[5], "r7", 32, PARAM_OUT); /* watchdog refresh register address */
985
986 buf_set_u32(reg_params[0].value, 0, 32, bytes);
987 buf_set_u32(reg_params[1].value, 0, 32, source->address);
988 buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
989 buf_set_u32(reg_params[3].value, 0, 32, address);
990 buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
991 buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER);
992
993 retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
994 0, NULL,
995 ARRAY_SIZE(reg_params), reg_params,
996 source->address, source->size,
997 write_algorithm->address, write_algorithm->address + sizeof(nrf5_flash_write_code) - 2,
998 &armv7m_info);
999
1000 target_free_working_area(target, source);
1001 target_free_working_area(target, write_algorithm);
1002
1003 destroy_reg_param(&reg_params[0]);
1004 destroy_reg_param(&reg_params[1]);
1005 destroy_reg_param(&reg_params[2]);
1006 destroy_reg_param(&reg_params[3]);
1007 destroy_reg_param(&reg_params[4]);
1008 destroy_reg_param(&reg_params[5]);
1009
1010 return retval;
1011 }
1012
1013 static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
1014 uint32_t offset, uint32_t count)
1015 {
1016 struct nrf5_info *chip;
1017
1018 int res = nrf5_get_probed_chip_if_halted(bank, &chip);
1019 if (res != ERROR_OK)
1020 return res;
1021
1022 assert(offset % 4 == 0);
1023 assert(count % 4 == 0);
1024
1025 /* UICR CLENR0 based protection used on nRF51 is somewhat clumsy:
1026 * RM reads: Code running from code region 1 will not be able to write
1027 * to code region 0.
1028 * Unfortunately the flash loader running from RAM can write to both
1029 * code regions without any hint the protection is violated.
1030 *
1031 * Update protection state and check if any flash sector to be written
1032 * is protected. */
1033 if (chip->features & NRF5_FEATURE_SERIES_51) {
1034
1035 res = nrf5_protect_check_clenr0(bank);
1036 if (res != ERROR_OK)
1037 return res;
1038
1039 for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
1040 struct flash_sector *bs = &bank->sectors[sector];
1041
1042 /* Start offset in or before this sector? */
1043 /* End offset in or behind this sector? */
1044 if ((offset < (bs->offset + bs->size))
1045 && ((offset + count - 1) >= bs->offset)
1046 && bs->is_protected == 1) {
1047 LOG_ERROR("Write refused, sector %d is protected", sector);
1048 return ERROR_FLASH_PROTECTED;
1049 }
1050 }
1051 }
1052
1053 res = nrf5_nvmc_write_enable(chip);
1054 if (res != ERROR_OK)
1055 goto error;
1056
1057 res = nrf5_ll_flash_write(chip, bank->base + offset, buffer, count);
1058 if (res != ERROR_OK)
1059 goto error;
1060
1061 return nrf5_nvmc_read_only(chip);
1062
1063 error:
1064 nrf5_nvmc_read_only(chip);
1065 LOG_ERROR("Failed to write to nrf5 flash");
1066 return res;
1067 }
1068
1069 static int nrf5_erase(struct flash_bank *bank, unsigned int first,
1070 unsigned int last)
1071 {
1072 int res;
1073 struct nrf5_info *chip;
1074
1075 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1076 if (res != ERROR_OK)
1077 return res;
1078
1079 /* UICR CLENR0 based protection used on nRF51 prevents erase
1080 * absolutely silently. NVMC has no flag to indicate the protection
1081 * was violated.
1082 *
1083 * Update protection state and check if any flash sector to be erased
1084 * is protected. */
1085 if (chip->features & NRF5_FEATURE_SERIES_51) {
1086
1087 res = nrf5_protect_check_clenr0(bank);
1088 if (res != ERROR_OK)
1089 return res;
1090 }
1091
1092 /* For each sector to be erased */
1093 for (unsigned int s = first; s <= last && res == ERROR_OK; s++) {
1094
1095 if (chip->features & NRF5_FEATURE_SERIES_51
1096 && bank->sectors[s].is_protected == 1) {
1097 LOG_ERROR("Flash sector %d is protected", s);
1098 return ERROR_FLASH_PROTECTED;
1099 }
1100
1101 res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
1102 if (res != ERROR_OK) {
1103 LOG_ERROR("Error erasing sector %d", s);
1104 return res;
1105 }
1106 }
1107
1108 return ERROR_OK;
1109 }
1110
1111 static void nrf5_free_driver_priv(struct flash_bank *bank)
1112 {
1113 struct nrf5_bank *nbank = bank->driver_priv;
1114 struct nrf5_info *chip = nbank->chip;
1115 if (!chip)
1116 return;
1117
1118 chip->refcount--;
1119 if (chip->refcount == 0) {
1120 free(chip);
1121 bank->driver_priv = NULL;
1122 }
1123 }
1124
1125 static struct nrf5_info *nrf5_get_chip(struct target *target)
1126 {
1127 struct flash_bank *bank_iter;
1128
1129 /* iterate over nrf5 banks of same target */
1130 for (bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
1131 if (bank_iter->driver != &nrf5_flash && bank_iter->driver != &nrf51_flash)
1132 continue;
1133
1134 if (bank_iter->target != target)
1135 continue;
1136
1137 struct nrf5_bank *nbank = bank_iter->driver_priv;
1138 if (!nbank)
1139 continue;
1140
1141 if (nbank->chip)
1142 return nbank->chip;
1143 }
1144 return NULL;
1145 }
1146
1147 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
1148 {
1149 struct nrf5_info *chip;
1150 struct nrf5_bank *nbank = NULL;
1151
1152 if (bank->driver == &nrf51_flash)
1153 LOG_WARNING("Flash driver 'nrf51' is deprecated! Use 'nrf5' instead.");
1154
1155 switch (bank->base) {
1156 case NRF5_FLASH_BASE:
1157 case NRF5_UICR_BASE:
1158 break;
1159 default:
1160 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
1161 return ERROR_FAIL;
1162 }
1163
1164 chip = nrf5_get_chip(bank->target);
1165 if (!chip) {
1166 /* Create a new chip */
1167 chip = calloc(1, sizeof(*chip));
1168 if (!chip)
1169 return ERROR_FAIL;
1170
1171 chip->target = bank->target;
1172 }
1173
1174 switch (bank->base) {
1175 case NRF5_FLASH_BASE:
1176 nbank = &chip->bank[0];
1177 break;
1178 case NRF5_UICR_BASE:
1179 nbank = &chip->bank[1];
1180 break;
1181 }
1182 assert(nbank);
1183
1184 chip->refcount++;
1185 nbank->chip = chip;
1186 nbank->probed = false;
1187 bank->driver_priv = nbank;
1188 bank->write_start_alignment = bank->write_end_alignment = 4;
1189
1190 return ERROR_OK;
1191 }
1192
1193 COMMAND_HANDLER(nrf5_handle_mass_erase_command)
1194 {
1195 int res;
1196 struct flash_bank *bank = NULL;
1197 struct target *target = get_current_target(CMD_CTX);
1198
1199 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1200 if (res != ERROR_OK)
1201 return res;
1202
1203 assert(bank);
1204
1205 struct nrf5_info *chip;
1206
1207 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1208 if (res != ERROR_OK)
1209 return res;
1210
1211 if (chip->features & NRF5_FEATURE_SERIES_51) {
1212 uint32_t ppfc;
1213 res = target_read_u32(target, NRF51_FICR_PPFC,
1214 &ppfc);
1215 if (res != ERROR_OK) {
1216 LOG_ERROR("Couldn't read PPFC register");
1217 return res;
1218 }
1219
1220 if ((ppfc & 0xFF) == 0x00) {
1221 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1222 "mass erase command won't work.");
1223 return ERROR_FAIL;
1224 }
1225 }
1226
1227 res = nrf5_erase_all(chip);
1228 if (res == ERROR_OK) {
1229 LOG_INFO("Mass erase completed.");
1230 if (chip->features & NRF5_FEATURE_SERIES_51)
1231 LOG_INFO("A reset or power cycle is required if the flash was protected before.");
1232
1233 } else {
1234 LOG_ERROR("Failed to erase the chip");
1235 }
1236
1237 return res;
1238 }
1239
1240 COMMAND_HANDLER(nrf5_handle_info_command)
1241 {
1242 int res;
1243 struct flash_bank *bank = NULL;
1244 struct target *target = get_current_target(CMD_CTX);
1245
1246 res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1247 if (res != ERROR_OK)
1248 return res;
1249
1250 assert(bank);
1251
1252 struct nrf5_info *chip;
1253
1254 res = nrf5_get_probed_chip_if_halted(bank, &chip);
1255 if (res != ERROR_OK)
1256 return res;
1257
1258 static struct {
1259 const uint32_t address;
1260 uint32_t value;
1261 } ficr[] = {
1262 { .address = NRF5_FICR_CODEPAGESIZE },
1263 { .address = NRF5_FICR_CODESIZE },
1264 { .address = NRF51_FICR_CLENR0 },
1265 { .address = NRF51_FICR_PPFC },
1266 { .address = NRF51_FICR_NUMRAMBLOCK },
1267 { .address = NRF51_FICR_SIZERAMBLOCK0 },
1268 { .address = NRF51_FICR_SIZERAMBLOCK1 },
1269 { .address = NRF51_FICR_SIZERAMBLOCK2 },
1270 { .address = NRF51_FICR_SIZERAMBLOCK3 },
1271 { .address = NRF5_FICR_CONFIGID },
1272 { .address = NRF5_FICR_DEVICEID0 },
1273 { .address = NRF5_FICR_DEVICEID1 },
1274 { .address = NRF5_FICR_ER0 },
1275 { .address = NRF5_FICR_ER1 },
1276 { .address = NRF5_FICR_ER2 },
1277 { .address = NRF5_FICR_ER3 },
1278 { .address = NRF5_FICR_IR0 },
1279 { .address = NRF5_FICR_IR1 },
1280 { .address = NRF5_FICR_IR2 },
1281 { .address = NRF5_FICR_IR3 },
1282 { .address = NRF5_FICR_DEVICEADDRTYPE },
1283 { .address = NRF5_FICR_DEVICEADDR0 },
1284 { .address = NRF5_FICR_DEVICEADDR1 },
1285 { .address = NRF51_FICR_OVERRIDEN },
1286 { .address = NRF51_FICR_NRF_1MBIT0 },
1287 { .address = NRF51_FICR_NRF_1MBIT1 },
1288 { .address = NRF51_FICR_NRF_1MBIT2 },
1289 { .address = NRF51_FICR_NRF_1MBIT3 },
1290 { .address = NRF51_FICR_NRF_1MBIT4 },
1291 { .address = NRF51_FICR_BLE_1MBIT0 },
1292 { .address = NRF51_FICR_BLE_1MBIT1 },
1293 { .address = NRF51_FICR_BLE_1MBIT2 },
1294 { .address = NRF51_FICR_BLE_1MBIT3 },
1295 { .address = NRF51_FICR_BLE_1MBIT4 },
1296 }, uicr[] = {
1297 { .address = NRF51_UICR_CLENR0, },
1298 { .address = NRF51_UICR_RBPCONF },
1299 { .address = NRF51_UICR_XTALFREQ },
1300 { .address = NRF51_UICR_FWID },
1301 };
1302
1303 for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1304 res = target_read_u32(chip->target, ficr[i].address,
1305 &ficr[i].value);
1306 if (res != ERROR_OK) {
1307 LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1308 return res;
1309 }
1310 }
1311
1312 for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1313 res = target_read_u32(chip->target, uicr[i].address,
1314 &uicr[i].value);
1315 if (res != ERROR_OK) {
1316 LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1317 return res;
1318 }
1319 }
1320
1321 command_print(CMD,
1322 "\n[factory information control block]\n\n"
1323 "code page size: %"PRIu32"B\n"
1324 "code memory size: %"PRIu32"kB\n"
1325 "code region 0 size: %"PRIu32"kB\n"
1326 "pre-programmed code: %s\n"
1327 "number of ram blocks: %"PRIu32"\n"
1328 "ram block 0 size: %"PRIu32"B\n"
1329 "ram block 1 size: %"PRIu32"B\n"
1330 "ram block 2 size: %"PRIu32"B\n"
1331 "ram block 3 size: %"PRIu32 "B\n"
1332 "config id: %" PRIx32 "\n"
1333 "device id: 0x%"PRIx32"%08"PRIx32"\n"
1334 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1335 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1336 "device address type: 0x%"PRIx32"\n"
1337 "device address: 0x%"PRIx32"%08"PRIx32"\n"
1338 "override enable: %"PRIx32"\n"
1339 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1340 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1341 "\n[user information control block]\n\n"
1342 "code region 0 size: %"PRIu32"kB\n"
1343 "read back protection configuration: %"PRIx32"\n"
1344 "reset value for XTALFREQ: %"PRIx32"\n"
1345 "firmware id: 0x%04"PRIx32,
1346 ficr[0].value,
1347 (ficr[1].value * ficr[0].value) / 1024,
1348 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1349 ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1350 ficr[4].value,
1351 ficr[5].value,
1352 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1353 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1354 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1355 ficr[9].value,
1356 ficr[10].value, ficr[11].value,
1357 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1358 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1359 ficr[20].value,
1360 ficr[21].value, ficr[22].value,
1361 ficr[23].value,
1362 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1363 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1364 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1365 uicr[1].value & 0xFFFF,
1366 uicr[2].value & 0xFF,
1367 uicr[3].value & 0xFFFF);
1368
1369 return ERROR_OK;
1370 }
1371
1372 static const struct command_registration nrf5_exec_command_handlers[] = {
1373 {
1374 .name = "mass_erase",
1375 .handler = nrf5_handle_mass_erase_command,
1376 .mode = COMMAND_EXEC,
1377 .help = "Erase all flash contents of the chip.",
1378 .usage = "",
1379 },
1380 {
1381 .name = "info",
1382 .handler = nrf5_handle_info_command,
1383 .mode = COMMAND_EXEC,
1384 .help = "Show FICR and UICR info.",
1385 .usage = "",
1386 },
1387 COMMAND_REGISTRATION_DONE
1388 };
1389
1390 static const struct command_registration nrf5_command_handlers[] = {
1391 {
1392 .name = "nrf5",
1393 .mode = COMMAND_ANY,
1394 .help = "nrf5 flash command group",
1395 .usage = "",
1396 .chain = nrf5_exec_command_handlers,
1397 },
1398 {
1399 .name = "nrf51",
1400 .mode = COMMAND_ANY,
1401 .help = "nrf51 flash command group",
1402 .usage = "",
1403 .chain = nrf5_exec_command_handlers,
1404 },
1405 COMMAND_REGISTRATION_DONE
1406 };
1407
1408 const struct flash_driver nrf5_flash = {
1409 .name = "nrf5",
1410 .commands = nrf5_command_handlers,
1411 .flash_bank_command = nrf5_flash_bank_command,
1412 .info = nrf5_info,
1413 .erase = nrf5_erase,
1414 .protect = nrf5_protect,
1415 .write = nrf5_write,
1416 .read = default_flash_read,
1417 .probe = nrf5_probe,
1418 .auto_probe = nrf5_auto_probe,
1419 .erase_check = default_flash_blank_check,
1420 .protect_check = nrf5_protect_check,
1421 .free_driver_priv = nrf5_free_driver_priv,
1422 };
1423
1424 /* We need to retain the flash-driver name as well as the commands
1425 * for backwards compatibility */
1426 const struct flash_driver nrf51_flash = {
1427 .name = "nrf51",
1428 .commands = nrf5_command_handlers,
1429 .flash_bank_command = nrf5_flash_bank_command,
1430 .info = nrf5_info,
1431 .erase = nrf5_erase,
1432 .protect = nrf5_protect,
1433 .write = nrf5_write,
1434 .read = default_flash_read,
1435 .probe = nrf5_probe,
1436 .auto_probe = nrf5_auto_probe,
1437 .erase_check = default_flash_blank_check,
1438 .protect_check = nrf5_protect_check,
1439 .free_driver_priv = nrf5_free_driver_priv,
1440 };
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