1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2013 Synapse Product Development *
5 * Andrey Smirnov <andrew.smironv@gmail.com> *
6 * Angus Gratton <gus@projectgus.com> *
7 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
8 ***************************************************************************/
15 #include <helper/binarybuffer.h>
16 #include <target/algorithm.h>
17 #include <target/armv7m.h>
18 #include <helper/types.h>
19 #include <helper/time_support.h>
21 /* Both those values are constant across the current spectrum ofr nRF5 devices */
22 #define WATCHDOG_REFRESH_REGISTER 0x40010600
23 #define WATCHDOG_REFRESH_VALUE 0x6e524635
26 NRF5_FLASH_BASE
= 0x00000000,
29 enum nrf5_ficr_registers
{
30 NRF5_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
32 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
34 NRF5_FICR_CODEPAGESIZE
= NRF5_FICR_REG(0x010),
35 NRF5_FICR_CODESIZE
= NRF5_FICR_REG(0x014),
37 NRF51_FICR_CLENR0
= NRF5_FICR_REG(0x028),
38 NRF51_FICR_PPFC
= NRF5_FICR_REG(0x02C),
39 NRF51_FICR_NUMRAMBLOCK
= NRF5_FICR_REG(0x034),
40 NRF51_FICR_SIZERAMBLOCK0
= NRF5_FICR_REG(0x038),
41 NRF51_FICR_SIZERAMBLOCK1
= NRF5_FICR_REG(0x03C),
42 NRF51_FICR_SIZERAMBLOCK2
= NRF5_FICR_REG(0x040),
43 NRF51_FICR_SIZERAMBLOCK3
= NRF5_FICR_REG(0x044),
45 /* CONFIGID is documented on nRF51 series only.
46 * On nRF52 is present but not documented */
47 NRF5_FICR_CONFIGID
= NRF5_FICR_REG(0x05C),
49 /* Following registers are available on nRF52 and on nRF51 since rev 3 */
50 NRF5_FICR_INFO_PART
= NRF5_FICR_REG(0x100),
51 NRF5_FICR_INFO_VARIANT
= NRF5_FICR_REG(0x104),
52 NRF5_FICR_INFO_PACKAGE
= NRF5_FICR_REG(0x108),
53 NRF5_FICR_INFO_RAM
= NRF5_FICR_REG(0x10C),
54 NRF5_FICR_INFO_FLASH
= NRF5_FICR_REG(0x110),
57 enum nrf5_uicr_registers
{
58 NRF5_UICR_BASE
= 0x10001000, /* User Information
59 * Configuration Registers */
61 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
63 NRF51_UICR_CLENR0
= NRF5_UICR_REG(0x000),
66 enum nrf5_nvmc_registers
{
67 NRF5_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
68 * Controller Registers */
70 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
72 NRF5_NVMC_READY
= NRF5_NVMC_REG(0x400),
73 NRF5_NVMC_CONFIG
= NRF5_NVMC_REG(0x504),
74 NRF5_NVMC_ERASEPAGE
= NRF5_NVMC_REG(0x508),
75 NRF5_NVMC_ERASEALL
= NRF5_NVMC_REG(0x50C),
76 NRF5_NVMC_ERASEUICR
= NRF5_NVMC_REG(0x514),
78 NRF5_BPROT_BASE
= 0x40000000,
81 enum nrf5_nvmc_config_bits
{
82 NRF5_NVMC_CONFIG_REN
= 0x00,
83 NRF5_NVMC_CONFIG_WEN
= 0x01,
84 NRF5_NVMC_CONFIG_EEN
= 0x02,
88 struct nrf52_ficr_info
{
97 NRF5_FEATURE_SERIES_51
= 1 << 0,
98 NRF5_FEATURE_SERIES_52
= 1 << 1,
99 NRF5_FEATURE_BPROT
= 1 << 2,
100 NRF5_FEATURE_ACL_PROT
= 1 << 3,
103 struct nrf5_device_spec
{
107 const char *build_code
;
108 unsigned int flash_size_kb
;
109 enum nrf5_features features
;
113 unsigned int refcount
;
116 struct nrf5_info
*chip
;
119 struct target
*target
;
121 /* chip identification stored in nrf5_probe() for use in nrf5_info() */
122 bool ficr_info_valid
;
123 struct nrf52_ficr_info ficr_info
;
124 const struct nrf5_device_spec
*spec
;
126 enum nrf5_features features
;
127 unsigned int flash_size_kb
;
128 unsigned int ram_size_kb
;
131 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
136 .build_code = bcode, \
137 .flash_size_kb = (fsize), \
138 .features = NRF5_FEATURE_SERIES_51, \
142 * The table maps known HWIDs to the part numbers, variant
143 * build code and some other info. For nRF51 rev 1 and 2 devices
144 * this is the only way how to get the part number and variant.
146 * All tested nRF51 rev 3 devices have FICR INFO fields
147 * but the fields are not documented in RM so we keep HWIDs in
150 * nRF52 and newer devices have FICR INFO documented, the autodetection
151 * can rely on it and HWIDs table is not used.
153 * The known devices table below is derived from the "nRF5x series
154 * compatibility matrix" documents.
156 * Up to date with Matrix v2.0, plus some additional HWIDs.
158 * The additional HWIDs apply where the build code in the matrix is
159 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
160 * for x==0, x!=0 means different (unspecified) HWIDs.
162 static const struct nrf5_device_spec nrf5_known_devices_table
[] = {
163 /* nRF51822 Devices (IC rev 1). */
164 NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
165 NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
166 NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
167 NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
168 NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
170 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
171 with built-in jlink seem to use engineering samples not listed
172 in the nRF51 Series Compatibility Matrix V1.0. */
173 NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
175 /* nRF51822 Devices (IC rev 2). */
176 NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
177 NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
178 NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
179 NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
180 NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
181 NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
182 NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
183 NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
184 NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
186 /* nRF51822 Devices (IC rev 3). */
187 NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
188 NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
189 NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
190 NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
191 NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
192 NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
193 NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
194 NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
195 NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
197 /* nRF51422 Devices (IC rev 1). */
198 NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
199 NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
200 NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
202 /* nRF51422 Devices (IC rev 2). */
203 NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
204 NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
205 NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
206 NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
208 /* nRF51422 Devices (IC rev 3). */
209 NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
210 NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
211 NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
212 NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
213 NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
214 NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
215 NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
217 /* The driver fully autodetects nRF52 series devices by FICR INFO,
218 * no need for nRF52xxx HWIDs in this table */
221 struct nrf5_device_package
{
226 /* Newer devices have FICR INFO.PACKAGE.
227 * This table converts its value to two character code */
228 static const struct nrf5_device_package nrf52_packages_table
[] = {
233 { 0x2004, "QI/CA" }, /* differs nRF52805, 810, 811: CA, nRF52833, 840: QI */
240 const struct flash_driver nrf5_flash
, nrf51_flash
;
242 static bool nrf5_bank_is_probed(const struct flash_bank
*bank
)
244 struct nrf5_bank
*nbank
= bank
->driver_priv
;
247 return nbank
->probed
;
250 static int nrf5_wait_for_nvmc(struct nrf5_info
*chip
)
254 int timeout_ms
= 340;
255 int64_t ts_start
= timeval_ms();
258 res
= target_read_u32(chip
->target
, NRF5_NVMC_READY
, &ready
);
259 if (res
!= ERROR_OK
) {
260 LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
264 if (ready
== 0x00000001)
269 } while ((timeval_ms()-ts_start
) < timeout_ms
);
271 LOG_DEBUG("Timed out waiting for NVMC_READY");
272 return ERROR_FLASH_BUSY
;
275 static int nrf5_nvmc_erase_enable(struct nrf5_info
*chip
)
278 res
= target_write_u32(chip
->target
,
280 NRF5_NVMC_CONFIG_EEN
);
282 if (res
!= ERROR_OK
) {
283 LOG_ERROR("Failed to enable erase operation");
288 According to NVMC examples in Nordic SDK busy status must be
289 checked after writing to NVMC_CONFIG
291 res
= nrf5_wait_for_nvmc(chip
);
293 LOG_ERROR("Erase enable did not complete");
298 static int nrf5_nvmc_write_enable(struct nrf5_info
*chip
)
301 res
= target_write_u32(chip
->target
,
303 NRF5_NVMC_CONFIG_WEN
);
305 if (res
!= ERROR_OK
) {
306 LOG_ERROR("Failed to enable write operation");
311 According to NVMC examples in Nordic SDK busy status must be
312 checked after writing to NVMC_CONFIG
314 res
= nrf5_wait_for_nvmc(chip
);
316 LOG_ERROR("Write enable did not complete");
321 static int nrf5_nvmc_read_only(struct nrf5_info
*chip
)
324 res
= target_write_u32(chip
->target
,
326 NRF5_NVMC_CONFIG_REN
);
328 if (res
!= ERROR_OK
) {
329 LOG_ERROR("Failed to enable read-only operation");
333 According to NVMC examples in Nordic SDK busy status must be
334 checked after writing to NVMC_CONFIG
336 res
= nrf5_wait_for_nvmc(chip
);
338 LOG_ERROR("Read only enable did not complete");
343 static int nrf5_nvmc_generic_erase(struct nrf5_info
*chip
,
344 uint32_t erase_register
, uint32_t erase_value
)
348 res
= nrf5_nvmc_erase_enable(chip
);
352 res
= target_write_u32(chip
->target
,
358 res
= nrf5_wait_for_nvmc(chip
);
362 return nrf5_nvmc_read_only(chip
);
365 nrf5_nvmc_read_only(chip
);
367 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
368 erase_register
, erase_value
);
372 static int nrf5_protect_check_clenr0(struct flash_bank
*bank
)
377 struct nrf5_bank
*nbank
= bank
->driver_priv
;
379 struct nrf5_info
*chip
= nbank
->chip
;
382 res
= target_read_u32(chip
->target
, NRF51_FICR_CLENR0
,
384 if (res
!= ERROR_OK
) {
385 LOG_ERROR("Couldn't read code region 0 size[FICR]");
389 if (clenr0
== 0xFFFFFFFF) {
390 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
392 if (res
!= ERROR_OK
) {
393 LOG_ERROR("Couldn't read code region 0 size[UICR]");
398 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
399 bank
->sectors
[i
].is_protected
=
400 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
405 static int nrf5_protect_check_bprot(struct flash_bank
*bank
)
407 struct nrf5_bank
*nbank
= bank
->driver_priv
;
409 struct nrf5_info
*chip
= nbank
->chip
;
412 static uint32_t nrf5_bprot_offsets
[4] = { 0x600, 0x604, 0x610, 0x614 };
413 uint32_t bprot_reg
= 0;
416 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
417 unsigned int bit
= i
% 32;
419 unsigned int n_reg
= i
/ 32;
420 if (n_reg
>= ARRAY_SIZE(nrf5_bprot_offsets
))
423 res
= target_read_u32(chip
->target
, NRF5_BPROT_BASE
+ nrf5_bprot_offsets
[n_reg
], &bprot_reg
);
427 bank
->sectors
[i
].is_protected
= (bprot_reg
& (1 << bit
)) ? 1 : 0;
432 static int nrf5_protect_check(struct flash_bank
*bank
)
434 /* UICR cannot be write protected so just return early */
435 if (bank
->base
== NRF5_UICR_BASE
)
438 struct nrf5_bank
*nbank
= bank
->driver_priv
;
440 struct nrf5_info
*chip
= nbank
->chip
;
443 if (chip
->features
& NRF5_FEATURE_BPROT
)
444 return nrf5_protect_check_bprot(bank
);
446 if (chip
->features
& NRF5_FEATURE_SERIES_51
)
447 return nrf5_protect_check_clenr0(bank
);
449 LOG_WARNING("Flash protection of this nRF device is not supported");
450 return ERROR_FLASH_OPER_UNSUPPORTED
;
453 static int nrf5_protect_clenr0(struct flash_bank
*bank
, int set
, unsigned int first
,
457 uint32_t clenr0
, ppfc
;
459 struct nrf5_bank
*nbank
= bank
->driver_priv
;
461 struct nrf5_info
*chip
= nbank
->chip
;
465 LOG_ERROR("Code region 0 must start at the beginning of the bank");
469 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
471 if (res
!= ERROR_OK
) {
472 LOG_ERROR("Couldn't read PPFC register");
476 if ((ppfc
& 0xFF) == 0x00) {
477 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
481 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
483 if (res
!= ERROR_OK
) {
484 LOG_ERROR("Couldn't read code region 0 size from UICR");
488 if (!set
|| clenr0
!= 0xFFFFFFFF) {
489 LOG_ERROR("You need to perform chip erase before changing the protection settings");
493 res
= nrf5_nvmc_write_enable(chip
);
497 clenr0
= bank
->sectors
[last
].offset
+ bank
->sectors
[last
].size
;
498 res
= target_write_u32(chip
->target
, NRF51_UICR_CLENR0
, clenr0
);
500 int res2
= nrf5_wait_for_nvmc(chip
);
506 LOG_INFO("A reset or power cycle is required for the new protection settings to take effect.");
508 LOG_ERROR("Couldn't write code region 0 size to UICR");
511 nrf5_nvmc_read_only(chip
);
516 static int nrf5_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
519 /* UICR cannot be write protected so just bail out early */
520 if (bank
->base
== NRF5_UICR_BASE
) {
521 LOG_ERROR("UICR page does not support protection");
522 return ERROR_FLASH_OPER_UNSUPPORTED
;
525 if (bank
->target
->state
!= TARGET_HALTED
) {
526 LOG_ERROR("Target not halted");
527 return ERROR_TARGET_NOT_HALTED
;
530 struct nrf5_bank
*nbank
= bank
->driver_priv
;
532 struct nrf5_info
*chip
= nbank
->chip
;
535 if (chip
->features
& NRF5_FEATURE_SERIES_51
)
536 return nrf5_protect_clenr0(bank
, set
, first
, last
);
538 LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
539 return ERROR_FLASH_OPER_UNSUPPORTED
;
542 static bool nrf5_info_variant_to_str(uint32_t variant
, char *bf
)
546 h_u32_to_be(b
, variant
);
547 if (isalnum(b
[0]) && isalnum(b
[1]) && isalnum(b
[2]) && isalnum(b
[3])) {
557 static const char *nrf5_decode_info_package(uint32_t package
)
559 for (size_t i
= 0; i
< ARRAY_SIZE(nrf52_packages_table
); i
++) {
560 if (nrf52_packages_table
[i
].package
== package
)
561 return nrf52_packages_table
[i
].code
;
566 static int get_nrf5_chip_type_str(const struct nrf5_info
*chip
, char *buf
, unsigned int buf_size
)
570 res
= snprintf(buf
, buf_size
, "nRF%s-%s(build code: %s)",
571 chip
->spec
->part
, chip
->spec
->variant
, chip
->spec
->build_code
);
572 } else if (chip
->ficr_info_valid
) {
574 nrf5_info_variant_to_str(chip
->ficr_info
.variant
, variant
);
575 res
= snprintf(buf
, buf_size
, "nRF%" PRIx32
"-%s%.2s(build code: %s)",
576 chip
->ficr_info
.part
,
577 nrf5_decode_info_package(chip
->ficr_info
.package
),
578 variant
, &variant
[2]);
580 res
= snprintf(buf
, buf_size
, "nRF51xxx (HWID 0x%04" PRIx16
")", chip
->hwid
);
584 if (res
<= 0 || (unsigned int)res
>= buf_size
) {
585 LOG_ERROR("BUG: buffer problem in %s", __func__
);
591 static int nrf5_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
593 struct nrf5_bank
*nbank
= bank
->driver_priv
;
595 struct nrf5_info
*chip
= nbank
->chip
;
598 char chip_type_str
[256];
599 if (get_nrf5_chip_type_str(chip
, chip_type_str
, sizeof(chip_type_str
)) != ERROR_OK
)
602 command_print_sameline(cmd
, "%s %ukB Flash, %ukB RAM",
603 chip_type_str
, chip
->flash_size_kb
, chip
->ram_size_kb
);
607 static int nrf5_read_ficr_info(struct nrf5_info
*chip
)
610 struct target
*target
= chip
->target
;
612 chip
->ficr_info_valid
= false;
614 res
= target_read_u32(target
, NRF5_FICR_INFO_PART
, &chip
->ficr_info
.part
);
615 if (res
!= ERROR_OK
) {
616 LOG_DEBUG("Couldn't read FICR INFO.PART register");
620 uint32_t series
= chip
->ficr_info
.part
& 0xfffff000;
623 chip
->features
= NRF5_FEATURE_SERIES_51
;
627 chip
->features
= NRF5_FEATURE_SERIES_52
;
629 switch (chip
->ficr_info
.part
) {
634 chip
->features
|= NRF5_FEATURE_BPROT
;
640 chip
->features
|= NRF5_FEATURE_ACL_PROT
;
646 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
647 PRIx32
, chip
->ficr_info
.part
);
648 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
651 /* Now we know the device has FICR INFO filled by something relevant:
652 * Although it is not documented, the tested nRF51 rev 3 devices
653 * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
654 * VARIANT and PACKAGE coding is unknown for a nRF51 device.
655 * nRF52 devices have FICR INFO documented and always filled. */
657 res
= target_read_u32(target
, NRF5_FICR_INFO_VARIANT
, &chip
->ficr_info
.variant
);
661 res
= target_read_u32(target
, NRF5_FICR_INFO_PACKAGE
, &chip
->ficr_info
.package
);
665 res
= target_read_u32(target
, NRF5_FICR_INFO_RAM
, &chip
->ficr_info
.ram
);
669 res
= target_read_u32(target
, NRF5_FICR_INFO_FLASH
, &chip
->ficr_info
.flash
);
673 chip
->ficr_info_valid
= true;
677 static int nrf5_get_ram_size(struct target
*target
, uint32_t *ram_size
)
683 uint32_t numramblock
;
684 res
= target_read_u32(target
, NRF51_FICR_NUMRAMBLOCK
, &numramblock
);
685 if (res
!= ERROR_OK
) {
686 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
690 if (numramblock
< 1 || numramblock
> 4) {
691 LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32
, numramblock
);
692 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
695 for (unsigned int i
= 0; i
< numramblock
; i
++) {
696 uint32_t sizeramblock
;
697 res
= target_read_u32(target
, NRF51_FICR_SIZERAMBLOCK0
+ sizeof(uint32_t)*i
, &sizeramblock
);
698 if (res
!= ERROR_OK
) {
699 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
702 if (sizeramblock
< 1024 || sizeramblock
> 65536)
703 LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32
, sizeramblock
);
705 *ram_size
+= sizeramblock
;
710 static int nrf5_probe(struct flash_bank
*bank
)
714 struct nrf5_bank
*nbank
= bank
->driver_priv
;
716 struct nrf5_info
*chip
= nbank
->chip
;
718 struct target
*target
= chip
->target
;
721 res
= target_read_u32(target
, NRF5_FICR_CONFIGID
, &configid
);
722 if (res
!= ERROR_OK
) {
723 LOG_ERROR("Couldn't read CONFIGID register");
727 /* HWID is stored in the lower two bytes of the CONFIGID register */
728 chip
->hwid
= configid
& 0xFFFF;
730 /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
731 chip
->features
= NRF5_FEATURE_SERIES_51
;
733 /* Don't bail out on error for the case that some old engineering
734 * sample has FICR INFO registers unreadable. We can proceed anyway. */
735 (void)nrf5_read_ficr_info(chip
);
738 for (size_t i
= 0; i
< ARRAY_SIZE(nrf5_known_devices_table
); i
++) {
739 if (chip
->hwid
== nrf5_known_devices_table
[i
].hwid
) {
740 chip
->spec
= &nrf5_known_devices_table
[i
];
741 chip
->features
= chip
->spec
->features
;
746 if (chip
->spec
&& chip
->ficr_info_valid
) {
747 /* check if HWID table gives the same part as FICR INFO */
748 if (chip
->ficr_info
.part
!= strtoul(chip
->spec
->part
, NULL
, 16))
749 LOG_WARNING("HWID 0x%04" PRIx32
" mismatch: FICR INFO.PART %"
750 PRIx32
, chip
->hwid
, chip
->ficr_info
.part
);
753 if (chip
->ficr_info_valid
) {
754 chip
->ram_size_kb
= chip
->ficr_info
.ram
;
757 nrf5_get_ram_size(target
, &ram_size
);
758 chip
->ram_size_kb
= ram_size
/ 1024;
761 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
762 uint32_t flash_page_size
;
763 res
= target_read_u32(chip
->target
, NRF5_FICR_CODEPAGESIZE
,
765 if (res
!= ERROR_OK
) {
766 LOG_ERROR("Couldn't read code page size");
770 /* Note the register name is misleading,
771 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
772 uint32_t num_sectors
;
773 res
= target_read_u32(chip
->target
, NRF5_FICR_CODESIZE
, &num_sectors
);
774 if (res
!= ERROR_OK
) {
775 LOG_ERROR("Couldn't read code memory size");
779 chip
->flash_size_kb
= num_sectors
* flash_page_size
/ 1024;
781 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
782 char chip_type_str
[256];
783 if (get_nrf5_chip_type_str(chip
, chip_type_str
, sizeof(chip_type_str
)) != ERROR_OK
)
785 const bool device_is_unknown
= (!chip
->spec
&& !chip
->ficr_info_valid
);
786 LOG_INFO("%s%s %ukB Flash, %ukB RAM",
787 device_is_unknown
? "Unknown device: " : "",
795 if (bank
->base
== NRF5_FLASH_BASE
) {
797 if (chip
->spec
&& chip
->flash_size_kb
!= chip
->spec
->flash_size_kb
)
798 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
799 if (chip
->ficr_info_valid
&& chip
->flash_size_kb
!= chip
->ficr_info
.flash
)
800 LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
802 bank
->num_sectors
= num_sectors
;
803 bank
->size
= num_sectors
* flash_page_size
;
805 bank
->sectors
= alloc_block_array(0, flash_page_size
, num_sectors
);
809 chip
->bank
[0].probed
= true;
812 bank
->num_sectors
= 1;
813 bank
->size
= flash_page_size
;
815 bank
->sectors
= alloc_block_array(0, flash_page_size
, num_sectors
);
819 bank
->sectors
[0].is_protected
= 0;
821 chip
->bank
[1].probed
= true;
827 static int nrf5_auto_probe(struct flash_bank
*bank
)
829 if (nrf5_bank_is_probed(bank
))
832 return nrf5_probe(bank
);
835 static int nrf5_erase_all(struct nrf5_info
*chip
)
837 LOG_DEBUG("Erasing all non-volatile memory");
838 return nrf5_nvmc_generic_erase(chip
,
843 static int nrf5_erase_page(struct flash_bank
*bank
,
844 struct nrf5_info
*chip
,
845 struct flash_sector
*sector
)
849 LOG_DEBUG("Erasing page at 0x%"PRIx32
, sector
->offset
);
851 if (bank
->base
== NRF5_UICR_BASE
) {
852 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
854 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
856 if (res
!= ERROR_OK
) {
857 LOG_ERROR("Couldn't read PPFC register");
861 if ((ppfc
& 0xFF) == 0xFF) {
862 /* We can't erase the UICR. Double-check to
863 see if it's already erased before complaining. */
864 default_flash_blank_check(bank
);
865 if (sector
->is_erased
== 1)
868 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
873 res
= nrf5_nvmc_generic_erase(chip
,
879 res
= nrf5_nvmc_generic_erase(chip
,
887 /* Start a low level flash write for the specified region */
888 static int nrf5_ll_flash_write(struct nrf5_info
*chip
, uint32_t address
, const uint8_t *buffer
, uint32_t bytes
)
890 struct target
*target
= chip
->target
;
891 uint32_t buffer_size
= 8192;
892 struct working_area
*write_algorithm
;
893 struct working_area
*source
;
894 struct reg_param reg_params
[6];
895 struct armv7m_algorithm armv7m_info
;
896 int retval
= ERROR_OK
;
898 static const uint8_t nrf5_flash_write_code
[] = {
899 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
902 LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32
" bytes=0x%"PRIx32
, address
, bytes
);
903 assert(bytes
% 4 == 0);
905 /* allocate working area with flash programming code */
906 if (target_alloc_working_area(target
, sizeof(nrf5_flash_write_code
),
907 &write_algorithm
) != ERROR_OK
) {
908 LOG_WARNING("no working area available, falling back to slow memory writes");
910 for (; bytes
> 0; bytes
-= 4) {
911 retval
= target_write_memory(target
, address
, 4, 1, buffer
);
912 if (retval
!= ERROR_OK
)
915 retval
= nrf5_wait_for_nvmc(chip
);
916 if (retval
!= ERROR_OK
)
926 retval
= target_write_buffer(target
, write_algorithm
->address
,
927 sizeof(nrf5_flash_write_code
),
928 nrf5_flash_write_code
);
929 if (retval
!= ERROR_OK
)
933 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
935 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
936 if (buffer_size
<= 256) {
937 /* free working area, write algorithm already allocated */
938 target_free_working_area(target
, write_algorithm
);
940 LOG_WARNING("No large enough working area available, can't do block memory writes");
941 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
945 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
946 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
948 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* byte count */
949 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer start */
950 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer end */
951 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
); /* target address */
952 init_reg_param(®_params
[4], "r6", 32, PARAM_OUT
); /* watchdog refresh value */
953 init_reg_param(®_params
[5], "r7", 32, PARAM_OUT
); /* watchdog refresh register address */
955 buf_set_u32(reg_params
[0].value
, 0, 32, bytes
);
956 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
957 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
+ source
->size
);
958 buf_set_u32(reg_params
[3].value
, 0, 32, address
);
959 buf_set_u32(reg_params
[4].value
, 0, 32, WATCHDOG_REFRESH_VALUE
);
960 buf_set_u32(reg_params
[5].value
, 0, 32, WATCHDOG_REFRESH_REGISTER
);
962 retval
= target_run_flash_async_algorithm(target
, buffer
, bytes
/4, 4,
964 ARRAY_SIZE(reg_params
), reg_params
,
965 source
->address
, source
->size
,
966 write_algorithm
->address
, write_algorithm
->address
+ sizeof(nrf5_flash_write_code
) - 2,
969 target_free_working_area(target
, source
);
970 target_free_working_area(target
, write_algorithm
);
972 destroy_reg_param(®_params
[0]);
973 destroy_reg_param(®_params
[1]);
974 destroy_reg_param(®_params
[2]);
975 destroy_reg_param(®_params
[3]);
976 destroy_reg_param(®_params
[4]);
977 destroy_reg_param(®_params
[5]);
982 static int nrf5_write(struct flash_bank
*bank
, const uint8_t *buffer
,
983 uint32_t offset
, uint32_t count
)
987 if (bank
->target
->state
!= TARGET_HALTED
) {
988 LOG_ERROR("Target not halted");
989 return ERROR_TARGET_NOT_HALTED
;
992 struct nrf5_bank
*nbank
= bank
->driver_priv
;
994 struct nrf5_info
*chip
= nbank
->chip
;
997 assert(offset
% 4 == 0);
998 assert(count
% 4 == 0);
1000 /* UICR CLENR0 based protection used on nRF51 is somewhat clumsy:
1001 * RM reads: Code running from code region 1 will not be able to write
1003 * Unfortunately the flash loader running from RAM can write to both
1004 * code regions without any hint the protection is violated.
1006 * Update protection state and check if any flash sector to be written
1008 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
1010 res
= nrf5_protect_check_clenr0(bank
);
1011 if (res
!= ERROR_OK
)
1014 for (unsigned int sector
= 0; sector
< bank
->num_sectors
; sector
++) {
1015 struct flash_sector
*bs
= &bank
->sectors
[sector
];
1017 /* Start offset in or before this sector? */
1018 /* End offset in or behind this sector? */
1019 if ((offset
< (bs
->offset
+ bs
->size
))
1020 && ((offset
+ count
- 1) >= bs
->offset
)
1021 && bs
->is_protected
== 1) {
1022 LOG_ERROR("Write refused, sector %d is protected", sector
);
1023 return ERROR_FLASH_PROTECTED
;
1028 res
= nrf5_nvmc_write_enable(chip
);
1029 if (res
!= ERROR_OK
)
1032 res
= nrf5_ll_flash_write(chip
, bank
->base
+ offset
, buffer
, count
);
1033 if (res
!= ERROR_OK
)
1036 return nrf5_nvmc_read_only(chip
);
1039 nrf5_nvmc_read_only(chip
);
1040 LOG_ERROR("Failed to write to nrf5 flash");
1044 static int nrf5_erase(struct flash_bank
*bank
, unsigned int first
,
1049 if (bank
->target
->state
!= TARGET_HALTED
) {
1050 LOG_ERROR("Target not halted");
1051 return ERROR_TARGET_NOT_HALTED
;
1054 struct nrf5_bank
*nbank
= bank
->driver_priv
;
1056 struct nrf5_info
*chip
= nbank
->chip
;
1059 /* UICR CLENR0 based protection used on nRF51 prevents erase
1060 * absolutely silently. NVMC has no flag to indicate the protection
1063 * Update protection state and check if any flash sector to be erased
1065 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
1067 res
= nrf5_protect_check_clenr0(bank
);
1068 if (res
!= ERROR_OK
)
1072 /* For each sector to be erased */
1073 for (unsigned int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++) {
1075 if (chip
->features
& NRF5_FEATURE_SERIES_51
1076 && bank
->sectors
[s
].is_protected
== 1) {
1077 LOG_ERROR("Flash sector %d is protected", s
);
1078 return ERROR_FLASH_PROTECTED
;
1081 res
= nrf5_erase_page(bank
, chip
, &bank
->sectors
[s
]);
1082 if (res
!= ERROR_OK
) {
1083 LOG_ERROR("Error erasing sector %d", s
);
1091 static void nrf5_free_driver_priv(struct flash_bank
*bank
)
1093 struct nrf5_bank
*nbank
= bank
->driver_priv
;
1095 struct nrf5_info
*chip
= nbank
->chip
;
1100 if (chip
->refcount
== 0) {
1102 bank
->driver_priv
= NULL
;
1106 static struct nrf5_info
*nrf5_get_chip(struct target
*target
)
1108 struct flash_bank
*bank_iter
;
1110 /* iterate over nrf5 banks of same target */
1111 for (bank_iter
= flash_bank_list(); bank_iter
; bank_iter
= bank_iter
->next
) {
1112 if (bank_iter
->driver
!= &nrf5_flash
&& bank_iter
->driver
!= &nrf51_flash
)
1115 if (bank_iter
->target
!= target
)
1118 struct nrf5_bank
*nbank
= bank_iter
->driver_priv
;
1128 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command
)
1130 struct nrf5_info
*chip
;
1131 struct nrf5_bank
*nbank
= NULL
;
1133 if (bank
->driver
== &nrf51_flash
)
1134 LOG_WARNING("Flash driver 'nrf51' is deprecated! Use 'nrf5' instead.");
1136 switch (bank
->base
) {
1137 case NRF5_FLASH_BASE
:
1138 case NRF5_UICR_BASE
:
1141 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT
, bank
->base
);
1145 chip
= nrf5_get_chip(bank
->target
);
1147 /* Create a new chip */
1148 chip
= calloc(1, sizeof(*chip
));
1152 chip
->target
= bank
->target
;
1155 switch (bank
->base
) {
1156 case NRF5_FLASH_BASE
:
1157 nbank
= &chip
->bank
[0];
1159 case NRF5_UICR_BASE
:
1160 nbank
= &chip
->bank
[1];
1167 nbank
->probed
= false;
1168 bank
->driver_priv
= nbank
;
1169 bank
->write_start_alignment
= bank
->write_end_alignment
= 4;
1174 COMMAND_HANDLER(nrf5_handle_mass_erase_command
)
1177 struct flash_bank
*bank
= NULL
;
1178 struct target
*target
= get_current_target(CMD_CTX
);
1180 res
= get_flash_bank_by_addr(target
, NRF5_FLASH_BASE
, true, &bank
);
1181 if (res
!= ERROR_OK
)
1186 if (target
->state
!= TARGET_HALTED
) {
1187 LOG_ERROR("Target not halted");
1188 return ERROR_TARGET_NOT_HALTED
;
1191 struct nrf5_bank
*nbank
= bank
->driver_priv
;
1193 struct nrf5_info
*chip
= nbank
->chip
;
1196 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
1198 res
= target_read_u32(target
, NRF51_FICR_PPFC
,
1200 if (res
!= ERROR_OK
) {
1201 LOG_ERROR("Couldn't read PPFC register");
1205 if ((ppfc
& 0xFF) == 0x00) {
1206 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1207 "mass erase command won't work.");
1212 res
= nrf5_erase_all(chip
);
1213 if (res
== ERROR_OK
) {
1214 LOG_INFO("Mass erase completed.");
1215 if (chip
->features
& NRF5_FEATURE_SERIES_51
)
1216 LOG_INFO("A reset or power cycle is required if the flash was protected before.");
1219 LOG_ERROR("Failed to erase the chip");
1226 static const struct command_registration nrf5_exec_command_handlers
[] = {
1228 .name
= "mass_erase",
1229 .handler
= nrf5_handle_mass_erase_command
,
1230 .mode
= COMMAND_EXEC
,
1231 .help
= "Erase all flash contents of the chip.",
1234 COMMAND_REGISTRATION_DONE
1237 static const struct command_registration nrf5_command_handlers
[] = {
1240 .mode
= COMMAND_ANY
,
1241 .help
= "nrf5 flash command group",
1243 .chain
= nrf5_exec_command_handlers
,
1247 .mode
= COMMAND_ANY
,
1248 .help
= "nrf51 flash command group",
1250 .chain
= nrf5_exec_command_handlers
,
1252 COMMAND_REGISTRATION_DONE
1255 const struct flash_driver nrf5_flash
= {
1257 .commands
= nrf5_command_handlers
,
1258 .flash_bank_command
= nrf5_flash_bank_command
,
1260 .erase
= nrf5_erase
,
1261 .protect
= nrf5_protect
,
1262 .write
= nrf5_write
,
1263 .read
= default_flash_read
,
1264 .probe
= nrf5_probe
,
1265 .auto_probe
= nrf5_auto_probe
,
1266 .erase_check
= default_flash_blank_check
,
1267 .protect_check
= nrf5_protect_check
,
1268 .free_driver_priv
= nrf5_free_driver_priv
,
1271 /* We need to retain the flash-driver name as well as the commands
1272 * for backwards compatibility */
1273 const struct flash_driver nrf51_flash
= {
1275 .commands
= nrf5_command_handlers
,
1276 .flash_bank_command
= nrf5_flash_bank_command
,
1278 .erase
= nrf5_erase
,
1279 .protect
= nrf5_protect
,
1280 .write
= nrf5_write
,
1281 .read
= default_flash_read
,
1282 .probe
= nrf5_probe
,
1283 .auto_probe
= nrf5_auto_probe
,
1284 .erase_check
= default_flash_blank_check
,
1285 .protect_check
= nrf5_protect_check
,
1286 .free_driver_priv
= nrf5_free_driver_priv
,
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