1 /***************************************************************************
2 * Copyright (C) 2018 by Square, Inc. *
3 * Steven Stallion <stallion@squareup.com> *
4 * James Zhao <hjz@squareup.com> *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
18 ***************************************************************************/
24 #include <flash/common.h>
25 #include <flash/nor/imp.h>
26 #include <helper/command.h>
27 #include <helper/log.h>
28 #include <helper/time_support.h>
29 #include <helper/types.h>
30 #include <target/esirisc.h>
31 #include <target/target.h>
33 /* eSi-TSMC Flash Registers */
34 #define CONTROL 0x00 /* Control Register */
35 #define TIMING0 0x04 /* Timing Register 0 */
36 #define TIMING1 0x08 /* Timing Register 1 */
37 #define TIMING2 0x0c /* Timing Register 2 */
38 #define UNLOCK1 0x18 /* Unlock 1 */
39 #define UNLOCK2 0x1c /* Unlock 2 */
40 #define ADDRESS 0x20 /* Erase/Program Address */
41 #define PB_DATA 0x24 /* Program Buffer Data */
42 #define PB_INDEX 0x28 /* Program Buffer Index */
43 #define STATUS 0x2c /* Status Register */
44 #define REDUN_0 0x30 /* Redundant Address 0 */
45 #define REDUN_1 0x34 /* Redundant Address 1 */
48 #define CONTROL_SLM (1<<0) /* Sleep Mode */
49 #define CONTROL_WP (1<<1) /* Register Write Protect */
50 #define CONTROL_E (1<<3) /* Erase */
51 #define CONTROL_EP (1<<4) /* Erase Page */
52 #define CONTROL_P (1<<5) /* Program Flash */
53 #define CONTROL_ERC (1<<6) /* Erase Reference Cell */
54 #define CONTROL_R (1<<7) /* Recall Trim Code */
55 #define CONTROL_AP (1<<8) /* Auto-Program */
58 #define TIMING0_R(x) (((x) << 0) & 0x3f) /* Read Wait States */
59 #define TIMING0_F(x) (((x) << 16) & 0xffff0000) /* Tnvh Clock Cycles */
60 #define TIMING1_E(x) (((x) << 0) & 0xffffff) /* Tme/Terase/Tre Clock Cycles */
61 #define TIMING2_P(x) (((x) << 0) & 0xffff) /* Tprog Clock Cycles */
62 #define TIMING2_H(x) (((x) << 16) & 0xff0000) /* Clock Cycles in 100ns */
63 #define TIMING2_T(x) (((x) << 24) & 0xf000000) /* Clock Cycles in 10ns */
66 #define STATUS_BUSY (1<<0) /* Busy (Erase/Program) */
67 #define STATUS_WER (1<<1) /* Write Protect Error */
68 #define STATUS_DR (1<<2) /* Disable Redundancy */
69 #define STATUS_DIS (1<<3) /* Discharged */
70 #define STATUS_BO (1<<4) /* Brown Out */
72 /* Redundant Address Fields */
73 #define REDUN_R (1<<0) /* Used */
74 #define REDUN_P(x) (((x) << 12) & 0x7f000) /* Redundant Page Address */
77 * The eSi-TSMC Flash manual provides two sets of timings based on the
78 * underlying flash process. By default, 90nm is assumed.
81 #define TNVH 5000 /* 5us */
82 #define TME 80000000 /* 80ms */
83 #define TERASE 160000000 /* 160ms */
84 #define TRE 100000000 /* 100ms */
85 #define TPROG 8000 /* 8us */
87 #define TNVH 5000 /* 5us */
88 #define TME 20000000 /* 20ms */
89 #define TERASE 40000000 /* 40ms */
90 #define TRE 40000000 /* 40ms */
91 #define TPROG 40000 /* 40us */
94 #define CONTROL_TIMEOUT 5000 /* 5s */
95 #define FLASH_PAGE_SIZE 4096
98 #define NUM_NS_PER_S 1000000000ULL
100 struct esirisc_flash_bank
{
104 uint32_t wait_states
;
107 static const struct command_registration esirisc_flash_command_handlers
[];
109 FLASH_BANK_COMMAND_HANDLER(esirisc_flash_bank_command
)
111 struct esirisc_flash_bank
*esirisc_info
;
112 struct command
*esirisc_cmd
;
115 return ERROR_COMMAND_SYNTAX_ERROR
;
117 esirisc_info
= calloc(1, sizeof(struct esirisc_flash_bank
));
119 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[6], esirisc_info
->cfg
);
120 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[7], esirisc_info
->clock
);
121 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[8], esirisc_info
->wait_states
);
123 bank
->driver_priv
= esirisc_info
;
125 /* register commands using existing esirisc context */
126 esirisc_cmd
= command_find_in_context(CMD_CTX
, "esirisc");
127 register_commands(CMD_CTX
, esirisc_cmd
, esirisc_flash_command_handlers
);
133 * Register writes are ignored if the control.WP flag is set; the
134 * following sequence is required to modify this flag even when
135 * protection is disabled.
137 static int esirisc_flash_unlock(struct flash_bank
*bank
)
139 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
140 struct target
*target
= bank
->target
;
142 target_write_u32(target
, esirisc_info
->cfg
+ UNLOCK1
, 0x7123);
143 target_write_u32(target
, esirisc_info
->cfg
+ UNLOCK2
, 0x812a);
144 target_write_u32(target
, esirisc_info
->cfg
+ UNLOCK1
, 0xbee1);
149 static int esirisc_flash_disable_protect(struct flash_bank
*bank
)
151 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
152 struct target
*target
= bank
->target
;
155 target_read_u32(target
, esirisc_info
->cfg
+ CONTROL
, &control
);
156 if (!(control
& CONTROL_WP
))
159 (void)esirisc_flash_unlock(bank
);
161 control
&= ~CONTROL_WP
;
163 target_write_u32(target
, esirisc_info
->cfg
+ CONTROL
, control
);
168 static int esirisc_flash_enable_protect(struct flash_bank
*bank
)
170 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
171 struct target
*target
= bank
->target
;
174 target_read_u32(target
, esirisc_info
->cfg
+ CONTROL
, &control
);
175 if (control
& CONTROL_WP
)
178 (void)esirisc_flash_unlock(bank
);
180 control
|= CONTROL_WP
;
182 target_write_u32(target
, esirisc_info
->cfg
+ CONTROL
, control
);
187 static int esirisc_flash_check_status(struct flash_bank
*bank
)
189 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
190 struct target
*target
= bank
->target
;
193 target_read_u32(target
, esirisc_info
->cfg
+ STATUS
, &status
);
194 if (status
& STATUS_WER
) {
195 LOG_ERROR("%s: bad status: 0x%" PRIx32
, bank
->name
, status
);
196 return ERROR_FLASH_OPERATION_FAILED
;
202 static int esirisc_flash_clear_status(struct flash_bank
*bank
)
204 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
205 struct target
*target
= bank
->target
;
207 target_write_u32(target
, esirisc_info
->cfg
+ STATUS
, STATUS_WER
);
212 static int esirisc_flash_wait(struct flash_bank
*bank
, int ms
)
214 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
215 struct target
*target
= bank
->target
;
221 target_read_u32(target
, esirisc_info
->cfg
+ STATUS
, &status
);
222 if (!(status
& STATUS_BUSY
))
225 if ((timeval_ms() - t
) > ms
)
226 return ERROR_TARGET_TIMEOUT
;
232 static int esirisc_flash_control(struct flash_bank
*bank
, uint32_t control
)
234 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
235 struct target
*target
= bank
->target
;
237 esirisc_flash_clear_status(bank
);
239 target_write_u32(target
, esirisc_info
->cfg
+ CONTROL
, control
);
241 int retval
= esirisc_flash_wait(bank
, CONTROL_TIMEOUT
);
242 if (retval
!= ERROR_OK
) {
243 LOG_ERROR("%s: control timed out: 0x%" PRIx32
, bank
->name
, control
);
247 return esirisc_flash_check_status(bank
);
250 static int esirisc_flash_recall(struct flash_bank
*bank
)
252 return esirisc_flash_control(bank
, CONTROL_R
);
255 static int esirisc_flash_erase(struct flash_bank
*bank
, unsigned int first
,
258 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
259 struct target
*target
= bank
->target
;
260 int retval
= ERROR_OK
;
262 if (target
->state
!= TARGET_HALTED
)
263 return ERROR_TARGET_NOT_HALTED
;
265 (void)esirisc_flash_disable_protect(bank
);
267 for (unsigned int page
= first
; page
< last
; ++page
) {
268 uint32_t address
= page
* FLASH_PAGE_SIZE
;
270 target_write_u32(target
, esirisc_info
->cfg
+ ADDRESS
, address
);
272 retval
= esirisc_flash_control(bank
, CONTROL_EP
);
273 if (retval
!= ERROR_OK
) {
274 LOG_ERROR("%s: failed to erase address: 0x%" PRIx32
, bank
->name
, address
);
279 (void)esirisc_flash_enable_protect(bank
);
284 static int esirisc_flash_mass_erase(struct flash_bank
*bank
)
286 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
287 struct target
*target
= bank
->target
;
290 if (target
->state
!= TARGET_HALTED
)
291 return ERROR_TARGET_NOT_HALTED
;
293 (void)esirisc_flash_disable_protect(bank
);
295 target_write_u32(target
, esirisc_info
->cfg
+ ADDRESS
, 0);
297 retval
= esirisc_flash_control(bank
, CONTROL_E
);
298 if (retval
!= ERROR_OK
)
299 LOG_ERROR("%s: failed to mass erase", bank
->name
);
301 (void)esirisc_flash_enable_protect(bank
);
307 * Per TSMC, the reference cell should be erased once per sample. This
308 * is typically done during wafer sort, however we include support for
309 * those that may need to calibrate flash at a later time.
311 static int esirisc_flash_ref_erase(struct flash_bank
*bank
)
313 struct target
*target
= bank
->target
;
316 if (target
->state
!= TARGET_HALTED
)
317 return ERROR_TARGET_NOT_HALTED
;
319 (void)esirisc_flash_disable_protect(bank
);
321 retval
= esirisc_flash_control(bank
, CONTROL_ERC
);
322 if (retval
!= ERROR_OK
)
323 LOG_ERROR("%s: failed to erase reference cell", bank
->name
);
325 (void)esirisc_flash_enable_protect(bank
);
330 static int esirisc_flash_fill_pb(struct flash_bank
*bank
,
331 const uint8_t *buffer
, uint32_t count
)
333 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
334 struct target
*target
= bank
->target
;
335 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
338 * The pb_index register is auto-incremented when pb_data is written
339 * and should be cleared before each operation.
341 target_write_u32(target
, esirisc_info
->cfg
+ PB_INDEX
, 0);
344 * The width of the pb_data register depends on the underlying
345 * target; writing one byte at a time incurs a significant
346 * performance penalty and should be avoided.
349 uint32_t max_bytes
= DIV_ROUND_UP(esirisc
->num_bits
, 8);
350 uint32_t num_bytes
= MIN(count
, max_bytes
);
352 target_write_buffer(target
, esirisc_info
->cfg
+ PB_DATA
, num_bytes
, buffer
);
361 static int esirisc_flash_write(struct flash_bank
*bank
,
362 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
364 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
365 struct target
*target
= bank
->target
;
366 int retval
= ERROR_OK
;
368 if (target
->state
!= TARGET_HALTED
)
369 return ERROR_TARGET_NOT_HALTED
;
371 (void)esirisc_flash_disable_protect(bank
);
374 * The address register is auto-incremented based on the contents of
375 * the pb_index register after each operation completes. It can be
376 * set once provided pb_index is cleared before each operation.
378 target_write_u32(target
, esirisc_info
->cfg
+ ADDRESS
, offset
);
381 * Care must be taken when filling the program buffer; a maximum of
382 * 32 bytes may be written at a time and may not cross a 32-byte
383 * boundary based on the current offset.
386 uint32_t max_bytes
= PB_MAX
- (offset
& 0x1f);
387 uint32_t num_bytes
= MIN(count
, max_bytes
);
389 esirisc_flash_fill_pb(bank
, buffer
, num_bytes
);
391 retval
= esirisc_flash_control(bank
, CONTROL_P
);
392 if (retval
!= ERROR_OK
) {
393 LOG_ERROR("%s: failed to program address: 0x%" PRIx32
, bank
->name
, offset
);
402 (void)esirisc_flash_enable_protect(bank
);
407 static uint32_t esirisc_flash_num_cycles(struct flash_bank
*bank
, uint64_t ns
)
409 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
411 /* apply scaling factor to avoid truncation */
412 uint64_t hz
= (uint64_t)esirisc_info
->clock
* 1000;
413 uint64_t num_cycles
= ((hz
/ NUM_NS_PER_S
) * ns
) / 1000;
415 if (hz
% NUM_NS_PER_S
> 0)
421 static int esirisc_flash_init(struct flash_bank
*bank
)
423 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
424 struct target
*target
= bank
->target
;
428 (void)esirisc_flash_disable_protect(bank
);
430 /* initialize timing registers */
431 value
= TIMING0_F(esirisc_flash_num_cycles(bank
, TNVH
))
432 | TIMING0_R(esirisc_info
->wait_states
);
434 LOG_DEBUG("TIMING0: 0x%" PRIx32
, value
);
435 target_write_u32(target
, esirisc_info
->cfg
+ TIMING0
, value
);
437 value
= TIMING1_E(esirisc_flash_num_cycles(bank
, TERASE
));
439 LOG_DEBUG("TIMING1: 0x%" PRIx32
, value
);
440 target_write_u32(target
, esirisc_info
->cfg
+ TIMING1
, value
);
442 value
= TIMING2_T(esirisc_flash_num_cycles(bank
, 10))
443 | TIMING2_H(esirisc_flash_num_cycles(bank
, 100))
444 | TIMING2_P(esirisc_flash_num_cycles(bank
, TPROG
));
446 LOG_DEBUG("TIMING2: 0x%" PRIx32
, value
);
447 target_write_u32(target
, esirisc_info
->cfg
+ TIMING2
, value
);
449 /* recall trim code */
450 retval
= esirisc_flash_recall(bank
);
451 if (retval
!= ERROR_OK
)
452 LOG_ERROR("%s: failed to recall trim code", bank
->name
);
454 (void)esirisc_flash_enable_protect(bank
);
459 static int esirisc_flash_probe(struct flash_bank
*bank
)
461 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
462 struct target
*target
= bank
->target
;
465 if (target
->state
!= TARGET_HALTED
)
466 return ERROR_TARGET_NOT_HALTED
;
468 bank
->num_sectors
= bank
->size
/ FLASH_PAGE_SIZE
;
469 bank
->sectors
= alloc_block_array(0, FLASH_PAGE_SIZE
, bank
->num_sectors
);
471 retval
= esirisc_flash_init(bank
);
472 if (retval
!= ERROR_OK
) {
473 LOG_ERROR("%s: failed to initialize bank", bank
->name
);
477 esirisc_info
->probed
= true;
482 static int esirisc_flash_auto_probe(struct flash_bank
*bank
)
484 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
486 if (esirisc_info
->probed
)
489 return esirisc_flash_probe(bank
);
492 static int esirisc_flash_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
494 struct esirisc_flash_bank
*esirisc_info
= bank
->driver_priv
;
496 snprintf(buf
, buf_size
,
497 "%4s cfg at 0x%" PRIx32
", clock %" PRId32
", wait_states %" PRId32
,
498 "", /* align with first line */
501 esirisc_info
->wait_states
);
506 COMMAND_HANDLER(handle_esirisc_flash_mass_erase_command
)
508 struct flash_bank
*bank
;
512 return ERROR_COMMAND_SYNTAX_ERROR
;
514 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
515 if (retval
!= ERROR_OK
)
518 retval
= esirisc_flash_mass_erase(bank
);
520 command_print(CMD
, "mass erase %s",
521 (retval
== ERROR_OK
) ? "successful" : "failed");
526 COMMAND_HANDLER(handle_esirisc_flash_ref_erase_command
)
528 struct flash_bank
*bank
;
532 return ERROR_COMMAND_SYNTAX_ERROR
;
534 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
535 if (retval
!= ERROR_OK
)
538 retval
= esirisc_flash_ref_erase(bank
);
540 command_print(CMD
, "erase reference cell %s",
541 (retval
== ERROR_OK
) ? "successful" : "failed");
546 static const struct command_registration esirisc_flash_exec_command_handlers
[] = {
548 .name
= "mass_erase",
549 .handler
= handle_esirisc_flash_mass_erase_command
,
550 .mode
= COMMAND_EXEC
,
551 .help
= "erase all pages in data memory",
556 .handler
= handle_esirisc_flash_ref_erase_command
,
557 .mode
= COMMAND_EXEC
,
558 .help
= "erase reference cell (uncommon)",
561 COMMAND_REGISTRATION_DONE
564 static const struct command_registration esirisc_flash_command_handlers
[] = {
567 .mode
= COMMAND_EXEC
,
568 .help
= "eSi-TSMC Flash command group",
570 .chain
= esirisc_flash_exec_command_handlers
,
572 COMMAND_REGISTRATION_DONE
575 const struct flash_driver esirisc_flash
= {
577 .usage
= "flash bank bank_id 'esirisc' base_address size_bytes 0 0 target "
578 "cfg_address clock_hz wait_states",
579 .flash_bank_command
= esirisc_flash_bank_command
,
580 .erase
= esirisc_flash_erase
,
581 .write
= esirisc_flash_write
,
582 .read
= default_flash_read
,
583 .probe
= esirisc_flash_probe
,
584 .auto_probe
= esirisc_flash_auto_probe
,
585 .erase_check
= default_flash_blank_check
,
586 .info
= esirisc_flash_info
,
587 .free_driver_priv
= default_flash_free_driver_priv
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)